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x86 指令集

转自 http://siyobik.info/index.php?module=x86

x86 Instruction Set Reference

Opcode Description
AAA ASCII Adjust After Addition
AAD ASCII Adjust AX Before Division
AAS ASCII Adjust AL After Subtraction
ADC Add with Carry
ADD Add
ADDPD Add Packed Double-Precision Floating-Point Values
ADDPS Add Packed Single-Precision Floating-Point Values
ADDSD Add Scalar Double-Precision Floating-Point Values
ADDSS Add Scalar Single-Precision Floating-Point Values
ADDSUBPD Packed Double-FP Add/Subtract
ADDSUBPS Packed Single-FP Add/Subtract
AND Logical AND
ANDPD Bitwise Logical AND of Packed Double-Precision Floating-Point Values
ANDPS Bitwise Logical AND of Packed Single-Precision Floating-Point Values
ANDNPD Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
ANDNPS Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values
ARPL Adjust RPL Field of Segment Selector
BOUND Check Array Index Against Bounds
BSF Bit Scan Forward
BSR Bit Scan Reverse
BSWAP Byte Swap
BT Bit Test
BTC Bit Test and Complement
BTR Bit Test and Reset
BTS Bit Test and Set
CALL Call Procedure
CBW/CWDE Convert Byte to Word/Convert Word to Doubleword
CLC Clear Carry Flag
CLD Clear Direction Flag
CLFLUSH Flush Cache Line
CLI Clear Interrupt Flag
CLTS Clear Task-Switched Flag in CR0
CMC Complement Carry Flag
CMOVcc Conditional Move
CMP Compare Two Operands
CMPPD Compare Packed Double-Precision Floating-Point Values
CMPPS Compare Packed Single-Precision Floating-Point Values
CMPS/CMPSB/CMPSW/CMPSD Compare String Operands
CMPSD Compare Scalar Double-Precision Floating-Point Values
CMPSS Compare Scalar Single-Precision Floating-Point Values
CMPXCHG Compare and Exchange
CMPXCHG8B Compare and Exchange 8 Bytes
COMISD Compare Scalar Ordered Double-Precision Floating- Point Values and Set EFLAGS
COMISS Compare Scalar Ordered Single-Precision Floating- Point Values and Set EFLAGS
CPUID CPU Identification
CVTDQ2PD Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
CVTDQ2PS Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
CVTPD2DQ Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
CVTPD2PI Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
CVTPD2PS Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
CVTPI2PD Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
CVTPI2PS Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
CVTPS2DQ Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
CVTPS2PD Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
CVTPS2PI Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
CVTSD2SI Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
CVTSD2SS Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
CVTSI2SD Convert Doubleword Integer to Scalar Double- Precision Floating-Point Value
CVTSI2SS Convert Doubleword Integer to Scalar Single- Precision Floating-Point Value
CVTSS2SD Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
CVTSS2SI Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
CVTTPD2PI Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
CVTTPD2DQ Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
CVTTPS2DQ Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
CVTTPS2PI Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
CVTTSD2SI Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Doubleword Integer
CVTTSS2SI Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
CWD/CDQ Convert Word to Doubleword/Convert Doubleword to Quadword
DAA Decimal Adjust AL after Addition
DAS Decimal Adjust AL after Subtraction
DEC Decrement by 1
DIV Unsigned Divide
DIVPD Divide Packed Double-Precision Floating-Point Values
DIVPS Divide Packed Single-Precision Floating-Point Values
DIVSD Divide Scalar Double-Precision Floating-Point Values
DIVSS Divide Scalar Single-Precision Floating-Point Values
EMMS Empty MMX Technology State
ENTER Make Stack Frame for Procedure Parameters
F2XM1 Compute 2x-1
FABS Absolute Value
FADD/FADDP/FIADD Add
FBLD Load Binary Coded Decimal
FBSTP Store BCD Integer and Pop
FCHS Change Sign
FCLEX/FNCLEX Clear Exceptions
FCMOVcc Floating-Point Conditional Move
FCOM/FCOMP/FCOMPP Compare Floating Point Values
FCOMI/FCOMIP/FUCOMI/FUCOMIP Compare Floating Point Values and Set EFLAGS
FCOS Cosine
FDECSTP Decrement Stack-Top Pointer
FDIV/FDIVP/FIDIV Divide
FDIVR/FDIVRP/FIDIVR Reverse Divide
FFREE Free Floating-Point Register
FICOM/FICOMP Compare Integer
FILD Load Integer
FINCSTP Increment Stack-Top Pointer
FINIT/FNINIT Initialize Floating-Point Unit
FIST/FISTP Store Integer
FISTTP Store Integer with Truncation
FLD Load Floating Point Value
FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ Load Constant
FLDCW Load x87 FPU Control Word
FLDENV Load x87 FPU Environment
FMUL/FMULP/FIMUL Multiply
FNOP No operation
FPATAN Partial Arctangent
FPREM Partial Remainder
FPREM1 Partial Remainder
FPTAN Partial Tangent
FRNDINT Round to Integer
FRSTOR Restore x87 FPU State
FSAVE/FNSAVE Store x87 FPU State
FSCALE Scale
FSIN Sine
FSINCOS Sine and Cosine
FSQRT Square Root
FST/FSTP Store Floating Point Value
FSTCW/FNSTCW Store x87 FPU Control Word
FSTENV/FNSTENV Store x87 FPU Environment
FSTSW/FNSTSW Store x87 FPU Status Word
FSUB/FSUBP/FISUB Subtract
FSUBR/FSUBRP/FISUBR Reverse Subtract
FTST Test Floating Point Value
FUCOM/FUCOMP/FUCOMPP Unordered Compare Floating Point Values
FXAM Examine Floating Point Value
FXCH Exchange Register Contents
FXRSTOR Restore x87 FPU, MMX Technology, SSE, and SSE2 State
FXSAVE Save x87 FPU, MMX Technology, SSE, and SSE2 State
FXTRACT Extract Exponent and Mantissa
FYL2X Compute y * log_2(x)
FYL2XP1 Compute y * log_2(x + 1)
HADDPD Packed Double-FP Horizontal Add
HADDPS Packed Single-FP Horizontal Add
HLT Halt
HSUBPD Packed Double-FP Horizontal Subtract
HSUBPS Packed Single-FP Horizontal Subtract
IDIV Signed Divide
IMUL Signed Multiply
IN Input from Port
INC Increment by 1
INS/INSB/INSW/INSD Input from Port to String
INT n/INTO/INT 3 Call to Interrupt Procedure
INVD Invalidate Internal Caches
INVLPG Invalidate TLB Entry
IRET/IRETD Interrupt Return
Jcc Jump if Condition Is Met
JMP Jump
LAHF Load Status Flags into AH Register
LAR Load Access Rights Byte
LDDQU Load Unaligned Integer 128 Bits
LDMXCSR Load MXCSR Register
LDS/LES/LFS/LGS/LSS Load Far Pointer
LEA Load Effective Address
LEAVE High Level Procedure Exit
LFENCE Load Fence
LGDT/LIDT Load Global/Interrupt Descriptor Table Register
LLDT Load Local Descriptor Table Register
LMSW Load Machine Status Word
LOCK Assert LOCK# Signal Prefix
LODS/LODSB/LODSW/LODSD Load String
LOOP/LOOPcc Loop According to ECX Counter
LSL Load Segment Limit
LTR Load Task Register
MASKMOVDQU Store Selected Bytes of Double Quadword
MASKMOVQ Store Selected Bytes of Quadword
MAXPD Return Maximum Packed Double-Precision Floating- Point Values
MAXPS Return Maximum Packed Single-Precision Floating-Point Values
MAXSD Return Maximum Scalar Double-Precision Floating-Point Value
MAXSS Return Maximum Scalar Single-Precision Floating-Point Value
MFENCE Memory Fence
MINPD Return Minimum Packed Double-Precision Floating-Point Values
MINPS Return Minimum Packed Single-Precision Floating-Point Values
MINSD Return Minimum Scalar Double-Precision Floating-Point Value
MINSS Return Minimum Scalar Single-Precision Floating-Point Value
MONITOR Setup Monitor Address
MOV Move
MOV Move to/from Control Registers
MOV Move to/from Debug Registers
MOVAPD Move Aligned Packed Double-Precision Floating-Point Values
MOVAPS Move Aligned Packed Single-Precision Floating-Point Values
MOVD Move Doubleword
MOVDDUP Move One Double-FP and Duplicate
MOVDQA Move Aligned Double Quadword
MOVDQU Move Unaligned Double Quadword
MOVDQ2Q Move Quadword from XMM to MMX Technology Register
MOVHLPS Move Packed Single-Precision Floating-Point Values High to Low
MOVHPD Move High Packed Double-Precision Floating-Point Value
MOVHPS Move High Packed Single-Precision Floating-Point Values
MOVLHPS Move Packed Single-Precision Floating-Point Values Low to High
MOVLPD Move Low Packed Double-Precision Floating-Point Value
MOVLPS Move Low Packed Single-Precision Floating-Point Values
MOVMSKPD Extract Packed Double-Precision Floating-Point Sign Mask
MOVMSKPS Extract Packed Single-Precision Floating-Point Sign Mask
MOVNTDQ Store Double Quadword Using Non-Temporal Hint
MOVNTI Store Doubleword Using Non-Temporal Hint
MOVNTPD Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
MOVNTPS Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint
MOVNTQ Store of Quadword Using Non-Temporal Hint
MOVSHDUP Move Packed Single-FP High and Duplicate
MOVSLDUP Move Packed Single-FP Low and Duplicate
MOVQ Move Quadword
MOVQ2DQ Move Quadword from MMX Technology to XMM Register
MOVS/MOVSB/MOVSW/MOVSD Move Data from String to String
MOVSD Move Scalar Double-Precision Floating-Point Value
MOVSS Move Scalar Single-Precision Floating-Point Values
MOVSX Move with Sign-Extension
MOVUPD Move Unaligned Packed Double-Precision Floating- Point Values
MOVUPS Move Unaligned Packed Single-Precision Floating- Point Values
MOVZX Move with Zero-Extend
MUL Unsigned Multiply
MULPD Multiply Packed Double-Precision Floating-Point Values
MULPS Multiply Packed Single-Precision Floating-Point Values
MULSD Multiply Scalar Double-Precision Floating-Point Values
MULSS Multiply Scalar Single-Precision Floating-Point Values
MWAIT Monitor Wait
NEG Two's Complement Negation
NOP No Operation
NOT One's Complement Negation
OR Logical Inclusive OR
ORPD Bitwise Logical OR of Double-Precision Floating-Point Values
ORPS Bitwise Logical OR of Single-Precision Floating-Point Values
OUT Output to Port
OUTS/OUTSB/OUTSW/OUTSD Output String to Port
PACKSSWB/PACKSSDW Pack with Signed Saturation
PACKUSWB Pack with Unsigned Saturation
PADDB/PADDW/PADDD Add Packed Integers
PADDQ Add Packed Quadword Integers
PADDSB/PADDSW Add Packed Signed Integers with Signed Saturation
PADDUSB/PADDUSW Add Packed Unsigned Integers with Unsigned Saturation
PAND Logical AND
PANDN Logical AND NOT
PAUSE Spin Loop Hint
PAVGB/PAVGW Average Packed Integers
PCMPEQB/PCMPEQW/PCMPEQD Compare Packed Data for Equal
PCMPGTB/PCMPGTW/PCMPGTD Compare Packed Signed Integers for Greater Than
PEXTRW Extract Word
PINSRW Insert Word
PMADDWD Multiply and Add Packed Integers
PMAXSW Maximum of Packed Signed Word Integers
PMAXUB Maximum of Packed Unsigned Byte Integers
PMINSW Minimum of Packed Signed Word Integers
PMINUB Minimum of Packed Unsigned Byte Integers
PMOVMSKB Move Byte Mask
PMULHUW Multiply Packed Unsigned Integers and Store High Result
PMULHW Multiply Packed Signed Integers and Store High Result
PMULLW Multiply Packed Signed Integers and Store Low Result
PMULUDQ Multiply Packed Unsigned Doubleword Integers
POP Pop a Value from the Stack
POPA/POPAD Pop All General-Purpose Registers
POPF/POPFD Pop Stack into EFLAGS Register
POR Bitwise Logical OR
PREFETCHh Prefetch Data Into Caches
PSADBW Compute Sum of Absolute Differences
PSHUFD Shuffle Packed Doublewords
PSHUFHW Shuffle Packed High Words
PSHUFLW Shuffle Packed Low Words
PSHUFW Shuffle Packed Words
PSLLDQ Shift Double Quadword Left Logical
PSLLW/PSLLD/PSLLQ Shift Packed Data Left Logical
PSRAW/PSRAD Shift Packed Data Right Arithmetic
PSRLDQ Shift Double Quadword Right Logical
PSRLW/PSRLD/PSRLQ Shift Packed Data Right Logical
PSUBB/PSUBW/PSUBD Subtract Packed Integers
PSUBQ Subtract Packed Quadword Integers
PSUBSB/PSUBSW Subtract Packed Signed Integers with Signed Saturation
PSUBUSB/PSUBUSW Subtract Packed Unsigned Integers with Unsigned Saturation
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ Unpack High Data
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ Unpack Low Data
PUSH Push Word or Doubleword Onto the Stack
PUSHA/PUSHAD Push All General-Purpose Registers
PUSHF/PUSHFD Push EFLAGS Register onto the Stack
PXOR Logical Exclusive OR
RCL/RCR/ROL/ROR Rotate
RCPPS Compute Reciprocals of Packed Single-Precision Floating-Point Values
RCPSS Compute Reciprocal of Scalar Single-Precision Floating- Point Values
RDMSR Read from Model Specific Register
RDPMC Read Performance-Monitoring Counters
RDTSC Read Time-Stamp Counter
REP/REPE/REPZ/REPNE/REPNZ Repeat String Operation Prefix
RET Return from Procedure
RSM Resume from System Management Mode
RSQRTPS Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values
RSQRTSS Compute Reciprocal of Square Root of Scalar Single- Precision Floating-Point Value
SAHF Store AH into Flags
SAL/SAR/SHL/SHR Shift
SBB Integer Subtraction with Borrow
SCAS/SCASB/SCASW/SCASD Scan String
SETcc Set Byte on Condition
SFENCE Store Fence
SGDT Store Global Descriptor Table Register
SHLD Double Precision Shift Left
SHRD Double Precision Shift Right
SHUFPD Shuffle Packed Double-Precision Floating-Point Values
SHUFPS Shuffle Packed Single-Precision Floating-Point Values
SIDT Store Interrupt Descriptor Table Register
SLDT Store Local Descriptor Table Register
SMSW Store Machine Status Word
SQRTPD Compute Square Roots of Packed Double-Precision Floating-Point Values
SQRTPS Compute Square Roots of Packed Single-Precision Floating-Point Values
SQRTSD Compute Square Root of Scalar Double-Precision Floating-Point Value
SQRTSS Compute Square Root of Scalar Single-Precision Floating-Point Value
STC Set Carry Flag
STD Set Direction Flag
STI Set Interrupt Flag
STMXCSR Store MXCSR Register State
STOS/STOSB/STOSW/STOSD Store String
STR Store Task Register
SUB Subtract
SUBPD Subtract Packed Double-Precision Floating-Point Values
SUBPS Subtract Packed Single-Precision Floating-Point Values
SUBSD Subtract Scalar Double-Precision Floating-Point Values
SUBSS Subtract Scalar Single-Precision Floating-Point Values
SYSENTER Fast System Call
SYSEXIT Fast Return from Fast System Call
TEST Logical Compare
UCOMISD Unordered Compare Scalar Double-Precision Floating- Point Values and Set EFLAGS
UCOMISS Unordered Compare Scalar Single-Precision Floating- Point Values and Set EFLAGS
UD2 Undefined Instruction
UNPCKHPD Unpack and Interleave High Packed Double- Precision Floating-Point Values
UNPCKHPS Unpack and Interleave High Packed Single-Precision Floating-Point Values
UNPCKLPD Unpack and Interleave Low Packed Double-Precision Floating-Point Values
UNPCKLPS Unpack and Interleave Low Packed Single-Precision Floating-Point Values
VERR/VERW Verify a Segment for Reading or Writing
WAIT/FWAIT Wait
WBINVD Write Back and Invalidate Cache
WRMSR Write to Model Specific Register
XADD Exchange and Add
XCHG Exchange Register/Memory with Register
XLAT/XLATB Table Look-up Translation
XOR Logical Exclusive OR
XORPD Bitwise Logical XOR for Double-Precision Floating-Point Values
XORPS Bitwise Logical XOR for Single-Precision Floating-Point Values




Jcc

Jump if Condition Is Met

Opcode Mnemonic Description
77 cb JA rel8 Jump short if above (CF=0 and ZF=0).
73 cb JAE rel8 Jump short if above or equal (CF=0).
72 cb JB rel8 Jump short if below (CF=1).
76 cb JBE rel8 Jump short if below or equal (CF=1 or ZF=1).
72 cb JC rel8 Jump short if carry (CF=1).
E3 cb JCXZ rel8 Jump short if CX register is 0.
E3 cb JECXZ rel8 Jump short if ECX register is 0.
74 cb JE rel8 Jump short if equal (ZF=1).
7F cb JG rel8 Jump short if greater (ZF=0 and SF=OF).
7D cb JGE rel8 Jump short if greater or equal (SF=OF).
7C cb JL rel8 Jump short if less (SF<>OF).
7E cb JLE rel8 Jump short if less or equal (ZF=1 or SF<>OF).
76 cb JNA rel8 Jump short if not above (CF=1 or ZF=1).
72 cb JNAE rel8 Jump short if not above or equal (CF=1).
73 cb JNB rel8 Jump short if not below (CF=0).
77 cb JNBE rel8 Jump short if not below or equal (CF=0 and ZF=0).
73 cb JNC rel8 Jump short if not carry (CF=0).
75 cb JNE rel8 Jump short if not equal (ZF=0).
7E cb JNG rel8 Jump short if not greater (ZF=1 or SF<>OF).
7C cb JNGE rel8 Jump short if not greater or equal (SF<>OF).
7D cb JNL rel8 Jump short if not less (SF=OF).
7F cb JNLE rel8 Jump short if not less or equal (ZF=0 and SF=OF).
71 cb JNO rel8 Jump short if not overflow (OF=0).
7B cb JNP rel8 Jump short if not parity (PF=0).
79 cb JNS rel8 Jump short if not sign (SF=0).
75 cb JNZ rel8 Jump short if not zero (ZF=0).
70 cb JO rel8 Jump short if overflow (OF=1).
7A cb JP rel8 Jump short if parity (PF=1).
7A cb JPE rel8 Jump short if parity even (PF=1).
7B cb JPO rel8 Jump short if parity odd (PF=0).
78 cb JS rel8 Jump short if sign (SF=1).
74 cb JZ rel8 Jump short if zero (ZF = 1).
0F 87 cw/cd JA rel16/32 Jump near if above (CF=0 and ZF=0).
0F 83 cw/cd JAE rel16/32 Jump near if above or equal (CF=0).
0F 82 cw/cd JB rel16/32 Jump near if below (CF=1).
0F 86 cw/cd JBE rel16/32 Jump near if below or equal (CF=1 or ZF=1).
0F 82 cw/cd JC rel16/32 Jump near if carry (CF=1).
0F 84 cw/cd JE rel16/32 Jump near if equal (ZF=1).
0F 84 cw/cd JZ rel16/32 Jump near if 0 (ZF=1).
0F 8F cw/cd JG rel16/32 Jump near if greater (ZF=0 and SF=OF).
0F 8D cw/cd JGE rel16/32 Jump near if greater or equal (SF=OF).
0F 8C cw/cd JL rel16/32 Jump near if less (SF<>OF).
0F 8E cw/cd JLE rel16/32 Jump near if less or equal (ZF=1 or SF<>OF).
0F 86 cw/cd JNA rel16/32 Jump near if not above (CF=1 or ZF=1).
0F 82 cw/cd JNAE rel16/32 Jump near if not above or equal (CF=1).
0F 83 cw/cd JNB rel16/32 Jump near if not below (CF=0).
0F 87 cw/cd JNBE rel16/32 Jump near if not below or equal (CF=0 and ZF=0).
0F 83 cw/cd JNC rel16/32 Jump near if not carry (CF=0).
0F 85 cw/cd JNE rel16/32 Jump near if not equal (ZF=0).
0F 8E cw/cd JNG rel16/32 Jump near if not greater (ZF=1 or SF<>OF).
0F 8C cw/cd JNGE rel16/32 Jump near if not greater or equal (SF<>OF).
0F 8D cw/cd JNL rel16/32 Jump near if not less (SF=OF).
0F 8F cw/cd JNLE rel16/32 Jump near if not less or equal (ZF=0 and SF=OF).
0F 81 cw/cd JNO rel16/32 Jump near if not overflow (OF=0).
0F 8B cw/cd JNP rel16/32 Jump near if not parity (PF=0).
0F 89 cw/cd JNS rel16/32 Jump near if not sign (SF=0).
0F 85 cw/cd JNZ rel16/32 Jump near if not zero (ZF=0).
0F 80 cw/cd JO rel16/32 Jump near if overflow (OF=1).
0F 8A cw/cd JP rel16/32 Jump near if parity (PF=1).
0F 8A cw/cd JPE rel16/32 Jump near if parity even (PF=1).
0F 8B cw/cd JPO rel16/32 Jump near if parity odd (PF=0).
0F 88 cw/cd JS rel16/32 Jump near if sign (SF=1).
0F 84 cw/cd JZ rel16/32 Jump near if 0 (ZF=1).
Description

Checks the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags are in the specified state (condition), performs a jump to the target instruction specified by the destination operand. A condition code (cc) is associated with each instruction to indicate the condition being tested for. If the condition is not satisfied, the jump is not performed and execution continues with the instruction following the Jcc instruction.

The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruction pointer in the EIP register). A relative offset (rel8, rel16, or rel32) is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 8-bit or 32-bit immediate value, which is added to the instruction pointer. Instruction coding is most efficient for offsets of -128 to +127. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared, resulting in a maximum instruction pointer size of 16 bits.

The conditions for each Jcc mnemonic are given in the "{description}" column of the table on the preceding page. The terms "less" and "greater" are used for comparisons of signed integers and the terms "above" and "below" are used for unsigned integers.

Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are defined for some opcodes. For example, the JA (jump if above) instruction and the JNBE (jump if not below or equal) instruction are alternate mnemonics for the opcode 77H.

The Jcc instruction does not support far jumps (jumps to other code segments). When the target for the conditional jump is in a different segment, use the opposite condition from the condition being tested for the Jcc instruction, and then access the target with an unconditional far jump (JMP instruction) to the other segment. For example, the following conditional far jump is illegal: JZ FARLABEL; To accomplish this far jump, use the following two instructions: JNZ BEYOND; JMP FARLABEL; BEYOND: The JECXZ and JCXZ instructions differ from the other Jcc instructions because they do not check the status flags. Instead they check the contents of the ECX and CX registers, respectively, for 0. Either the CX or ECX register is chosen according to the address-size attribute.

These instructions are useful at the beginning of a conditional loop that terminates with a conditional loop instruction (such as LOOPNE). They prevent entering the loop when the ECX or CX register is equal to 0, which would cause the loop to execute 232 or 64K times, respectively, instead of zero times.

All conditional jumps are converted to code fetches of one or two cache lines, regardless of jump address or cacheability.

Operation
if(Condition == true) {
            EIP = EIP + SignExtend(Destination);
            if(OperandSize == 16) EIP = EIP & 0xFFFF;
            else /*OperandSize == 32*/ if(EIP < CS.Base || EIP > CS.Limit) Exception(GP);
            }
            
Flags affected

None.

Protected Mode Exceptions
#GP(0) If the offset being jumped to is beyond the limits of the CS segment.
Real-Address Mode Exceptions
#GP If the offset being jumped to is beyond the limits of the CS segment or is outside of the effective address space from 0 to FFFFH. This condition can occur if a 32-bit address size override prefix is used.
Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode


posted on 2011-03-19 20:24 coreBugZJ 阅读(3892) 评论(1)  编辑 收藏 引用 所属分类: Assemble


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