/* 
(C) OOMusou 2008 http://oomusou.cnblogs.com

Filename    : DE2_NIOS_Lite.v
Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
Description : DE2_NIOS lite version
Release     : 08/08/2008 1.0
*/
module DE2_NIOS_Lite (
  input         CLOCK_50,     // On Board 50 MHz
  input  [3:0]  KEY,          // Pushbutton[3:0]
  input  [17:0] SW,           // Toggle Switch[17:0]
  output [8:0]  LEDG,         // LED Green[8:0]
  output [17:0] LEDR,         // LED Red[17:0]
  output [6:0]  HEX0,         // Seven Segment Digit 0
  output [6:0]  HEX1,         // Seven Segment Digit 1
  output [6:0]  HEX2,         // Seven Segment Digit 2
  output [6:0]  HEX3,         // Seven Segment Digit 3
  output [6:0]  HEX4,         // Seven Segment Digit 4
  output [6:0]  HEX5,         // Seven Segment Digit 5
  output [6:0]  HEX6,         // Seven Segment Digit 6
  output [6:0]  HEX7,         // Seven Segment Digit 7
  inout  [15:0] DRAM_DQ,      // SDRAM Data bus 16 Bits
  output [11:0] DRAM_ADDR,    // SDRAM Address bus 12 Bits
  output        DRAM_LDQM,    // SDRAM Low-byte Data Mask 
  output        DRAM_UDQM,    // SDRAM High-byte Data Mask
  output        DRAM_WE_N,    // SDRAM Write Enable
  output        DRAM_CAS_N,   // SDRAM Column Address Strobe
  output        DRAM_RAS_N,   // SDRAM Row Address Strobe
  output        DRAM_CS_N,    // SDRAM Chip Select
  output        DRAM_BA_0,    // SDRAM Bank Address 0
  output        DRAM_BA_1,    // SDRAM Bank Address 0
  output        DRAM_CLK,     // SDRAM Clock
  output        DRAM_CKE,     // SDRAM Clock Enable
  inout  [7:0]  FL_DQ,        // FLASH Data bus 8 Bits
  output [21:0] FL_ADDR,      // FLASH Address bus 22 Bits
  output        FL_WE_N,      // FLASH Write Enable
  output        FL_RST_N,     // FLASH Reset
  output        FL_OE_N,      // FLASH Output Enable
  output        FL_CE_N,      // FLASH Chip Enable
  inout  [15:0] SRAM_DQ,      // SRAM Data bus 16 Bits
  output [17:0] SRAM_ADDR,    // SRAM Address bus 18 Bits
  output        SRAM_UB_N,    // SRAM Low-byte Data Mask 
  output        SRAM_LB_N,    // SRAM High-byte Data Mask 
  output        SRAM_WE_N,    // SRAM Write Enable
  output        SRAM_CE_N,    // SRAM Chip Enable
  output        SRAM_OE_N     // SRAM Output Enable
);

wire CPU_CLK;
wire CPU_RESET;

assign FL_RST_N = 1'b1;

Reset_Delay u0 (
  .iRST(KEY[0]),
  .iCLK(CLOCK_50),
  .oRESET(CPU_RESET)
);

SDRAM_PLL u1 (
  .inclk0(CLOCK_50),
  .c0(DRAM_CLK),
  .c1(CPU_CLK)
);

nios_ii u2 (
  .clk(CPU_CLK),
  .clk_50(CLOCK_50),
  .reset_n(CPU_RESET),
  // KEY
  .in_port_to_the_key_pio(KEY),
  // SW
  .in_port_to_the_sw_pio(SW),
  // LEDG
  .out_port_from_the_ledg_pio(LEDG),
  // LEDR
  .out_port_from_the_ledr_pio(LEDR),
  // SEG7
  .oSEG0_from_the_seg7(HEX0),
  .oSEG1_from_the_seg7(HEX1),
  .oSEG2_from_the_seg7(HEX2),
  .oSEG3_from_the_seg7(HEX3),
  .oSEG4_from_the_seg7(HEX4),
  .oSEG5_from_the_seg7(HEX5),
  .oSEG6_from_the_seg7(HEX6),
  .oSEG7_from_the_seg7(HEX7),
  // SDRAM
  .zs_addr_from_the_sdram(DRAM_ADDR),
  .zs_ba_from_the_sdram({DRAM_BA_1,DRAM_BA_0}),
  .zs_cas_n_from_the_sdram(DRAM_CAS_N),
  .zs_cke_from_the_sdram(DRAM_CKE),
  .zs_cs_n_from_the_sdram(DRAM_CS_N),
  .zs_dq_to_and_from_the_sdram(DRAM_DQ),
  .zs_dqm_from_the_sdram({DRAM_UDQM,DRAM_LDQM}),
  .zs_ras_n_from_the_sdram(DRAM_RAS_N),
  .zs_we_n_from_the_sdram(DRAM_WE_N),
  // SRAM
  .SRAM_ADDR_from_the_sram(SRAM_ADDR),
  .SRAM_CE_N_from_the_sram(SRAM_CE_N),
  .SRAM_DQ_to_and_from_the_sram(SRAM_DQ),
  .SRAM_LB_N_from_the_sram(SRAM_LB_N),
  .SRAM_OE_N_from_the_sram(SRAM_OE_N),
  .SRAM_UB_N_from_the_sram(SRAM_UB_N),
  .SRAM_WE_N_from_the_sram(SRAM_WE_N),
  // FLASH
  .address_to_the_cfi_flash(FL_ADDR),
  .data_to_and_from_the_cfi_flash(FL_DQ),
  .read_n_to_the_cfi_flash(FL_OE_N),
  .select_n_to_the_cfi_flash(FL_CE_N),
  .write_n_to_the_cfi_flash(FL_WE_N)
);

endmodule