Analysis & Synthesis report for DE2_NIOS_Lite
Sat Aug 23 09:39:35 2008
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Analysis & Synthesis DSP Block Usage Summary
  9. State Machine - |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_next
 10. State Machine - |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state
 11. State Machine - |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_next
 12. State Machine - |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state
 13. State Machine - |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state
 14. State Machine - |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state
 15. State Machine - |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state
 16. State Machine - |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state
 17. State Machine - |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize
 18. Registers Protected by Synthesis
 19. Logic Cells Representing Combinational Loops
 20. Registers Removed During Synthesis
 21. Removed Registers Triggering Further Register Optimizations
 22. General Register Statistics
 23. Inverted Register Statistics
 24. Multiplexer Restructuring Statistics (Restructuring Performed)
 25. Source assignments for nios_ii:u2|clock_0:the_clock_0
 26. Source assignments for nios_ii:u2|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync
 27. Source assignments for nios_ii:u2|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync
 28. Source assignments for nios_ii:u2|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync
 29. Source assignments for nios_ii:u2|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync
 30. Source assignments for nios_ii:u2|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe
 31. Source assignments for nios_ii:u2|clock_1:the_clock_1
 32. Source assignments for nios_ii:u2|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync
 33. Source assignments for nios_ii:u2|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync
 34. Source assignments for nios_ii:u2|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync
 35. Source assignments for nios_ii:u2|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync
 36. Source assignments for nios_ii:u2|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe
 37. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qed1:auto_generated
 38. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_u0g1:auto_generated
 39. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_pkf1:auto_generated
 40. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_p2f1:auto_generated
 41. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_q2f1:auto_generated
 42. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_j9f1:auto_generated
 43. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram|altsyncram_29f1:auto_generated
 44. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_9vc1:auto_generated
 45. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
 46. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
 47. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_t072:auto_generated
 48. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated
 49. Source assignments for nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1
 50. Source assignments for nios_ii:u2|jtag_uart:the_jtag_uart
 51. Source assignments for nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
 52. Source assignments for nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
 53. Source assignments for nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated
 54. Source assignments for nios_ii:u2|sdram:the_sdram
 55. Source assignments for nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave
 56. Source assignments for nios_ii:u2|nios_ii_reset_clk_domain_synch_module:nios_ii_reset_clk_domain_synch
 57. Source assignments for nios_ii:u2|nios_ii_reset_clk_50_domain_synch_module:nios_ii_reset_clk_50_domain_synch
 58. Source assignments for sld_hub:sld_hub_inst
 59. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 60. Parameter Settings for User Entity Instance: SDRAM_PLL:u1|altpll:altpll_component
 61. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data
 62. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram
 63. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag
 64. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram
 65. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht
 66. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram
 67. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a
 68. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram
 69. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b
 70. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram
 71. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag
 72. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram
 73. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data
 74. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram
 75. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim
 76. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram
 77. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1
 78. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2
 79. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component
 80. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 81. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component
 82. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 83. Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1
 84. Parameter Settings for User Entity Instance: nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
 85. Parameter Settings for User Entity Instance: nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
 86. Parameter Settings for User Entity Instance: nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
 87. Parameter Settings for User Entity Instance: nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram
 88. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 89. altmult_add Parameter Settings by Entity Instance
 90. scfifo Parameter Settings by Entity Instance
 91. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sat Aug 23 09:39:35 2008         ;
; Quartus II Version                 ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
; Revision Name                      ; DE2_NIOS_Lite                                 ;
; Top-level Entity Name              ; DE2_NIOS_Lite                                 ;
; Family                             ; Cyclone II                                    ;
; Total logic elements               ; 3,828                                         ;
;     Total combinational functions  ; 3,828                                         ;
;     Dedicated logic registers      ; 2,742                                         ;
; Total registers                    ; 2742                                          ;
; Total pins                         ; 221                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 392,576                                       ;
; Embedded Multiplier 9-bit elements ; 4                                             ;
; Total PLLs                         ; 1                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                          ; DE2_NIOS_Lite      ; DE2_NIOS_Lite      ;
; Family name                                                                    ; Cyclone II         ; Stratix II         ;
; Use Generated Physical Constraints File                                        ; Off                ;                    ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone II/Cyclone III                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                 ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                       ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------+
; DE2_NIOS_Lite.v                  ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/DE2_NIOS_Lite.v                     ;
; Reset_Delay.v                    ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/Reset_Delay.v                       ;
; SDRAM_PLL.v                      ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/SDRAM_PLL.v                         ;
; altpll.tdf                       ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altpll.tdf            ;
; aglobal72.inc                    ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/aglobal72.inc         ;
; stratix_pll.inc                  ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/stratix_pll.inc       ;
; stratixii_pll.inc                ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/stratixii_pll.inc     ;
; cycloneii_pll.inc                ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/cycloneii_pll.inc     ;
; nios_ii.v                        ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/nios_ii.v                           ;
; clock_0.v                        ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/clock_0.v                           ;
; clock_1.v                        ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/clock_1.v                           ;
; cpu.v                            ; yes             ; Encrypted File               ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu.v                               ;
; cpu_test_bench.v                 ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu_test_bench.v                    ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/lpm_decode.inc        ;
; a_rdenreg.inc                    ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_qed1.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_qed1.tdf              ;
; db/altsyncram_u0g1.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_u0g1.tdf              ;
; cpu_ic_tag_ram.mif               ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu_ic_tag_ram.mif                  ;
; db/altsyncram_pkf1.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_pkf1.tdf              ;
; cpu_bht_ram.mif                  ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu_bht_ram.mif                     ;
; db/altsyncram_p2f1.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_p2f1.tdf              ;
; cpu_rf_ram_a.mif                 ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu_rf_ram_a.mif                    ;
; db/altsyncram_q2f1.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_q2f1.tdf              ;
; cpu_rf_ram_b.mif                 ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu_rf_ram_b.mif                    ;
; db/altsyncram_j9f1.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_j9f1.tdf              ;
; cpu_dc_tag_ram.mif               ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu_dc_tag_ram.mif                  ;
; db/altsyncram_29f1.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_29f1.tdf              ;
; db/altsyncram_9vc1.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_9vc1.tdf              ;
; cpu_mult_cell.v                  ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu_mult_cell.v                     ;
; altmult_add.tdf                  ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altmult_add.tdf       ;
; stratix_mac_mult.inc             ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/stratix_mac_mult.inc  ;
; stratix_mac_out.inc              ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/stratix_mac_out.inc   ;
; db/mult_add_4cr2.tdf             ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/mult_add_4cr2.tdf                ;
; db/ded_mult_2o81.tdf             ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/ded_mult_2o81.tdf                ;
; db/dffpipe_93c.tdf               ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/dffpipe_93c.tdf                  ;
; db/mult_add_6cr2.tdf             ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/mult_add_6cr2.tdf                ;
; db/altsyncram_t072.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_t072.tdf              ;
; cpu_ociram_default_contents.mif  ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu_ociram_default_contents.mif     ;
; db/altsyncram_e502.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_e502.tdf              ;
; cpu_jtag_debug_module_wrapper.v  ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu_jtag_debug_module_wrapper.v     ;
; cpu_jtag_debug_module.v          ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/cpu_jtag_debug_module.v             ;
; jtag_uart.v                      ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/jtag_uart.v                         ;
; scfifo.tdf                       ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/scfifo.tdf            ;
; a_regfifo.inc                    ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/a_regfifo.inc         ;
; a_dpfifo.inc                     ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/a_dpfifo.inc          ;
; a_i2fifo.inc                     ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/a_i2fifo.inc          ;
; a_fffifo.inc                     ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/a_fffifo.inc          ;
; a_f2fifo.inc                     ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/a_f2fifo.inc          ;
; db/scfifo_1n21.tdf               ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/scfifo_1n21.tdf                  ;
; db/a_dpfifo_8t21.tdf             ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/a_dpfifo_8t21.tdf                ;
; db/a_fefifo_7cf.tdf              ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/a_fefifo_7cf.tdf                 ;
; db/cntr_rj7.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/cntr_rj7.tdf                     ;
; db/dpram_5h21.tdf                ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/dpram_5h21.tdf                   ;
; db/altsyncram_9tl1.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_9tl1.tdf              ;
; db/cntr_fjb.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/cntr_fjb.tdf                     ;
; alt_jtag_atlantic.v              ; yes             ; Encrypted Megafunction       ; c:/altera/72/quartus/libraries/megafunctions/alt_jtag_atlantic.v   ;
; key_pio.v                        ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/key_pio.v                           ;
; ledg_pio.v                       ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/ledg_pio.v                          ;
; ledr_pio.v                       ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/ledr_pio.v                          ;
; onchip_mem.v                     ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.v                        ;
; db/altsyncram_olb1.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/altsyncram_olb1.tdf              ;
; onchip_mem.hex                   ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex                      ;
; db/decode_3oa.tdf                ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/decode_3oa.tdf                   ;
; db/mux_0kb.tdf                   ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/mux_0kb.tdf                      ;
; sdram.v                          ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/sdram.v                             ;
; seg7.v                           ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/seg7.v                              ;
; SEG7_LUT_8.v                     ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/SEG7_LUT_8.v                        ;
; SEG7_LUT.v                       ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/SEG7_LUT.v                          ;
; sram.v                           ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/sram.v                              ;
; SRAM_16Bit_512K.v                ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/SRAM_16Bit_512K.v                   ;
; sw_pio.v                         ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/sw_pio.v                            ;
; sysid.v                          ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/sysid.v                             ;
; timer.v                          ; yes             ; Other                        ; D:/0Clare/DE2/DE2_NIOS_Lite_11/timer.v                             ;
; sld_hub.vhd                      ; yes             ; Encrypted Megafunction       ; c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd           ;
; lpm_shiftreg.tdf                 ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/lpm_shiftreg.tdf      ;
; lpm_constant.inc                 ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/lpm_constant.inc      ;
; dffeea.inc                       ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/dffeea.inc            ;
; lpm_decode.tdf                   ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/lpm_decode.tdf        ;
; declut.inc                       ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/declut.inc            ;
; altshift.inc                     ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altshift.inc          ;
; lpm_compare.inc                  ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/lpm_compare.inc       ;
; db/decode_aoi.tdf                ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_NIOS_Lite_11/db/decode_aoi.tdf                   ;
; sld_dffex.vhd                    ; yes             ; Encrypted Megafunction       ; c:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd         ;
; sld_rom_sr.vhd                   ; yes             ; Encrypted Megafunction       ; c:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd        ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------+


+------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                              ;
+---------------------------------------------+--------------------------------------------+
; Resource                                    ; Usage                                      ;
+---------------------------------------------+--------------------------------------------+
; Estimated Total logic elements              ; 3,828                                      ;
;                                             ;                                            ;
; Total combinational functions               ; 3828                                       ;
; Logic element usage by number of LUT inputs ;                                            ;
;     -- 4 input functions                    ; 1996                                       ;
;     -- 3 input functions                    ; 1320                                       ;
;     -- <=2 input functions                  ; 512                                        ;
;                                             ;                                            ;
; Logic elements by mode                      ;                                            ;
;     -- normal mode                          ; 3540                                       ;
;     -- arithmetic mode                      ; 288                                        ;
;                                             ;                                            ;
; Total registers                             ; 2742                                       ;
;     -- Dedicated logic registers            ; 2742                                       ;
;     -- I/O registers                        ; 0                                          ;
;                                             ;                                            ;
; I/O pins                                    ; 221                                        ;
; Total memory bits                           ; 392576                                     ;
; Embedded Multiplier 9-bit elements          ; 4                                          ;
; Total PLLs                                  ; 1                                          ;
; Maximum fan-out node                        ; SDRAM_PLL:u1|altpll:altpll_component|_clk0 ;
; Maximum fan-out                             ; 2447                                       ;
; Total fan-out                               ; 29461                                      ;
; Average fan-out                             ; 4.13                                       ;
+---------------------------------------------+--------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+---------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                  ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                             ; Library Name ;
+---------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |DE2_NIOS_Lite                                                                              ; 3828 (2)          ; 2742 (0)     ; 392576      ; 4            ; 0       ; 2         ; 221  ; 0            ; |DE2_NIOS_Lite                                                                                                                                                                                                                                  ; work         ;
;    |Reset_Delay:u0|                                                                         ; 33 (33)           ; 25 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|Reset_Delay:u0                                                                                                                                                                                                                   ; work         ;
;    |SDRAM_PLL:u1|                                                                           ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|SDRAM_PLL:u1                                                                                                                                                                                                                     ; work         ;
;       |altpll:altpll_component|                                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|SDRAM_PLL:u1|altpll:altpll_component                                                                                                                                                                                             ; work         ;
;    |nios_ii:u2|                                                                             ; 3686 (1)          ; 2635 (0)     ; 392576      ; 4            ; 0       ; 2         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2                                                                                                                                                                                                                       ; work         ;
;       |clock_0:the_clock_0|                                                                 ; 34 (17)           ; 130 (112)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0                                                                                                                                                                                                   ; work         ;
;          |clock_0_edge_to_pulse:read_done_edge_to_pulse|                                    ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                                     ; work         ;
;          |clock_0_edge_to_pulse:read_request_edge_to_pulse|                                 ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                                  ; work         ;
;          |clock_0_edge_to_pulse:write_request_edge_to_pulse|                                ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                                 ; work         ;
;          |clock_0_master_FSM:master_FSM|                                                    ; 8 (8)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM                                                                                                                                                                     ; work         ;
;          |clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|               ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync                                                                                                                                ; work         ;
;          |clock_0_slave_FSM:slave_FSM|                                                      ; 6 (6)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM                                                                                                                                                                       ; work         ;
;          |clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|           ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync                                                                                                                            ; work         ;
;          |clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|         ; 1 (1)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync                                                                                                                          ; work         ;
;       |clock_0_in_arbitrator:the_clock_0_in|                                                ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0_in_arbitrator:the_clock_0_in                                                                                                                                                                                  ; work         ;
;       |clock_0_out_arbitrator:the_clock_0_out|                                              ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_0_out_arbitrator:the_clock_0_out                                                                                                                                                                                ; work         ;
;       |clock_1:the_clock_1|                                                                 ; 24 (1)            ; 136 (112)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1                                                                                                                                                                                                   ; work         ;
;          |clock_1_edge_to_pulse:read_done_edge_to_pulse|                                    ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                                     ; work         ;
;          |clock_1_edge_to_pulse:read_request_edge_to_pulse|                                 ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                                  ; work         ;
;          |clock_1_edge_to_pulse:write_done_edge_to_pulse|                                   ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_edge_to_pulse:write_done_edge_to_pulse                                                                                                                                                    ; work         ;
;          |clock_1_edge_to_pulse:write_request_edge_to_pulse|                                ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                                 ; work         ;
;          |clock_1_master_FSM:master_FSM|                                                    ; 9 (9)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM                                                                                                                                                                     ; work         ;
;          |clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|               ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync                                                                                                                                ; work         ;
;          |clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|             ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync                                                                                                                              ; work         ;
;          |clock_1_slave_FSM:slave_FSM|                                                      ; 12 (12)           ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM                                                                                                                                                                       ; work         ;
;          |clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|           ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync                                                                                                                            ; work         ;
;          |clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|         ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync                                                                                                                          ; work         ;
;       |clock_1_in_arbitrator:the_clock_1_in|                                                ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1_in_arbitrator:the_clock_1_in                                                                                                                                                                                  ; work         ;
;       |clock_1_out_arbitrator:the_clock_1_out|                                              ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|clock_1_out_arbitrator:the_clock_1_out                                                                                                                                                                                ; work         ;
;       |cpu:the_cpu|                                                                         ; 2085 (1853)       ; 1582 (1406)  ; 63872       ; 4            ; 0       ; 2         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu                                                                                                                                                                                                           ; work         ;
;          |cpu_bht_module:cpu_bht|                                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht                                                                                                                                                                                    ; work         ;
;             |altsyncram:the_altsyncram|                                                     ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram                                                                                                                                                          ; work         ;
;                |altsyncram_pkf1:auto_generated|                                             ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_pkf1:auto_generated                                                                                                                           ; work         ;
;          |cpu_dc_data_module:cpu_dc_data|                                                   ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data                                                                                                                                                                            ; work         ;
;             |altsyncram:the_altsyncram|                                                     ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram                                                                                                                                                  ; work         ;
;                |altsyncram_29f1:auto_generated|                                             ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram|altsyncram_29f1:auto_generated                                                                                                                   ; work         ;
;          |cpu_dc_tag_module:cpu_dc_tag|                                                     ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag                                                                                                                                                                              ; work         ;
;             |altsyncram:the_altsyncram|                                                     ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram                                                                                                                                                    ; work         ;
;                |altsyncram_j9f1:auto_generated|                                             ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_j9f1:auto_generated                                                                                                                     ; work         ;
;          |cpu_dc_victim_module:cpu_dc_victim|                                               ; 0 (0)             ; 0 (0)        ; 256         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim                                                                                                                                                                        ; work         ;
;             |altsyncram:the_altsyncram|                                                     ; 0 (0)             ; 0 (0)        ; 256         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram                                                                                                                                              ; work         ;
;                |altsyncram_9vc1:auto_generated|                                             ; 0 (0)             ; 0 (0)        ; 256         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_9vc1:auto_generated                                                                                                               ; work         ;
;          |cpu_ic_data_module:cpu_ic_data|                                                   ; 0 (0)             ; 0 (0)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data                                                                                                                                                                            ; work         ;
;             |altsyncram:the_altsyncram|                                                     ; 0 (0)             ; 0 (0)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram                                                                                                                                                  ; work         ;
;                |altsyncram_qed1:auto_generated|                                             ; 0 (0)             ; 0 (0)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qed1:auto_generated                                                                                                                   ; work         ;
;          |cpu_ic_tag_module:cpu_ic_tag|                                                     ; 0 (0)             ; 0 (0)        ; 2688        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag                                                                                                                                                                              ; work         ;
;             |altsyncram:the_altsyncram|                                                     ; 0 (0)             ; 0 (0)        ; 2688        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram                                                                                                                                                    ; work         ;
;                |altsyncram_u0g1:auto_generated|                                             ; 0 (0)             ; 0 (0)        ; 2688        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_u0g1:auto_generated                                                                                                                     ; work         ;
;          |cpu_mult_cell:the_cpu_mult_cell|                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 4            ; 0       ; 2         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell                                                                                                                                                                           ; work         ;
;             |altmult_add:the_altmult_add_part_1|                                            ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1                                                                                                                                        ; work         ;
;                |mult_add_4cr2:auto_generated|                                               ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated                                                                                                           ; work         ;
;                   |ded_mult_2o81:ded_mult1|                                                 ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1                                                                                   ; work         ;
;             |altmult_add:the_altmult_add_part_2|                                            ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2                                                                                                                                        ; work         ;
;                |mult_add_6cr2:auto_generated|                                               ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated                                                                                                           ; work         ;
;                   |ded_mult_2o81:ded_mult1|                                                 ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1                                                                                   ; work         ;
;          |cpu_nios2_oci:the_cpu_nios2_oci|                                                  ; 221 (9)           ; 176 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci                                                                                                                                                                           ; work         ;
;             |cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|               ; 104 (0)           ; 90 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper                                                                                                           ; work         ;
;                |cpu_jtag_debug_module:the_cpu_jtag_debug_module1|                           ; 104 (104)         ; 90 (90)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1                                                          ; work         ;
;             |cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|                                 ; 11 (11)           ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg                                                                                                                             ; work         ;
;             |cpu_nios2_oci_break:the_cpu_nios2_oci_break|                                   ; 33 (33)           ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break                                                                                                                               ; work         ;
;             |cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|                                   ; 11 (11)           ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug                                                                                                                               ; work         ;
;             |cpu_nios2_ocimem:the_cpu_nios2_ocimem|                                         ; 53 (53)           ; 44 (44)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem                                                                                                                                     ; work         ;
;                |cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component| ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component                                                          ; work         ;
;                   |altsyncram:the_altsyncram|                                               ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram                                ; work         ;
;                      |altsyncram_t072:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_t072:auto_generated ; work         ;
;          |cpu_register_bank_a_module:cpu_register_bank_a|                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a                                                                                                                                                            ; work         ;
;             |altsyncram:the_altsyncram|                                                     ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram                                                                                                                                  ; work         ;
;                |altsyncram_p2f1:auto_generated|                                             ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_p2f1:auto_generated                                                                                                   ; work         ;
;          |cpu_register_bank_b_module:cpu_register_bank_b|                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b                                                                                                                                                            ; work         ;
;             |altsyncram:the_altsyncram|                                                     ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram                                                                                                                                  ; work         ;
;                |altsyncram_q2f1:auto_generated|                                             ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_q2f1:auto_generated                                                                                                   ; work         ;
;          |cpu_test_bench:the_cpu_test_bench|                                                ; 11 (11)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench                                                                                                                                                                         ; work         ;
;       |cpu_data_master_arbitrator:the_cpu_data_master|                                      ; 302 (302)         ; 47 (47)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu_data_master_arbitrator:the_cpu_data_master                                                                                                                                                                        ; work         ;
;       |cpu_instruction_master_arbitrator:the_cpu_instruction_master|                        ; 166 (166)         ; 47 (47)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu_instruction_master_arbitrator:the_cpu_instruction_master                                                                                                                                                          ; work         ;
;       |cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|                          ; 49 (49)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module                                                                                                                                                            ; work         ;
;       |jtag_uart:the_jtag_uart|                                                             ; 143 (42)          ; 107 (13)     ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart                                                                                                                                                                                               ; work         ;
;          |alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|                                    ; 51 (51)           ; 54 (54)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic                                                                                                                                                 ; work         ;
;          |jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r                                                                                                                                                     ; work         ;
;             |scfifo:rfifo|                                                                  ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo                                                                                                                                        ; work         ;
;                |scfifo_1n21:auto_generated|                                                 ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated                                                                                                             ; work         ;
;                   |a_dpfifo_8t21:dpfifo|                                                    ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo                                                                                        ; work         ;
;                      |a_fefifo_7cf:fifo_state|                                              ; 13 (7)            ; 8 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state                                                                ; work         ;
;                         |cntr_rj7:count_usedw|                                              ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw                                           ; work         ;
;                      |cntr_fjb:rd_ptr_count|                                                ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:rd_ptr_count                                                                  ; work         ;
;                      |cntr_fjb:wr_ptr|                                                      ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:wr_ptr                                                                        ; work         ;
;                      |dpram_5h21:FIFOram|                                                   ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram                                                                     ; work         ;
;                         |altsyncram_9tl1:altsyncram2|                                       ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2                                         ; work         ;
;          |jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w                                                                                                                                                     ; work         ;
;             |scfifo:wfifo|                                                                  ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo                                                                                                                                        ; work         ;
;                |scfifo_1n21:auto_generated|                                                 ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated                                                                                                             ; work         ;
;                   |a_dpfifo_8t21:dpfifo|                                                    ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo                                                                                        ; work         ;
;                      |a_fefifo_7cf:fifo_state|                                              ; 13 (7)            ; 8 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state                                                                ; work         ;
;                         |cntr_rj7:count_usedw|                                              ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw                                           ; work         ;
;                      |cntr_fjb:rd_ptr_count|                                                ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:rd_ptr_count                                                                  ; work         ;
;                      |cntr_fjb:wr_ptr|                                                      ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:wr_ptr                                                                        ; work         ;
;                      |dpram_5h21:FIFOram|                                                   ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram                                                                     ; work         ;
;                         |altsyncram_9tl1:altsyncram2|                                       ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2                                         ; work         ;
;       |jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|              ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave                                                                                                                                                ; work         ;
;       |key_pio:the_key_pio|                                                                 ; 4 (4)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|key_pio:the_key_pio                                                                                                                                                                                                   ; work         ;
;       |key_pio_s1_arbitrator:the_key_pio_s1|                                                ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|key_pio_s1_arbitrator:the_key_pio_s1                                                                                                                                                                                  ; work         ;
;       |ledg_pio:the_ledg_pio|                                                               ; 1 (1)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|ledg_pio:the_ledg_pio                                                                                                                                                                                                 ; work         ;
;       |ledg_pio_s1_arbitrator:the_ledg_pio_s1|                                              ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|ledg_pio_s1_arbitrator:the_ledg_pio_s1                                                                                                                                                                                ; work         ;
;       |ledr_pio:the_ledr_pio|                                                               ; 1 (1)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|ledr_pio:the_ledr_pio                                                                                                                                                                                                 ; work         ;
;       |ledr_pio_s1_arbitrator:the_ledr_pio_s1|                                              ; 3 (3)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|ledr_pio_s1_arbitrator:the_ledr_pio_s1                                                                                                                                                                                ; work         ;
;       |nios_ii_reset_clk_50_domain_synch_module:nios_ii_reset_clk_50_domain_synch|          ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|nios_ii_reset_clk_50_domain_synch_module:nios_ii_reset_clk_50_domain_synch                                                                                                                                            ; work         ;
;       |nios_ii_reset_clk_domain_synch_module:nios_ii_reset_clk_domain_synch|                ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|nios_ii_reset_clk_domain_synch_module:nios_ii_reset_clk_domain_synch                                                                                                                                                  ; work         ;
;       |onchip_mem:the_onchip_mem|                                                           ; 70 (0)            ; 2 (0)        ; 327680      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|onchip_mem:the_onchip_mem                                                                                                                                                                                             ; work         ;
;          |altsyncram:the_altsyncram|                                                        ; 70 (0)            ; 2 (0)        ; 327680      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram                                                                                                                                                                   ; work         ;
;             |altsyncram_olb1:auto_generated|                                                ; 70 (0)            ; 2 (2)        ; 327680      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated                                                                                                                                    ; work         ;
;                |decode_3oa:decode3|                                                         ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated|decode_3oa:decode3                                                                                                                 ; work         ;
;                |decode_3oa:deep_decode|                                                     ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated|decode_3oa:deep_decode                                                                                                             ; work         ;
;                |mux_0kb:mux2|                                                               ; 64 (64)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated|mux_0kb:mux2                                                                                                                       ; work         ;
;       |onchip_mem_s1_arbitrator:the_onchip_mem_s1|                                          ; 52 (52)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1                                                                                                                                                                            ; work         ;
;       |sdram:the_sdram|                                                                     ; 263 (213)         ; 238 (152)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram                                                                                                                                                                                                       ; work         ;
;          |sdram_input_efifo_module:the_sdram_input_efifo_module|                            ; 50 (50)           ; 86 (86)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module                                                                                                                                                 ; work         ;
;       |sdram_s1_arbitrator:the_sdram_s1|                                                    ; 102 (52)          ; 34 (3)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1                                                                                                                                                                                      ; work         ;
;          |rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1| ; 25 (25)           ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1                                                                                                     ; work         ;
;          |rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1| ; 25 (25)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1                                                                                                     ; work         ;
;       |seg7:the_seg7|                                                                       ; 56 (0)            ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7:the_seg7                                                                                                                                                                                                         ; work         ;
;          |SEG7_LUT_8:the_SEG7_LUT_8|                                                        ; 56 (0)            ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8                                                                                                                                                                               ; work         ;
;             |SEG7_LUT:u0|                                                                   ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u0                                                                                                                                                                   ; work         ;
;             |SEG7_LUT:u1|                                                                   ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u1                                                                                                                                                                   ; work         ;
;             |SEG7_LUT:u2|                                                                   ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u2                                                                                                                                                                   ; work         ;
;             |SEG7_LUT:u3|                                                                   ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u3                                                                                                                                                                   ; work         ;
;             |SEG7_LUT:u4|                                                                   ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u4                                                                                                                                                                   ; work         ;
;             |SEG7_LUT:u5|                                                                   ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u5                                                                                                                                                                   ; work         ;
;             |SEG7_LUT:u6|                                                                   ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u6                                                                                                                                                                   ; work         ;
;             |SEG7_LUT:u7|                                                                   ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u7                                                                                                                                                                   ; work         ;
;       |seg7_avalon_slave_0_arbitrator:the_seg7_avalon_slave_0|                              ; 3 (3)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|seg7_avalon_slave_0_arbitrator:the_seg7_avalon_slave_0                                                                                                                                                                ; work         ;
;       |sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0|                              ; 74 (74)           ; 15 (15)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0                                                                                                                                                                ; work         ;
;       |sw_pio:the_sw_pio|                                                                   ; 18 (18)           ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|sw_pio:the_sw_pio                                                                                                                                                                                                     ; work         ;
;       |sw_pio_s1_arbitrator:the_sw_pio_s1|                                                  ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|sw_pio_s1_arbitrator:the_sw_pio_s1                                                                                                                                                                                    ; work         ;
;       |sysid_control_slave_arbitrator:the_sysid_control_slave|                              ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|sysid_control_slave_arbitrator:the_sysid_control_slave                                                                                                                                                                ; work         ;
;       |timer:the_timer|                                                                     ; 130 (130)         ; 120 (120)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|timer:the_timer                                                                                                                                                                                                       ; work         ;
;       |timer_s1_arbitrator:the_timer_s1|                                                    ; 6 (6)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|timer_s1_arbitrator:the_timer_s1                                                                                                                                                                                      ; work         ;
;       |tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|            ; 80 (80)           ; 63 (63)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave                                                                                                                                              ; work         ;
;    |sld_hub:sld_hub_inst|                                                                   ; 107 (48)          ; 82 (7)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst                                                                                                                                                                                                             ; work         ;
;       |lpm_decode:instruction_decoder|                                                      ; 5 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder                                                                                                                                                                              ; work         ;
;          |decode_aoi:auto_generated|                                                        ; 5 (5)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated                                                                                                                                                    ; work         ;
;       |lpm_shiftreg:jtag_ir_register|                                                       ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register                                                                                                                                                                               ; work         ;
;       |sld_dffex:BROADCAST|                                                                 ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_dffex:BROADCAST                                                                                                                                                                                         ; work         ;
;       |sld_dffex:IRF_ENA_0|                                                                 ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0                                                                                                                                                                                         ; work         ;
;       |sld_dffex:IRF_ENA|                                                                   ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA                                                                                                                                                                                           ; work         ;
;       |sld_dffex:IRSR|                                                                      ; 6 (6)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_dffex:IRSR                                                                                                                                                                                              ; work         ;
;       |sld_dffex:RESET|                                                                     ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_dffex:RESET                                                                                                                                                                                             ; work         ;
;       |sld_dffex:\GEN_IRF:1:IRF|                                                            ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF                                                                                                                                                                                    ; work         ;
;       |sld_dffex:\GEN_IRF:2:IRF|                                                            ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF                                                                                                                                                                                    ; work         ;
;       |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|                                                   ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF                                                                                                                                                                           ; work         ;
;       |sld_dffex:\GEN_SHADOW_IRF:2:S_IRF|                                                   ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF                                                                                                                                                                           ; work         ;
;       |sld_jtag_state_machine:jtag_state_machine|                                           ; 20 (20)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine                                                                                                                                                                   ; work         ;
;       |sld_rom_sr:HUB_INFO_REG|                                                             ; 24 (24)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG                                                                                                                                                                                     ; work         ;
+---------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                                             ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+---------------------------------+
; Name                                                                                                                                                                                                                                        ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF                             ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+---------------------------------+
; nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_pkf1:auto_generated|ALTSYNCRAM                                                                                                                           ; AUTO ; Simple Dual Port ; 256          ; 2            ; 256          ; 2            ; 512    ; cpu_bht_ram.mif                 ;
; nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram|altsyncram_29f1:auto_generated|ALTSYNCRAM                                                                                                                   ; AUTO ; Simple Dual Port ; 512          ; 32           ; 512          ; 32           ; 16384  ; None                            ;
; nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_j9f1:auto_generated|ALTSYNCRAM                                                                                                                     ; AUTO ; Simple Dual Port ; 64           ; 16           ; 64           ; 16           ; 1024   ; cpu_dc_tag_ram.mif              ;
; nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_9vc1:auto_generated|ALTSYNCRAM                                                                                                               ; AUTO ; Simple Dual Port ; 8            ; 32           ; 8            ; 32           ; 256    ; None                            ;
; nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qed1:auto_generated|ALTSYNCRAM                                                                                                                   ; AUTO ; Simple Dual Port ; 1024         ; 32           ; 1024         ; 32           ; 32768  ; None                            ;
; nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_u0g1:auto_generated|ALTSYNCRAM                                                                                                                     ; AUTO ; Simple Dual Port ; 128          ; 21           ; 128          ; 21           ; 2688   ; cpu_ic_tag_ram.mif              ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_t072:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port   ; 256          ; 32           ; 256          ; 32           ; 8192   ; cpu_ociram_default_contents.mif ;
; nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_p2f1:auto_generated|ALTSYNCRAM                                                                                                   ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024   ; cpu_rf_ram_a.mif                ;
; nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_q2f1:auto_generated|ALTSYNCRAM                                                                                                   ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024   ; cpu_rf_ram_b.mif                ;
; nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2|ALTSYNCRAM                                         ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512    ; None                            ;
; nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2|ALTSYNCRAM                                         ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512    ; None                            ;
; nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated|ALTSYNCRAM                                                                                                                                    ; AUTO ; Single Port      ; 10240        ; 32           ; --           ; --           ; 327680 ; onchip_mem.hex                  ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+---------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 2           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 4           ;
; Signed Embedded Multipliers           ; 0           ;
; Unsigned Embedded Multipliers         ; 2           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_next                             ;
+------------------+------------------+------------------+------------------+------------------+
; Name             ; m_next.010000000 ; m_next.000010000 ; m_next.000001000 ; m_next.000000001 ;
+------------------+------------------+------------------+------------------+------------------+
; m_next.000000001 ; 0                ; 0                ; 0                ; 0                ;
; m_next.000001000 ; 0                ; 0                ; 1                ; 1                ;
; m_next.000010000 ; 0                ; 1                ; 0                ; 1                ;
; m_next.010000000 ; 1                ; 0                ; 0                ; 1                ;
+------------------+------------------+------------------+------------------+------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state                                                                                                                                     ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; m_state.100000000 ; m_state.010000000 ; m_state.001000000 ; m_state.000100000 ; m_state.000010000 ; m_state.000001000 ; m_state.000000100 ; m_state.000000010 ; m_state.000000001 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; m_state.000000001 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; m_state.000000010 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; m_state.000000100 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; m_state.000001000 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; m_state.000010000 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.000100000 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.001000000 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.010000000 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.100000000 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------+
; State Machine - |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_next ;
+------------+------------+------------+------------+--------------+
; Name       ; i_next.111 ; i_next.101 ; i_next.010 ; i_next.000   ;
+------------+------------+------------+------------+--------------+
; i_next.000 ; 0          ; 0          ; 0          ; 0            ;
; i_next.010 ; 0          ; 0          ; 1          ; 1            ;
; i_next.101 ; 0          ; 1          ; 0          ; 1            ;
; i_next.111 ; 1          ; 0          ; 0          ; 1            ;
+------------+------------+------------+------------+--------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state                               ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; Name        ; i_state.111 ; i_state.101 ; i_state.011 ; i_state.010 ; i_state.001 ; i_state.000 ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; i_state.000 ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ;
; i_state.001 ; 0           ; 0           ; 0           ; 0           ; 1           ; 1           ;
; i_state.010 ; 0           ; 0           ; 0           ; 1           ; 0           ; 1           ;
; i_state.011 ; 0           ; 0           ; 1           ; 0           ; 0           ; 1           ;
; i_state.101 ; 0           ; 1           ; 0           ; 0           ; 0           ; 1           ;
; i_state.111 ; 1           ; 0           ; 0           ; 0           ; 0           ; 1           ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state ;
+------------------+------------------+------------------+-------------------------------------------------+
; Name             ; master_state.100 ; master_state.010 ; master_state.001                                ;
+------------------+------------------+------------------+-------------------------------------------------+
; master_state.001 ; 0                ; 0                ; 0                                               ;
; master_state.010 ; 0                ; 1                ; 1                                               ;
; master_state.100 ; 1                ; 0                ; 1                                               ;
+------------------+------------------+------------------+-------------------------------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state ;
+-----------------+-----------------+-----------------+-------------------------------------------------+
; Name            ; slave_state.100 ; slave_state.010 ; slave_state.001                                 ;
+-----------------+-----------------+-----------------+-------------------------------------------------+
; slave_state.001 ; 0               ; 0               ; 0                                               ;
; slave_state.010 ; 0               ; 1               ; 1                                               ;
; slave_state.100 ; 1               ; 0               ; 1                                               ;
+-----------------+-----------------+-----------------+-------------------------------------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state ;
+------------------+------------------+------------------+-------------------------------------------------+
; Name             ; master_state.100 ; master_state.010 ; master_state.001                                ;
+------------------+------------------+------------------+-------------------------------------------------+
; master_state.001 ; 0                ; 0                ; 0                                               ;
; master_state.010 ; 0                ; 1                ; 1                                               ;
; master_state.100 ; 1                ; 0                ; 1                                               ;
+------------------+------------------+------------------+-------------------------------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state ;
+-----------------+-----------------+-----------------+-------------------------------------------------+
; Name            ; slave_state.100 ; slave_state.010 ; slave_state.001                                 ;
+-----------------+-----------------+-----------------+-------------------------------------------------+
; slave_state.001 ; 0               ; 0               ; 0                                               ;
; slave_state.010 ; 0               ; 1               ; 1                                               ;
; slave_state.100 ; 1               ; 0               ; 1                                               ;
+-----------------+-----------------+-----------------+-------------------------------------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize ;
+------------+------------+------------+------------+------------+------------+---------------------------------------------------------------------------------------------------------------------------------+
; Name       ; DRsize.101 ; DRsize.100 ; DRsize.011 ; DRsize.010 ; DRsize.001 ; DRsize.000                                                                                                                      ;
+------------+------------+------------+------------+------------+------------+---------------------------------------------------------------------------------------------------------------------------------+
; DRsize.000 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0                                                                                                                               ;
; DRsize.001 ; 0          ; 0          ; 0          ; 0          ; 1          ; 1                                                                                                                               ;
; DRsize.010 ; 0          ; 0          ; 0          ; 1          ; 0          ; 1                                                                                                                               ;
; DRsize.011 ; 0          ; 0          ; 1          ; 0          ; 0          ; 1                                                                                                                               ;
; DRsize.100 ; 0          ; 1          ; 0          ; 0          ; 0          ; 1                                                                                                                               ;
; DRsize.101 ; 1          ; 0          ; 0          ; 0          ; 0          ; 1                                                                                                                               ;
+------------+------------+------------+------------+------------+------------+---------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                      ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+--------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; nios_ii:u2|nios_ii_reset_clk_domain_synch_module:nios_ii_reset_clk_domain_synch|data_out                           ; yes                                                              ; yes                                        ;
; nios_ii:u2|nios_ii_reset_clk_50_domain_synch_module:nios_ii_reset_clk_50_domain_synch|data_out                     ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_out         ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_out       ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_out         ; yes                                                              ; yes                                        ;
; nios_ii:u2|nios_ii_reset_clk_domain_synch_module:nios_ii_reset_clk_domain_synch|data_in_d1                         ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[9]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[9]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[22]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[22]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[10]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[10]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[11]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[11]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[12]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[12]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[13]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[13]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[14]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[14]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[15]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[15]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[16]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[16]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[17]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[17]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[18]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[18]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[19]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[19]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[20]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[20]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[21]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[21]                                                                  ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[1]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[1]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|nios_ii_reset_clk_50_domain_synch_module:nios_ii_reset_clk_50_domain_synch|data_in_d1                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[2]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[2]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[3]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[3]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[4]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[4]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[5]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[5]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[6]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[6]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[7]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[7]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_address[8]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_address[8]                                                                   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_byteenable[0]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_byteenable[0]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_byteenable[1]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_byteenable[1]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1       ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_in_d1     ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_in_d1       ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_out     ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_out   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|data_out     ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|data_out   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[9]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[9]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[22]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[22]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[10]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[10]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[11]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[11]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[12]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[12]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[13]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[13]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[14]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[14]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[15]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[15]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[16]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[16]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[17]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[17]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[18]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[18]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[19]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[19]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[20]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[20]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[21]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[21]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[1]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[1]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[2]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[2]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[3]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[3]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[4]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[4]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[5]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[5]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[6]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[6]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[7]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[7]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_address_d1[8]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_address_d1[8]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_byteenable_d1[0]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_byteenable_d1[0]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_byteenable_d1[1]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_byteenable_d1[1]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_in_d1   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_in_d1 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|data_in_d1   ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|data_in_d1 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[0]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[0]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[1]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[1]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[2]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[2]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[3]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[3]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[4]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[4]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[5]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[5]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[6]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[6]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[7]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[7]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[8]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[8]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[9]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[9]                                                                 ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[10]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[10]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[11]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[11]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[12]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[12]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[13]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[13]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[14]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[14]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|master_writedata[15]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|master_writedata[15]                                                                ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[0]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[0]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[1]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[1]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[2]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[2]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[3]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[3]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[4]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[4]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[5]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[5]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[6]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[6]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[7]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[7]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[8]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[8]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[9]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[9]                                                               ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[10]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[10]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[11]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[11]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[12]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[12]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[13]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[13]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[14]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[14]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_1:the_clock_1|slave_writedata_d1[15]                                                              ; yes                                                              ; yes                                        ;
; nios_ii:u2|clock_0:the_clock_0|slave_writedata_d1[15]                                                              ; yes                                                              ; yes                                        ;
+--------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+-------------------------------------------------------------+
; Logic Cells Representing Combinational Loops                ;
+--------------------------------------------------------+----+
; Logic Cell Name                                        ;    ;
+--------------------------------------------------------+----+
; nios_ii:u2|cpu:the_cpu|Mn_rot_step2[24]~320            ;    ;
; nios_ii:u2|cpu:the_cpu|Mn_rot_step2[23]~321            ;    ;
; nios_ii:u2|cpu:the_cpu|Mn_rot_step2[22]~322            ;    ;
; nios_ii:u2|cpu:the_cpu|Mn_rot_step2[21]~323            ;    ;
; nios_ii:u2|cpu:the_cpu|Mn_rot_step2[20]~324            ;    ;
; nios_ii:u2|cpu:the_cpu|Mn_rot_step2[19]~325            ;    ;
; nios_ii:u2|cpu:the_cpu|Mn_rot_step2[2]~327             ;    ;
; nios_ii:u2|cpu:the_cpu|Mn_rot_step2[1]~326             ;    ;
; nios_ii:u2|cpu:the_cpu|M_rot_step1[24]~8780            ;    ;
; nios_ii:u2|cpu:the_cpu|M_rot_step1[23]~8781            ;    ;
; Number of logic cells representing combinational loops ; 10 ;
+--------------------------------------------------------+----+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                       ; Reason for Removal                                                                                                                              ;
+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[0..35]                     ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|i_addr[4..5]                                                                                             ; Stuck at VCC due to stuck port data_in                                                                                                          ;
; nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1|d1_reasons_to_wait                                                            ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|A_ipending_reg[2..31]                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_im_addr[0..6]                      ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_wrap                               ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_break_pulse                   ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_goto0                         ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_goto1                         ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit0                          ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit1                          ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit2                          ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit3                          ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_break                         ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|E_xbrk_goto0                       ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|E_xbrk_goto1                       ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|M_xbrk_goto0                       ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit3_latch                  ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit2_latch                  ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit1_latch                  ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit0_latch                  ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[2..31]             ; Stuck at VCC due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|M_xbrk_goto1                       ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[0..16]                   ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable                                                         ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|d1_reasons_to_wait                                                                      ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter                                                              ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|last_cycle_clock_1_out_granted_slave_sdram_s1                                           ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|last_cycle_clock_0_out_granted_slave_sdram_s1                                           ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[1]                                                  ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_reg_firsttransfer                                                              ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|d1_tristate_bridge_avalon_slave_end_xfer        ; Merged with nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|d1_reasons_to_wait                              ;
; nios_ii:u2|timer_s1_arbitrator:the_timer_s1|d1_timer_s1_end_xfer                                                                    ; Merged with nios_ii:u2|timer_s1_arbitrator:the_timer_s1|d1_reasons_to_wait                                                                      ;
; nios_ii:u2|sysid_control_slave_arbitrator:the_sysid_control_slave|d1_sysid_control_slave_end_xfer                                   ; Merged with nios_ii:u2|sysid_control_slave_arbitrator:the_sysid_control_slave|d1_reasons_to_wait                                                ;
; nios_ii:u2|sw_pio_s1_arbitrator:the_sw_pio_s1|d1_sw_pio_s1_end_xfer                                                                 ; Merged with nios_ii:u2|sw_pio_s1_arbitrator:the_sw_pio_s1|d1_reasons_to_wait                                                                    ;
; nios_ii:u2|sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0|d1_sram_avalon_slave_0_end_xfer                                   ; Merged with nios_ii:u2|sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0|d1_reasons_to_wait                                                ;
; nios_ii:u2|seg7_avalon_slave_0_arbitrator:the_seg7_avalon_slave_0|d1_seg7_avalon_slave_0_end_xfer                                   ; Merged with nios_ii:u2|seg7_avalon_slave_0_arbitrator:the_seg7_avalon_slave_0|d1_reasons_to_wait                                                ;
; nios_ii:u2|sdram:the_sdram|i_addr[0..3,6..10]                                                                                       ; Merged with nios_ii:u2|sdram:the_sdram|i_addr[11]                                                                                               ;
; nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1|onchip_mem_s1_arb_addend[0]                                                   ; Merged with nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1|onchip_mem_s1_arb_addend[1]                                                   ;
; nios_ii:u2|ledr_pio_s1_arbitrator:the_ledr_pio_s1|d1_ledr_pio_s1_end_xfer                                                           ; Merged with nios_ii:u2|ledr_pio_s1_arbitrator:the_ledr_pio_s1|d1_reasons_to_wait                                                                ;
; nios_ii:u2|ledg_pio_s1_arbitrator:the_ledg_pio_s1|d1_ledg_pio_s1_end_xfer                                                           ; Merged with nios_ii:u2|ledg_pio_s1_arbitrator:the_ledg_pio_s1|d1_reasons_to_wait                                                                ;
; nios_ii:u2|key_pio_s1_arbitrator:the_key_pio_s1|d1_key_pio_s1_end_xfer                                                              ; Merged with nios_ii:u2|key_pio_s1_arbitrator:the_key_pio_s1|d1_reasons_to_wait                                                                  ;
; nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_cpu_jtag_debug_module_end_xfer                             ; Merged with nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait                                            ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigger_state                    ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_write_request                                                      ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_6 ; Merged with nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_6 ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_5 ; Merged with nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_5 ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_4 ; Merged with nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_4 ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_3 ; Merged with nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_3 ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_2 ; Merged with nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_2 ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_1 ; Merged with nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_1 ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_0 ; Merged with nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_0 ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_break                         ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigbrktype                      ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu:the_cpu|D_ctrl_jmp_direct                                                                                            ; Merged with nios_ii:u2|cpu:the_cpu|D_ctrl_a_not_src                                                                                             ;
; nios_ii:u2|cpu:the_cpu|D_ctrl_b_is_dst                                                                                              ; Merged with nios_ii:u2|cpu:the_cpu|D_ctrl_b_not_src                                                                                             ;
; nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1|onchip_mem_s1_arb_share_counter[2]                                            ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_share_counter[2]                    ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|sdram:the_sdram|m_next~64                                                                                                ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|m_next~65                                                                                                ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|m_next~68                                                                                                ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|m_next~69                                                                                                ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|m_next~71                                                                                                ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|i_next~17                                                                                                ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|i_next~18                                                                                                ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|i_next~19                                                                                                ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|i_state~56                                                                                               ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|i_state~57                                                                                               ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|sdram:the_sdram|i_state~58                                                                                               ; Lost fanout                                                                                                                                     ;
; nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.100                                                          ; Stuck at GND due to stuck port data_in                                                                                                          ;
; nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rst1                                               ; Merged with nios_ii:u2|cpu:the_cpu|reset_d1                                                                                                     ;
; nios_ii:u2|cpu:the_cpu|reset_d1                                                                                                     ; Merged with nios_ii:u2|clock_0:the_clock_0|slave_byteenable_d1[1]                                                                               ;
; nios_ii:u2|sdram:the_sdram|m_count[2]                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                          ;
; Total Number of Removed Registers = 197                                                                                             ;                                                                                                                                                 ;
+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                      ;
+-------------------------------------------------------------------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                     ; Reason for Removal        ; Registers Removed due to This Register                                                                           ;
+-------------------------------------------------------------------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------------------------------------+
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit0        ; Stuck at GND              ; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit3,      ;
;                                                                                                                   ; due to stuck port data_in ; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_break,     ;
;                                                                                                                   ;                           ; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|E_xbrk_goto0,   ;
;                                                                                                                   ;                           ; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|E_xbrk_goto1,   ;
;                                                                                                                   ;                           ; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|M_xbrk_goto0,   ;
;                                                                                                                   ;                           ; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|M_xbrk_goto1    ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_break_pulse ; Stuck at GND              ; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_break,     ;
;                                                                                                                   ; due to stuck port data_in ; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigbrktype   ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable                                       ; Stuck at GND              ; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|d1_reasons_to_wait,                                                  ;
;                                                                                                                   ; due to stuck port data_in ; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[1]                               ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_goto0       ; Stuck at GND              ; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigger_state ;
;                                                                                                                   ; due to stuck port data_in ;                                                                                                                  ;
+-------------------------------------------------------------------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 2742  ;
; Number of registers using Synchronous Clear  ; 63    ;
; Number of registers using Synchronous Load   ; 310   ;
; Number of registers using Asynchronous Clear ; 2531  ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1773  ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                ;
+---------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                 ; Fan out ;
+---------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; nios_ii:u2|timer:the_timer|internal_counter[0]                                                                                                    ; 3       ;
; nios_ii:u2|timer:the_timer|internal_counter[1]                                                                                                    ; 3       ;
; nios_ii:u2|timer:the_timer|internal_counter[2]                                                                                                    ; 3       ;
; nios_ii:u2|timer:the_timer|internal_counter[3]                                                                                                    ; 3       ;
; nios_ii:u2|timer:the_timer|internal_counter[4]                                                                                                    ; 3       ;
; nios_ii:u2|timer:the_timer|internal_counter[7]                                                                                                    ; 3       ;
; nios_ii:u2|timer:the_timer|internal_counter[9]                                                                                                    ; 3       ;
; nios_ii:u2|timer:the_timer|internal_counter[10]                                                                                                   ; 3       ;
; nios_ii:u2|timer:the_timer|internal_counter[15]                                                                                                   ; 3       ;
; nios_ii:u2|timer:the_timer|internal_counter[16]                                                                                                   ; 3       ;
; nios_ii:u2|sdram:the_sdram|m_cmd[0]                                                                                                               ; 2       ;
; nios_ii:u2|sdram:the_sdram|m_cmd[1]                                                                                                               ; 2       ;
; nios_ii:u2|sdram:the_sdram|m_cmd[2]                                                                                                               ; 2       ;
; nios_ii:u2|sdram:the_sdram|m_cmd[3]                                                                                                               ; 1       ;
; nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|write_n_to_the_cfi_flash                                      ; 1       ;
; nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|read_n_to_the_cfi_flash                                       ; 1       ;
; nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|select_n_to_the_cfi_flash                                     ; 1       ;
; nios_ii:u2|sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0|sram_avalon_slave_0_arb_addend[0]                                               ; 6       ;
; nios_ii:u2|sdram:the_sdram|i_addr[11]                                                                                                             ; 10      ;
; nios_ii:u2|sdram:the_sdram|i_cmd[0]                                                                                                               ; 2       ;
; nios_ii:u2|sdram:the_sdram|i_cmd[1]                                                                                                               ; 2       ;
; nios_ii:u2|sdram:the_sdram|i_cmd[2]                                                                                                               ; 2       ;
; nios_ii:u2|sdram:the_sdram|i_cmd[3]                                                                                                               ; 2       ;
; nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_avalon_slave_arb_addend[0]                    ; 6       ;
; nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]                                         ; 6       ;
; nios_ii:u2|jtag_uart:the_jtag_uart|av_waitrequest                                                                                                 ; 3       ;
; nios_ii:u2|sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0|sram_avalon_slave_0_reg_firsttransfer                                           ; 1       ;
; nios_ii:u2|cpu:the_cpu|M_pipe_flush                                                                                                               ; 40      ;
; nios_ii:u2|cpu:the_cpu|hbreak_enabled                                                                                                             ; 40      ;
; nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[9]                                                         ; 11      ;
; nios_ii:u2|jtag_uart:the_jtag_uart|t_dav                                                                                                          ; 3       ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|fifo_contains_ones_n ; 3       ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|fifo_contains_ones_n ; 3       ;
; nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0]                                                                                ; 5       ;
; nios_ii:u2|sdram:the_sdram|refresh_counter[12]                                                                                                    ; 2       ;
; nios_ii:u2|sdram:the_sdram|refresh_counter[9]                                                                                                     ; 2       ;
; nios_ii:u2|sdram:the_sdram|refresh_counter[8]                                                                                                     ; 2       ;
; nios_ii:u2|sdram:the_sdram|refresh_counter[7]                                                                                                     ; 2       ;
; nios_ii:u2|sdram:the_sdram|refresh_counter[3]                                                                                                     ; 2       ;
; nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_avalon_slave_reg_firsttransfer                ; 1       ;
; nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_reg_firsttransfer                                     ; 2       ;
; nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1|onchip_mem_s1_reg_firsttransfer                                                             ; 1       ;
; nios_ii:u2|cpu:the_cpu|M_pipe_flush_waddr[22]                                                                                                     ; 1       ;
; nios_ii:u2|cpu:the_cpu|M_pipe_flush_waddr[20]                                                                                                     ; 1       ;
; nios_ii:u2|cpu:the_cpu|ic_tag_clr_valid_bits                                                                                                      ; 1       ;
; nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rst2                                                             ; 2       ;
; nios_ii:u2|cpu:the_cpu|A_wr_dst_reg_from_M                                                                                                        ; 66      ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[1]                               ; 2       ;
; nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[0]                               ; 2       ;
; nios_ii:u2|timer:the_timer|period_l_register[1]                                                                                                   ; 2       ;
; nios_ii:u2|timer:the_timer|period_l_register[9]                                                                                                   ; 2       ;
; nios_ii:u2|timer:the_timer|period_l_register[0]                                                                                                   ; 2       ;
; nios_ii:u2|timer:the_timer|period_h_register[0]                                                                                                   ; 2       ;
; nios_ii:u2|timer:the_timer|period_l_register[15]                                                                                                  ; 2       ;
; nios_ii:u2|timer:the_timer|period_l_register[7]                                                                                                   ; 2       ;
; nios_ii:u2|timer:the_timer|period_l_register[4]                                                                                                   ; 2       ;
; nios_ii:u2|timer:the_timer|period_l_register[3]                                                                                                   ; 2       ;
; nios_ii:u2|timer:the_timer|period_l_register[2]                                                                                                   ; 2       ;
; nios_ii:u2|timer:the_timer|period_l_register[10]                                                                                                  ; 2       ;
; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                                  ; 2       ;
; Total number of inverted registers = 60                                                                                                           ;         ;
+---------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_latency_counter[0]                                                                                   ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_latency_counter[0]                                                              ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|d_byteenable[1]                                                                                                                                         ;
; 3:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|d_address_line_field[5]                                                                                                                                 ;
; 3:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|ic_tag_wraddress[1]                                                                                                                                     ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|M_mem_byte_en[0]                                                                                                                                        ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|A_slow_inst_result[0]                                                                                                                                   ;
; 3:1                ; 26 bits   ; 52 LEs        ; 52 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|D_iw[11]                                                                                                                                                ;
; 3:1                ; 30 bits   ; 60 LEs        ; 60 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|A_inst_result[23]                                                                                                                                       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|A_inst_result[1]                                                                                                                                        ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|ic_fill_ap_cnt[2]                                                                                                                                       ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|ic_fill_ap_offset[1]                                                                                                                                    ;
; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[0]                                                                                    ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|d_writedata[18]                                                                                                                                         ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|A_dc_rd_addr_cnt[3]                                                                                                                                     ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|A_dc_rd_data_cnt[1]                                                                                                                                     ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|A_dc_wr_data_cnt[2]                                                                                                                                     ;
; 4:1                ; 18 bits   ; 36 LEs        ; 36 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonDReg[1]                                                                        ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonDReg[23]                                                                       ;
; 4:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[8]                                                                        ;
; 4:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|E_src2[20]                                                                                                                                              ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cfi_flash_s1_wait_counter[4]                                                               ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0|sram_avalon_slave_0_wait_counter[0]                                                                          ;
; 4:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonDReg[2]                                                                        ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|M_st_data[31]                                                                                                                                           ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|d_address_offset_field[1]                                                                                                                               ;
; 5:1                ; 32 bits   ; 96 LEs        ; 32 LEs               ; 64 LEs                 ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[0]                                                            ;
; 5:1                ; 21 bits   ; 63 LEs        ; 63 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|M_pipe_flush_waddr[11]                                                                                                                                  ;
; 5:1                ; 32 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|E_src1[6]                                                                                                                                               ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_bank[1]                                                                                                                                           ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|M_mem_byte_en[2]                                                                                                                                        ;
; 6:1                ; 13 bits   ; 52 LEs        ; 52 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|F_pc[22]                                                                                                                                                ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_count[0]                                                                                                                                          ;
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_addr[8]                                                                                                                                           ;
; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_addr[5]                                                                                                                                           ;
; 7:1                ; 6 bits    ; 24 LEs        ; 18 LEs               ; 6 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_addr[7]                                                                                                                                           ;
; 12:1               ; 41 bits   ; 328 LEs       ; 0 LEs                ; 328 LEs                ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|active_data[9]                                                                                                                                      ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_data[14]                                                                                                                                          ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|M_pipe_flush_waddr[22]                                                                                                                                  ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0|sram_avalon_slave_0_arb_share_counter_next_value[2]                                                          ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cfgdout[3]                                                                        ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[2]                                                                                                             ;
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_avalon_slave_arb_share_counter_next_value[0]                               ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|E_logic_result[5]                                                                                                                                       ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1|onchip_mem_s1_arb_share_counter_next_value[2]                                                                            ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_share_counter_next_value[0]                                                    ;
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|F_iw[5]                                                                                                                                                 ;
; 3:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|dc_data_rd_port_addr[4]                                                                                                                                 ;
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|dc_data_wr_port_addr[6]                                                                                                                                 ;
; 3:1                ; 35 bits   ; 70 LEs        ; 70 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|dc_data_wr_port_data[10]                                                                                                                                ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated|mux_0kb:mux2|result_node[16]                                                     ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Selector3                                                                                                           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_avalon_slave_arb_share_set_values[0]                                       ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|comb~2                                                                                                                                              ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|updated_one_count~18                              ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|updated_one_count~15                              ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|E_alu_result[1]                                                                                                                                         ;
; 4:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|E_alu_result[7]                                                                                                                                         ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|D_dst_regnum[4]                                                                                                                                         ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|dc_data_wr_port_byte_en[0]                                                                                                                              ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[0]                                                                                                             ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Selector0                                                                                                           ;
; 5:1                ; 6 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|E_alu_result[30]                                                                                                                                        ;
; 5:1                ; 14 bits   ; 42 LEs        ; 42 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|E_alu_result[15]                                                                                                                                        ;
; 5:1                ; 32 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|D_src2_reg[10]                                                                                                                                          ;
; 5:1                ; 16 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|A_wr_data_unfiltered[24]                                                                                                                                ;
; 5:1                ; 8 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|A_wr_data_unfiltered[11]                                                                                                                                ;
; 6:1                ; 8 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|A_wr_data_unfiltered[0]                                                                                                                                 ;
; 6:1                ; 10 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]                                                                                                                                ;
; 11:1               ; 2 bits    ; 14 LEs        ; 4 LEs                ; 10 LEs                 ; No         ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|Selector34                                                                                                                                          ;
; 16:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; No         ; |DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|Selector28                                                                                                                                          ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[37] ;
; 6:1                ; 6 bits    ; 24 LEs        ; 18 LEs               ; 6 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[12] ;
; 6:1                ; 18 bits   ; 72 LEs        ; 36 LEs               ; 36 LEs                 ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[21] ;
; 6:1                ; 7 bits    ; 28 LEs        ; 21 LEs               ; 7 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[4]  ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[1]                                                                                      ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                   ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[7]                                                                                   ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |DE2_NIOS_Lite|nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[1]                                                                                   ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]                                                                                                                                       ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]                                                                                                                   ;
; 28:1               ; 4 bits    ; 72 LEs        ; 48 LEs               ; 24 LEs                 ; Yes        ; |DE2_NIOS_Lite|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_0:the_clock_0                                  ;
+-------------------+-------+----------------------------+-------------------------------+
; Assignment        ; Value ; From                       ; To                            ;
+-------------------+-------+----------------------------+-------------------------------+
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]           ;
; CUT               ; ON    ; *                          ; slave_readdata[15]            ;
; CUT               ; ON    ; *                          ; slave_readdata[14]            ;
; CUT               ; ON    ; *                          ; slave_readdata[13]            ;
; CUT               ; ON    ; *                          ; slave_readdata[12]            ;
; CUT               ; ON    ; *                          ; slave_readdata[11]            ;
; CUT               ; ON    ; *                          ; slave_readdata[10]            ;
; CUT               ; ON    ; *                          ; slave_readdata[9]             ;
; CUT               ; ON    ; *                          ; slave_readdata[8]             ;
; CUT               ; ON    ; *                          ; slave_readdata[7]             ;
; CUT               ; ON    ; *                          ; slave_readdata[6]             ;
; CUT               ; ON    ; *                          ; slave_readdata[5]             ;
; CUT               ; ON    ; *                          ; slave_readdata[4]             ;
; CUT               ; ON    ; *                          ; slave_readdata[3]             ;
; CUT               ; ON    ; *                          ; slave_readdata[2]             ;
; CUT               ; ON    ; *                          ; slave_readdata[1]             ;
; CUT               ; ON    ; *                          ; slave_readdata[0]             ;
; CUT               ; ON    ; *                          ; slave_readdata[15]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[14]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[13]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[12]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[11]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[10]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[9]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[8]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[7]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[6]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[5]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[4]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[3]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[2]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[1]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[0]~reg0        ;
; CUT               ; ON    ; slave_writedata_d1[15]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[15]        ;
; CUT               ; ON    ; slave_writedata_d1[14]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[14]        ;
; CUT               ; ON    ; slave_writedata_d1[13]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[13]        ;
; CUT               ; ON    ; slave_writedata_d1[12]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[12]        ;
; CUT               ; ON    ; slave_writedata_d1[11]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[11]        ;
; CUT               ; ON    ; slave_writedata_d1[10]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[10]        ;
; CUT               ; ON    ; slave_writedata_d1[9]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[9]         ;
; CUT               ; ON    ; slave_writedata_d1[8]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[8]         ;
; CUT               ; ON    ; slave_writedata_d1[7]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[7]         ;
; CUT               ; ON    ; slave_writedata_d1[6]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[6]         ;
; CUT               ; ON    ; slave_writedata_d1[5]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[5]         ;
; CUT               ; ON    ; slave_writedata_d1[4]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[4]         ;
; CUT               ; ON    ; slave_writedata_d1[3]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[3]         ;
; CUT               ; ON    ; slave_writedata_d1[2]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[2]         ;
; CUT               ; ON    ; slave_writedata_d1[1]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[1]         ;
; CUT               ; ON    ; slave_writedata_d1[0]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[0]         ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]~reg0      ;
; CUT               ; ON    ; slave_address_d1[22]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[22]          ;
; CUT               ; ON    ; slave_address_d1[21]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[21]          ;
; CUT               ; ON    ; slave_address_d1[20]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[20]          ;
; CUT               ; ON    ; slave_address_d1[19]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[19]          ;
; CUT               ; ON    ; slave_address_d1[18]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[18]          ;
; CUT               ; ON    ; slave_address_d1[17]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[17]          ;
; CUT               ; ON    ; slave_address_d1[16]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[16]          ;
; CUT               ; ON    ; slave_address_d1[15]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[15]          ;
; CUT               ; ON    ; slave_address_d1[14]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[14]          ;
; CUT               ; ON    ; slave_address_d1[13]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[13]          ;
; CUT               ; ON    ; slave_address_d1[12]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[12]          ;
; CUT               ; ON    ; slave_address_d1[11]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[11]          ;
; CUT               ; ON    ; slave_address_d1[10]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[10]          ;
; CUT               ; ON    ; slave_address_d1[9]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[9]           ;
; CUT               ; ON    ; slave_address_d1[8]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[8]           ;
; CUT               ; ON    ; slave_address_d1[7]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[7]           ;
; CUT               ; ON    ; slave_address_d1[6]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[6]           ;
; CUT               ; ON    ; slave_address_d1[5]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[5]           ;
; CUT               ; ON    ; slave_address_d1[4]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[4]           ;
; CUT               ; ON    ; slave_address_d1[3]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[3]           ;
; CUT               ; ON    ; slave_address_d1[2]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[2]           ;
; CUT               ; ON    ; slave_address_d1[1]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[1]           ;
; CUT               ; ON    ; slave_address_d1[0]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[0]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]~reg0        ;
; CUT               ; ON    ; slave_nativeaddress_d1[21] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[21]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[20] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[20]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[19] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[19]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[18] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[18]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[17] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[17]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[16] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[16]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[15] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[15]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[14] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[14]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[13] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[13]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[12] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[12]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[11] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[11]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[10] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[10]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[9]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[9]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[8]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[8]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[7]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[7]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[6]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[6]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[5]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[5]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[4]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[4]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[3]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[3]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[2]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[2]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[1]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[1]     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]~reg0     ;
; CUT               ; ON    ; slave_nativeaddress_d1[0]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[0]     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]~reg0  ;
; CUT               ; ON    ; slave_byteenable_d1[1]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[1]        ;
; CUT               ; ON    ; slave_byteenable_d1[0]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[0]        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]~reg0     ;
+-------------------+-------+----------------------------+-------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync ;
+-------------------+-------+------+---------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                    ;
+-------------------+-------+------+---------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                              ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                         ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                            ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                            ;
+-------------------+-------+------+---------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                      ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                           ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                              ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                              ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                        ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                  ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                             ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                          ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                    ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                               ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                  ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                  ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe ;
+-------------------+-------+------------+----------------------------------------------------+
; Assignment        ; Value ; From       ; To                                                 ;
+-------------------+-------+------------+----------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -          ; data_out                                           ;
; PRESERVE_REGISTER ; ON    ; -          ; data_out~reg0                                      ;
; CUT               ; ON    ; data_in_d1 ; *                                                  ;
; PRESERVE_REGISTER ; ON    ; -          ; data_in_d1                                         ;
+-------------------+-------+------------+----------------------------------------------------+


+----------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_1:the_clock_1                                  ;
+-------------------+-------+----------------------------+-------------------------------+
; Assignment        ; Value ; From                       ; To                            ;
+-------------------+-------+----------------------------+-------------------------------+
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]           ;
; CUT               ; ON    ; *                          ; slave_readdata[15]            ;
; CUT               ; ON    ; *                          ; slave_readdata[14]            ;
; CUT               ; ON    ; *                          ; slave_readdata[13]            ;
; CUT               ; ON    ; *                          ; slave_readdata[12]            ;
; CUT               ; ON    ; *                          ; slave_readdata[11]            ;
; CUT               ; ON    ; *                          ; slave_readdata[10]            ;
; CUT               ; ON    ; *                          ; slave_readdata[9]             ;
; CUT               ; ON    ; *                          ; slave_readdata[8]             ;
; CUT               ; ON    ; *                          ; slave_readdata[7]             ;
; CUT               ; ON    ; *                          ; slave_readdata[6]             ;
; CUT               ; ON    ; *                          ; slave_readdata[5]             ;
; CUT               ; ON    ; *                          ; slave_readdata[4]             ;
; CUT               ; ON    ; *                          ; slave_readdata[3]             ;
; CUT               ; ON    ; *                          ; slave_readdata[2]             ;
; CUT               ; ON    ; *                          ; slave_readdata[1]             ;
; CUT               ; ON    ; *                          ; slave_readdata[0]             ;
; CUT               ; ON    ; *                          ; slave_readdata[15]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[14]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[13]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[12]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[11]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[10]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[9]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[8]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[7]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[6]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[5]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[4]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[3]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[2]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[1]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[0]~reg0        ;
; CUT               ; ON    ; slave_writedata_d1[15]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[15]        ;
; CUT               ; ON    ; slave_writedata_d1[14]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[14]        ;
; CUT               ; ON    ; slave_writedata_d1[13]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[13]        ;
; CUT               ; ON    ; slave_writedata_d1[12]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[12]        ;
; CUT               ; ON    ; slave_writedata_d1[11]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[11]        ;
; CUT               ; ON    ; slave_writedata_d1[10]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[10]        ;
; CUT               ; ON    ; slave_writedata_d1[9]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[9]         ;
; CUT               ; ON    ; slave_writedata_d1[8]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[8]         ;
; CUT               ; ON    ; slave_writedata_d1[7]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[7]         ;
; CUT               ; ON    ; slave_writedata_d1[6]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[6]         ;
; CUT               ; ON    ; slave_writedata_d1[5]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[5]         ;
; CUT               ; ON    ; slave_writedata_d1[4]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[4]         ;
; CUT               ; ON    ; slave_writedata_d1[3]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[3]         ;
; CUT               ; ON    ; slave_writedata_d1[2]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[2]         ;
; CUT               ; ON    ; slave_writedata_d1[1]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[1]         ;
; CUT               ; ON    ; slave_writedata_d1[0]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[0]         ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]~reg0      ;
; CUT               ; ON    ; slave_address_d1[22]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[22]          ;
; CUT               ; ON    ; slave_address_d1[21]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[21]          ;
; CUT               ; ON    ; slave_address_d1[20]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[20]          ;
; CUT               ; ON    ; slave_address_d1[19]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[19]          ;
; CUT               ; ON    ; slave_address_d1[18]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[18]          ;
; CUT               ; ON    ; slave_address_d1[17]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[17]          ;
; CUT               ; ON    ; slave_address_d1[16]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[16]          ;
; CUT               ; ON    ; slave_address_d1[15]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[15]          ;
; CUT               ; ON    ; slave_address_d1[14]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[14]          ;
; CUT               ; ON    ; slave_address_d1[13]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[13]          ;
; CUT               ; ON    ; slave_address_d1[12]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[12]          ;
; CUT               ; ON    ; slave_address_d1[11]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[11]          ;
; CUT               ; ON    ; slave_address_d1[10]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[10]          ;
; CUT               ; ON    ; slave_address_d1[9]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[9]           ;
; CUT               ; ON    ; slave_address_d1[8]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[8]           ;
; CUT               ; ON    ; slave_address_d1[7]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[7]           ;
; CUT               ; ON    ; slave_address_d1[6]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[6]           ;
; CUT               ; ON    ; slave_address_d1[5]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[5]           ;
; CUT               ; ON    ; slave_address_d1[4]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[4]           ;
; CUT               ; ON    ; slave_address_d1[3]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[3]           ;
; CUT               ; ON    ; slave_address_d1[2]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[2]           ;
; CUT               ; ON    ; slave_address_d1[1]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[1]           ;
; CUT               ; ON    ; slave_address_d1[0]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[0]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]~reg0        ;
; CUT               ; ON    ; slave_nativeaddress_d1[21] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[21]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[20] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[20]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[19] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[19]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[18] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[18]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[17] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[17]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[16] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[16]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[15] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[15]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[14] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[14]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[13] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[13]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[12] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[12]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[11] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[11]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[10] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[10]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[9]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[9]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[8]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[8]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[7]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[7]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[6]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[6]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[5]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[5]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[4]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[4]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[3]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[3]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[2]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[2]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[1]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[1]     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]~reg0     ;
; CUT               ; ON    ; slave_nativeaddress_d1[0]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[0]     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]~reg0  ;
; CUT               ; ON    ; slave_byteenable_d1[1]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[1]        ;
; CUT               ; ON    ; slave_byteenable_d1[0]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[0]        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]~reg0     ;
+-------------------+-------+----------------------------+-------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync ;
+-------------------+-------+------+---------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                    ;
+-------------------+-------+------+---------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                              ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                         ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                            ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                            ;
+-------------------+-------+------+---------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                      ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                           ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                              ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                              ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                        ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                  ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                             ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                          ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                    ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                               ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                  ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                  ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe ;
+-------------------+-------+------------+----------------------------------------------------+
; Assignment        ; Value ; From       ; To                                                 ;
+-------------------+-------+------------+----------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -          ; data_out                                           ;
; PRESERVE_REGISTER ; ON    ; -          ; data_out~reg0                                      ;
; CUT               ; ON    ; data_in_d1 ; *                                                  ;
; PRESERVE_REGISTER ; ON    ; -          ; data_in_d1                                         ;
+-------------------+-------+------------+----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qed1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                      ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                       ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_u0g1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                    ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                     ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_pkf1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                              ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                               ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_p2f1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                      ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                       ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_q2f1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                      ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                       ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_j9f1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                    ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                     ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram|altsyncram_29f1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                      ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                       ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_9vc1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                          ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                           ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_t072:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                        ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                         ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                            ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                             ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1 ;
+---------------------------+----------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value          ; From ; To                                                                                                                                         ;
+---------------------------+----------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; D101,R101      ; -    ; ir_out[1]                                                                                                                                  ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,R101      ; -    ; ir_out[0]                                                                                                                                  ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[37]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[36]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[35]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[34]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[33]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[32]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[31]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[30]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[29]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[28]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[27]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[26]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[25]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[24]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[23]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[22]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[21]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[20]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[19]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[18]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[17]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[16]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[15]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[14]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[13]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[12]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[11]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[10]                                                                                                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[9]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[8]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[7]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[6]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[5]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[4]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[3]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[2]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[1]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[0]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[4]~reg0                                                                                                                                ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[3]~reg0                                                                                                                                ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[2]~reg0                                                                                                                                ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[1]~reg0                                                                                                                                ;
; SUPPRESS_DA_RULE_INTERNAL ; D101           ; -    ; jxdr                                                                                                                                       ;
; SUPPRESS_DA_RULE_INTERNAL ; D101           ; -    ; dr_update2                                                                                                                                 ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,R101      ; -    ; ir_out[1]~reg0                                                                                                                             ;
; SUPPRESS_DA_RULE_INTERNAL ; R101           ; -    ; in_between_shiftdr_and_updatedr                                                                                                            ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,R101      ; -    ; ir_out[0]~reg0                                                                                                                             ;
; SUPPRESS_DA_RULE_INTERNAL ; D101           ; -    ; dr_update1                                                                                                                                 ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[37]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[36]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[35]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[34]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[33]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[32]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[31]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[30]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[29]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[28]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[27]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[26]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[25]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[24]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[23]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[22]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[21]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[20]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[19]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[18]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[17]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[16]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[15]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[14]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[13]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[12]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[11]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[10]                                                                                                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[9]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[8]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[7]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[6]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[5]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[4]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[3]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[2]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[1]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; sr[0]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; DRsize.000                                                                                                                                 ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; DRsize.001                                                                                                                                 ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; DRsize.010                                                                                                                                 ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; DRsize.011                                                                                                                                 ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; DRsize.100                                                                                                                                 ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; DRsize.101                                                                                                                                 ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; ir[1]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D101,D103,R101 ; -    ; ir[0]                                                                                                                                      ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[0]~reg0                                                                                                                                ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[5]~reg0                                                                                                                                ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[6]~reg0                                                                                                                                ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[7]~reg0                                                                                                                                ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[8]~reg0                                                                                                                                ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[9]~reg0                                                                                                                                ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[10]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[11]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[12]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[13]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[14]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[15]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[16]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[17]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[18]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[19]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[20]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[21]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[22]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[23]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[24]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[25]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[26]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[27]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[28]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[29]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[30]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[31]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[32]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[33]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[34]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[35]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[36]~reg0                                                                                                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; D103           ; -    ; jdo[37]~reg0                                                                                                                               ;
+---------------------------+----------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------+
; Source assignments for nios_ii:u2|jtag_uart:the_jtag_uart   ;
+---------------------------+---------------------+------+----+
; Assignment                ; Value               ; From ; To ;
+---------------------------+---------------------+------+----+
; SUPPRESS_DA_RULE_INTERNAL ; R101,C106,D101,D103 ; -    ; -  ;
+---------------------------+---------------------+------+----+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                     ;
+---------------------------------+--------------------+------+--------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                      ;
+---------------------------------+--------------------+------+--------------------------------------------------------+


+---------------------------------------------------------------+
; Source assignments for nios_ii:u2|sdram:the_sdram             ;
+-----------------------------+-------+------+------------------+
; Assignment                  ; Value ; From ; To               ;
+-----------------------------+-------+------+------------------+
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[15]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[14]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[13]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[12]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[11]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[10]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[9]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[8]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[7]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[6]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[5]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[4]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[3]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[2]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[1]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[0]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[3]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[2]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[1]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[0]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_bank[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_bank[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[11]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[10]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[9]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[8]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[7]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[6]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[5]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[4]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[3]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[2]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[15]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[15]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[14]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[14]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[13]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[13]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[12]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[12]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[11]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[11]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[10]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[10]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[9]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[9]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[8]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[8]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[7]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[7]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[6]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[6]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[5]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[5]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[4]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[4]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[3]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[3]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[2]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[2]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[1]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[0]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_dqm[1]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_dqm[0]         ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; oe               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[15]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[14]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[13]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[12]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[11]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[10]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[9]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[8]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[7]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[6]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[5]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[4]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[3]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[2]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[1]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[0]~reg0  ;
+-----------------------------+-------+------+------------------+


+------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave ;
+-----------------------------+-------+------+---------------------------------------------------------------+
; Assignment                  ; Value ; From ; To                                                            ;
+-----------------------------+-------+------+---------------------------------------------------------------+
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[21]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[20]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[19]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[18]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[17]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[16]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[15]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[14]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[13]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[12]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[11]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[10]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[9]                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[8]                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[7]                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[6]                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[5]                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[4]                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[3]                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[2]                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[1]                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[0]                                   ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[7]                    ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[6]                    ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[5]                    ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[4]                    ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[3]                    ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[2]                    ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[1]                    ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[0]                    ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; read_n_to_the_cfi_flash                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; select_n_to_the_cfi_flash                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; write_n_to_the_cfi_flash                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; select_n_to_the_cfi_flash~reg0                                ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[7]~reg0               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[6]~reg0               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[5]~reg0               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[4]~reg0               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[3]~reg0               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[2]~reg0               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[1]~reg0               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_data_to_and_from_the_cfi_flash[0]~reg0               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_data_to_and_from_the_cfi_flash[7]                 ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_data_to_and_from_the_cfi_flash[6]                 ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_data_to_and_from_the_cfi_flash[5]                 ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_data_to_and_from_the_cfi_flash[4]                 ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_data_to_and_from_the_cfi_flash[3]                 ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_data_to_and_from_the_cfi_flash[2]                 ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_data_to_and_from_the_cfi_flash[1]                 ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_data_to_and_from_the_cfi_flash[0]                 ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; d1_in_a_write_cycle                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; read_n_to_the_cfi_flash~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; write_n_to_the_cfi_flash~reg0                                 ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[21]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[20]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[19]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[18]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[17]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[16]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[15]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[14]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[13]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[12]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[11]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[10]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[9]~reg0                              ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[8]~reg0                              ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[7]~reg0                              ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[6]~reg0                              ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[5]~reg0                              ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[4]~reg0                              ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[3]~reg0                              ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[2]~reg0                              ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[1]~reg0                              ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; address_to_the_cfi_flash[0]~reg0                              ;
+-----------------------------+-------+------+---------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|nios_ii_reset_clk_domain_synch_module:nios_ii_reset_clk_domain_synch ;
+---------------------------+-------+------+-------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                          ;
+---------------------------+-------+------+-------------------------------------------------------------+
; PRESERVE_REGISTER         ; ON    ; -    ; data_out                                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; R101  ; -    ; data_out                                                    ;
; PRESERVE_REGISTER         ; ON    ; -    ; data_out~reg0                                               ;
; SUPPRESS_DA_RULE_INTERNAL ; R101  ; -    ; data_out~reg0                                               ;
; MAX_DELAY                 ; 100ns ; -    ; data_in_d1                                                  ;
; PRESERVE_REGISTER         ; ON    ; -    ; data_in_d1                                                  ;
; SUPPRESS_DA_RULE_INTERNAL ; R101  ; -    ; data_in_d1                                                  ;
+---------------------------+-------+------+-------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Source assignments for nios_ii:u2|nios_ii_reset_clk_50_domain_synch_module:nios_ii_reset_clk_50_domain_synch ;
+---------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                ;
+---------------------------+-------+------+-------------------------------------------------------------------+
; PRESERVE_REGISTER         ; ON    ; -    ; data_out                                                          ;
; SUPPRESS_DA_RULE_INTERNAL ; R101  ; -    ; data_out                                                          ;
; PRESERVE_REGISTER         ; ON    ; -    ; data_out~reg0                                                     ;
; SUPPRESS_DA_RULE_INTERNAL ; R101  ; -    ; data_out~reg0                                                     ;
; MAX_DELAY                 ; 100ns ; -    ; data_in_d1                                                        ;
; PRESERVE_REGISTER         ; ON    ; -    ; data_in_d1                                                        ;
; SUPPRESS_DA_RULE_INTERNAL ; R101  ; -    ; data_in_d1                                                        ;
+---------------------------+-------+------+-------------------------------------------------------------------+


+----------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst              ;
+------------------------------+-------+------+------------+
; Assignment                   ; Value ; From ; To         ;
+------------------------------+-------+------+------------+
; IGNORE_LCELL_BUFFERS         ; OFF   ; -    ; -          ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF   ; -    ; -          ;
; NOT_GATE_PUSH_BACK           ; OFF   ; -    ; CLR_SIGNAL ;
; POWER_UP_LEVEL               ; LOW   ; -    ; CLR_SIGNAL ;
+------------------------------+-------+------+------------+


+---------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+----------------------+-------+------+-------------------------------+
; Assignment           ; Value ; From ; To                            ;
+----------------------+-------+------+-------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                             ;
+----------------------+-------+------+-------------------------------+


+-----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: SDRAM_PLL:u1|altpll:altpll_component ;
+-------------------------------+-------------------+-------------------------------+
; Parameter Name                ; Value             ; Type                          ;
+-------------------------------+-------------------+-------------------------------+
; OPERATION_MODE                ; NORMAL            ; Untyped                       ;
; PLL_TYPE                      ; FAST              ; Untyped                       ;
; QUALIFY_CONF_DONE             ; OFF               ; Untyped                       ;
; COMPENSATE_CLOCK              ; CLK0              ; Untyped                       ;
; SCAN_CHAIN                    ; LONG              ; Untyped                       ;
; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                       ;
; INCLK0_INPUT_FREQUENCY        ; 20000             ; Signed Integer                ;
; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                       ;
; GATE_LOCK_SIGNAL              ; NO                ; Untyped                       ;
; GATE_LOCK_COUNTER             ; 0                 ; Untyped                       ;
; LOCK_HIGH                     ; 1                 ; Untyped                       ;
; LOCK_LOW                      ; 1                 ; Untyped                       ;
; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                       ;
; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                       ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                       ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                       ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                       ;
; SKIP_VCO                      ; OFF               ; Untyped                       ;
; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                       ;
; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                       ;
; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                       ;
; BANDWIDTH                     ; 0                 ; Untyped                       ;
; BANDWIDTH_TYPE                ; AUTO              ; Untyped                       ;
; SPREAD_FREQUENCY              ; 0                 ; Untyped                       ;
; DOWN_SPREAD                   ; 0                 ; Untyped                       ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                       ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                       ;
; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                       ;
; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                       ;
; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                       ;
; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                       ;
; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                       ;
; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                       ;
; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                       ;
; CLK2_MULTIPLY_BY              ; 1                 ; Signed Integer                ;
; CLK1_MULTIPLY_BY              ; 2                 ; Signed Integer                ;
; CLK0_MULTIPLY_BY              ; 1                 ; Signed Integer                ;
; CLK9_DIVIDE_BY                ; 0                 ; Untyped                       ;
; CLK8_DIVIDE_BY                ; 0                 ; Untyped                       ;
; CLK7_DIVIDE_BY                ; 0                 ; Untyped                       ;
; CLK6_DIVIDE_BY                ; 0                 ; Untyped                       ;
; CLK5_DIVIDE_BY                ; 1                 ; Untyped                       ;
; CLK4_DIVIDE_BY                ; 1                 ; Untyped                       ;
; CLK3_DIVIDE_BY                ; 1                 ; Untyped                       ;
; CLK2_DIVIDE_BY                ; 2                 ; Signed Integer                ;
; CLK1_DIVIDE_BY                ; 1                 ; Signed Integer                ;
; CLK0_DIVIDE_BY                ; 1                 ; Signed Integer                ;
; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK1_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK0_PHASE_SHIFT              ; -3000             ; Untyped                       ;
; CLK5_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK4_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK3_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK2_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK1_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK0_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK9_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK8_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK7_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK6_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK5_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK4_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK3_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK2_DUTY_CYCLE               ; 50                ; Signed Integer                ;
; CLK1_DUTY_CYCLE               ; 50                ; Signed Integer                ;
; CLK0_DUTY_CYCLE               ; 50                ; Signed Integer                ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; LOCK_WINDOW_UI                ;  0.05             ; Untyped                       ;
; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                       ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                       ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                       ;
; DPA_MULTIPLY_BY               ; 0                 ; Untyped                       ;
; DPA_DIVIDE_BY                 ; 1                 ; Untyped                       ;
; DPA_DIVIDER                   ; 0                 ; Untyped                       ;
; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                       ;
; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                       ;
; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                       ;
; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                       ;
; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                       ;
; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                       ;
; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                       ;
; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                       ;
; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                       ;
; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                       ;
; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                       ;
; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                       ;
; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                       ;
; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                       ;
; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                       ;
; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                       ;
; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                       ;
; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                       ;
; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                       ;
; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                       ;
; VCO_MULTIPLY_BY               ; 0                 ; Untyped                       ;
; VCO_DIVIDE_BY                 ; 0                 ; Untyped                       ;
; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                       ;
; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                       ;
; VCO_MIN                       ; 0                 ; Untyped                       ;
; VCO_MAX                       ; 0                 ; Untyped                       ;
; VCO_CENTER                    ; 0                 ; Untyped                       ;
; PFD_MIN                       ; 0                 ; Untyped                       ;
; PFD_MAX                       ; 0                 ; Untyped                       ;
; M_INITIAL                     ; 0                 ; Untyped                       ;
; M                             ; 0                 ; Untyped                       ;
; N                             ; 1                 ; Untyped                       ;
; M2                            ; 1                 ; Untyped                       ;
; N2                            ; 1                 ; Untyped                       ;
; SS                            ; 1                 ; Untyped                       ;
; C0_HIGH                       ; 0                 ; Untyped                       ;
; C1_HIGH                       ; 0                 ; Untyped                       ;
; C2_HIGH                       ; 0                 ; Untyped                       ;
; C3_HIGH                       ; 0                 ; Untyped                       ;
; C4_HIGH                       ; 0                 ; Untyped                       ;
; C5_HIGH                       ; 0                 ; Untyped                       ;
; C6_HIGH                       ; 0                 ; Untyped                       ;
; C7_HIGH                       ; 0                 ; Untyped                       ;
; C8_HIGH                       ; 0                 ; Untyped                       ;
; C9_HIGH                       ; 0                 ; Untyped                       ;
; C0_LOW                        ; 0                 ; Untyped                       ;
; C1_LOW                        ; 0                 ; Untyped                       ;
; C2_LOW                        ; 0                 ; Untyped                       ;
; C3_LOW                        ; 0                 ; Untyped                       ;
; C4_LOW                        ; 0                 ; Untyped                       ;
; C5_LOW                        ; 0                 ; Untyped                       ;
; C6_LOW                        ; 0                 ; Untyped                       ;
; C7_LOW                        ; 0                 ; Untyped                       ;
; C8_LOW                        ; 0                 ; Untyped                       ;
; C9_LOW                        ; 0                 ; Untyped                       ;
; C0_INITIAL                    ; 0                 ; Untyped                       ;
; C1_INITIAL                    ; 0                 ; Untyped                       ;
; C2_INITIAL                    ; 0                 ; Untyped                       ;
; C3_INITIAL                    ; 0                 ; Untyped                       ;
; C4_INITIAL                    ; 0                 ; Untyped                       ;
; C5_INITIAL                    ; 0                 ; Untyped                       ;
; C6_INITIAL                    ; 0                 ; Untyped                       ;
; C7_INITIAL                    ; 0                 ; Untyped                       ;
; C8_INITIAL                    ; 0                 ; Untyped                       ;
; C9_INITIAL                    ; 0                 ; Untyped                       ;
; C0_MODE                       ; BYPASS            ; Untyped                       ;
; C1_MODE                       ; BYPASS            ; Untyped                       ;
; C2_MODE                       ; BYPASS            ; Untyped                       ;
; C3_MODE                       ; BYPASS            ; Untyped                       ;
; C4_MODE                       ; BYPASS            ; Untyped                       ;
; C5_MODE                       ; BYPASS            ; Untyped                       ;
; C6_MODE                       ; BYPASS            ; Untyped                       ;
; C7_MODE                       ; BYPASS            ; Untyped                       ;
; C8_MODE                       ; BYPASS            ; Untyped                       ;
; C9_MODE                       ; BYPASS            ; Untyped                       ;
; C0_PH                         ; 0                 ; Untyped                       ;
; C1_PH                         ; 0                 ; Untyped                       ;
; C2_PH                         ; 0                 ; Untyped                       ;
; C3_PH                         ; 0                 ; Untyped                       ;
; C4_PH                         ; 0                 ; Untyped                       ;
; C5_PH                         ; 0                 ; Untyped                       ;
; C6_PH                         ; 0                 ; Untyped                       ;
; C7_PH                         ; 0                 ; Untyped                       ;
; C8_PH                         ; 0                 ; Untyped                       ;
; C9_PH                         ; 0                 ; Untyped                       ;
; L0_HIGH                       ; 1                 ; Untyped                       ;
; L1_HIGH                       ; 1                 ; Untyped                       ;
; G0_HIGH                       ; 1                 ; Untyped                       ;
; G1_HIGH                       ; 1                 ; Untyped                       ;
; G2_HIGH                       ; 1                 ; Untyped                       ;
; G3_HIGH                       ; 1                 ; Untyped                       ;
; E0_HIGH                       ; 1                 ; Untyped                       ;
; E1_HIGH                       ; 1                 ; Untyped                       ;
; E2_HIGH                       ; 1                 ; Untyped                       ;
; E3_HIGH                       ; 1                 ; Untyped                       ;
; L0_LOW                        ; 1                 ; Untyped                       ;
; L1_LOW                        ; 1                 ; Untyped                       ;
; G0_LOW                        ; 1                 ; Untyped                       ;
; G1_LOW                        ; 1                 ; Untyped                       ;
; G2_LOW                        ; 1                 ; Untyped                       ;
; G3_LOW                        ; 1                 ; Untyped                       ;
; E0_LOW                        ; 1                 ; Untyped                       ;
; E1_LOW                        ; 1                 ; Untyped                       ;
; E2_LOW                        ; 1                 ; Untyped                       ;
; E3_LOW                        ; 1                 ; Untyped                       ;
; L0_INITIAL                    ; 1                 ; Untyped                       ;
; L1_INITIAL                    ; 1                 ; Untyped                       ;
; G0_INITIAL                    ; 1                 ; Untyped                       ;
; G1_INITIAL                    ; 1                 ; Untyped                       ;
; G2_INITIAL                    ; 1                 ; Untyped                       ;
; G3_INITIAL                    ; 1                 ; Untyped                       ;
; E0_INITIAL                    ; 1                 ; Untyped                       ;
; E1_INITIAL                    ; 1                 ; Untyped                       ;
; E2_INITIAL                    ; 1                 ; Untyped                       ;
; E3_INITIAL                    ; 1                 ; Untyped                       ;
; L0_MODE                       ; BYPASS            ; Untyped                       ;
; L1_MODE                       ; BYPASS            ; Untyped                       ;
; G0_MODE                       ; BYPASS            ; Untyped                       ;
; G1_MODE                       ; BYPASS            ; Untyped                       ;
; G2_MODE                       ; BYPASS            ; Untyped                       ;
; G3_MODE                       ; BYPASS            ; Untyped                       ;
; E0_MODE                       ; BYPASS            ; Untyped                       ;
; E1_MODE                       ; BYPASS            ; Untyped                       ;
; E2_MODE                       ; BYPASS            ; Untyped                       ;
; E3_MODE                       ; BYPASS            ; Untyped                       ;
; L0_PH                         ; 0                 ; Untyped                       ;
; L1_PH                         ; 0                 ; Untyped                       ;
; G0_PH                         ; 0                 ; Untyped                       ;
; G1_PH                         ; 0                 ; Untyped                       ;
; G2_PH                         ; 0                 ; Untyped                       ;
; G3_PH                         ; 0                 ; Untyped                       ;
; E0_PH                         ; 0                 ; Untyped                       ;
; E1_PH                         ; 0                 ; Untyped                       ;
; E2_PH                         ; 0                 ; Untyped                       ;
; E3_PH                         ; 0                 ; Untyped                       ;
; M_PH                          ; 0                 ; Untyped                       ;
; C1_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C2_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C3_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C4_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C5_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C6_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C7_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C8_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C9_USE_CASC_IN                ; OFF               ; Untyped                       ;
; CLK0_COUNTER                  ; G0                ; Untyped                       ;
; CLK1_COUNTER                  ; G0                ; Untyped                       ;
; CLK2_COUNTER                  ; G0                ; Untyped                       ;
; CLK3_COUNTER                  ; G0                ; Untyped                       ;
; CLK4_COUNTER                  ; G0                ; Untyped                       ;
; CLK5_COUNTER                  ; G0                ; Untyped                       ;
; CLK6_COUNTER                  ; E0                ; Untyped                       ;
; CLK7_COUNTER                  ; E1                ; Untyped                       ;
; CLK8_COUNTER                  ; E2                ; Untyped                       ;
; CLK9_COUNTER                  ; E3                ; Untyped                       ;
; L0_TIME_DELAY                 ; 0                 ; Untyped                       ;
; L1_TIME_DELAY                 ; 0                 ; Untyped                       ;
; G0_TIME_DELAY                 ; 0                 ; Untyped                       ;
; G1_TIME_DELAY                 ; 0                 ; Untyped                       ;
; G2_TIME_DELAY                 ; 0                 ; Untyped                       ;
; G3_TIME_DELAY                 ; 0                 ; Untyped                       ;
; E0_TIME_DELAY                 ; 0                 ; Untyped                       ;
; E1_TIME_DELAY                 ; 0                 ; Untyped                       ;
; E2_TIME_DELAY                 ; 0                 ; Untyped                       ;
; E3_TIME_DELAY                 ; 0                 ; Untyped                       ;
; M_TIME_DELAY                  ; 0                 ; Untyped                       ;
; N_TIME_DELAY                  ; 0                 ; Untyped                       ;
; EXTCLK3_COUNTER               ; E3                ; Untyped                       ;
; EXTCLK2_COUNTER               ; E2                ; Untyped                       ;
; EXTCLK1_COUNTER               ; E1                ; Untyped                       ;
; EXTCLK0_COUNTER               ; E0                ; Untyped                       ;
; ENABLE0_COUNTER               ; L0                ; Untyped                       ;
; ENABLE1_COUNTER               ; L0                ; Untyped                       ;
; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                       ;
; LOOP_FILTER_R                 ;  1.000000         ; Untyped                       ;
; LOOP_FILTER_C                 ; 5                 ; Untyped                       ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                       ;
; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                       ;
; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                       ;
; VCO_POST_SCALE                ; 0                 ; Untyped                       ;
; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                       ;
; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                       ;
; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                       ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II        ; Untyped                       ;
; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLKENA0               ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLKENA1               ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLKENA2               ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLKENA3               ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLK0                     ; PORT_USED         ; Untyped                       ;
; PORT_CLK1                     ; PORT_USED         ; Untyped                       ;
; PORT_CLK2                     ; PORT_USED         ; Untyped                       ;
; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLK6                     ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_CLK7                     ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_CLK8                     ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_CLK9                     ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCLKOUT1                 ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCLKOUT0                 ; PORT_UNUSED       ; Untyped                       ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                       ;
; PORT_INCLK0                   ; PORT_USED         ; Untyped                       ;
; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                       ;
; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                       ;
; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                       ;
; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                       ;
; PORT_ENABLE0                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_ENABLE1                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_LOCKED                   ; PORT_UNUSED       ; Untyped                       ;
; PORT_CONFIGUPDATE             ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_PHASEDONE                ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_PHASESTEP                ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_PHASEUPDOWN              ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_SCANCLKENA               ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_PHASECOUNTERSELECT       ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                       ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                       ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C6_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C7_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C8_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C9_TEST_SOURCE                ; 5                 ; Untyped                       ;
; CBXI_PARAMETER                ; NOTHING           ; Untyped                       ;
; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                       ;
; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                       ;
; WIDTH_CLOCK                   ; 6                 ; Untyped                       ;
; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                       ;
; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                       ;
; DEVICE_FAMILY                 ; Cyclone II        ; Untyped                       ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped                       ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                    ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                  ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                  ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                ;
+-------------------------------+-------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data ;
+----------------+--------+--------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                     ;
+----------------+--------+--------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                   ;
+----------------+--------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                             ;
+------------------------------------+----------------------+------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                          ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                       ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                     ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                   ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                          ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                          ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                   ;
; WIDTHAD_A                          ; 10                   ; Signed Integer                                                   ;
; NUMWORDS_A                         ; 1024                 ; Signed Integer                                                   ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                          ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                          ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                          ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                          ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                          ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                          ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                   ;
; WIDTHAD_B                          ; 10                   ; Signed Integer                                                   ;
; NUMWORDS_B                         ; 1024                 ; Signed Integer                                                   ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                          ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                          ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                          ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                          ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                          ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                          ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                          ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                          ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                          ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                          ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                          ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                          ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                          ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                          ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                          ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                          ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                          ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                          ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                          ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                          ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                          ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                          ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                          ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                          ;
; CBXI_PARAMETER                     ; altsyncram_qed1      ; Untyped                                                          ;
+------------------------------------+----------------------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag ;
+----------------+--------------------+------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                       ;
+----------------+--------------------+------------------------------------------------------------+
; lpm_file       ; cpu_ic_tag_ram.mif ; String                                                     ;
+----------------+--------------------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+----------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                           ;
+------------------------------------+----------------------+----------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                        ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                 ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                        ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                        ;
; WIDTH_A                            ; 21                   ; Signed Integer                                                 ;
; WIDTHAD_A                          ; 7                    ; Signed Integer                                                 ;
; NUMWORDS_A                         ; 128                  ; Signed Integer                                                 ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                        ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                        ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                        ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                        ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                        ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                        ;
; WIDTH_B                            ; 21                   ; Signed Integer                                                 ;
; WIDTHAD_B                          ; 7                    ; Signed Integer                                                 ;
; NUMWORDS_B                         ; 128                  ; Signed Integer                                                 ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                        ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                        ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                        ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                        ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                        ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                        ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                        ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                        ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                        ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                        ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                        ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                        ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                        ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                        ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                        ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                        ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                        ;
; INIT_FILE                          ; cpu_ic_tag_ram.mif   ; Untyped                                                        ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                        ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                        ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                        ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                        ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                        ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                        ;
; CBXI_PARAMETER                     ; altsyncram_u0g1      ; Untyped                                                        ;
+------------------------------------+----------------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht ;
+----------------+-----------------+---------------------------------------------------------+
; Parameter Name ; Value           ; Type                                                    ;
+----------------+-----------------+---------------------------------------------------------+
; lpm_file       ; cpu_bht_ram.mif ; String                                                  ;
+----------------+-----------------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+----------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                     ;
+------------------------------------+----------------------+----------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                  ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                               ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                             ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                             ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                           ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                  ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                  ;
; WIDTH_A                            ; 2                    ; Signed Integer                                           ;
; WIDTHAD_A                          ; 8                    ; Signed Integer                                           ;
; NUMWORDS_A                         ; 256                  ; Signed Integer                                           ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                  ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                  ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                  ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                  ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                  ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                  ;
; WIDTH_B                            ; 2                    ; Signed Integer                                           ;
; WIDTHAD_B                          ; 8                    ; Signed Integer                                           ;
; NUMWORDS_B                         ; 256                  ; Signed Integer                                           ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                  ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                  ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                  ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                  ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                  ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                  ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                  ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                  ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                  ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                  ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                  ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                  ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                  ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                  ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                  ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                  ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                  ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                  ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                  ;
; INIT_FILE                          ; cpu_bht_ram.mif      ; Untyped                                                  ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                  ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                           ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                  ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                  ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                  ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                  ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                  ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                  ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                  ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                  ;
; CBXI_PARAMETER                     ; altsyncram_pkf1      ; Untyped                                                  ;
+------------------------------------+----------------------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a ;
+----------------+------------------+--------------------------------------------------------------------------------+
; Parameter Name ; Value            ; Type                                                                           ;
+----------------+------------------+--------------------------------------------------------------------------------+
; lpm_file       ; cpu_rf_ram_a.mif ; String                                                                         ;
+----------------+------------------+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                             ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                          ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                       ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                     ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                   ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                          ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                          ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                   ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                                                                   ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                                                                   ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                          ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                          ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                          ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                          ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                          ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                          ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                   ;
; WIDTHAD_B                          ; 5                    ; Signed Integer                                                                   ;
; NUMWORDS_B                         ; 32                   ; Signed Integer                                                                   ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                          ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                                          ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                          ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                          ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                          ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                          ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                          ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                          ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                          ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                          ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                          ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                          ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                          ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                          ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                          ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                          ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                          ;
; INIT_FILE                          ; cpu_rf_ram_a.mif     ; Untyped                                                                          ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                          ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                          ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                          ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                          ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                                          ;
; CBXI_PARAMETER                     ; altsyncram_p2f1      ; Untyped                                                                          ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b ;
+----------------+------------------+--------------------------------------------------------------------------------+
; Parameter Name ; Value            ; Type                                                                           ;
+----------------+------------------+--------------------------------------------------------------------------------+
; lpm_file       ; cpu_rf_ram_b.mif ; String                                                                         ;
+----------------+------------------+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                             ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                          ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                       ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                     ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                   ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                          ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                          ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                   ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                                                                   ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                                                                   ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                          ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                          ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                          ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                          ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                          ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                          ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                   ;
; WIDTHAD_B                          ; 5                    ; Signed Integer                                                                   ;
; NUMWORDS_B                         ; 32                   ; Signed Integer                                                                   ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                          ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                                          ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                          ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                          ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                          ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                          ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                          ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                          ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                          ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                          ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                          ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                          ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                          ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                          ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                          ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                          ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                          ;
; INIT_FILE                          ; cpu_rf_ram_b.mif     ; Untyped                                                                          ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                          ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                          ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                          ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                          ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                                          ;
; CBXI_PARAMETER                     ; altsyncram_q2f1      ; Untyped                                                                          ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag ;
+----------------+--------------------+------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                       ;
+----------------+--------------------+------------------------------------------------------------+
; lpm_file       ; cpu_dc_tag_ram.mif ; String                                                     ;
+----------------+--------------------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+----------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                           ;
+------------------------------------+----------------------+----------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                        ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                 ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                        ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                        ;
; WIDTH_A                            ; 16                   ; Signed Integer                                                 ;
; WIDTHAD_A                          ; 6                    ; Signed Integer                                                 ;
; NUMWORDS_A                         ; 64                   ; Signed Integer                                                 ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                        ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                        ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                        ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                        ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                        ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                        ;
; WIDTH_B                            ; 16                   ; Signed Integer                                                 ;
; WIDTHAD_B                          ; 6                    ; Signed Integer                                                 ;
; NUMWORDS_B                         ; 64                   ; Signed Integer                                                 ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                        ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                        ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                        ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                        ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                        ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                        ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                        ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                        ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                        ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                        ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                        ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                        ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                        ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                        ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                        ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                        ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                        ;
; INIT_FILE                          ; cpu_dc_tag_ram.mif   ; Untyped                                                        ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                        ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                        ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                        ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                        ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                        ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                        ;
; CBXI_PARAMETER                     ; altsyncram_j9f1      ; Untyped                                                        ;
+------------------------------------+----------------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data ;
+----------------+--------+--------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                     ;
+----------------+--------+--------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                   ;
+----------------+--------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                             ;
+------------------------------------+----------------------+------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                          ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                       ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                     ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                   ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                          ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                          ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                   ;
; WIDTHAD_A                          ; 9                    ; Signed Integer                                                   ;
; NUMWORDS_A                         ; 512                  ; Signed Integer                                                   ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                          ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                          ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                          ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                          ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                          ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                          ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                   ;
; WIDTHAD_B                          ; 9                    ; Signed Integer                                                   ;
; NUMWORDS_B                         ; 512                  ; Signed Integer                                                   ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                          ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                          ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                          ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                          ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                          ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                          ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                          ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                          ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                          ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                          ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                          ;
; WIDTH_BYTEENA_A                    ; 4                    ; Signed Integer                                                   ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                          ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                          ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                          ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                          ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                          ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                          ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                          ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                          ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                          ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                          ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                          ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                          ;
; CBXI_PARAMETER                     ; altsyncram_29f1      ; Untyped                                                          ;
+------------------------------------+----------------------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim ;
+----------------+--------+------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                         ;
+----------------+--------+------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                       ;
+----------------+--------+------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+----------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                 ;
+------------------------------------+----------------------+----------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                              ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                       ;
; WIDTHAD_A                          ; 3                    ; Signed Integer                                                       ;
; NUMWORDS_A                         ; 8                    ; Signed Integer                                                       ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                              ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                       ;
; WIDTHAD_B                          ; 3                    ; Signed Integer                                                       ;
; NUMWORDS_B                         ; 8                    ; Signed Integer                                                       ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                              ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                              ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                       ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                              ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                              ;
; CBXI_PARAMETER                     ; altsyncram_9vc1      ; Untyped                                                              ;
+------------------------------------+----------------------+----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1 ;
+---------------------------------------+-------------------+----------------------------------------------------------------------------+
; Parameter Name                        ; Value             ; Type                                                                       ;
+---------------------------------------+-------------------+----------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON                ; AUTO_CARRY                                                                 ;
; IGNORE_CARRY_BUFFERS                  ; OFF               ; IGNORE_CARRY                                                               ;
; AUTO_CASCADE_CHAINS                   ; ON                ; AUTO_CASCADE                                                               ;
; IGNORE_CASCADE_BUFFERS                ; OFF               ; IGNORE_CASCADE                                                             ;
; ACCUM_DIRECTION                       ; ADD               ; Untyped                                                                    ;
; ACCUM_SLOAD_ACLR                      ; ACLR3             ; Untyped                                                                    ;
; ACCUM_SLOAD_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                    ;
; ACCUM_SLOAD_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                    ;
; ACCUM_SLOAD_REGISTER                  ; CLOCK0            ; Untyped                                                                    ;
; ACCUMULATOR                           ; NO                ; Untyped                                                                    ;
; ADDER1_ROUNDING                       ; NO                ; Untyped                                                                    ;
; ADDER3_ROUNDING                       ; NO                ; Untyped                                                                    ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR0             ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; UNREGISTERED      ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_ACLR                         ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_ADDER                        ; NO                ; Untyped                                                                    ;
; CHAINOUT_REGISTER                     ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_ROUND_OUTPUT_ACLR            ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_ROUND_OUTPUT_REGISTER        ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_ROUNDING                     ; NO                ; Untyped                                                                    ;
; CHAINOUT_SATURATE_ACLR                ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_SATURATE_OUTPUT_ACLR         ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_SATURATE_OUTPUT_REGISTER     ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_SATURATE_PIPELINE_ACLR       ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_SATURATE_PIPELINE_REGISTER   ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_SATURATE_REGISTER            ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_SATURATION                   ; NO                ; Untyped                                                                    ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; YES               ; Untyped                                                                    ;
; DSP_BLOCK_BALANCING                   ; AUTO              ; Untyped                                                                    ;
; EXTRA_LATENCY                         ; 0                 ; Untyped                                                                    ;
; INPUT_ACLR_A0                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_A1                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_A2                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_A3                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_B0                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_B1                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_B2                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_B3                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_REGISTER_A0                     ; UNREGISTERED      ; Untyped                                                                    ;
; INPUT_REGISTER_A1                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_REGISTER_A2                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_REGISTER_A3                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_REGISTER_B0                     ; UNREGISTERED      ; Untyped                                                                    ;
; INPUT_REGISTER_B1                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_REGISTER_B2                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_REGISTER_B3                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_SOURCE_A0                       ; DATAA             ; Untyped                                                                    ;
; INPUT_SOURCE_A1                       ; DATAA             ; Untyped                                                                    ;
; INPUT_SOURCE_A2                       ; DATAA             ; Untyped                                                                    ;
; INPUT_SOURCE_A3                       ; DATAA             ; Untyped                                                                    ;
; INPUT_SOURCE_B0                       ; DATAB             ; Untyped                                                                    ;
; INPUT_SOURCE_B1                       ; DATAB             ; Untyped                                                                    ;
; INPUT_SOURCE_B2                       ; DATAB             ; Untyped                                                                    ;
; INPUT_SOURCE_B3                       ; DATAB             ; Untyped                                                                    ;
; MULT01_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                    ;
; MULT01_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                    ;
; MULT01_SATURATION_ACLR                ; ACLR2             ; Untyped                                                                    ;
; MULT01_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                    ;
; MULT23_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                    ;
; MULT23_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                    ;
; MULT23_SATURATION_ACLR                ; ACLR3             ; Untyped                                                                    ;
; MULT23_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                    ;
; MULTIPLIER01_ROUNDING                 ; NO                ; Untyped                                                                    ;
; MULTIPLIER01_SATURATION               ; NO                ; Untyped                                                                    ;
; MULTIPLIER1_DIRECTION                 ; ADD               ; Untyped                                                                    ;
; MULTIPLIER23_ROUNDING                 ; NO                ; Untyped                                                                    ;
; MULTIPLIER23_SATURATION               ; NO                ; Untyped                                                                    ;
; MULTIPLIER3_DIRECTION                 ; ADD               ; Untyped                                                                    ;
; MULTIPLIER_ACLR0                      ; ACLR0             ; Untyped                                                                    ;
; MULTIPLIER_ACLR1                      ; ACLR3             ; Untyped                                                                    ;
; MULTIPLIER_ACLR2                      ; ACLR3             ; Untyped                                                                    ;
; MULTIPLIER_ACLR3                      ; ACLR3             ; Untyped                                                                    ;
; MULTIPLIER_REGISTER0                  ; CLOCK0            ; Untyped                                                                    ;
; MULTIPLIER_REGISTER1                  ; CLOCK0            ; Untyped                                                                    ;
; MULTIPLIER_REGISTER2                  ; CLOCK0            ; Untyped                                                                    ;
; MULTIPLIER_REGISTER3                  ; CLOCK0            ; Untyped                                                                    ;
; NUMBER_OF_MULTIPLIERS                 ; 1                 ; Signed Integer                                                             ;
; OUTPUT_ACLR                           ; ACLR3             ; Untyped                                                                    ;
; OUTPUT_REGISTER                       ; UNREGISTERED      ; Untyped                                                                    ;
; OUTPUT_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                    ;
; OUTPUT_ROUND_PIPELINE_ACLR            ; ACLR3             ; Untyped                                                                    ;
; OUTPUT_ROUND_PIPELINE_REGISTER        ; CLOCK0            ; Untyped                                                                    ;
; OUTPUT_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                    ;
; OUTPUT_ROUND_TYPE                     ; NEAREST_INTEGER   ; Untyped                                                                    ;
; OUTPUT_ROUNDING                       ; NO                ; Untyped                                                                    ;
; OUTPUT_SATURATE_ACLR                  ; ACLR3             ; Untyped                                                                    ;
; OUTPUT_SATURATE_PIPELINE_ACLR         ; ACLR3             ; Untyped                                                                    ;
; OUTPUT_SATURATE_PIPELINE_REGISTER     ; CLOCK0            ; Untyped                                                                    ;
; OUTPUT_SATURATE_REGISTER              ; CLOCK0            ; Untyped                                                                    ;
; OUTPUT_SATURATE_TYPE                  ; ASYMMETRIC        ; Untyped                                                                    ;
; OUTPUT_SATURATION                     ; NO                ; Untyped                                                                    ;
; port_addnsub1                         ; PORT_UNUSED       ; Untyped                                                                    ;
; port_addnsub3                         ; PORT_CONNECTIVITY ; Untyped                                                                    ;
; PORT_CHAINOUT_SAT_IS_OVERFLOW         ; PORT_UNUSED       ; Untyped                                                                    ;
; PORT_MULT0_IS_SATURATED               ; UNUSED            ; Untyped                                                                    ;
; PORT_MULT1_IS_SATURATED               ; UNUSED            ; Untyped                                                                    ;
; PORT_MULT2_IS_SATURATED               ; UNUSED            ; Untyped                                                                    ;
; PORT_MULT3_IS_SATURATED               ; UNUSED            ; Untyped                                                                    ;
; PORT_OUTPUT_IS_OVERFLOW               ; PORT_UNUSED       ; Untyped                                                                    ;
; port_signa                            ; PORT_UNUSED       ; Untyped                                                                    ;
; port_signb                            ; PORT_UNUSED       ; Untyped                                                                    ;
; REPRESENTATION_A                      ; UNSIGNED          ; Untyped                                                                    ;
; REPRESENTATION_B                      ; UNSIGNED          ; Untyped                                                                    ;
; ROTATE_ACLR                           ; ACLR3             ; Untyped                                                                    ;
; ROTATE_OUTPUT_ACLR                    ; ACLR3             ; Untyped                                                                    ;
; ROTATE_OUTPUT_REGISTER                ; CLOCK0            ; Untyped                                                                    ;
; ROTATE_PIPELINE_ACLR                  ; ACLR3             ; Untyped                                                                    ;
; ROTATE_PIPELINE_REGISTER              ; CLOCK0            ; Untyped                                                                    ;
; ROTATE_REGISTER                       ; CLOCK0            ; Untyped                                                                    ;
; WIDTH_MSB                             ; 17                ; Untyped                                                                    ;
; WIDTH_SATURATE_SIGN                   ; 1                 ; Untyped                                                                    ;
; SCANOUTA_ACLR                         ; ACLR3             ; Untyped                                                                    ;
; SCANOUTA_REGISTER                     ; UNREGISTERED      ; Untyped                                                                    ;
; SHIFT_MODE                            ; NO                ; Untyped                                                                    ;
; SHIFT_RIGHT_ACLR                      ; ACLR3             ; Untyped                                                                    ;
; SHIFT_RIGHT_OUTPUT_ACLR               ; ACLR3             ; Untyped                                                                    ;
; SHIFT_RIGHT_OUTPUT_REGISTER           ; CLOCK0            ; Untyped                                                                    ;
; SHIFT_RIGHT_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                    ;
; SHIFT_RIGHT_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                    ;
; SHIFT_RIGHT_REGISTER                  ; CLOCK0            ; Untyped                                                                    ;
; SIGNED_ACLR_A                         ; ACLR3             ; Untyped                                                                    ;
; SIGNED_ACLR_B                         ; ACLR3             ; Untyped                                                                    ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR0             ; Untyped                                                                    ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR0             ; Untyped                                                                    ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0            ; Untyped                                                                    ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0            ; Untyped                                                                    ;
; SIGNED_REGISTER_A                     ; UNREGISTERED      ; Untyped                                                                    ;
; SIGNED_REGISTER_B                     ; UNREGISTERED      ; Untyped                                                                    ;
; WIDTH_A                               ; 16                ; Signed Integer                                                             ;
; WIDTH_B                               ; 16                ; Signed Integer                                                             ;
; WIDTH_CHAININ                         ; 1                 ; Untyped                                                                    ;
; WIDTH_RESULT                          ; 32                ; Signed Integer                                                             ;
; ZERO_CHAINOUT_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                    ;
; ZERO_CHAINOUT_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                    ;
; ZERO_LOOPBACK_ACLR                    ; ACLR3             ; Untyped                                                                    ;
; ZERO_LOOPBACK_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                    ;
; ZERO_LOOPBACK_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                    ;
; ZERO_LOOPBACK_PIPELINE_ACLR           ; ACLR3             ; Untyped                                                                    ;
; ZERO_LOOPBACK_PIPELINE_REGISTER       ; CLOCK0            ; Untyped                                                                    ;
; ZERO_LOOPBACK_REGISTER                ; CLOCK0            ; Untyped                                                                    ;
; CBXI_PARAMETER                        ; mult_add_4cr2     ; Untyped                                                                    ;
; DEVICE_FAMILY                         ; Cyclone II        ; Untyped                                                                    ;
+---------------------------------------+-------------------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2 ;
+---------------------------------------+-------------------+----------------------------------------------------------------------------+
; Parameter Name                        ; Value             ; Type                                                                       ;
+---------------------------------------+-------------------+----------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON                ; AUTO_CARRY                                                                 ;
; IGNORE_CARRY_BUFFERS                  ; OFF               ; IGNORE_CARRY                                                               ;
; AUTO_CASCADE_CHAINS                   ; ON                ; AUTO_CASCADE                                                               ;
; IGNORE_CASCADE_BUFFERS                ; OFF               ; IGNORE_CASCADE                                                             ;
; ACCUM_DIRECTION                       ; ADD               ; Untyped                                                                    ;
; ACCUM_SLOAD_ACLR                      ; ACLR3             ; Untyped                                                                    ;
; ACCUM_SLOAD_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                    ;
; ACCUM_SLOAD_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                    ;
; ACCUM_SLOAD_REGISTER                  ; CLOCK0            ; Untyped                                                                    ;
; ACCUMULATOR                           ; NO                ; Untyped                                                                    ;
; ADDER1_ROUNDING                       ; NO                ; Untyped                                                                    ;
; ADDER3_ROUNDING                       ; NO                ; Untyped                                                                    ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR0             ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3             ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0            ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; UNREGISTERED      ; Untyped                                                                    ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_ACLR                         ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_ADDER                        ; NO                ; Untyped                                                                    ;
; CHAINOUT_REGISTER                     ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_ROUND_OUTPUT_ACLR            ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_ROUND_OUTPUT_REGISTER        ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_ROUNDING                     ; NO                ; Untyped                                                                    ;
; CHAINOUT_SATURATE_ACLR                ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_SATURATE_OUTPUT_ACLR         ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_SATURATE_OUTPUT_REGISTER     ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_SATURATE_PIPELINE_ACLR       ; ACLR3             ; Untyped                                                                    ;
; CHAINOUT_SATURATE_PIPELINE_REGISTER   ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_SATURATE_REGISTER            ; CLOCK0            ; Untyped                                                                    ;
; CHAINOUT_SATURATION                   ; NO                ; Untyped                                                                    ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; YES               ; Untyped                                                                    ;
; DSP_BLOCK_BALANCING                   ; AUTO              ; Untyped                                                                    ;
; EXTRA_LATENCY                         ; 0                 ; Untyped                                                                    ;
; INPUT_ACLR_A0                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_A1                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_A2                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_A3                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_B0                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_B1                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_B2                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_ACLR_B3                         ; ACLR3             ; Untyped                                                                    ;
; INPUT_REGISTER_A0                     ; UNREGISTERED      ; Untyped                                                                    ;
; INPUT_REGISTER_A1                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_REGISTER_A2                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_REGISTER_A3                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_REGISTER_B0                     ; UNREGISTERED      ; Untyped                                                                    ;
; INPUT_REGISTER_B1                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_REGISTER_B2                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_REGISTER_B3                     ; CLOCK0            ; Untyped                                                                    ;
; INPUT_SOURCE_A0                       ; DATAA             ; Untyped                                                                    ;
; INPUT_SOURCE_A1                       ; DATAA             ; Untyped                                                                    ;
; INPUT_SOURCE_A2                       ; DATAA             ; Untyped                                                                    ;
; INPUT_SOURCE_A3                       ; DATAA             ; Untyped                                                                    ;
; INPUT_SOURCE_B0                       ; DATAB             ; Untyped                                                                    ;
; INPUT_SOURCE_B1                       ; DATAB             ; Untyped                                                                    ;
; INPUT_SOURCE_B2                       ; DATAB             ; Untyped                                                                    ;
; INPUT_SOURCE_B3                       ; DATAB             ; Untyped                                                                    ;
; MULT01_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                    ;
; MULT01_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                    ;
; MULT01_SATURATION_ACLR                ; ACLR2             ; Untyped                                                                    ;
; MULT01_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                    ;
; MULT23_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                    ;
; MULT23_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                    ;
; MULT23_SATURATION_ACLR                ; ACLR3             ; Untyped                                                                    ;
; MULT23_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                    ;
; MULTIPLIER01_ROUNDING                 ; NO                ; Untyped                                                                    ;
; MULTIPLIER01_SATURATION               ; NO                ; Untyped                                                                    ;
; MULTIPLIER1_DIRECTION                 ; ADD               ; Untyped                                                                    ;
; MULTIPLIER23_ROUNDING                 ; NO                ; Untyped                                                                    ;
; MULTIPLIER23_SATURATION               ; NO                ; Untyped                                                                    ;
; MULTIPLIER3_DIRECTION                 ; ADD               ; Untyped                                                                    ;
; MULTIPLIER_ACLR0                      ; ACLR0             ; Untyped                                                                    ;
; MULTIPLIER_ACLR1                      ; ACLR3             ; Untyped                                                                    ;
; MULTIPLIER_ACLR2                      ; ACLR3             ; Untyped                                                                    ;
; MULTIPLIER_ACLR3                      ; ACLR3             ; Untyped                                                                    ;
; MULTIPLIER_REGISTER0                  ; CLOCK0            ; Untyped                                                                    ;
; MULTIPLIER_REGISTER1                  ; CLOCK0            ; Untyped                                                                    ;
; MULTIPLIER_REGISTER2                  ; CLOCK0            ; Untyped                                                                    ;
; MULTIPLIER_REGISTER3                  ; CLOCK0            ; Untyped                                                                    ;
; NUMBER_OF_MULTIPLIERS                 ; 1                 ; Signed Integer                                                             ;
; OUTPUT_ACLR                           ; ACLR3             ; Untyped                                                                    ;
; OUTPUT_REGISTER                       ; UNREGISTERED      ; Untyped                                                                    ;
; OUTPUT_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                    ;
; OUTPUT_ROUND_PIPELINE_ACLR            ; ACLR3             ; Untyped                                                                    ;
; OUTPUT_ROUND_PIPELINE_REGISTER        ; CLOCK0            ; Untyped                                                                    ;
; OUTPUT_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                    ;
; OUTPUT_ROUND_TYPE                     ; NEAREST_INTEGER   ; Untyped                                                                    ;
; OUTPUT_ROUNDING                       ; NO                ; Untyped                                                                    ;
; OUTPUT_SATURATE_ACLR                  ; ACLR3             ; Untyped                                                                    ;
; OUTPUT_SATURATE_PIPELINE_ACLR         ; ACLR3             ; Untyped                                                                    ;
; OUTPUT_SATURATE_PIPELINE_REGISTER     ; CLOCK0            ; Untyped                                                                    ;
; OUTPUT_SATURATE_REGISTER              ; CLOCK0            ; Untyped                                                                    ;
; OUTPUT_SATURATE_TYPE                  ; ASYMMETRIC        ; Untyped                                                                    ;
; OUTPUT_SATURATION                     ; NO                ; Untyped                                                                    ;
; port_addnsub1                         ; PORT_UNUSED       ; Untyped                                                                    ;
; port_addnsub3                         ; PORT_CONNECTIVITY ; Untyped                                                                    ;
; PORT_CHAINOUT_SAT_IS_OVERFLOW         ; PORT_UNUSED       ; Untyped                                                                    ;
; PORT_MULT0_IS_SATURATED               ; UNUSED            ; Untyped                                                                    ;
; PORT_MULT1_IS_SATURATED               ; UNUSED            ; Untyped                                                                    ;
; PORT_MULT2_IS_SATURATED               ; UNUSED            ; Untyped                                                                    ;
; PORT_MULT3_IS_SATURATED               ; UNUSED            ; Untyped                                                                    ;
; PORT_OUTPUT_IS_OVERFLOW               ; PORT_UNUSED       ; Untyped                                                                    ;
; port_signa                            ; PORT_UNUSED       ; Untyped                                                                    ;
; port_signb                            ; PORT_UNUSED       ; Untyped                                                                    ;
; REPRESENTATION_A                      ; UNSIGNED          ; Untyped                                                                    ;
; REPRESENTATION_B                      ; UNSIGNED          ; Untyped                                                                    ;
; ROTATE_ACLR                           ; ACLR3             ; Untyped                                                                    ;
; ROTATE_OUTPUT_ACLR                    ; ACLR3             ; Untyped                                                                    ;
; ROTATE_OUTPUT_REGISTER                ; CLOCK0            ; Untyped                                                                    ;
; ROTATE_PIPELINE_ACLR                  ; ACLR3             ; Untyped                                                                    ;
; ROTATE_PIPELINE_REGISTER              ; CLOCK0            ; Untyped                                                                    ;
; ROTATE_REGISTER                       ; CLOCK0            ; Untyped                                                                    ;
; WIDTH_MSB                             ; 17                ; Untyped                                                                    ;
; WIDTH_SATURATE_SIGN                   ; 1                 ; Untyped                                                                    ;
; SCANOUTA_ACLR                         ; ACLR3             ; Untyped                                                                    ;
; SCANOUTA_REGISTER                     ; UNREGISTERED      ; Untyped                                                                    ;
; SHIFT_MODE                            ; NO                ; Untyped                                                                    ;
; SHIFT_RIGHT_ACLR                      ; ACLR3             ; Untyped                                                                    ;
; SHIFT_RIGHT_OUTPUT_ACLR               ; ACLR3             ; Untyped                                                                    ;
; SHIFT_RIGHT_OUTPUT_REGISTER           ; CLOCK0            ; Untyped                                                                    ;
; SHIFT_RIGHT_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                    ;
; SHIFT_RIGHT_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                    ;
; SHIFT_RIGHT_REGISTER                  ; CLOCK0            ; Untyped                                                                    ;
; SIGNED_ACLR_A                         ; ACLR3             ; Untyped                                                                    ;
; SIGNED_ACLR_B                         ; ACLR3             ; Untyped                                                                    ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR0             ; Untyped                                                                    ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR0             ; Untyped                                                                    ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0            ; Untyped                                                                    ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0            ; Untyped                                                                    ;
; SIGNED_REGISTER_A                     ; UNREGISTERED      ; Untyped                                                                    ;
; SIGNED_REGISTER_B                     ; UNREGISTERED      ; Untyped                                                                    ;
; WIDTH_A                               ; 16                ; Signed Integer                                                             ;
; WIDTH_B                               ; 16                ; Signed Integer                                                             ;
; WIDTH_CHAININ                         ; 1                 ; Untyped                                                                    ;
; WIDTH_RESULT                          ; 16                ; Signed Integer                                                             ;
; ZERO_CHAINOUT_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                    ;
; ZERO_CHAINOUT_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                    ;
; ZERO_LOOPBACK_ACLR                    ; ACLR3             ; Untyped                                                                    ;
; ZERO_LOOPBACK_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                    ;
; ZERO_LOOPBACK_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                    ;
; ZERO_LOOPBACK_PIPELINE_ACLR           ; ACLR3             ; Untyped                                                                    ;
; ZERO_LOOPBACK_PIPELINE_REGISTER       ; CLOCK0            ; Untyped                                                                    ;
; ZERO_LOOPBACK_REGISTER                ; CLOCK0            ; Untyped                                                                    ;
; CBXI_PARAMETER                        ; mult_add_6cr2     ; Untyped                                                                    ;
; DEVICE_FAMILY                         ; Cyclone II        ; Untyped                                                                    ;
+---------------------------------------+-------------------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component ;
+----------------+---------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value                           ; Type                                                                                                                                                              ;
+----------------+---------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; cpu_ociram_default_contents.mif ; String                                                                                                                                                            ;
+----------------+---------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+---------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                           ; Type                                                                                                                                                                    ;
+------------------------------------+---------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                               ; Untyped                                                                                                                                                                 ;
; AUTO_CARRY_CHAINS                  ; ON                              ; AUTO_CARRY                                                                                                                                                              ;
; IGNORE_CARRY_BUFFERS               ; OFF                             ; IGNORE_CARRY                                                                                                                                                            ;
; AUTO_CASCADE_CHAINS                ; ON                              ; AUTO_CASCADE                                                                                                                                                            ;
; IGNORE_CASCADE_BUFFERS             ; OFF                             ; IGNORE_CASCADE                                                                                                                                                          ;
; WIDTH_BYTEENA                      ; 1                               ; Untyped                                                                                                                                                                 ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT                 ; Untyped                                                                                                                                                                 ;
; WIDTH_A                            ; 32                              ; Signed Integer                                                                                                                                                          ;
; WIDTHAD_A                          ; 8                               ; Signed Integer                                                                                                                                                          ;
; NUMWORDS_A                         ; 256                             ; Signed Integer                                                                                                                                                          ;
; OUTDATA_REG_A                      ; UNREGISTERED                    ; Untyped                                                                                                                                                                 ;
; ADDRESS_ACLR_A                     ; NONE                            ; Untyped                                                                                                                                                                 ;
; OUTDATA_ACLR_A                     ; NONE                            ; Untyped                                                                                                                                                                 ;
; WRCONTROL_ACLR_A                   ; NONE                            ; Untyped                                                                                                                                                                 ;
; INDATA_ACLR_A                      ; NONE                            ; Untyped                                                                                                                                                                 ;
; BYTEENA_ACLR_A                     ; NONE                            ; Untyped                                                                                                                                                                 ;
; WIDTH_B                            ; 32                              ; Signed Integer                                                                                                                                                          ;
; WIDTHAD_B                          ; 8                               ; Signed Integer                                                                                                                                                          ;
; NUMWORDS_B                         ; 256                             ; Signed Integer                                                                                                                                                          ;
; INDATA_REG_B                       ; CLOCK1                          ; Untyped                                                                                                                                                                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                          ; Untyped                                                                                                                                                                 ;
; RDCONTROL_REG_B                    ; CLOCK1                          ; Untyped                                                                                                                                                                 ;
; ADDRESS_REG_B                      ; CLOCK1                          ; Untyped                                                                                                                                                                 ;
; OUTDATA_REG_B                      ; UNREGISTERED                    ; Untyped                                                                                                                                                                 ;
; BYTEENA_REG_B                      ; CLOCK1                          ; Untyped                                                                                                                                                                 ;
; INDATA_ACLR_B                      ; NONE                            ; Untyped                                                                                                                                                                 ;
; WRCONTROL_ACLR_B                   ; NONE                            ; Untyped                                                                                                                                                                 ;
; ADDRESS_ACLR_B                     ; NONE                            ; Untyped                                                                                                                                                                 ;
; OUTDATA_ACLR_B                     ; NONE                            ; Untyped                                                                                                                                                                 ;
; RDCONTROL_ACLR_B                   ; NONE                            ; Untyped                                                                                                                                                                 ;
; BYTEENA_ACLR_B                     ; NONE                            ; Untyped                                                                                                                                                                 ;
; WIDTH_BYTEENA_A                    ; 4                               ; Signed Integer                                                                                                                                                          ;
; WIDTH_BYTEENA_B                    ; 1                               ; Untyped                                                                                                                                                                 ;
; RAM_BLOCK_TYPE                     ; AUTO                            ; Untyped                                                                                                                                                                 ;
; BYTE_SIZE                          ; 8                               ; Untyped                                                                                                                                                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                        ; Untyped                                                                                                                                                                 ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ            ; Untyped                                                                                                                                                                 ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ            ; Untyped                                                                                                                                                                 ;
; INIT_FILE                          ; cpu_ociram_default_contents.mif ; Untyped                                                                                                                                                                 ;
; INIT_FILE_LAYOUT                   ; PORT_A                          ; Untyped                                                                                                                                                                 ;
; MAXIMUM_DEPTH                      ; 0                               ; Untyped                                                                                                                                                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                          ; Untyped                                                                                                                                                                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                          ; Untyped                                                                                                                                                                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                          ; Untyped                                                                                                                                                                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                          ; Untyped                                                                                                                                                                 ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                 ; Untyped                                                                                                                                                                 ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                 ; Untyped                                                                                                                                                                 ;
; ENABLE_ECC                         ; FALSE                           ; Untyped                                                                                                                                                                 ;
; DEVICE_FAMILY                      ; Cyclone II                      ; Untyped                                                                                                                                                                 ;
; CBXI_PARAMETER                     ; altsyncram_t072                 ; Untyped                                                                                                                                                                 ;
+------------------------------------+---------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component ;
+----------------+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                           ;
+----------------+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                                                                                                                                         ;
+----------------+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                   ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                             ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                           ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                           ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                         ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT      ; Untyped                                                                                                                                                                                ;
; WIDTH_A                            ; 36                   ; Signed Integer                                                                                                                                                                         ;
; WIDTHAD_A                          ; 7                    ; Signed Integer                                                                                                                                                                         ;
; NUMWORDS_A                         ; 128                  ; Signed Integer                                                                                                                                                                         ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                ;
; WIDTH_B                            ; 36                   ; Signed Integer                                                                                                                                                                         ;
; WIDTHAD_B                          ; 7                    ; Signed Integer                                                                                                                                                                         ;
; NUMWORDS_B                         ; 128                  ; Signed Integer                                                                                                                                                                         ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                                                                                ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                                                                                                                ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                                                                                                                                                ;
; CBXI_PARAMETER                     ; altsyncram_e502      ; Untyped                                                                                                                                                                                ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1 ;
+-------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value     ; Type                                                                                                                                                                           ;
+-------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SLD_AUTO_INSTANCE_INDEX ; YES       ; String                                                                                                                                                                         ;
; SLD_NODE_INFO           ; 286279168 ; Signed Integer                                                                                                                                                                 ;
+-------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                           ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                 ;
; lpm_width               ; 8           ; Signed Integer                                                                                 ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                                 ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                        ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                        ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                        ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                        ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                        ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                        ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                                        ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                        ;
; CBXI_PARAMETER          ; scfifo_1n21 ; Untyped                                                                                        ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                           ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                 ;
; lpm_width               ; 8           ; Signed Integer                                                                                 ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                                 ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                        ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                        ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                        ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                        ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                        ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                        ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                                        ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                        ;
; CBXI_PARAMETER          ; scfifo_1n21 ; Untyped                                                                                        ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic ;
+-------------------+----------------------------------+------------------------------------------------------------------------+
; Parameter Name    ; Value                            ; Type                                                                   ;
+-------------------+----------------------------------+------------------------------------------------------------------------+
; INSTANCE_ID       ; 0                                ; Signed Integer                                                         ;
; SLD_NODE_INFO     ; 00001100000000000110111000000000 ; Unsigned Binary                                                        ;
; LOG2_TXFIFO_DEPTH ; 6                                ; Signed Integer                                                         ;
; LOG2_RXFIFO_DEPTH ; 6                                ; Signed Integer                                                         ;
; RESERVED          ; 0                                ; Signed Integer                                                         ;
; DATA_WIDTH        ; 8                                ; Signed Integer                                                         ;
; NODE_IR_WIDTH     ; 1                                ; Signed Integer                                                         ;
; SCAN_LENGTH       ; 11                               ; Signed Integer                                                         ;
+-------------------+----------------------------------+------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                            ;
+------------------------------------+----------------------+-------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                         ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                      ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                    ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                    ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                  ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                         ;
; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                                         ;
; WIDTH_A                            ; 32                   ; Signed Integer                                  ;
; WIDTHAD_A                          ; 14                   ; Signed Integer                                  ;
; NUMWORDS_A                         ; 10240                ; Signed Integer                                  ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                         ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                         ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                         ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                         ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                         ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                         ;
; WIDTH_B                            ; 1                    ; Untyped                                         ;
; WIDTHAD_B                          ; 1                    ; Untyped                                         ;
; NUMWORDS_B                         ; 1                    ; Untyped                                         ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                         ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                         ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                         ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                         ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                         ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                         ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                         ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                         ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                         ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                         ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                         ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                         ;
; WIDTH_BYTEENA_A                    ; 4                    ; Signed Integer                                  ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                         ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                         ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                                  ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                         ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                         ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                         ;
; INIT_FILE                          ; onchip_mem.hex       ; Untyped                                         ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                         ;
; MAXIMUM_DEPTH                      ; 10240                ; Signed Integer                                  ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                         ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                         ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                         ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                         ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                         ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                         ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                         ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                         ;
; CBXI_PARAMETER                     ; altsyncram_olb1      ; Untyped                                         ;
+------------------------------------+----------------------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst                                         ;
+--------------------------+------------------------------------------------------------------+-----------------+
; Parameter Name           ; Value                                                            ; Type            ;
+--------------------------+------------------------------------------------------------------+-----------------+
; sld_hub_ip_version       ; 1                                                                ; Untyped         ;
; sld_hub_ip_minor_version ; 3                                                                ; Untyped         ;
; sld_common_ip_version    ; 0                                                                ; Untyped         ;
; device_family            ; Cyclone II                                                       ; Untyped         ;
; n_nodes                  ; 2                                                                ; Untyped         ;
; n_sel_bits               ; 2                                                                ; Untyped         ;
; n_node_ir_bits           ; 5                                                                ; Untyped         ;
; node_info                ; 0000110000000000011011100000000000010001000100000100011000000000 ; Unsigned Binary ;
; compilation_mode         ; 1                                                                ; Untyped         ;
+--------------------------+------------------------------------------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------+
; altmult_add Parameter Settings by Entity Instance                                                                                 ;
+---------------------------------------+-------------------------------------------------------------------------------------------+
; Name                                  ; Value                                                                                     ;
+---------------------------------------+-------------------------------------------------------------------------------------------+
; Number of entity instances            ; 2                                                                                         ;
; Entity Instance                       ; nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                       ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                         ;
;     -- port_signa                     ; PORT_UNUSED                                                                               ;
;     -- port_signb                     ; PORT_UNUSED                                                                               ;
;     -- REPRESENTATION_A               ; UNSIGNED                                                                                  ;
;     -- REPRESENTATION_B               ; UNSIGNED                                                                                  ;
;     -- WIDTH_A                        ; 16                                                                                        ;
;     -- WIDTH_B                        ; 16                                                                                        ;
;     -- WIDTH_RESULT                   ; 32                                                                                        ;
; Entity Instance                       ; nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                       ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                         ;
;     -- port_signa                     ; PORT_UNUSED                                                                               ;
;     -- port_signb                     ; PORT_UNUSED                                                                               ;
;     -- REPRESENTATION_A               ; UNSIGNED                                                                                  ;
;     -- REPRESENTATION_B               ; UNSIGNED                                                                                  ;
;     -- WIDTH_A                        ; 16                                                                                        ;
;     -- WIDTH_B                        ; 16                                                                                        ;
;     -- WIDTH_RESULT                   ; 16                                                                                        ;
+---------------------------------------+-------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                                                                           ;
+----------------------------+-------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                     ;
+----------------------------+-------------------------------------------------------------------------------------------+
; Number of entity instances ; 2                                                                                         ;
; Entity Instance            ; nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo ;
;     -- FIFO Type           ; Single Clock                                                                              ;
;     -- lpm_width           ; 8                                                                                         ;
;     -- LPM_NUMWORDS        ; 64                                                                                        ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                       ;
;     -- USE_EAB             ; ON                                                                                        ;
; Entity Instance            ; nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo ;
;     -- FIFO Type           ; Single Clock                                                                              ;
;     -- lpm_width           ; 8                                                                                         ;
;     -- LPM_NUMWORDS        ; 64                                                                                        ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                       ;
;     -- USE_EAB             ; ON                                                                                        ;
+----------------------------+-------------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Sat Aug 23 09:38:29 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_NIOS_Lite -c DE2_NIOS_Lite
Info: Found 1 design units, including 1 entities, in source file DE2_NIOS_Lite.v
    Info: Found entity 1: DE2_NIOS_Lite
Info: Elaborating entity "DE2_NIOS_Lite" for the top level hierarchy
Warning: Using design file Reset_Delay.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: Reset_Delay
Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:u0"
Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(18): truncated value with size 32 to match size of target (24)
Warning: Using design file SDRAM_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SDRAM_PLL
Info: Elaborating entity "SDRAM_PLL" for hierarchy "SDRAM_PLL:u1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "SDRAM_PLL:u1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "SDRAM_PLL:u1|altpll:altpll_component"
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(54)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(343)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(536)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(843)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(1042)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(1552)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(2133)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(2506)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(2802)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(3057)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(3320)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(3594)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(4753)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(5223)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(5493)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(5938)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(6190)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(6444)
Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at nios_ii.v(6733)
Warning: Using design file nios_ii.v, which is not specified as a design file for the current project, but contains definitions for 27 design units and 27 entities in project
    Info: Found entity 1: clock_0_in_arbitrator
    Info: Found entity 2: clock_0_out_arbitrator
    Info: Found entity 3: clock_1_in_arbitrator
    Info: Found entity 4: clock_1_out_arbitrator
    Info: Found entity 5: cpu_jtag_debug_module_arbitrator
    Info: Found entity 6: cpu_data_master_arbitrator
    Info: Found entity 7: cpu_instruction_master_arbitrator
    Info: Found entity 8: jtag_uart_avalon_jtag_slave_arbitrator
    Info: Found entity 9: key_pio_s1_arbitrator
    Info: Found entity 10: ledg_pio_s1_arbitrator
    Info: Found entity 11: ledr_pio_s1_arbitrator
    Info: Found entity 12: onchip_mem_s1_arbitrator
    Info: Found entity 13: rdv_fifo_for_clock_0_out_to_sdram_s1_module
    Info: Found entity 14: rdv_fifo_for_clock_1_out_to_sdram_s1_module
    Info: Found entity 15: sdram_s1_arbitrator
    Info: Found entity 16: seg7_avalon_slave_0_arbitrator
    Info: Found entity 17: sram_avalon_slave_0_arbitrator
    Info: Found entity 18: sw_pio_s1_arbitrator
    Info: Found entity 19: sysid_control_slave_arbitrator
    Info: Found entity 20: timer_s1_arbitrator
    Info: Found entity 21: tristate_bridge_avalon_slave_arbitrator
    Info: Found entity 22: tristate_bridge_bridge_arbitrator
    Info: Found entity 23: nios_ii_reset_clk_domain_synch_module
    Info: Found entity 24: nios_ii_reset_clk_50_domain_synch_module
    Info: Found entity 25: nios_ii
    Info: Found entity 26: cfi_flash_lane0_module
    Info: Found entity 27: cfi_flash
Info: Elaborating entity "nios_ii" for hierarchy "nios_ii:u2"
Info: Elaborating entity "clock_0_in_arbitrator" for hierarchy "nios_ii:u2|clock_0_in_arbitrator:the_clock_0_in"
Info: Elaborating entity "clock_0_out_arbitrator" for hierarchy "nios_ii:u2|clock_0_out_arbitrator:the_clock_0_out"
Warning: Using design file clock_0.v, which is not specified as a design file for the current project, but contains definitions for 9 design units and 9 entities in project
    Info: Found entity 1: clock_0_master_read_done_sync_module
    Info: Found entity 2: clock_0_master_write_done_sync_module
    Info: Found entity 3: clock_0_edge_to_pulse
    Info: Found entity 4: clock_0_slave_FSM
    Info: Found entity 5: clock_0_slave_read_request_sync_module
    Info: Found entity 6: clock_0_slave_write_request_sync_module
    Info: Found entity 7: clock_0_master_FSM
    Info: Found entity 8: clock_0_bit_pipe
    Info: Found entity 9: clock_0
Info: Elaborating entity "clock_0" for hierarchy "nios_ii:u2|clock_0:the_clock_0"
Info: Elaborating entity "clock_0_master_read_done_sync_module" for hierarchy "nios_ii:u2|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync"
Info: Elaborating entity "clock_0_master_write_done_sync_module" for hierarchy "nios_ii:u2|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync"
Info: Elaborating entity "clock_0_edge_to_pulse" for hierarchy "nios_ii:u2|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse"
Info: Elaborating entity "clock_0_slave_FSM" for hierarchy "nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM"
Info: Elaborating entity "clock_0_slave_read_request_sync_module" for hierarchy "nios_ii:u2|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync"
Info: Elaborating entity "clock_0_slave_write_request_sync_module" for hierarchy "nios_ii:u2|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync"
Info: Elaborating entity "clock_0_master_FSM" for hierarchy "nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM"
Info: Elaborating entity "clock_0_bit_pipe" for hierarchy "nios_ii:u2|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe"
Info: Elaborating entity "clock_1_in_arbitrator" for hierarchy "nios_ii:u2|clock_1_in_arbitrator:the_clock_1_in"
Info: Elaborating entity "clock_1_out_arbitrator" for hierarchy "nios_ii:u2|clock_1_out_arbitrator:the_clock_1_out"
Warning: Using design file clock_1.v, which is not specified as a design file for the current project, but contains definitions for 9 design units and 9 entities in project
    Info: Found entity 1: clock_1_master_read_done_sync_module
    Info: Found entity 2: clock_1_master_write_done_sync_module
    Info: Found entity 3: clock_1_edge_to_pulse
    Info: Found entity 4: clock_1_slave_FSM
    Info: Found entity 5: clock_1_slave_read_request_sync_module
    Info: Found entity 6: clock_1_slave_write_request_sync_module
    Info: Found entity 7: clock_1_master_FSM
    Info: Found entity 8: clock_1_bit_pipe
    Info: Found entity 9: clock_1
Info: Elaborating entity "clock_1" for hierarchy "nios_ii:u2|clock_1:the_clock_1"
Info: Elaborating entity "clock_1_master_read_done_sync_module" for hierarchy "nios_ii:u2|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync"
Info: Elaborating entity "clock_1_master_write_done_sync_module" for hierarchy "nios_ii:u2|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync"
Info: Elaborating entity "clock_1_edge_to_pulse" for hierarchy "nios_ii:u2|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse"
Info: Elaborating entity "clock_1_slave_FSM" for hierarchy "nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM"
Info: Elaborating entity "clock_1_slave_read_request_sync_module" for hierarchy "nios_ii:u2|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync"
Info: Elaborating entity "clock_1_slave_write_request_sync_module" for hierarchy "nios_ii:u2|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync"
Info: Elaborating entity "clock_1_master_FSM" for hierarchy "nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM"
Info: Elaborating entity "clock_1_bit_pipe" for hierarchy "nios_ii:u2|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe"
Info: Elaborating entity "cpu_jtag_debug_module_arbitrator" for hierarchy "nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module"
Info: Elaborating entity "cpu_data_master_arbitrator" for hierarchy "nios_ii:u2|cpu_data_master_arbitrator:the_cpu_data_master"
Info: Elaborating entity "cpu_instruction_master_arbitrator" for hierarchy "nios_ii:u2|cpu_instruction_master_arbitrator:the_cpu_instruction_master"
Info: Found 30 design units, including 30 entities, in source file cpu.v
    Info: Found entity 1: cpu_ic_data_module
    Info: Found entity 2: cpu_ic_tag_module
    Info: Found entity 3: cpu_bht_module
    Info: Found entity 4: cpu_register_bank_a_module
    Info: Found entity 5: cpu_register_bank_b_module
    Info: Found entity 6: cpu_dc_tag_module
    Info: Found entity 7: cpu_dc_data_module
    Info: Found entity 8: cpu_dc_victim_module
    Info: Found entity 9: cpu_nios2_oci_debug
    Info: Found entity 10: cpu_ociram_lpm_dram_bdp_component_module
    Info: Found entity 11: cpu_nios2_ocimem
    Info: Found entity 12: cpu_nios2_avalon_reg
    Info: Found entity 13: cpu_nios2_oci_break
    Info: Found entity 14: cpu_nios2_oci_xbrk
    Info: Found entity 15: cpu_nios2_oci_match_paired
    Info: Found entity 16: cpu_nios2_oci_match_single
    Info: Found entity 17: cpu_nios2_oci_dbrk
    Info: Found entity 18: cpu_nios2_oci_itrace
    Info: Found entity 19: cpu_nios2_oci_td_mode
    Info: Found entity 20: cpu_nios2_oci_dtrace
    Info: Found entity 21: cpu_nios2_oci_compute_tm_count
    Info: Found entity 22: cpu_nios2_oci_fifowp_inc
    Info: Found entity 23: cpu_nios2_oci_fifocount_inc
    Info: Found entity 24: cpu_nios2_oci_fifo
    Info: Found entity 25: cpu_nios2_oci_pib
    Info: Found entity 26: cpu_traceram_lpm_dram_bdp_component_module
    Info: Found entity 27: cpu_nios2_oci_im
    Info: Found entity 28: cpu_nios2_performance_monitors
    Info: Found entity 29: cpu_nios2_oci
    Info: Found entity 30: cpu
Info: Elaborating entity "cpu" for hierarchy "nios_ii:u2|cpu:the_cpu"
Warning: Using design file cpu_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_test_bench
Info: Elaborating entity "cpu_test_bench" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench"
Info: Elaborating entity "cpu_ic_data_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qed1.tdf
    Info: Found entity 1: altsyncram_qed1
Info: Elaborating entity "altsyncram_qed1" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qed1:auto_generated"
Info: Elaborating entity "cpu_ic_tag_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag"
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_u0g1.tdf
    Info: Found entity 1: altsyncram_u0g1
Info: Elaborating entity "altsyncram_u0g1" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_u0g1:auto_generated"
Info: Elaborating entity "cpu_bht_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht"
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pkf1.tdf
    Info: Found entity 1: altsyncram_pkf1
Info: Elaborating entity "altsyncram_pkf1" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_pkf1:auto_generated"
Info: Elaborating entity "cpu_register_bank_a_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a"
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_p2f1.tdf
    Info: Found entity 1: altsyncram_p2f1
Info: Elaborating entity "altsyncram_p2f1" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_p2f1:auto_generated"
Info: Elaborating entity "cpu_register_bank_b_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b"
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_q2f1.tdf
    Info: Found entity 1: altsyncram_q2f1
Info: Elaborating entity "altsyncram_q2f1" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_q2f1:auto_generated"
Info: Elaborating entity "cpu_dc_tag_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag"
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_j9f1.tdf
    Info: Found entity 1: altsyncram_j9f1
Info: Elaborating entity "altsyncram_j9f1" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_j9f1:auto_generated"
Info: Elaborating entity "cpu_dc_data_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data"
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_29f1.tdf
    Info: Found entity 1: altsyncram_29f1
Info: Elaborating entity "altsyncram_29f1" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram|altsyncram_29f1:auto_generated"
Info: Elaborating entity "cpu_dc_victim_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim"
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9vc1.tdf
    Info: Found entity 1: altsyncram_9vc1
Info: Elaborating entity "altsyncram_9vc1" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_9vc1:auto_generated"
Warning: Using design file cpu_mult_cell.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_mult_cell
Info: Elaborating entity "cpu_mult_cell" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altmult_add.tdf
    Info: Found entity 1: altmult_add
Info: Elaborating entity "altmult_add" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_4cr2.tdf
    Info: Found entity 1: mult_add_4cr2
Info: Elaborating entity "mult_add_4cr2" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/ded_mult_2o81.tdf
    Info: Found entity 1: ded_mult_2o81
Info: Elaborating entity "ded_mult_2o81" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf
    Info: Found entity 1: dffpipe_93c
Info: Elaborating entity "dffpipe_93c" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result"
Info: Elaborating entity "altmult_add" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_6cr2.tdf
    Info: Found entity 1: mult_add_6cr2
Info: Elaborating entity "mult_add_6cr2" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated"
Info: Elaborating entity "cpu_nios2_oci" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci"
Info: Elaborating entity "cpu_nios2_oci_debug" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug"
Info: Elaborating entity "cpu_nios2_ocimem" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem"
Info: Elaborating entity "cpu_ociram_lpm_dram_bdp_component_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_t072.tdf
    Info: Found entity 1: altsyncram_t072
Info: Elaborating entity "altsyncram_t072" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_t072:auto_generated"
Info: Elaborating entity "cpu_nios2_avalon_reg" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg"
Info: Elaborating entity "cpu_nios2_oci_break" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break"
Info: Elaborating entity "cpu_nios2_oci_xbrk" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk"
Info: Elaborating entity "cpu_nios2_oci_dbrk" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk"
Info: Elaborating entity "cpu_nios2_oci_match_paired" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_paired:cpu_nios2_oci_dbrk_hit0_match_paired"
Info: Elaborating entity "cpu_nios2_oci_match_single" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit0_match_single"
Info: Elaborating entity "cpu_nios2_oci_itrace" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace"
Info: Elaborating entity "cpu_nios2_oci_dtrace" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace"
Info: Elaborating entity "cpu_nios2_oci_td_mode" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace|cpu_nios2_oci_td_mode:cpu_nios2_oci_trc_ctrl_td_mode"
Info: Elaborating entity "cpu_nios2_oci_fifo" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo"
Info: Elaborating entity "cpu_nios2_oci_compute_tm_count" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_compute_tm_count:cpu_nios2_oci_compute_tm_count_tm_count"
Info: Elaborating entity "cpu_nios2_oci_fifowp_inc" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifowp_inc:cpu_nios2_oci_fifowp_inc_fifowp"
Info: Elaborating entity "cpu_nios2_oci_fifocount_inc" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifocount_inc:cpu_nios2_oci_fifocount_inc_fifocount"
Info: Elaborating entity "cpu_nios2_oci_pib" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib"
Info: Elaborating entity "cpu_nios2_oci_im" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im"
Info: Elaborating entity "cpu_traceram_lpm_dram_bdp_component_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_e502.tdf
    Info: Found entity 1: altsyncram_e502
Info: Elaborating entity "altsyncram_e502" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated"
Warning: Using design file cpu_jtag_debug_module_wrapper.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_jtag_debug_module_wrapper
Info: Elaborating entity "cpu_jtag_debug_module_wrapper" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper"
Warning: Using design file cpu_jtag_debug_module.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_jtag_debug_module
Info: Elaborating entity "cpu_jtag_debug_module" for hierarchy "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1"
Info: Elaborating entity "jtag_uart_avalon_jtag_slave_arbitrator" for hierarchy "nios_ii:u2|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave"
Warning: Using design file jtag_uart.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project
    Info: Found entity 1: jtag_uart_log_module
    Info: Found entity 2: jtag_uart_sim_scfifo_w
    Info: Found entity 3: jtag_uart_scfifo_w
    Info: Found entity 4: jtag_uart_drom_module
    Info: Found entity 5: jtag_uart_sim_scfifo_r
    Info: Found entity 6: jtag_uart_scfifo_r
    Info: Found entity 7: jtag_uart
Info: Elaborating entity "jtag_uart" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart"
Info: Elaborating entity "jtag_uart_scfifo_w" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Elaborating entity "scfifo" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo"
Info: Elaborated megafunction instantiation "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_1n21.tdf
    Info: Found entity 1: scfifo_1n21
Info: Elaborating entity "scfifo_1n21" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_8t21.tdf
    Info: Found entity 1: a_dpfifo_8t21
Info: Elaborating entity "a_dpfifo_8t21" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf
    Info: Found entity 1: a_fefifo_7cf
Info: Elaborating entity "a_fefifo_7cf" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_rj7.tdf
    Info: Found entity 1: cntr_rj7
Info: Elaborating entity "cntr_rj7" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_5h21.tdf
    Info: Found entity 1: dpram_5h21
Info: Elaborating entity "dpram_5h21" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9tl1.tdf
    Info: Found entity 1: altsyncram_9tl1
Info: Elaborating entity "altsyncram_9tl1" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2"
Info: Found 1 design units, including 1 entities, in source file db/cntr_fjb.tdf
    Info: Found entity 1: cntr_fjb
Info: Elaborating entity "cntr_fjb" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:rd_ptr_count"
Info: Elaborating entity "jtag_uart_scfifo_r" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/alt_jtag_atlantic.v
    Info: Found entity 1: alt_jtag_atlantic
Info: Elaborating entity "alt_jtag_atlantic" for hierarchy "nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic"
Info: Elaborated megafunction instantiation "nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic"
Info: Elaborating entity "key_pio_s1_arbitrator" for hierarchy "nios_ii:u2|key_pio_s1_arbitrator:the_key_pio_s1"
Warning: Using design file key_pio.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: key_pio
Info: Elaborating entity "key_pio" for hierarchy "nios_ii:u2|key_pio:the_key_pio"
Info: Elaborating entity "ledg_pio_s1_arbitrator" for hierarchy "nios_ii:u2|ledg_pio_s1_arbitrator:the_ledg_pio_s1"
Warning: Using design file ledg_pio.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ledg_pio
Info: Elaborating entity "ledg_pio" for hierarchy "nios_ii:u2|ledg_pio:the_ledg_pio"
Info: Elaborating entity "ledr_pio_s1_arbitrator" for hierarchy "nios_ii:u2|ledr_pio_s1_arbitrator:the_ledr_pio_s1"
Warning: Using design file ledr_pio.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ledr_pio
Info: Elaborating entity "ledr_pio" for hierarchy "nios_ii:u2|ledr_pio:the_ledr_pio"
Info: Elaborating entity "onchip_mem_s1_arbitrator" for hierarchy "nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1"
Warning: Using design file onchip_mem.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: onchip_mem
Info: Elaborating entity "onchip_mem" for hierarchy "nios_ii:u2|onchip_mem:the_onchip_mem"
Info: Elaborating entity "altsyncram" for hierarchy "nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_olb1.tdf
    Info: Found entity 1: altsyncram_olb1
Info: Elaborating entity "altsyncram_olb1" for hierarchy "nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated"
Warning: Width of data items in D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex is greater than the memory width. Wrapping data items to subsequent addresses. Found 1280 warnings, reporting 10
    Warning: Data at line (2) of memory initialization file "D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (3) of memory initialization file "D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (4) of memory initialization file "D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (5) of memory initialization file "D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (6) of memory initialization file "D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (7) of memory initialization file "D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (8) of memory initialization file "D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (9) of memory initialization file "D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (10) of memory initialization file "D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (11) of memory initialization file "D:/0Clare/DE2/DE2_NIOS_Lite_11/onchip_mem.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Info: Found 1 design units, including 1 entities, in source file db/decode_3oa.tdf
    Info: Found entity 1: decode_3oa
Info: Elaborating entity "decode_3oa" for hierarchy "nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated|decode_3oa:decode3"
Info: Found 1 design units, including 1 entities, in source file db/mux_0kb.tdf
    Info: Found entity 1: mux_0kb
Info: Elaborating entity "mux_0kb" for hierarchy "nios_ii:u2|onchip_mem:the_onchip_mem|altsyncram:the_altsyncram|altsyncram_olb1:auto_generated|mux_0kb:mux2"
Info: Elaborating entity "sdram_s1_arbitrator" for hierarchy "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1"
Info: Elaborating entity "rdv_fifo_for_clock_0_out_to_sdram_s1_module" for hierarchy "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1"
Info: Elaborating entity "rdv_fifo_for_clock_1_out_to_sdram_s1_module" for hierarchy "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1"
Warning: Using design file sdram.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project
    Info: Found entity 1: sdram_input_efifo_module
    Info: Found entity 2: sdram
Info: Elaborating entity "sdram" for hierarchy "nios_ii:u2|sdram:the_sdram"
Warning (10766): Verilog HDL warning at sdram.v(352): ignoring full_case attribute on case statement with explicit default
Info: Elaborating entity "sdram_input_efifo_module" for hierarchy "nios_ii:u2|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module"
Warning (10766): Verilog HDL warning at sdram.v(67): ignoring full_case attribute on case statement with explicit default
Warning (10766): Verilog HDL warning at sdram.v(93): ignoring full_case attribute on case statement with explicit default
Warning (10766): Verilog HDL warning at sdram.v(129): ignoring full_case attribute on case statement with explicit default
Info: Elaborating entity "seg7_avalon_slave_0_arbitrator" for hierarchy "nios_ii:u2|seg7_avalon_slave_0_arbitrator:the_seg7_avalon_slave_0"
Warning: Using design file seg7.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: seg7
Info: Elaborating entity "seg7" for hierarchy "nios_ii:u2|seg7:the_seg7"
Warning: Using design file SEG7_LUT_8.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SEG7_LUT_8
Info: Elaborating entity "SEG7_LUT_8" for hierarchy "nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8"
Warning: Using design file SEG7_LUT.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SEG7_LUT
Info: Elaborating entity "SEG7_LUT" for hierarchy "nios_ii:u2|seg7:the_seg7|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u0"
Info: Elaborating entity "sram_avalon_slave_0_arbitrator" for hierarchy "nios_ii:u2|sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0"
Warning: Using design file sram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sram
Info: Elaborating entity "sram" for hierarchy "nios_ii:u2|sram:the_sram"
Warning: Using design file SRAM_16Bit_512K.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SRAM_16Bit_512K
Info: Elaborating entity "SRAM_16Bit_512K" for hierarchy "nios_ii:u2|sram:the_sram|SRAM_16Bit_512K:the_SRAM_16Bit_512K"
Info: Elaborating entity "sw_pio_s1_arbitrator" for hierarchy "nios_ii:u2|sw_pio_s1_arbitrator:the_sw_pio_s1"
Warning: Using design file sw_pio.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sw_pio
Info: Elaborating entity "sw_pio" for hierarchy "nios_ii:u2|sw_pio:the_sw_pio"
Info: Elaborating entity "sysid_control_slave_arbitrator" for hierarchy "nios_ii:u2|sysid_control_slave_arbitrator:the_sysid_control_slave"
Warning: Using design file sysid.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sysid
Info: Elaborating entity "sysid" for hierarchy "nios_ii:u2|sysid:the_sysid"
Info: Elaborating entity "timer_s1_arbitrator" for hierarchy "nios_ii:u2|timer_s1_arbitrator:the_timer_s1"
Warning: Using design file timer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: timer
Info: Elaborating entity "timer" for hierarchy "nios_ii:u2|timer:the_timer"
Info: Elaborating entity "tristate_bridge_avalon_slave_arbitrator" for hierarchy "nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave"
Info: Elaborating entity "nios_ii_reset_clk_domain_synch_module" for hierarchy "nios_ii:u2|nios_ii_reset_clk_domain_synch_module:nios_ii_reset_clk_domain_synch"
Info: Elaborating entity "nios_ii_reset_clk_50_domain_synch_module" for hierarchy "nios_ii:u2|nios_ii_reset_clk_50_domain_synch_module:nios_ii_reset_clk_50_domain_synch"
Warning (12020): Port "address_b" on the entity instantiation of "cpu_traceram_lpm_dram_bdp_component" is connected to a signal of width 17. The formal width of the signal in the module is 7.  Extra bits will be ignored.
Warning (12020): Port "jdo" on the entity instantiation of "the_cpu_nios2_oci_itrace" is connected to a signal of width 38. The formal width of the signal in the module is 16.  Extra bits will be ignored.
Warning (12020): Port "dbrk" on the entity instantiation of "cpu_nios2_oci_dbrk_hit3_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning (12020): Port "dbrk" on the entity instantiation of "cpu_nios2_oci_dbrk_hit2_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning (12020): Port "dbrka" on the entity instantiation of "cpu_nios2_oci_dbrk_hit2_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning (12020): Port "dbrkb" on the entity instantiation of "cpu_nios2_oci_dbrk_hit2_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning (12020): Port "dbrk" on the entity instantiation of "cpu_nios2_oci_dbrk_hit1_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning (12020): Port "dbrk" on the entity instantiation of "cpu_nios2_oci_dbrk_hit0_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning (12020): Port "dbrka" on the entity instantiation of "cpu_nios2_oci_dbrk_hit0_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning (12020): Port "dbrkb" on the entity instantiation of "cpu_nios2_oci_dbrk_hit0_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Info: Power-up level of register "nios_ii:u2|sdram:the_sdram|i_addr[5]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|sdram:the_sdram|i_addr[5]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|sdram:the_sdram|i_addr[4]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|sdram:the_sdram|i_addr[4]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1|d1_reasons_to_wait" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[31]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[30]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[29]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[28]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[27]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[26]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[25]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[24]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[23]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[22]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[21]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[20]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[19]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[18]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[17]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[16]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[15]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[14]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[13]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[12]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[11]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[10]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[9]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[8]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|A_ipending_reg[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_im_addr[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_im_addr[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_im_addr[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_im_addr[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_im_addr[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_im_addr[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_im_addr[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_wrap" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_break_pulse" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_goto0" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_goto1" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit0" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit1" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit2" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_break" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|E_xbrk_goto0" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|E_xbrk_goto1" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|M_xbrk_goto0" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit3_latch" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit2_latch" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit1_latch" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit0_latch" with stuck data_in port to stuck value GND
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[31]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[31]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[30]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[30]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[29]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[29]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[28]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[28]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[27]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[27]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[26]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[26]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[25]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[25]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[24]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[24]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[23]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[23]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[22]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[22]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[21]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[21]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[20]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[20]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[19]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[19]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[18]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[18]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[17]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[17]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[16]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[16]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[15]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[15]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[14]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[14]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[13]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[13]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[12]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[12]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[11]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[11]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[10]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[10]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[9]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[9]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[8]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[8]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[7]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[7]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[6]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[6]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[5]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[5]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[4]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[4]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[3]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[3]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[2]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[2]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|M_xbrk_goto1" with stuck data_in port to stuck value GND
Warning: Synthesized away the following node(s):
    Warning: Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[0]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[1]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[2]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[3]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[4]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[5]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[6]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[7]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[8]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[9]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[10]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[11]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[12]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[13]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[14]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[15]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[16]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[17]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[18]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[19]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[20]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[21]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[22]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[23]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[24]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[25]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[26]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[27]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[28]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[29]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[30]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[31]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[32]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[33]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[34]"
        Warning (14320): Synthesized away node "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[35]"
Warning (14130): Reduced register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|d1_tristate_bridge_avalon_slave_end_xfer" merged to single register "nios_ii:u2|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "nios_ii:u2|timer_s1_arbitrator:the_timer_s1|d1_timer_s1_end_xfer" merged to single register "nios_ii:u2|timer_s1_arbitrator:the_timer_s1|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "nios_ii:u2|sysid_control_slave_arbitrator:the_sysid_control_slave|d1_sysid_control_slave_end_xfer" merged to single register "nios_ii:u2|sysid_control_slave_arbitrator:the_sysid_control_slave|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "nios_ii:u2|sw_pio_s1_arbitrator:the_sw_pio_s1|d1_sw_pio_s1_end_xfer" merged to single register "nios_ii:u2|sw_pio_s1_arbitrator:the_sw_pio_s1|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "nios_ii:u2|sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0|d1_sram_avalon_slave_0_end_xfer" merged to single register "nios_ii:u2|sram_avalon_slave_0_arbitrator:the_sram_avalon_slave_0|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "nios_ii:u2|seg7_avalon_slave_0_arbitrator:the_seg7_avalon_slave_0|d1_seg7_avalon_slave_0_end_xfer" merged to single register "nios_ii:u2|seg7_avalon_slave_0_arbitrator:the_seg7_avalon_slave_0|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "nios_ii:u2|sdram:the_sdram|i_addr[0]" merged to single register "nios_ii:u2|sdram:the_sdram|i_addr[11]"
    Info: Duplicate register "nios_ii:u2|sdram:the_sdram|i_addr[1]" merged to single register "nios_ii:u2|sdram:the_sdram|i_addr[11]"
    Info: Duplicate register "nios_ii:u2|sdram:the_sdram|i_addr[2]" merged to single register "nios_ii:u2|sdram:the_sdram|i_addr[11]"
    Info: Duplicate register "nios_ii:u2|sdram:the_sdram|i_addr[3]" merged to single register "nios_ii:u2|sdram:the_sdram|i_addr[11]"
    Info: Duplicate register "nios_ii:u2|sdram:the_sdram|i_addr[6]" merged to single register "nios_ii:u2|sdram:the_sdram|i_addr[11]"
    Info: Duplicate register "nios_ii:u2|sdram:the_sdram|i_addr[7]" merged to single register "nios_ii:u2|sdram:the_sdram|i_addr[11]"
    Info: Duplicate register "nios_ii:u2|sdram:the_sdram|i_addr[8]" merged to single register "nios_ii:u2|sdram:the_sdram|i_addr[11]"
    Info: Duplicate register "nios_ii:u2|sdram:the_sdram|i_addr[9]" merged to single register "nios_ii:u2|sdram:the_sdram|i_addr[11]"
    Info: Duplicate register "nios_ii:u2|sdram:the_sdram|i_addr[10]" merged to single register "nios_ii:u2|sdram:the_sdram|i_addr[11]"
    Info: Duplicate register "nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1|onchip_mem_s1_arb_addend[0]" merged to single register "nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1|onchip_mem_s1_arb_addend[1]", power-up level changed
    Info: Duplicate register "nios_ii:u2|ledr_pio_s1_arbitrator:the_ledr_pio_s1|d1_ledr_pio_s1_end_xfer" merged to single register "nios_ii:u2|ledr_pio_s1_arbitrator:the_ledr_pio_s1|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "nios_ii:u2|ledg_pio_s1_arbitrator:the_ledg_pio_s1|d1_ledg_pio_s1_end_xfer" merged to single register "nios_ii:u2|ledg_pio_s1_arbitrator:the_ledg_pio_s1|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "nios_ii:u2|key_pio_s1_arbitrator:the_key_pio_s1|d1_key_pio_s1_end_xfer" merged to single register "nios_ii:u2|key_pio_s1_arbitrator:the_key_pio_s1|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_cpu_jtag_debug_module_end_xfer" merged to single register "nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait", power-up level changed
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigger_state" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_write_request" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_6" merged to single register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_6"
    Info: Duplicate register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_5" merged to single register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_5"
    Info: Duplicate register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_4" merged to single register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_4"
    Info: Duplicate register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_3" merged to single register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_3"
    Info: Duplicate register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_2" merged to single register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_2"
    Info: Duplicate register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_1" merged to single register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_1"
    Info: Duplicate register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_0_out_to_sdram_s1_module:rdv_fifo_for_clock_0_out_to_sdram_s1|full_0" merged to single register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_clock_1_out_to_sdram_s1_module:rdv_fifo_for_clock_1_out_to_sdram_s1|full_0"
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_break" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigbrktype" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "nios_ii:u2|cpu:the_cpu|D_ctrl_jmp_direct" merged to single register "nios_ii:u2|cpu:the_cpu|D_ctrl_a_not_src"
    Info: Duplicate register "nios_ii:u2|cpu:the_cpu|D_ctrl_b_is_dst" merged to single register "nios_ii:u2|cpu:the_cpu|D_ctrl_b_not_src"
Warning (14130): Reduced register "nios_ii:u2|onchip_mem_s1_arbitrator:the_onchip_mem_s1|onchip_mem_s1_arb_share_counter[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_share_counter[2]" with stuck data_in port to stuck value GND
Info: State machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_next" contains 4 states
Info: State machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state" contains 9 states
Info: State machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_next" contains 4 states
Info: State machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state" contains 6 states
Info: State machine "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state" contains 3 states
Info: State machine "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state" contains 3 states
Info: State machine "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state" contains 3 states
Info: State machine "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_next"
Info: Encoding result for state machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_next"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_next.010000000"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_next.000010000"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_next.000001000"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_next.000000001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_next.000000001" uses code string "0000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_next.000001000" uses code string "0011"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_next.000010000" uses code string "0101"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_next.010000000" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state"
Info: Encoding result for state machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state"
    Info: Completed encoding using 9 state bits
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_state.100000000"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_state.010000000"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_state.001000000"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_state.000100000"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_state.000010000"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_state.000001000"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_state.000000100"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_state.000000010"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|m_state.000000001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state.000000001" uses code string "000000000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state.000000010" uses code string "000000011"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state.000000100" uses code string "000000101"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state.000001000" uses code string "000001001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state.000010000" uses code string "000010001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state.000100000" uses code string "000100001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state.001000000" uses code string "001000001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state.010000000" uses code string "010000001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|m_state.100000000" uses code string "100000001"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_next"
Info: Encoding result for state machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_next"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|i_next.111"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|i_next.101"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|i_next.010"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|i_next.000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_next.000" uses code string "0000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_next.010" uses code string "0011"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_next.101" uses code string "0101"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_next.111" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state"
Info: Encoding result for state machine "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|i_state.111"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|i_state.101"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|i_state.011"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|i_state.010"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|i_state.001"
        Info: Encoded state bit "nios_ii:u2|sdram:the_sdram|i_state.000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state.000" uses code string "000000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state.001" uses code string "000011"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state.010" uses code string "000101"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state.011" uses code string "001001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state.101" uses code string "010001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|sdram:the_sdram|i_state.111" uses code string "100001"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state"
Info: Encoding result for state machine "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.100"
        Info: Encoded state bit "nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.010"
        Info: Encoded state bit "nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.001" uses code string "000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.010" uses code string "011"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.100" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state"
Info: Encoding result for state machine "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.100"
        Info: Encoded state bit "nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.010"
        Info: Encoded state bit "nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.001" uses code string "000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.010" uses code string "011"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.100" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state"
Info: Encoding result for state machine "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.100"
        Info: Encoded state bit "nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.010"
        Info: Encoded state bit "nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.001" uses code string "000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.010" uses code string "011"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.100" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state"
Info: Encoding result for state machine "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.100"
        Info: Encoded state bit "nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.010"
        Info: Encoded state bit "nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.001" uses code string "000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.010" uses code string "011"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.100" uses code string "101"
Warning (14130): Reduced register "nios_ii:u2|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.100" with stuck data_in port to stuck value GND
Info: State machine "|DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize"
Info: Encoding result for state machine "|DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.101"
        Info: Encoded state bit "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.100"
        Info: Encoded state bit "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.011"
        Info: Encoded state bit "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.010"
        Info: Encoded state bit "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.001"
        Info: Encoded state bit "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.000" uses code string "000000"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.001" uses code string "000011"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.010" uses code string "000101"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.011" uses code string "001001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.100" uses code string "010001"
    Info: State "|DE2_NIOS_Lite|nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.101" uses code string "100001"
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.001" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize.011" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rst1" merged to single register "nios_ii:u2|cpu:the_cpu|reset_d1"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Duplicate registers merged to single register
    Info: Duplicate register "nios_ii:u2|cpu:the_cpu|reset_d1" merged to single register "nios_ii:u2|clock_0:the_clock_0|slave_byteenable_d1[1]", power-up level changed
Warning (14130): Reduced register "nios_ii:u2|sdram:the_sdram|m_count[2]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "DRAM_CKE" stuck at VCC
    Warning (13410): Pin "FL_RST_N" stuck at VCC
Info: 71 registers lost all their fanouts during netlist optimizations. The first 71 are displayed below.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[0]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[1]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[2]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[3]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[4]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[5]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[6]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[7]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[8]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[9]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[10]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[11]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[12]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[13]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[14]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[15]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[16]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[17]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[18]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[19]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[20]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[21]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[22]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[23]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[24]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[25]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[26]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[27]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[28]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[29]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[30]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[31]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[32]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[33]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[34]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[35]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit3" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[0]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[16]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[15]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[14]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[13]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[12]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[11]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[10]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[9]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[8]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[7]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[6]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[5]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[4]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[3]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[2]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[1]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|d1_reasons_to_wait" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|last_cycle_clock_1_out_granted_slave_sdram_s1" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|last_cycle_clock_0_out_granted_slave_sdram_s1" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[1]" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_reg_firsttransfer" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|m_next~64" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|m_next~65" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|m_next~68" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|m_next~69" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|m_next~71" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|i_next~17" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|i_next~18" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|i_next~19" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|i_state~56" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|i_state~57" lost all its fanouts during netlist optimizations.
    Info: Register "nios_ii:u2|sdram:the_sdram|i_state~58" lost all its fanouts during netlist optimizations.
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 5774 device resources after synthesis - the final resource count might be different
    Info: Implemented 26 input pins
    Info: Implemented 155 output pins
    Info: Implemented 40 bidirectional pins
    Info: Implemented 5204 logic cells
    Info: Implemented 343 RAM segments
    Info: Implemented 1 ClockLock PLLs
    Info: Implemented 4 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 206 warnings
    Info: Allocated 227 megabytes of memory during processing
    Info: Processing ended: Sat Aug 23 09:39:35 2008
    Info: Elapsed time: 00:01:06


