SYSTEM nios_ii
{
   System_Wizard_Version = "7.20";
   System_Wizard_Build = "207";
   # 
   # Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF
   # Date: 2008.08.29.14:09:13
   # 
   #    clock_source "clk"
   #    altera_nios2 "cpu"
   #    sram_16bit_512k "sram"
   #    altera_avalon_sysid "sysid"
   #    altera_avalon_jtag_uart "jtag_uart"
   #    altera_avalon_timer "timer"
   # 
   #    Contains 14 connections.
   # 
   Builder_Application = "sopc_builder_ca";
   #. values for Builder_Application are:
   #.    sopc_builder_preview --> 6.1p, 7.0p prerelease versions
   #.    sopc_builder_ca      --> 7.1 and later
   #.    (missing) --> 6.0 or earlier
   WIZARD_SCRIPT_ARGUMENTS 
   {
      hdl_language = "verilog";
      device_family = "CYCLONEII";
      device_family_id = "CYCLONEII";
      generate_sdk = "0";
      do_build_sim = "0";
      hardcopy_compatible = "0";
      CLOCKS 
      {
         CLOCK clk
         {
            frequency = "100000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "clk";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "clk.clk";
         }
      }
      clock_freq = "100000000";
      clock_freq = "100000000";
      clock_freq = "100000000";
      clock_freq = "100000000";
      clock_freq = "100000000";
      clock_freq = "100000000";
      clock_freq = "100000000";
      clock_freq = "100000000";
      clock_freq = "100000000";
      clock_freq = "100000000";
      clock_freq = "100000000";
      board_class = "";
      view_master_columns = "1";
      view_master_priorities = "0";
      generate_hdl = "";
      bustype_column_width = "0";
      clock_column_width = "80";
      name_column_width = "75";
      desc_column_width = "75";
      base_column_width = "75";
      end_column_width = "75";
   }
   MODULE cpu
   {
      MASTER instruction_master
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_address
            {
               type = "address";
               width = "25";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT i_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT i_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "25";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "";
            Linewrap_Bursts = "";
            Burst_On_Burst_Boundaries_Only = "";
            Always_Burst_Max_Burst = "";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Address_Group = "0";
            Has_IRQ = "0";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-0";
         }
         MEMORY_MAP 
         {
            Entry cpu/jtag_debug_module
            {
               address = "0x01920800";
               span = "0x00000800";
            }
            Entry sram/avalon_slave_0
            {
               address = "0x01880000";
               span = "0x00080000";
            }
         }
      }
      MASTER custom_instruction_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Is_Custom_Instruction = "1";
            Is_Enabled = "0";
            Max_Address_Width = "8";
            Base_Address = "N/A";
            Is_Visible = "0";
         }
         PORT_WIRING 
         {
            PORT dataa
            {
               type = "dataa";
               width = "32";
               direction = "output";
            }
            PORT datab
            {
               type = "datab";
               width = "32";
               direction = "output";
            }
            PORT result
            {
               type = "result";
               width = "32";
               direction = "input";
            }
            PORT clk_en
            {
               type = "clk_en";
               width = "1";
               direction = "output";
            }
            PORT reset
            {
               type = "reset";
               width = "1";
               direction = "output";
            }
            PORT start
            {
               type = "start";
               width = "1";
               direction = "output";
            }
            PORT done
            {
               type = "done";
               width = "1";
               direction = "input";
            }
            PORT n
            {
               type = "n";
               width = "8";
               direction = "output";
            }
            PORT a
            {
               type = "a";
               width = "5";
               direction = "output";
            }
            PORT b
            {
               type = "b";
               width = "5";
               direction = "output";
            }
            PORT c
            {
               type = "c";
               width = "5";
               direction = "output";
            }
            PORT readra
            {
               type = "readra";
               width = "1";
               direction = "output";
            }
            PORT readrb
            {
               type = "readrb";
               width = "1";
               direction = "output";
            }
            PORT writerc
            {
               type = "writerc";
               width = "1";
               direction = "output";
            }
         }
      }
      SLAVE jtag_debug_module
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "2048";
            Read_Latency = "0";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "9";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Accepts_External_Connections = "1";
            Requires_Internal_Connections = "";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x01920800";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x01920800";
            }
            Base_Address = "0x01920800";
            Is_Readable = "1";
            Is_Writeable = "1";
            Uses_Tri_State_Data_Bus = "0";
            Has_IRQ = "0";
            JTAG_Hub_Base_Id = "1118278";
            JTAG_Hub_Instance_Id = "0";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
         PORT_WIRING 
         {
            PORT jtag_debug_module_address
            {
               type = "address";
               width = "9";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_begintransfer
            {
               type = "begintransfer";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_debugaccess
            {
               type = "debugaccess";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_reset
            {
               type = "reset";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_resetrequest
            {
               type = "resetrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_select
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
         }
      }
      MASTER data_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Irq_Scheme = "individual_requests";
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "25";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Data_Master = "1";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
            Interrupt_Range = "0-31";
         }
         PORT_WIRING 
         {
            PORT d_irq
            {
               type = "irq";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_address
            {
               type = "address";
               width = "25";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_debugaccess_to_roms
            {
               type = "debugaccess";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry cpu/jtag_debug_module
            {
               address = "0x01920800";
               span = "0x00000800";
            }
            Entry sram/avalon_slave_0
            {
               address = "0x01880000";
               span = "0x00080000";
            }
            Entry sysid/control_slave
            {
               address = "0x01921060";
               span = "0x00000008";
            }
            Entry jtag_uart/avalon_jtag_slave
            {
               address = "0x01921068";
               span = "0x00000008";
            }
            Entry timer/s1
            {
               address = "0x01921000";
               span = "0x00000020";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         cache_has_dcache = "1";
         cache_dcache_size = "2048";
         cache_dcache_line_size = "32";
         cache_dcache_bursts = "0";
         cache_dcache_ram_block_type = "AUTO";
         num_tightly_coupled_data_masters = "0";
         gui_num_tightly_coupled_data_masters = "0";
         gui_include_tightly_coupled_data_masters = "0";
         gui_omit_avalon_data_master = "0";
         cache_has_icache = "1";
         cache_icache_size = "4096";
         cache_icache_line_size = "32";
         cache_icache_ram_block_type = "AUTO";
         cache_icache_bursts = "0";
         num_tightly_coupled_instruction_masters = "0";
         gui_num_tightly_coupled_instruction_masters = "0";
         gui_include_tightly_coupled_instruction_masters = "0";
         debug_level = "2";
         include_oci = "1";
         oci_sbi_enabled = "1";
         oci_num_xbrk = "0";
         oci_num_dbrk = "0";
         oci_dbrk_trace = "0";
         oci_dbrk_pairs = "0";
         oci_onchip_trace = "0";
         oci_offchip_trace = "0";
         oci_data_trace = "0";
         include_third_party_debug_port = "0";
         oci_trace_addr_width = "7";
         oci_trigger_arming = "1";
         oci_debugreq_signals = "0";
         oci_embedded_pll = "1";
         oci_num_pm = "0";
         oci_pm_width = "32";
         performance_counters_present = "0";
         performance_counters_width = "32";
         always_encrypt = "1";
         debug_simgen = "0";
         activate_model_checker = "0";
         activate_test_end_checker = "0";
         activate_trace = "1";
         activate_monitors = "1";
         clear_x_bits_ld_non_bypass = "1";
         bit_31_bypass_dcache = "1";
         always_bypass_dcache = "0";
         hdl_sim_caches_cleared = "1";
         hbreak_test = "0";
         allow_full_address_range = "0";
         branch_prediction_type = "Dynamic";
         bht_ptr_sz = "8";
         bht_index_pc_only = "0";
         gui_branch_prediction_type = "Automatic";
         full_waveform_signals = "0";
         export_pcb = "0";
         avalon_debug_port_present = "0";
         gui_illegal_instructions_trap = "0";
         gui_illegal_memory_access_detection = "0";
         illegal_mem_exc = "0";
         slave_access_error_exc = "0";
         division_error_exc = "0";
         gui_mmu_present = "0";
         process_id_num_bits = "10";
         dtlb_ptr_sz = "7";
         itlb_ptr_sz = "7";
         dtlb_num_ways = "4";
         itlb_num_ways = "4";
         udtlb_num_entries = "6";
         uitlb_num_entries = "4";
         fast_tlb_miss_exc_slave = "";
         fast_tlb_miss_exc_offset = "0x00000000";
         hardware_divide_present = "0";
         gui_hardware_divide_setting = "0";
         hardware_multiply_present = "1";
         hardware_multiply_impl = "embedded_mul";
         shift_rot_impl = "fast_le_shift";
         gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";
         reset_slave = "sram/avalon_slave_0";
         break_slave = "cpu/jtag_debug_module";
         exc_slave = "sram/avalon_slave_0";
         reset_offset = "0x00000000";
         break_offset = "0x00000020";
         exc_offset = "0x00000020";
         cpu_reset = "0";
         CPU_Implementation = "fast";
         cpu_selection = "f";
         device_family_id = "CYCLONEII";
         address_stall_present = "1";
         dsp_block_supports_shift = "0";
         mrams_present = "0";
         do_generate = "1";
         cpuid_value = "0";
         cpuid_sz = "1";
         dont_overwrite_cpuid = "1";
         allow_legacy_sdk = "1";
         legacy_sdk_support = "1";
         inst_addr_width = "25";
         data_addr_width = "25";
         asp_debug = "0";
         asp_core_debug = "0";
         CPU_Architecture = "nios2";
         cache_icache_burst_type = "none";
         include_debug = "0";
         include_trace = "0";
         hardware_multiply_uses_les = "0";
         hardware_multiply_omits_msw = "1";
         big_endian = "0";
         break_slave_override = "";
         break_offset_override = "0x20";
         altera_show_unreleased_features = "0";
         altera_show_unpublished_features = "0";
         altera_internal_test = "0";
         alt_log_port_base = "";
         alt_log_port_type = "";
         mmu_present = "0";
         nmi_present = "0";
         fast_intr_present = "0";
         num_shadow_regs = "0";
         illegal_instructions_trap = "0";
         illegal_memory_access_detection = "0";
         cache_omit_dcache = "0";
         cache_omit_icache = "0";
         omit_instruction_master = "0";
         omit_data_master = "0";
         ras_ptr_sz = "4";
         jtb_ptr_sz = "5";
         ibuf_ptr_sz = "4";
         iss_trace_on = "0";
         iss_trace_warning = "1";
         iss_trace_info = "1";
         iss_trace_disassembly = "0";
         iss_trace_registers = "0";
         iss_trace_instr_count = "0";
         iss_software_debug = "0";
         iss_software_debug_port = "9996";
         iss_memory_dump_start = "";
         iss_memory_dump_end = "";
         Boot_Copier = "boot_loader_cfi.srec";
         Boot_Copier_EPCS = "boot_loader_epcs.srec";
         Boot_Copier_EPCS_SII_CIII = "boot_loader_epcs_sii_ciii.srec";
         Boot_Copier_BE = "boot_loader_cfi_be.srec";
         Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";
         Boot_Copier_EPCS_SII_CIII_BE = "boot_loader_epcs_sii_ciii_be.srec";
         CONSTANTS 
         {
            CONSTANT __nios_catch_irqs__
            {
               value = "1";
               comment = "Include panic handler for all irqs (needs uart)";
            }
            CONSTANT __nios_use_constructors__
            {
               value = "1";
               comment = "Call c++ static constructors";
            }
            CONSTANT __nios_use_small_printf__
            {
               value = "1";
               comment = "Smaller non-ANSI printf, with no floating point";
            }
            CONSTANT nasys_has_icache
            {
               value = "1";
               comment = "True if instruction cache present";
            }
            CONSTANT nasys_icache_size
            {
               value = "4096";
               comment = "Size in bytes of instruction cache";
            }
            CONSTANT nasys_icache_line_size
            {
               value = "32";
               comment = "Size in bytes of each icache line";
            }
            CONSTANT nasys_icache_line_size_log2
            {
               value = "5";
               comment = "Log2 size in bytes of each icache line";
            }
            CONSTANT nasys_has_dcache
            {
               value = "1";
               comment = "True if instruction cache present";
            }
            CONSTANT nasys_dcache_size
            {
               value = "2048";
               comment = "Size in bytes of data cache";
            }
            CONSTANT nasys_dcache_line_size
            {
               value = "32";
               comment = "Size in bytes of each dcache line";
            }
            CONSTANT nasys_dcache_line_size_log2
            {
               value = "5";
               comment = "Log2 size in bytes of each dcache line";
            }
         }
         license_status = "";
         mainmem_slave = "sram/avalon_slave_0";
         datamem_slave = "sram/avalon_slave_0";
         maincomm_slave = "";
         germs_monitor_id = "";
         advanced_exc = "0";
      }
      class = "altera_nios2";
      class_version = "7.071";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "clk";
         Has_Clock = "1";
         Parameters_Signature = "";
         Is_CPU = "1";
         Instantiate_In_System_Module = "1";
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,CYCLONE,CYCLONEII,CYCLONEIII";
         Default_Module_Name = "cpu";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = "Nios II/f
            <br>&nbsp;&nbsp;4-Kbyte Instruction Cache
            <br>&nbsp;&nbsp;2-Kbyte Data Cache
            <br>&nbsp;&nbsp;JTAG Debug Module
            ";
            MESSAGES 
            {
            }
         }
      }
      iss_model_name = "altera_nios2";
      HDL_INFO 
      {
         # The list of files associated with this module (for synthesis
         # and other purposes) depends on the users' wizard-choices.
         # This section will be filled-in by the Generator_Program
         # after the module logic has been created and the
         # various filenames are known.
      }
      MASTER tightly_coupled_instruction_master_0
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_1
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_2
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_3
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER data_master2
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
         }
      }
      MASTER tightly_coupled_data_master_0
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_1
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_2
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_3
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      PORT_WIRING 
      {
         PORT jtag_debug_trigout
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_clk
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_data
         {
            width = "18";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT clkx2
         {
            width = "1";
            direction = "input";
            Is_Enabled = "0";
            visible = "0";
         }
      }
   }
   MODULE sram
   {
      SLAVE avalon_slave_0
      {
         PORT_WIRING 
         {
            PORT iDATA
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT oDATA
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT iADDR
            {
               type = "address";
               width = "18";
               direction = "input";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT iWE_N
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT iOE_N
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT iCE_N
            {
               type = "chipselect_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT iBE_N
            {
               type = "byteenable_n";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_DQ
            {
               type = "export";
               width = "16";
               direction = "inout";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_ADDR
            {
               type = "export";
               width = "18";
               direction = "output";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_UB_N
            {
               type = "export";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_LB_N
            {
               type = "export";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_WE_N
            {
               type = "export";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_CE_N
            {
               type = "export";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_OE_N
            {
               type = "export";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
               width_expression = "";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "20ns";
            Read_Wait_States = "20ns";
            Hold_Time = "20ns";
            Setup_Time = "20ns";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "524288";
            Read_Latency = "0";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "18";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x01880000";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x01880000";
            }
            Base_Address = "0x01880000";
            Address_Group = "1";
            Has_Clock = "0";
            Has_Base_Address = "1";
            Has_IRQ = "0";
            Active_CS_Through_Read_Latency = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
         COMPONENT_BUILDER 
         {
            AVS_SETTINGS 
            {
               Setup_Value = "20";
               Read_Wait_Value = "20";
               Write_Wait_Value = "20";
               Hold_Value = "20";
               Timing_Units = "ns";
               Read_Latency_Value = "0";
               Minimum_Arbitration_Shares = "1";
               Active_CS_Through_Read_Latency = "0";
               Max_Pending_Read_Transactions_Value = "1";
               Address_Alignment = "dynamic";
               Is_Printable_Device = "0";
               Interleave_Bursts = "0";
               interface_name = "Avalon Slave";
               external_wait = "0";
               Is_Memory_Device = "1";
            }
         }
      }
      PORT_WIRING 
      {
         PORT iCLK
         {
            type = "clk";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            width_expression = "";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
      class = "sram_16bit_512k";
      class_version = "1.0";
      COMPONENT_BUILDER 
      {
         GLS_SETTINGS 
         {
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         hdl_parameters 
         {
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "clk";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
         }
      }
   }
   MODULE sysid
   {
      SLAVE control_slave
      {
         PORT_WIRING 
         {
            PORT clock
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x01921060";
            }
            Base_Address = "0x01921060";
            Has_IRQ = "0";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      class = "altera_avalon_sysid";
      class_version = "7.071";
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Fixed_Module_Name = "sysid";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         Has_Clock = "1";
         View 
         {
            Settings_Summary = "No system ID yet.  <br> 
                                  A unique ID is assigned every time <br> 
                                  the system is generated.";
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         id = "795050627";
         timestamp = "1219990146";
         regenerate_values = "0";
      }
      HDL_INFO 
      {
         # The list of files associated with this module (for synthesis
         # and other purposes) depends on the users' wizard-choices.
         # This section will be filled-in by the Generator_Program
         # after the module logic has been created and the
         # various filenames are known.
      }
      PORT_WIRING 
      {
         # The number and kind of ports that appear on this module
         # depends on the user's wizard-choices.
         # This section will be filled-in by the Generator_Program
         # after the module logic has been created and the ports are known.
         #
      }
   }
   MODULE jtag_uart
   {
      SLAVE avalon_jtag_slave
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT av_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_address
            {
               type = "address";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT av_write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               type = "dataavailable";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT readyfordata
            {
               type = "readyfordata";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT rst_n
            {
               type = "reset_n";
               direction = "input";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            JTAG_Hub_Base_Id = "262254";
            JTAG_Hub_Instance_Id = "0";
            Connection_Limit = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x01921068";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "0";
            }
            Base_Address = "0x01921068";
            Address_Group = "0";
         }
      }
      class = "altera_avalon_jtag_uart";
      class_version = "7.071";
      iss_model_name = "altera_avalon_jtag_uart";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         write_depth = "64";
         read_depth = "64";
         write_threshold = "8";
         read_threshold = "8";
         read_char_stream = "";
         showascii = "1";
         read_le = "0";
         write_le = "0";
         altera_show_unreleased_jtag_uart_features = "0";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL av_chipselect
            {
               name = "av_chipselect";
            }
            SIGNAL av_address
            {
               name = "av_address";
               radix = "hexadecimal";
            }
            SIGNAL av_read_n
            {
               name = "av_read_n";
            }
            SIGNAL av_readdata
            {
               name = "av_readdata";
               radix = "hexadecimal";
            }
            SIGNAL av_write_n
            {
               name = "av_write_n";
            }
            SIGNAL av_writedata
            {
               name = "av_writedata";
               radix = "hexadecimal";
            }
            SIGNAL av_waitrequest
            {
               name = "av_waitrequest";
            }
            SIGNAL dataavailable
            {
               name = "dataavailable";
            }
            SIGNAL readyfordata
            {
               name = "readyfordata";
            }
            SIGNAL av_irq
            {
               name = "av_irq";
            }
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "nios2-terminal";
         }
         INTERACTIVE_OUT log
         {
            enable = "1";
            exe = "perl -- atail-f.pl";
            file = "_output_stream.dat";
            radix = "ascii";
            signals = "temp,list";
         }
         Fix_Me_Up = "";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "clk";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         Iss_Launch_Telnet = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
                <br>Read  Depth: 64; Read  IRQ Threshold: 8";
         }
      }
   }
   MODULE timer
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x01921000";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "1";
            }
            Base_Address = "0x01921000";
            Address_Group = "0";
         }
      }
      class = "altera_avalon_timer";
      class_version = "7.071";
      iss_model_name = "altera_avalon_timer";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = "Timer with 1 ms timeout period.";
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
         Clock_Source = "clk";
         Has_Clock = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         always_run = "0";
         fixed_period = "0";
         snapshot = "1";
         period = "1.0";
         period_units = "ms";
         reset_output = "0";
         timeout_pulse_output = "0";
         load_value = "99999";
         mult = "0.001";
      }
   }
}
