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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.615 ns
From           : SRAM_DQ[3]
To             : nios_ii:u2|cpu:the_cpu|d_readdata_d1[19]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.306 ns
From           : nios_ii:u2|cpu:the_cpu|d_byteenable[0]
To             : SRAM_ADDR[5]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.612 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.410 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'SDRAM_PLL:u1|altpll:altpll_component|_clk1'
Slack          : 1.284 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 134.55 MHz ( period = 7.432 ns )
From           : nios_ii:u2|cpu:the_cpu|M_rot_step1[31]
To             : nios_ii:u2|cpu:the_cpu|Mn_rot_step2[7]
From Clock     : SDRAM_PLL:u1|altpll:altpll_component|_clk1
To Clock       : SDRAM_PLL:u1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : 15.459 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 220.22 MHz ( period = 4.541 ns )
From           : Reset_Delay:u0|Cont[11]
To             : Reset_Delay:u0|Cont[8]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 134.19 MHz ( period = 7.452 ns )
From           : sld_hub:sld_hub_inst|jtag_debug_mode
To             : nios_ii:u2|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'SDRAM_PLL:u1|altpll:altpll_component|_clk1'
Slack          : 0.391 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : nios_ii:u2|jtag_uart:the_jtag_uart|woverflow
To             : nios_ii:u2|jtag_uart:the_jtag_uart|woverflow
From Clock     : SDRAM_PLL:u1|altpll:altpll_component|_clk1
To Clock       : SDRAM_PLL:u1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : 0.391 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : Reset_Delay:u0|Cont[0]
To             : Reset_Delay:u0|Cont[0]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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