-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--D1_Frame_Cont[0] is CCD_Capture:u3|Frame_Cont[0]
D1_Frame_Cont[0] = DFFEAS(D1L3, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[1] is CCD_Capture:u3|Frame_Cont[1]
D1_Frame_Cont[1] = DFFEAS(D1L6, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[2] is CCD_Capture:u3|Frame_Cont[2]
D1_Frame_Cont[2] = DFFEAS(D1L9, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[3] is CCD_Capture:u3|Frame_Cont[3]
D1_Frame_Cont[3] = DFFEAS(D1L12, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--Q1L1 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[0]~70
Q1L1 = D1_Frame_Cont[2] & !D1_Frame_Cont[1] & (D1_Frame_Cont[0] $ !D1_Frame_Cont[3]) # !D1_Frame_Cont[2] & D1_Frame_Cont[0] & (D1_Frame_Cont[1] $ !D1_Frame_Cont[3]);


--Q1L2 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[1]~71
Q1L2 = D1_Frame_Cont[1] & (D1_Frame_Cont[0] & (D1_Frame_Cont[3]) # !D1_Frame_Cont[0] & D1_Frame_Cont[2]) # !D1_Frame_Cont[1] & D1_Frame_Cont[2] & (D1_Frame_Cont[0] $ D1_Frame_Cont[3]);


--Q1L3 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[2]~72
Q1L3 = D1_Frame_Cont[2] & D1_Frame_Cont[3] & (D1_Frame_Cont[1] # !D1_Frame_Cont[0]) # !D1_Frame_Cont[2] & !D1_Frame_Cont[0] & D1_Frame_Cont[1] & !D1_Frame_Cont[3];


--Q1L4 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[3]~73
Q1L4 = D1_Frame_Cont[0] & (D1_Frame_Cont[1] $ !D1_Frame_Cont[2]) # !D1_Frame_Cont[0] & (D1_Frame_Cont[1] & !D1_Frame_Cont[2] & D1_Frame_Cont[3] # !D1_Frame_Cont[1] & D1_Frame_Cont[2] & !D1_Frame_Cont[3]);


--Q1L5 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[4]~74
Q1L5 = D1_Frame_Cont[1] & D1_Frame_Cont[0] & (!D1_Frame_Cont[3]) # !D1_Frame_Cont[1] & (D1_Frame_Cont[2] & (!D1_Frame_Cont[3]) # !D1_Frame_Cont[2] & D1_Frame_Cont[0]);


--Q1L6 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[5]~75
Q1L6 = D1_Frame_Cont[0] & (D1_Frame_Cont[3] $ (D1_Frame_Cont[1] # !D1_Frame_Cont[2])) # !D1_Frame_Cont[0] & D1_Frame_Cont[1] & !D1_Frame_Cont[2] & !D1_Frame_Cont[3];


--Q1L7 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[6]~76
Q1L7 = D1_Frame_Cont[0] & (D1_Frame_Cont[3] # D1_Frame_Cont[1] $ D1_Frame_Cont[2]) # !D1_Frame_Cont[0] & (D1_Frame_Cont[1] # D1_Frame_Cont[2] $ D1_Frame_Cont[3]);


--D1_Frame_Cont[4] is CCD_Capture:u3|Frame_Cont[4]
D1_Frame_Cont[4] = DFFEAS(D1L15, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[5] is CCD_Capture:u3|Frame_Cont[5]
D1_Frame_Cont[5] = DFFEAS(D1L18, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[6] is CCD_Capture:u3|Frame_Cont[6]
D1_Frame_Cont[6] = DFFEAS(D1L21, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[7] is CCD_Capture:u3|Frame_Cont[7]
D1_Frame_Cont[7] = DFFEAS(D1L24, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--Q2L1 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[0]~70
Q2L1 = D1_Frame_Cont[6] & !D1_Frame_Cont[5] & (D1_Frame_Cont[4] $ !D1_Frame_Cont[7]) # !D1_Frame_Cont[6] & D1_Frame_Cont[4] & (D1_Frame_Cont[5] $ !D1_Frame_Cont[7]);


--Q2L2 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[1]~71
Q2L2 = D1_Frame_Cont[5] & (D1_Frame_Cont[4] & (D1_Frame_Cont[7]) # !D1_Frame_Cont[4] & D1_Frame_Cont[6]) # !D1_Frame_Cont[5] & D1_Frame_Cont[6] & (D1_Frame_Cont[4] $ D1_Frame_Cont[7]);


--Q2L3 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[2]~72
Q2L3 = D1_Frame_Cont[6] & D1_Frame_Cont[7] & (D1_Frame_Cont[5] # !D1_Frame_Cont[4]) # !D1_Frame_Cont[6] & !D1_Frame_Cont[4] & D1_Frame_Cont[5] & !D1_Frame_Cont[7];


--Q2L4 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[3]~73
Q2L4 = D1_Frame_Cont[4] & (D1_Frame_Cont[5] $ !D1_Frame_Cont[6]) # !D1_Frame_Cont[4] & (D1_Frame_Cont[5] & !D1_Frame_Cont[6] & D1_Frame_Cont[7] # !D1_Frame_Cont[5] & D1_Frame_Cont[6] & !D1_Frame_Cont[7]);


--Q2L5 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[4]~74
Q2L5 = D1_Frame_Cont[5] & D1_Frame_Cont[4] & (!D1_Frame_Cont[7]) # !D1_Frame_Cont[5] & (D1_Frame_Cont[6] & (!D1_Frame_Cont[7]) # !D1_Frame_Cont[6] & D1_Frame_Cont[4]);


--Q2L6 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[5]~75
Q2L6 = D1_Frame_Cont[4] & (D1_Frame_Cont[7] $ (D1_Frame_Cont[5] # !D1_Frame_Cont[6])) # !D1_Frame_Cont[4] & D1_Frame_Cont[5] & !D1_Frame_Cont[6] & !D1_Frame_Cont[7];


--Q2L7 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[6]~76
Q2L7 = D1_Frame_Cont[4] & (D1_Frame_Cont[7] # D1_Frame_Cont[5] $ D1_Frame_Cont[6]) # !D1_Frame_Cont[4] & (D1_Frame_Cont[5] # D1_Frame_Cont[6] $ D1_Frame_Cont[7]);


--D1_Frame_Cont[8] is CCD_Capture:u3|Frame_Cont[8]
D1_Frame_Cont[8] = DFFEAS(D1L27, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[9] is CCD_Capture:u3|Frame_Cont[9]
D1_Frame_Cont[9] = DFFEAS(D1L30, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[10] is CCD_Capture:u3|Frame_Cont[10]
D1_Frame_Cont[10] = DFFEAS(D1L33, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[11] is CCD_Capture:u3|Frame_Cont[11]
D1_Frame_Cont[11] = DFFEAS(D1L36, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--Q3L1 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[0]~70
Q3L1 = D1_Frame_Cont[10] & !D1_Frame_Cont[9] & (D1_Frame_Cont[8] $ !D1_Frame_Cont[11]) # !D1_Frame_Cont[10] & D1_Frame_Cont[8] & (D1_Frame_Cont[9] $ !D1_Frame_Cont[11]);


--Q3L2 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[1]~71
Q3L2 = D1_Frame_Cont[9] & (D1_Frame_Cont[8] & (D1_Frame_Cont[11]) # !D1_Frame_Cont[8] & D1_Frame_Cont[10]) # !D1_Frame_Cont[9] & D1_Frame_Cont[10] & (D1_Frame_Cont[8] $ D1_Frame_Cont[11]);


--Q3L3 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[2]~72
Q3L3 = D1_Frame_Cont[10] & D1_Frame_Cont[11] & (D1_Frame_Cont[9] # !D1_Frame_Cont[8]) # !D1_Frame_Cont[10] & !D1_Frame_Cont[8] & D1_Frame_Cont[9] & !D1_Frame_Cont[11];


--Q3L4 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[3]~73
Q3L4 = D1_Frame_Cont[8] & (D1_Frame_Cont[9] $ !D1_Frame_Cont[10]) # !D1_Frame_Cont[8] & (D1_Frame_Cont[9] & !D1_Frame_Cont[10] & D1_Frame_Cont[11] # !D1_Frame_Cont[9] & D1_Frame_Cont[10] & !D1_Frame_Cont[11]);


--Q3L5 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[4]~74
Q3L5 = D1_Frame_Cont[9] & D1_Frame_Cont[8] & (!D1_Frame_Cont[11]) # !D1_Frame_Cont[9] & (D1_Frame_Cont[10] & (!D1_Frame_Cont[11]) # !D1_Frame_Cont[10] & D1_Frame_Cont[8]);


--Q3L6 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[5]~75
Q3L6 = D1_Frame_Cont[8] & (D1_Frame_Cont[11] $ (D1_Frame_Cont[9] # !D1_Frame_Cont[10])) # !D1_Frame_Cont[8] & D1_Frame_Cont[9] & !D1_Frame_Cont[10] & !D1_Frame_Cont[11];


--Q3L7 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[6]~76
Q3L7 = D1_Frame_Cont[8] & (D1_Frame_Cont[11] # D1_Frame_Cont[9] $ D1_Frame_Cont[10]) # !D1_Frame_Cont[8] & (D1_Frame_Cont[9] # D1_Frame_Cont[10] $ D1_Frame_Cont[11]);


--D1_Frame_Cont[12] is CCD_Capture:u3|Frame_Cont[12]
D1_Frame_Cont[12] = DFFEAS(D1L39, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[13] is CCD_Capture:u3|Frame_Cont[13]
D1_Frame_Cont[13] = DFFEAS(D1L42, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[14] is CCD_Capture:u3|Frame_Cont[14]
D1_Frame_Cont[14] = DFFEAS(D1L45, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[15] is CCD_Capture:u3|Frame_Cont[15]
D1_Frame_Cont[15] = DFFEAS(D1L48, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--Q4L1 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[0]~70
Q4L1 = D1_Frame_Cont[14] & !D1_Frame_Cont[13] & (D1_Frame_Cont[12] $ !D1_Frame_Cont[15]) # !D1_Frame_Cont[14] & D1_Frame_Cont[12] & (D1_Frame_Cont[13] $ !D1_Frame_Cont[15]);


--Q4L2 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[1]~71
Q4L2 = D1_Frame_Cont[13] & (D1_Frame_Cont[12] & (D1_Frame_Cont[15]) # !D1_Frame_Cont[12] & D1_Frame_Cont[14]) # !D1_Frame_Cont[13] & D1_Frame_Cont[14] & (D1_Frame_Cont[12] $ D1_Frame_Cont[15]);


--Q4L3 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[2]~72
Q4L3 = D1_Frame_Cont[14] & D1_Frame_Cont[15] & (D1_Frame_Cont[13] # !D1_Frame_Cont[12]) # !D1_Frame_Cont[14] & !D1_Frame_Cont[12] & D1_Frame_Cont[13] & !D1_Frame_Cont[15];


--Q4L4 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[3]~73
Q4L4 = D1_Frame_Cont[12] & (D1_Frame_Cont[13] $ !D1_Frame_Cont[14]) # !D1_Frame_Cont[12] & (D1_Frame_Cont[13] & !D1_Frame_Cont[14] & D1_Frame_Cont[15] # !D1_Frame_Cont[13] & D1_Frame_Cont[14] & !D1_Frame_Cont[15]);


--Q4L5 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[4]~74
Q4L5 = D1_Frame_Cont[13] & D1_Frame_Cont[12] & (!D1_Frame_Cont[15]) # !D1_Frame_Cont[13] & (D1_Frame_Cont[14] & (!D1_Frame_Cont[15]) # !D1_Frame_Cont[14] & D1_Frame_Cont[12]);


--Q4L6 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[5]~75
Q4L6 = D1_Frame_Cont[12] & (D1_Frame_Cont[15] $ (D1_Frame_Cont[13] # !D1_Frame_Cont[14])) # !D1_Frame_Cont[12] & D1_Frame_Cont[13] & !D1_Frame_Cont[14] & !D1_Frame_Cont[15];


--Q4L7 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[6]~76
Q4L7 = D1_Frame_Cont[12] & (D1_Frame_Cont[15] # D1_Frame_Cont[13] $ D1_Frame_Cont[14]) # !D1_Frame_Cont[12] & (D1_Frame_Cont[13] # D1_Frame_Cont[14] $ D1_Frame_Cont[15]);


--D1_Frame_Cont[16] is CCD_Capture:u3|Frame_Cont[16]
D1_Frame_Cont[16] = DFFEAS(D1L51, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[17] is CCD_Capture:u3|Frame_Cont[17]
D1_Frame_Cont[17] = DFFEAS(D1L54, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[18] is CCD_Capture:u3|Frame_Cont[18]
D1_Frame_Cont[18] = DFFEAS(D1L57, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[19] is CCD_Capture:u3|Frame_Cont[19]
D1_Frame_Cont[19] = DFFEAS(D1L60, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--Q5L1 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[0]~70
Q5L1 = D1_Frame_Cont[18] & !D1_Frame_Cont[17] & (D1_Frame_Cont[16] $ !D1_Frame_Cont[19]) # !D1_Frame_Cont[18] & D1_Frame_Cont[16] & (D1_Frame_Cont[17] $ !D1_Frame_Cont[19]);


--Q5L2 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[1]~71
Q5L2 = D1_Frame_Cont[17] & (D1_Frame_Cont[16] & (D1_Frame_Cont[19]) # !D1_Frame_Cont[16] & D1_Frame_Cont[18]) # !D1_Frame_Cont[17] & D1_Frame_Cont[18] & (D1_Frame_Cont[16] $ D1_Frame_Cont[19]);


--Q5L3 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[2]~72
Q5L3 = D1_Frame_Cont[18] & D1_Frame_Cont[19] & (D1_Frame_Cont[17] # !D1_Frame_Cont[16]) # !D1_Frame_Cont[18] & !D1_Frame_Cont[16] & D1_Frame_Cont[17] & !D1_Frame_Cont[19];


--Q5L4 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[3]~73
Q5L4 = D1_Frame_Cont[16] & (D1_Frame_Cont[17] $ !D1_Frame_Cont[18]) # !D1_Frame_Cont[16] & (D1_Frame_Cont[17] & !D1_Frame_Cont[18] & D1_Frame_Cont[19] # !D1_Frame_Cont[17] & D1_Frame_Cont[18] & !D1_Frame_Cont[19]);


--Q5L5 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[4]~74
Q5L5 = D1_Frame_Cont[17] & D1_Frame_Cont[16] & (!D1_Frame_Cont[19]) # !D1_Frame_Cont[17] & (D1_Frame_Cont[18] & (!D1_Frame_Cont[19]) # !D1_Frame_Cont[18] & D1_Frame_Cont[16]);


--Q5L6 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[5]~75
Q5L6 = D1_Frame_Cont[16] & (D1_Frame_Cont[19] $ (D1_Frame_Cont[17] # !D1_Frame_Cont[18])) # !D1_Frame_Cont[16] & D1_Frame_Cont[17] & !D1_Frame_Cont[18] & !D1_Frame_Cont[19];


--Q5L7 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[6]~76
Q5L7 = D1_Frame_Cont[16] & (D1_Frame_Cont[19] # D1_Frame_Cont[17] $ D1_Frame_Cont[18]) # !D1_Frame_Cont[16] & (D1_Frame_Cont[17] # D1_Frame_Cont[18] $ D1_Frame_Cont[19]);


--D1_Frame_Cont[20] is CCD_Capture:u3|Frame_Cont[20]
D1_Frame_Cont[20] = DFFEAS(D1L63, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[21] is CCD_Capture:u3|Frame_Cont[21]
D1_Frame_Cont[21] = DFFEAS(D1L66, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[22] is CCD_Capture:u3|Frame_Cont[22]
D1_Frame_Cont[22] = DFFEAS(D1L69, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[23] is CCD_Capture:u3|Frame_Cont[23]
D1_Frame_Cont[23] = DFFEAS(D1L72, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--Q6L1 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[0]~70
Q6L1 = D1_Frame_Cont[22] & !D1_Frame_Cont[21] & (D1_Frame_Cont[20] $ !D1_Frame_Cont[23]) # !D1_Frame_Cont[22] & D1_Frame_Cont[20] & (D1_Frame_Cont[21] $ !D1_Frame_Cont[23]);


--Q6L2 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[1]~71
Q6L2 = D1_Frame_Cont[21] & (D1_Frame_Cont[20] & (D1_Frame_Cont[23]) # !D1_Frame_Cont[20] & D1_Frame_Cont[22]) # !D1_Frame_Cont[21] & D1_Frame_Cont[22] & (D1_Frame_Cont[20] $ D1_Frame_Cont[23]);


--Q6L3 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[2]~72
Q6L3 = D1_Frame_Cont[22] & D1_Frame_Cont[23] & (D1_Frame_Cont[21] # !D1_Frame_Cont[20]) # !D1_Frame_Cont[22] & !D1_Frame_Cont[20] & D1_Frame_Cont[21] & !D1_Frame_Cont[23];


--Q6L4 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[3]~73
Q6L4 = D1_Frame_Cont[20] & (D1_Frame_Cont[21] $ !D1_Frame_Cont[22]) # !D1_Frame_Cont[20] & (D1_Frame_Cont[21] & !D1_Frame_Cont[22] & D1_Frame_Cont[23] # !D1_Frame_Cont[21] & D1_Frame_Cont[22] & !D1_Frame_Cont[23]);


--Q6L5 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[4]~74
Q6L5 = D1_Frame_Cont[21] & D1_Frame_Cont[20] & (!D1_Frame_Cont[23]) # !D1_Frame_Cont[21] & (D1_Frame_Cont[22] & (!D1_Frame_Cont[23]) # !D1_Frame_Cont[22] & D1_Frame_Cont[20]);


--Q6L6 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[5]~75
Q6L6 = D1_Frame_Cont[20] & (D1_Frame_Cont[23] $ (D1_Frame_Cont[21] # !D1_Frame_Cont[22])) # !D1_Frame_Cont[20] & D1_Frame_Cont[21] & !D1_Frame_Cont[22] & !D1_Frame_Cont[23];


--Q6L7 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[6]~76
Q6L7 = D1_Frame_Cont[20] & (D1_Frame_Cont[23] # D1_Frame_Cont[21] $ D1_Frame_Cont[22]) # !D1_Frame_Cont[20] & (D1_Frame_Cont[21] # D1_Frame_Cont[22] $ D1_Frame_Cont[23]);


--D1_Frame_Cont[24] is CCD_Capture:u3|Frame_Cont[24]
D1_Frame_Cont[24] = DFFEAS(D1L75, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[25] is CCD_Capture:u3|Frame_Cont[25]
D1_Frame_Cont[25] = DFFEAS(D1L78, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[26] is CCD_Capture:u3|Frame_Cont[26]
D1_Frame_Cont[26] = DFFEAS(D1L81, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[27] is CCD_Capture:u3|Frame_Cont[27]
D1_Frame_Cont[27] = DFFEAS(D1L84, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--Q7L1 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[0]~70
Q7L1 = D1_Frame_Cont[26] & !D1_Frame_Cont[25] & (D1_Frame_Cont[24] $ !D1_Frame_Cont[27]) # !D1_Frame_Cont[26] & D1_Frame_Cont[24] & (D1_Frame_Cont[25] $ !D1_Frame_Cont[27]);


--Q7L2 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[1]~71
Q7L2 = D1_Frame_Cont[25] & (D1_Frame_Cont[24] & (D1_Frame_Cont[27]) # !D1_Frame_Cont[24] & D1_Frame_Cont[26]) # !D1_Frame_Cont[25] & D1_Frame_Cont[26] & (D1_Frame_Cont[24] $ D1_Frame_Cont[27]);


--Q7L3 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[2]~72
Q7L3 = D1_Frame_Cont[26] & D1_Frame_Cont[27] & (D1_Frame_Cont[25] # !D1_Frame_Cont[24]) # !D1_Frame_Cont[26] & !D1_Frame_Cont[24] & D1_Frame_Cont[25] & !D1_Frame_Cont[27];


--Q7L4 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[3]~73
Q7L4 = D1_Frame_Cont[24] & (D1_Frame_Cont[25] $ !D1_Frame_Cont[26]) # !D1_Frame_Cont[24] & (D1_Frame_Cont[25] & !D1_Frame_Cont[26] & D1_Frame_Cont[27] # !D1_Frame_Cont[25] & D1_Frame_Cont[26] & !D1_Frame_Cont[27]);


--Q7L5 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[4]~74
Q7L5 = D1_Frame_Cont[25] & D1_Frame_Cont[24] & (!D1_Frame_Cont[27]) # !D1_Frame_Cont[25] & (D1_Frame_Cont[26] & (!D1_Frame_Cont[27]) # !D1_Frame_Cont[26] & D1_Frame_Cont[24]);


--Q7L6 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[5]~75
Q7L6 = D1_Frame_Cont[24] & (D1_Frame_Cont[27] $ (D1_Frame_Cont[25] # !D1_Frame_Cont[26])) # !D1_Frame_Cont[24] & D1_Frame_Cont[25] & !D1_Frame_Cont[26] & !D1_Frame_Cont[27];


--Q7L7 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[6]~76
Q7L7 = D1_Frame_Cont[24] & (D1_Frame_Cont[27] # D1_Frame_Cont[25] $ D1_Frame_Cont[26]) # !D1_Frame_Cont[24] & (D1_Frame_Cont[25] # D1_Frame_Cont[26] $ D1_Frame_Cont[27]);


--D1_Frame_Cont[28] is CCD_Capture:u3|Frame_Cont[28]
D1_Frame_Cont[28] = DFFEAS(D1L87, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[29] is CCD_Capture:u3|Frame_Cont[29]
D1_Frame_Cont[29] = DFFEAS(D1L90, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[30] is CCD_Capture:u3|Frame_Cont[30]
D1_Frame_Cont[30] = DFFEAS(D1L93, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[31] is CCD_Capture:u3|Frame_Cont[31]
D1_Frame_Cont[31] = DFFEAS(D1L96, CCD_PIXCLK, C1_oRST_1,  , D1L167,  ,  ,  ,  );


--Q8L1 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[0]~70
Q8L1 = D1_Frame_Cont[30] & !D1_Frame_Cont[29] & (D1_Frame_Cont[28] $ !D1_Frame_Cont[31]) # !D1_Frame_Cont[30] & D1_Frame_Cont[28] & (D1_Frame_Cont[29] $ !D1_Frame_Cont[31]);


--Q8L2 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[1]~71
Q8L2 = D1_Frame_Cont[29] & (D1_Frame_Cont[28] & (D1_Frame_Cont[31]) # !D1_Frame_Cont[28] & D1_Frame_Cont[30]) # !D1_Frame_Cont[29] & D1_Frame_Cont[30] & (D1_Frame_Cont[28] $ D1_Frame_Cont[31]);


--Q8L3 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[2]~72
Q8L3 = D1_Frame_Cont[30] & D1_Frame_Cont[31] & (D1_Frame_Cont[29] # !D1_Frame_Cont[28]) # !D1_Frame_Cont[30] & !D1_Frame_Cont[28] & D1_Frame_Cont[29] & !D1_Frame_Cont[31];


--Q8L4 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[3]~73
Q8L4 = D1_Frame_Cont[28] & (D1_Frame_Cont[29] $ !D1_Frame_Cont[30]) # !D1_Frame_Cont[28] & (D1_Frame_Cont[29] & !D1_Frame_Cont[30] & D1_Frame_Cont[31] # !D1_Frame_Cont[29] & D1_Frame_Cont[30] & !D1_Frame_Cont[31]);


--Q8L5 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[4]~74
Q8L5 = D1_Frame_Cont[29] & D1_Frame_Cont[28] & (!D1_Frame_Cont[31]) # !D1_Frame_Cont[29] & (D1_Frame_Cont[30] & (!D1_Frame_Cont[31]) # !D1_Frame_Cont[30] & D1_Frame_Cont[28]);


--Q8L6 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[5]~75
Q8L6 = D1_Frame_Cont[28] & (D1_Frame_Cont[31] $ (D1_Frame_Cont[29] # !D1_Frame_Cont[30])) # !D1_Frame_Cont[28] & D1_Frame_Cont[29] & !D1_Frame_Cont[30] & !D1_Frame_Cont[31];


--Q8L7 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[6]~76
Q8L7 = D1_Frame_Cont[28] & (D1_Frame_Cont[31] # D1_Frame_Cont[29] $ D1_Frame_Cont[30]) # !D1_Frame_Cont[28] & (D1_Frame_Cont[29] # D1_Frame_Cont[30] $ D1_Frame_Cont[31]);


--D1_Y_Cont[0] is CCD_Capture:u3|Y_Cont[0]
D1_Y_Cont[0] = DFFEAS(D1L140, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[1] is CCD_Capture:u3|Y_Cont[1]
D1_Y_Cont[1] = DFFEAS(D1L143, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[2] is CCD_Capture:u3|Y_Cont[2]
D1_Y_Cont[2] = DFFEAS(D1L146, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[3] is CCD_Capture:u3|Y_Cont[3]
D1_Y_Cont[3] = DFFEAS(D1L149, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[4] is CCD_Capture:u3|Y_Cont[4]
D1_Y_Cont[4] = DFFEAS(D1L152, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[5] is CCD_Capture:u3|Y_Cont[5]
D1_Y_Cont[5] = DFFEAS(D1L155, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[6] is CCD_Capture:u3|Y_Cont[6]
D1_Y_Cont[6] = DFFEAS(D1L158, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[7] is CCD_Capture:u3|Y_Cont[7]
D1_Y_Cont[7] = DFFEAS(D1L161, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[8] is CCD_Capture:u3|Y_Cont[8]
D1_Y_Cont[8] = DFFEAS(D1L164, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--G1_SA[0] is Sdram_Control_4Port:u6|SA[0]
G1_SA[0] = DFFEAS(G1L72, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[1] is Sdram_Control_4Port:u6|SA[1]
G1_SA[1] = DFFEAS(G1L73, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[2] is Sdram_Control_4Port:u6|SA[2]
G1_SA[2] = DFFEAS(G1L74, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[3] is Sdram_Control_4Port:u6|SA[3]
G1_SA[3] = DFFEAS(G1L75, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[4] is Sdram_Control_4Port:u6|SA[4]
G1_SA[4] = DFFEAS(G1L76, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[5] is Sdram_Control_4Port:u6|SA[5]
G1_SA[5] = DFFEAS(G1L77, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[6] is Sdram_Control_4Port:u6|SA[6]
G1_SA[6] = DFFEAS(G1L78, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[7] is Sdram_Control_4Port:u6|SA[7]
G1_SA[7] = DFFEAS(G1L79, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[8] is Sdram_Control_4Port:u6|SA[8]
G1_SA[8] = DFFEAS(G1L80, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[9] is Sdram_Control_4Port:u6|SA[9]
G1_SA[9] = DFFEAS(G1L81, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[10] is Sdram_Control_4Port:u6|SA[10]
G1_SA[10] = DFFEAS(G1L82, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[11] is Sdram_Control_4Port:u6|SA[11]
G1_SA[11] = DFFEAS(G1L83, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_DQM[1] is Sdram_Control_4Port:u6|DQM[1]
G1_DQM[1] = DFFEAS(G1L14, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_WE_N is Sdram_Control_4Port:u6|WE_N
G1_WE_N = DFFEAS(G1L112, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_CAS_N is Sdram_Control_4Port:u6|CAS_N
G1_CAS_N = DFFEAS(G1L5, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_RAS_N is Sdram_Control_4Port:u6|RAS_N
G1_RAS_N = DFFEAS(G1L50, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_CS_N[0] is Sdram_Control_4Port:u6|CS_N[0]
G1_CS_N[0] = DFFEAS(R1_CS_N[0], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_BA[0] is Sdram_Control_4Port:u6|BA[0]
G1_BA[0] = DFFEAS(R1_BA[0], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_BA[1] is Sdram_Control_4Port:u6|BA[1]
G1_BA[1] = DFFEAS(R1_BA[1], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--KB1__clk0 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
KB1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());

--KB1__clk1 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1
KB1__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());


--CCD_MCLK is CCD_MCLK
CCD_MCLK = DFFEAS(A1L8, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--B1_oVGA_H_SYNC is VGA_Controller:u1|oVGA_H_SYNC
B1_oVGA_H_SYNC = DFFEAS(B1L42, CCD_MCLK, C1_oRST_2,  ,  ,  ,  ,  ,  );


--B1_oVGA_V_SYNC is VGA_Controller:u1|oVGA_V_SYNC
B1_oVGA_V_SYNC = DFFEAS(B1L117, CCD_MCLK, C1_oRST_2,  ,  ,  ,  ,  ,  );


--B1_oVGA_BLANK is VGA_Controller:u1|oVGA_BLANK
B1_oVGA_BLANK = B1_oVGA_H_SYNC & B1_oVGA_V_SYNC;


--GB4_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[0]_PORT_A_data_in = VCC;
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = G1_mDATAOUT[0];
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = CCD_MCLK;
GB4_q_a[0]_clock_1 = KB1__clk0;
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !C1_oRST_0;
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0] = GB4_q_a[0]_PORT_A_data_out_reg[0];


--B1_V_Cont[6] is VGA_Controller:u1|V_Cont[6]
B1_V_Cont[6] = DFFEAS(B1L68, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[7] is VGA_Controller:u1|V_Cont[7]
B1_V_Cont[7] = DFFEAS(B1L71, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[8] is VGA_Controller:u1|V_Cont[8]
B1_V_Cont[8] = DFFEAS(B1L74, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1L38 is VGA_Controller:u1|LessThan~1087
B1L38 = !B1_V_Cont[6] & !B1_V_Cont[7] & !B1_V_Cont[8];


--B1_V_Cont[1] is VGA_Controller:u1|V_Cont[1]
B1_V_Cont[1] = DFFEAS(B1L53, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[2] is VGA_Controller:u1|V_Cont[2]
B1_V_Cont[2] = DFFEAS(B1L56, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[3] is VGA_Controller:u1|V_Cont[3]
B1_V_Cont[3] = DFFEAS(B1L59, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1L39 is VGA_Controller:u1|LessThan~1088
B1L39 = !B1_V_Cont[1] & !B1_V_Cont[2] & !B1_V_Cont[3];


--B1_V_Cont[4] is VGA_Controller:u1|V_Cont[4]
B1_V_Cont[4] = DFFEAS(B1L62, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[5] is VGA_Controller:u1|V_Cont[5]
B1_V_Cont[5] = DFFEAS(B1L65, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1L40 is VGA_Controller:u1|LessThan~1089
B1L40 = B1L39 & !B1_V_Cont[4] # !B1_V_Cont[5];


--B1_V_Cont[9] is VGA_Controller:u1|V_Cont[9]
B1_V_Cont[9] = DFFEAS(B1L77, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1L41 is VGA_Controller:u1|LessThan~1090
B1L41 = B1_V_Cont[4] # B1_V_Cont[5] # !B1L39 # !B1L38;


--B1L114 is VGA_Controller:u1|oVGA_R~266
B1L114 = B1_V_Cont[9] & (!B1L41) # !B1_V_Cont[9] & (!B1L40 # !B1L38);


--B1_H_Cont[4] is VGA_Controller:u1|H_Cont[4]
B1_H_Cont[4] = DFFEAS(B1L20, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1_H_Cont[5] is VGA_Controller:u1|H_Cont[5]
B1_H_Cont[5] = DFFEAS(B1L23, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1_H_Cont[6] is VGA_Controller:u1|H_Cont[6]
B1_H_Cont[6] = DFFEAS(B1L27, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1L1 is VGA_Controller:u1|Equal~115
B1L1 = !B1_H_Cont[4] & !B1_H_Cont[5] & !B1_H_Cont[6];


--B1_H_Cont[7] is VGA_Controller:u1|H_Cont[7]
B1_H_Cont[7] = DFFEAS(B1L30, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1_H_Cont[8] is VGA_Controller:u1|H_Cont[8]
B1_H_Cont[8] = DFFEAS(B1L33, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1_H_Cont[9] is VGA_Controller:u1|H_Cont[9]
B1_H_Cont[9] = DFFEAS(B1L36, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1L115 is VGA_Controller:u1|oVGA_R~267
B1L115 = B1_H_Cont[8] & (B1L1 & !B1_H_Cont[7] # !B1_H_Cont[9]) # !B1_H_Cont[8] & (B1_H_Cont[9] # !B1L1 & B1_H_Cont[7]);


--B1L104 is VGA_Controller:u1|oVGA_R[0]~268
B1L104 = GB4_q_a[0] & B1L114 & B1L115;


--GB4_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[1]_PORT_A_data_in = VCC;
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = G1_mDATAOUT[1];
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = CCD_MCLK;
GB4_q_a[1]_clock_1 = KB1__clk0;
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !C1_oRST_0;
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1] = GB4_q_a[1]_PORT_A_data_out_reg[0];


--B1L105 is VGA_Controller:u1|oVGA_R[1]~269
B1L105 = GB4_q_a[1] & B1L114 & B1L115;


--GB4_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[2]_PORT_A_data_in = VCC;
GB4_q_a[2]_PORT_A_data_in_reg = DFFE(GB4_q_a[2]_PORT_A_data_in, GB4_q_a[2]_clock_0, , , GB4_q_a[2]_clock_enable_0);
GB4_q_a[2]_PORT_B_data_in = G1_mDATAOUT[2];
GB4_q_a[2]_PORT_B_data_in_reg = DFFE(GB4_q_a[2]_PORT_B_data_in, GB4_q_a[2]_clock_1, , , GB4_q_a[2]_clock_enable_1);
GB4_q_a[2]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[2]_PORT_A_address_reg = DFFE(GB4_q_a[2]_PORT_A_address, GB4_q_a[2]_clock_0, , , GB4_q_a[2]_clock_enable_0);
GB4_q_a[2]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[2]_PORT_B_address_reg = DFFE(GB4_q_a[2]_PORT_B_address, GB4_q_a[2]_clock_1, , , GB4_q_a[2]_clock_enable_1);
GB4_q_a[2]_PORT_A_write_enable = GND;
GB4_q_a[2]_PORT_A_write_enable_reg = DFFE(GB4_q_a[2]_PORT_A_write_enable, GB4_q_a[2]_clock_0, , , GB4_q_a[2]_clock_enable_0);
GB4_q_a[2]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[2]_PORT_B_write_enable_reg = DFFE(GB4_q_a[2]_PORT_B_write_enable, GB4_q_a[2]_clock_1, , , GB4_q_a[2]_clock_enable_1);
GB4_q_a[2]_clock_0 = CCD_MCLK;
GB4_q_a[2]_clock_1 = KB1__clk0;
GB4_q_a[2]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[2]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[2]_clear_1 = !C1_oRST_0;
GB4_q_a[2]_PORT_A_data_out = MEMORY(GB4_q_a[2]_PORT_A_data_in_reg, GB4_q_a[2]_PORT_B_data_in_reg, GB4_q_a[2]_PORT_A_address_reg, GB4_q_a[2]_PORT_B_address_reg, GB4_q_a[2]_PORT_A_write_enable_reg, GB4_q_a[2]_PORT_B_write_enable_reg, , , GB4_q_a[2]_clock_0, GB4_q_a[2]_clock_1, GB4_q_a[2]_clock_enable_0, GB4_q_a[2]_clock_enable_1, , GB4_q_a[2]_clear_1);
GB4_q_a[2]_PORT_A_data_out_reg = DFFE(GB4_q_a[2]_PORT_A_data_out, GB4_q_a[2]_clock_0, GB4_q_a[2]_clear_1, , GB4_q_a[2]_clock_enable_0);
GB4_q_a[2] = GB4_q_a[2]_PORT_A_data_out_reg[0];


--B1L106 is VGA_Controller:u1|oVGA_R[2]~270
B1L106 = GB4_q_a[2] & B1L114 & B1L115;


--GB4_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[3]_PORT_A_data_in = VCC;
GB4_q_a[3]_PORT_A_data_in_reg = DFFE(GB4_q_a[3]_PORT_A_data_in, GB4_q_a[3]_clock_0, , , GB4_q_a[3]_clock_enable_0);
GB4_q_a[3]_PORT_B_data_in = G1_mDATAOUT[3];
GB4_q_a[3]_PORT_B_data_in_reg = DFFE(GB4_q_a[3]_PORT_B_data_in, GB4_q_a[3]_clock_1, , , GB4_q_a[3]_clock_enable_1);
GB4_q_a[3]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[3]_PORT_A_address_reg = DFFE(GB4_q_a[3]_PORT_A_address, GB4_q_a[3]_clock_0, , , GB4_q_a[3]_clock_enable_0);
GB4_q_a[3]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[3]_PORT_B_address_reg = DFFE(GB4_q_a[3]_PORT_B_address, GB4_q_a[3]_clock_1, , , GB4_q_a[3]_clock_enable_1);
GB4_q_a[3]_PORT_A_write_enable = GND;
GB4_q_a[3]_PORT_A_write_enable_reg = DFFE(GB4_q_a[3]_PORT_A_write_enable, GB4_q_a[3]_clock_0, , , GB4_q_a[3]_clock_enable_0);
GB4_q_a[3]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[3]_PORT_B_write_enable_reg = DFFE(GB4_q_a[3]_PORT_B_write_enable, GB4_q_a[3]_clock_1, , , GB4_q_a[3]_clock_enable_1);
GB4_q_a[3]_clock_0 = CCD_MCLK;
GB4_q_a[3]_clock_1 = KB1__clk0;
GB4_q_a[3]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[3]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[3]_clear_1 = !C1_oRST_0;
GB4_q_a[3]_PORT_A_data_out = MEMORY(GB4_q_a[3]_PORT_A_data_in_reg, GB4_q_a[3]_PORT_B_data_in_reg, GB4_q_a[3]_PORT_A_address_reg, GB4_q_a[3]_PORT_B_address_reg, GB4_q_a[3]_PORT_A_write_enable_reg, GB4_q_a[3]_PORT_B_write_enable_reg, , , GB4_q_a[3]_clock_0, GB4_q_a[3]_clock_1, GB4_q_a[3]_clock_enable_0, GB4_q_a[3]_clock_enable_1, , GB4_q_a[3]_clear_1);
GB4_q_a[3]_PORT_A_data_out_reg = DFFE(GB4_q_a[3]_PORT_A_data_out, GB4_q_a[3]_clock_0, GB4_q_a[3]_clear_1, , GB4_q_a[3]_clock_enable_0);
GB4_q_a[3] = GB4_q_a[3]_PORT_A_data_out_reg[0];


--B1L107 is VGA_Controller:u1|oVGA_R[3]~271
B1L107 = GB4_q_a[3] & B1L114 & B1L115;


--GB4_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[4]_PORT_A_data_in = VCC;
GB4_q_a[4]_PORT_A_data_in_reg = DFFE(GB4_q_a[4]_PORT_A_data_in, GB4_q_a[4]_clock_0, , , GB4_q_a[4]_clock_enable_0);
GB4_q_a[4]_PORT_B_data_in = G1_mDATAOUT[4];
GB4_q_a[4]_PORT_B_data_in_reg = DFFE(GB4_q_a[4]_PORT_B_data_in, GB4_q_a[4]_clock_1, , , GB4_q_a[4]_clock_enable_1);
GB4_q_a[4]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[4]_PORT_A_address_reg = DFFE(GB4_q_a[4]_PORT_A_address, GB4_q_a[4]_clock_0, , , GB4_q_a[4]_clock_enable_0);
GB4_q_a[4]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[4]_PORT_B_address_reg = DFFE(GB4_q_a[4]_PORT_B_address, GB4_q_a[4]_clock_1, , , GB4_q_a[4]_clock_enable_1);
GB4_q_a[4]_PORT_A_write_enable = GND;
GB4_q_a[4]_PORT_A_write_enable_reg = DFFE(GB4_q_a[4]_PORT_A_write_enable, GB4_q_a[4]_clock_0, , , GB4_q_a[4]_clock_enable_0);
GB4_q_a[4]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[4]_PORT_B_write_enable_reg = DFFE(GB4_q_a[4]_PORT_B_write_enable, GB4_q_a[4]_clock_1, , , GB4_q_a[4]_clock_enable_1);
GB4_q_a[4]_clock_0 = CCD_MCLK;
GB4_q_a[4]_clock_1 = KB1__clk0;
GB4_q_a[4]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[4]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[4]_clear_1 = !C1_oRST_0;
GB4_q_a[4]_PORT_A_data_out = MEMORY(GB4_q_a[4]_PORT_A_data_in_reg, GB4_q_a[4]_PORT_B_data_in_reg, GB4_q_a[4]_PORT_A_address_reg, GB4_q_a[4]_PORT_B_address_reg, GB4_q_a[4]_PORT_A_write_enable_reg, GB4_q_a[4]_PORT_B_write_enable_reg, , , GB4_q_a[4]_clock_0, GB4_q_a[4]_clock_1, GB4_q_a[4]_clock_enable_0, GB4_q_a[4]_clock_enable_1, , GB4_q_a[4]_clear_1);
GB4_q_a[4]_PORT_A_data_out_reg = DFFE(GB4_q_a[4]_PORT_A_data_out, GB4_q_a[4]_clock_0, GB4_q_a[4]_clear_1, , GB4_q_a[4]_clock_enable_0);
GB4_q_a[4] = GB4_q_a[4]_PORT_A_data_out_reg[0];


--B1L108 is VGA_Controller:u1|oVGA_R[4]~272
B1L108 = GB4_q_a[4] & B1L114 & B1L115;


--GB4_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[5]_PORT_A_data_in = VCC;
GB4_q_a[5]_PORT_A_data_in_reg = DFFE(GB4_q_a[5]_PORT_A_data_in, GB4_q_a[5]_clock_0, , , GB4_q_a[5]_clock_enable_0);
GB4_q_a[5]_PORT_B_data_in = G1_mDATAOUT[5];
GB4_q_a[5]_PORT_B_data_in_reg = DFFE(GB4_q_a[5]_PORT_B_data_in, GB4_q_a[5]_clock_1, , , GB4_q_a[5]_clock_enable_1);
GB4_q_a[5]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[5]_PORT_A_address_reg = DFFE(GB4_q_a[5]_PORT_A_address, GB4_q_a[5]_clock_0, , , GB4_q_a[5]_clock_enable_0);
GB4_q_a[5]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[5]_PORT_B_address_reg = DFFE(GB4_q_a[5]_PORT_B_address, GB4_q_a[5]_clock_1, , , GB4_q_a[5]_clock_enable_1);
GB4_q_a[5]_PORT_A_write_enable = GND;
GB4_q_a[5]_PORT_A_write_enable_reg = DFFE(GB4_q_a[5]_PORT_A_write_enable, GB4_q_a[5]_clock_0, , , GB4_q_a[5]_clock_enable_0);
GB4_q_a[5]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[5]_PORT_B_write_enable_reg = DFFE(GB4_q_a[5]_PORT_B_write_enable, GB4_q_a[5]_clock_1, , , GB4_q_a[5]_clock_enable_1);
GB4_q_a[5]_clock_0 = CCD_MCLK;
GB4_q_a[5]_clock_1 = KB1__clk0;
GB4_q_a[5]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[5]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[5]_clear_1 = !C1_oRST_0;
GB4_q_a[5]_PORT_A_data_out = MEMORY(GB4_q_a[5]_PORT_A_data_in_reg, GB4_q_a[5]_PORT_B_data_in_reg, GB4_q_a[5]_PORT_A_address_reg, GB4_q_a[5]_PORT_B_address_reg, GB4_q_a[5]_PORT_A_write_enable_reg, GB4_q_a[5]_PORT_B_write_enable_reg, , , GB4_q_a[5]_clock_0, GB4_q_a[5]_clock_1, GB4_q_a[5]_clock_enable_0, GB4_q_a[5]_clock_enable_1, , GB4_q_a[5]_clear_1);
GB4_q_a[5]_PORT_A_data_out_reg = DFFE(GB4_q_a[5]_PORT_A_data_out, GB4_q_a[5]_clock_0, GB4_q_a[5]_clear_1, , GB4_q_a[5]_clock_enable_0);
GB4_q_a[5] = GB4_q_a[5]_PORT_A_data_out_reg[0];


--B1L109 is VGA_Controller:u1|oVGA_R[5]~273
B1L109 = GB4_q_a[5] & B1L114 & B1L115;


--GB4_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[6]_PORT_A_data_in = VCC;
GB4_q_a[6]_PORT_A_data_in_reg = DFFE(GB4_q_a[6]_PORT_A_data_in, GB4_q_a[6]_clock_0, , , GB4_q_a[6]_clock_enable_0);
GB4_q_a[6]_PORT_B_data_in = G1_mDATAOUT[6];
GB4_q_a[6]_PORT_B_data_in_reg = DFFE(GB4_q_a[6]_PORT_B_data_in, GB4_q_a[6]_clock_1, , , GB4_q_a[6]_clock_enable_1);
GB4_q_a[6]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[6]_PORT_A_address_reg = DFFE(GB4_q_a[6]_PORT_A_address, GB4_q_a[6]_clock_0, , , GB4_q_a[6]_clock_enable_0);
GB4_q_a[6]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[6]_PORT_B_address_reg = DFFE(GB4_q_a[6]_PORT_B_address, GB4_q_a[6]_clock_1, , , GB4_q_a[6]_clock_enable_1);
GB4_q_a[6]_PORT_A_write_enable = GND;
GB4_q_a[6]_PORT_A_write_enable_reg = DFFE(GB4_q_a[6]_PORT_A_write_enable, GB4_q_a[6]_clock_0, , , GB4_q_a[6]_clock_enable_0);
GB4_q_a[6]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[6]_PORT_B_write_enable_reg = DFFE(GB4_q_a[6]_PORT_B_write_enable, GB4_q_a[6]_clock_1, , , GB4_q_a[6]_clock_enable_1);
GB4_q_a[6]_clock_0 = CCD_MCLK;
GB4_q_a[6]_clock_1 = KB1__clk0;
GB4_q_a[6]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[6]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[6]_clear_1 = !C1_oRST_0;
GB4_q_a[6]_PORT_A_data_out = MEMORY(GB4_q_a[6]_PORT_A_data_in_reg, GB4_q_a[6]_PORT_B_data_in_reg, GB4_q_a[6]_PORT_A_address_reg, GB4_q_a[6]_PORT_B_address_reg, GB4_q_a[6]_PORT_A_write_enable_reg, GB4_q_a[6]_PORT_B_write_enable_reg, , , GB4_q_a[6]_clock_0, GB4_q_a[6]_clock_1, GB4_q_a[6]_clock_enable_0, GB4_q_a[6]_clock_enable_1, , GB4_q_a[6]_clear_1);
GB4_q_a[6]_PORT_A_data_out_reg = DFFE(GB4_q_a[6]_PORT_A_data_out, GB4_q_a[6]_clock_0, GB4_q_a[6]_clear_1, , GB4_q_a[6]_clock_enable_0);
GB4_q_a[6] = GB4_q_a[6]_PORT_A_data_out_reg[0];


--B1L110 is VGA_Controller:u1|oVGA_R[6]~274
B1L110 = GB4_q_a[6] & B1L114 & B1L115;


--GB4_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[7]_PORT_A_data_in = VCC;
GB4_q_a[7]_PORT_A_data_in_reg = DFFE(GB4_q_a[7]_PORT_A_data_in, GB4_q_a[7]_clock_0, , , GB4_q_a[7]_clock_enable_0);
GB4_q_a[7]_PORT_B_data_in = G1_mDATAOUT[7];
GB4_q_a[7]_PORT_B_data_in_reg = DFFE(GB4_q_a[7]_PORT_B_data_in, GB4_q_a[7]_clock_1, , , GB4_q_a[7]_clock_enable_1);
GB4_q_a[7]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[7]_PORT_A_address_reg = DFFE(GB4_q_a[7]_PORT_A_address, GB4_q_a[7]_clock_0, , , GB4_q_a[7]_clock_enable_0);
GB4_q_a[7]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[7]_PORT_B_address_reg = DFFE(GB4_q_a[7]_PORT_B_address, GB4_q_a[7]_clock_1, , , GB4_q_a[7]_clock_enable_1);
GB4_q_a[7]_PORT_A_write_enable = GND;
GB4_q_a[7]_PORT_A_write_enable_reg = DFFE(GB4_q_a[7]_PORT_A_write_enable, GB4_q_a[7]_clock_0, , , GB4_q_a[7]_clock_enable_0);
GB4_q_a[7]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[7]_PORT_B_write_enable_reg = DFFE(GB4_q_a[7]_PORT_B_write_enable, GB4_q_a[7]_clock_1, , , GB4_q_a[7]_clock_enable_1);
GB4_q_a[7]_clock_0 = CCD_MCLK;
GB4_q_a[7]_clock_1 = KB1__clk0;
GB4_q_a[7]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[7]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[7]_clear_1 = !C1_oRST_0;
GB4_q_a[7]_PORT_A_data_out = MEMORY(GB4_q_a[7]_PORT_A_data_in_reg, GB4_q_a[7]_PORT_B_data_in_reg, GB4_q_a[7]_PORT_A_address_reg, GB4_q_a[7]_PORT_B_address_reg, GB4_q_a[7]_PORT_A_write_enable_reg, GB4_q_a[7]_PORT_B_write_enable_reg, , , GB4_q_a[7]_clock_0, GB4_q_a[7]_clock_1, GB4_q_a[7]_clock_enable_0, GB4_q_a[7]_clock_enable_1, , GB4_q_a[7]_clear_1);
GB4_q_a[7]_PORT_A_data_out_reg = DFFE(GB4_q_a[7]_PORT_A_data_out, GB4_q_a[7]_clock_0, GB4_q_a[7]_clear_1, , GB4_q_a[7]_clock_enable_0);
GB4_q_a[7] = GB4_q_a[7]_PORT_A_data_out_reg[0];


--B1L111 is VGA_Controller:u1|oVGA_R[7]~275
B1L111 = GB4_q_a[7] & B1L114 & B1L115;


--GB4_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[8]_PORT_A_data_in = VCC;
GB4_q_a[8]_PORT_A_data_in_reg = DFFE(GB4_q_a[8]_PORT_A_data_in, GB4_q_a[8]_clock_0, , , GB4_q_a[8]_clock_enable_0);
GB4_q_a[8]_PORT_B_data_in = G1_mDATAOUT[8];
GB4_q_a[8]_PORT_B_data_in_reg = DFFE(GB4_q_a[8]_PORT_B_data_in, GB4_q_a[8]_clock_1, , , GB4_q_a[8]_clock_enable_1);
GB4_q_a[8]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[8]_PORT_A_address_reg = DFFE(GB4_q_a[8]_PORT_A_address, GB4_q_a[8]_clock_0, , , GB4_q_a[8]_clock_enable_0);
GB4_q_a[8]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[8]_PORT_B_address_reg = DFFE(GB4_q_a[8]_PORT_B_address, GB4_q_a[8]_clock_1, , , GB4_q_a[8]_clock_enable_1);
GB4_q_a[8]_PORT_A_write_enable = GND;
GB4_q_a[8]_PORT_A_write_enable_reg = DFFE(GB4_q_a[8]_PORT_A_write_enable, GB4_q_a[8]_clock_0, , , GB4_q_a[8]_clock_enable_0);
GB4_q_a[8]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[8]_PORT_B_write_enable_reg = DFFE(GB4_q_a[8]_PORT_B_write_enable, GB4_q_a[8]_clock_1, , , GB4_q_a[8]_clock_enable_1);
GB4_q_a[8]_clock_0 = CCD_MCLK;
GB4_q_a[8]_clock_1 = KB1__clk0;
GB4_q_a[8]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[8]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[8]_clear_1 = !C1_oRST_0;
GB4_q_a[8]_PORT_A_data_out = MEMORY(GB4_q_a[8]_PORT_A_data_in_reg, GB4_q_a[8]_PORT_B_data_in_reg, GB4_q_a[8]_PORT_A_address_reg, GB4_q_a[8]_PORT_B_address_reg, GB4_q_a[8]_PORT_A_write_enable_reg, GB4_q_a[8]_PORT_B_write_enable_reg, , , GB4_q_a[8]_clock_0, GB4_q_a[8]_clock_1, GB4_q_a[8]_clock_enable_0, GB4_q_a[8]_clock_enable_1, , GB4_q_a[8]_clear_1);
GB4_q_a[8]_PORT_A_data_out_reg = DFFE(GB4_q_a[8]_PORT_A_data_out, GB4_q_a[8]_clock_0, GB4_q_a[8]_clear_1, , GB4_q_a[8]_clock_enable_0);
GB4_q_a[8] = GB4_q_a[8]_PORT_A_data_out_reg[0];


--B1L112 is VGA_Controller:u1|oVGA_R[8]~276
B1L112 = GB4_q_a[8] & B1L114 & B1L115;


--GB4_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[9]_PORT_A_data_in = VCC;
GB4_q_a[9]_PORT_A_data_in_reg = DFFE(GB4_q_a[9]_PORT_A_data_in, GB4_q_a[9]_clock_0, , , GB4_q_a[9]_clock_enable_0);
GB4_q_a[9]_PORT_B_data_in = G1_mDATAOUT[9];
GB4_q_a[9]_PORT_B_data_in_reg = DFFE(GB4_q_a[9]_PORT_B_data_in, GB4_q_a[9]_clock_1, , , GB4_q_a[9]_clock_enable_1);
GB4_q_a[9]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[9]_PORT_A_address_reg = DFFE(GB4_q_a[9]_PORT_A_address, GB4_q_a[9]_clock_0, , , GB4_q_a[9]_clock_enable_0);
GB4_q_a[9]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[9]_PORT_B_address_reg = DFFE(GB4_q_a[9]_PORT_B_address, GB4_q_a[9]_clock_1, , , GB4_q_a[9]_clock_enable_1);
GB4_q_a[9]_PORT_A_write_enable = GND;
GB4_q_a[9]_PORT_A_write_enable_reg = DFFE(GB4_q_a[9]_PORT_A_write_enable, GB4_q_a[9]_clock_0, , , GB4_q_a[9]_clock_enable_0);
GB4_q_a[9]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[9]_PORT_B_write_enable_reg = DFFE(GB4_q_a[9]_PORT_B_write_enable, GB4_q_a[9]_clock_1, , , GB4_q_a[9]_clock_enable_1);
GB4_q_a[9]_clock_0 = CCD_MCLK;
GB4_q_a[9]_clock_1 = KB1__clk0;
GB4_q_a[9]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[9]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[9]_clear_1 = !C1_oRST_0;
GB4_q_a[9]_PORT_A_data_out = MEMORY(GB4_q_a[9]_PORT_A_data_in_reg, GB4_q_a[9]_PORT_B_data_in_reg, GB4_q_a[9]_PORT_A_address_reg, GB4_q_a[9]_PORT_B_address_reg, GB4_q_a[9]_PORT_A_write_enable_reg, GB4_q_a[9]_PORT_B_write_enable_reg, , , GB4_q_a[9]_clock_0, GB4_q_a[9]_clock_1, GB4_q_a[9]_clock_enable_0, GB4_q_a[9]_clock_enable_1, , GB4_q_a[9]_clear_1);
GB4_q_a[9]_PORT_A_data_out_reg = DFFE(GB4_q_a[9]_PORT_A_data_out, GB4_q_a[9]_clock_0, GB4_q_a[9]_clear_1, , GB4_q_a[9]_clock_enable_0);
GB4_q_a[9] = GB4_q_a[9]_PORT_A_data_out_reg[0];


--B1L113 is VGA_Controller:u1|oVGA_R[9]~277
B1L113 = GB4_q_a[9] & B1L114 & B1L115;


--GB4_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[10]_PORT_A_data_in = VCC;
GB4_q_a[10]_PORT_A_data_in_reg = DFFE(GB4_q_a[10]_PORT_A_data_in, GB4_q_a[10]_clock_0, , , GB4_q_a[10]_clock_enable_0);
GB4_q_a[10]_PORT_B_data_in = G1_mDATAOUT[10];
GB4_q_a[10]_PORT_B_data_in_reg = DFFE(GB4_q_a[10]_PORT_B_data_in, GB4_q_a[10]_clock_1, , , GB4_q_a[10]_clock_enable_1);
GB4_q_a[10]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[10]_PORT_A_address_reg = DFFE(GB4_q_a[10]_PORT_A_address, GB4_q_a[10]_clock_0, , , GB4_q_a[10]_clock_enable_0);
GB4_q_a[10]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[10]_PORT_B_address_reg = DFFE(GB4_q_a[10]_PORT_B_address, GB4_q_a[10]_clock_1, , , GB4_q_a[10]_clock_enable_1);
GB4_q_a[10]_PORT_A_write_enable = GND;
GB4_q_a[10]_PORT_A_write_enable_reg = DFFE(GB4_q_a[10]_PORT_A_write_enable, GB4_q_a[10]_clock_0, , , GB4_q_a[10]_clock_enable_0);
GB4_q_a[10]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[10]_PORT_B_write_enable_reg = DFFE(GB4_q_a[10]_PORT_B_write_enable, GB4_q_a[10]_clock_1, , , GB4_q_a[10]_clock_enable_1);
GB4_q_a[10]_clock_0 = CCD_MCLK;
GB4_q_a[10]_clock_1 = KB1__clk0;
GB4_q_a[10]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[10]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[10]_clear_1 = !C1_oRST_0;
GB4_q_a[10]_PORT_A_data_out = MEMORY(GB4_q_a[10]_PORT_A_data_in_reg, GB4_q_a[10]_PORT_B_data_in_reg, GB4_q_a[10]_PORT_A_address_reg, GB4_q_a[10]_PORT_B_address_reg, GB4_q_a[10]_PORT_A_write_enable_reg, GB4_q_a[10]_PORT_B_write_enable_reg, , , GB4_q_a[10]_clock_0, GB4_q_a[10]_clock_1, GB4_q_a[10]_clock_enable_0, GB4_q_a[10]_clock_enable_1, , GB4_q_a[10]_clear_1);
GB4_q_a[10]_PORT_A_data_out_reg = DFFE(GB4_q_a[10]_PORT_A_data_out, GB4_q_a[10]_clock_0, GB4_q_a[10]_clear_1, , GB4_q_a[10]_clock_enable_0);
GB4_q_a[10] = GB4_q_a[10]_PORT_A_data_out_reg[0];


--B1L93 is VGA_Controller:u1|oVGA_G[0]~110
B1L93 = GB4_q_a[10] & B1L114 & B1L115;


--GB4_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[11]_PORT_A_data_in = VCC;
GB4_q_a[11]_PORT_A_data_in_reg = DFFE(GB4_q_a[11]_PORT_A_data_in, GB4_q_a[11]_clock_0, , , GB4_q_a[11]_clock_enable_0);
GB4_q_a[11]_PORT_B_data_in = G1_mDATAOUT[11];
GB4_q_a[11]_PORT_B_data_in_reg = DFFE(GB4_q_a[11]_PORT_B_data_in, GB4_q_a[11]_clock_1, , , GB4_q_a[11]_clock_enable_1);
GB4_q_a[11]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[11]_PORT_A_address_reg = DFFE(GB4_q_a[11]_PORT_A_address, GB4_q_a[11]_clock_0, , , GB4_q_a[11]_clock_enable_0);
GB4_q_a[11]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[11]_PORT_B_address_reg = DFFE(GB4_q_a[11]_PORT_B_address, GB4_q_a[11]_clock_1, , , GB4_q_a[11]_clock_enable_1);
GB4_q_a[11]_PORT_A_write_enable = GND;
GB4_q_a[11]_PORT_A_write_enable_reg = DFFE(GB4_q_a[11]_PORT_A_write_enable, GB4_q_a[11]_clock_0, , , GB4_q_a[11]_clock_enable_0);
GB4_q_a[11]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[11]_PORT_B_write_enable_reg = DFFE(GB4_q_a[11]_PORT_B_write_enable, GB4_q_a[11]_clock_1, , , GB4_q_a[11]_clock_enable_1);
GB4_q_a[11]_clock_0 = CCD_MCLK;
GB4_q_a[11]_clock_1 = KB1__clk0;
GB4_q_a[11]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[11]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[11]_clear_1 = !C1_oRST_0;
GB4_q_a[11]_PORT_A_data_out = MEMORY(GB4_q_a[11]_PORT_A_data_in_reg, GB4_q_a[11]_PORT_B_data_in_reg, GB4_q_a[11]_PORT_A_address_reg, GB4_q_a[11]_PORT_B_address_reg, GB4_q_a[11]_PORT_A_write_enable_reg, GB4_q_a[11]_PORT_B_write_enable_reg, , , GB4_q_a[11]_clock_0, GB4_q_a[11]_clock_1, GB4_q_a[11]_clock_enable_0, GB4_q_a[11]_clock_enable_1, , GB4_q_a[11]_clear_1);
GB4_q_a[11]_PORT_A_data_out_reg = DFFE(GB4_q_a[11]_PORT_A_data_out, GB4_q_a[11]_clock_0, GB4_q_a[11]_clear_1, , GB4_q_a[11]_clock_enable_0);
GB4_q_a[11] = GB4_q_a[11]_PORT_A_data_out_reg[0];


--B1L94 is VGA_Controller:u1|oVGA_G[1]~111
B1L94 = GB4_q_a[11] & B1L114 & B1L115;


--GB4_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[12]_PORT_A_data_in = VCC;
GB4_q_a[12]_PORT_A_data_in_reg = DFFE(GB4_q_a[12]_PORT_A_data_in, GB4_q_a[12]_clock_0, , , GB4_q_a[12]_clock_enable_0);
GB4_q_a[12]_PORT_B_data_in = G1_mDATAOUT[12];
GB4_q_a[12]_PORT_B_data_in_reg = DFFE(GB4_q_a[12]_PORT_B_data_in, GB4_q_a[12]_clock_1, , , GB4_q_a[12]_clock_enable_1);
GB4_q_a[12]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[12]_PORT_A_address_reg = DFFE(GB4_q_a[12]_PORT_A_address, GB4_q_a[12]_clock_0, , , GB4_q_a[12]_clock_enable_0);
GB4_q_a[12]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[12]_PORT_B_address_reg = DFFE(GB4_q_a[12]_PORT_B_address, GB4_q_a[12]_clock_1, , , GB4_q_a[12]_clock_enable_1);
GB4_q_a[12]_PORT_A_write_enable = GND;
GB4_q_a[12]_PORT_A_write_enable_reg = DFFE(GB4_q_a[12]_PORT_A_write_enable, GB4_q_a[12]_clock_0, , , GB4_q_a[12]_clock_enable_0);
GB4_q_a[12]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[12]_PORT_B_write_enable_reg = DFFE(GB4_q_a[12]_PORT_B_write_enable, GB4_q_a[12]_clock_1, , , GB4_q_a[12]_clock_enable_1);
GB4_q_a[12]_clock_0 = CCD_MCLK;
GB4_q_a[12]_clock_1 = KB1__clk0;
GB4_q_a[12]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[12]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[12]_clear_1 = !C1_oRST_0;
GB4_q_a[12]_PORT_A_data_out = MEMORY(GB4_q_a[12]_PORT_A_data_in_reg, GB4_q_a[12]_PORT_B_data_in_reg, GB4_q_a[12]_PORT_A_address_reg, GB4_q_a[12]_PORT_B_address_reg, GB4_q_a[12]_PORT_A_write_enable_reg, GB4_q_a[12]_PORT_B_write_enable_reg, , , GB4_q_a[12]_clock_0, GB4_q_a[12]_clock_1, GB4_q_a[12]_clock_enable_0, GB4_q_a[12]_clock_enable_1, , GB4_q_a[12]_clear_1);
GB4_q_a[12]_PORT_A_data_out_reg = DFFE(GB4_q_a[12]_PORT_A_data_out, GB4_q_a[12]_clock_0, GB4_q_a[12]_clear_1, , GB4_q_a[12]_clock_enable_0);
GB4_q_a[12] = GB4_q_a[12]_PORT_A_data_out_reg[0];


--B1L95 is VGA_Controller:u1|oVGA_G[2]~112
B1L95 = GB4_q_a[12] & B1L114 & B1L115;


--GB4_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[13]_PORT_A_data_in = VCC;
GB4_q_a[13]_PORT_A_data_in_reg = DFFE(GB4_q_a[13]_PORT_A_data_in, GB4_q_a[13]_clock_0, , , GB4_q_a[13]_clock_enable_0);
GB4_q_a[13]_PORT_B_data_in = G1_mDATAOUT[13];
GB4_q_a[13]_PORT_B_data_in_reg = DFFE(GB4_q_a[13]_PORT_B_data_in, GB4_q_a[13]_clock_1, , , GB4_q_a[13]_clock_enable_1);
GB4_q_a[13]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[13]_PORT_A_address_reg = DFFE(GB4_q_a[13]_PORT_A_address, GB4_q_a[13]_clock_0, , , GB4_q_a[13]_clock_enable_0);
GB4_q_a[13]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[13]_PORT_B_address_reg = DFFE(GB4_q_a[13]_PORT_B_address, GB4_q_a[13]_clock_1, , , GB4_q_a[13]_clock_enable_1);
GB4_q_a[13]_PORT_A_write_enable = GND;
GB4_q_a[13]_PORT_A_write_enable_reg = DFFE(GB4_q_a[13]_PORT_A_write_enable, GB4_q_a[13]_clock_0, , , GB4_q_a[13]_clock_enable_0);
GB4_q_a[13]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[13]_PORT_B_write_enable_reg = DFFE(GB4_q_a[13]_PORT_B_write_enable, GB4_q_a[13]_clock_1, , , GB4_q_a[13]_clock_enable_1);
GB4_q_a[13]_clock_0 = CCD_MCLK;
GB4_q_a[13]_clock_1 = KB1__clk0;
GB4_q_a[13]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[13]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[13]_clear_1 = !C1_oRST_0;
GB4_q_a[13]_PORT_A_data_out = MEMORY(GB4_q_a[13]_PORT_A_data_in_reg, GB4_q_a[13]_PORT_B_data_in_reg, GB4_q_a[13]_PORT_A_address_reg, GB4_q_a[13]_PORT_B_address_reg, GB4_q_a[13]_PORT_A_write_enable_reg, GB4_q_a[13]_PORT_B_write_enable_reg, , , GB4_q_a[13]_clock_0, GB4_q_a[13]_clock_1, GB4_q_a[13]_clock_enable_0, GB4_q_a[13]_clock_enable_1, , GB4_q_a[13]_clear_1);
GB4_q_a[13]_PORT_A_data_out_reg = DFFE(GB4_q_a[13]_PORT_A_data_out, GB4_q_a[13]_clock_0, GB4_q_a[13]_clear_1, , GB4_q_a[13]_clock_enable_0);
GB4_q_a[13] = GB4_q_a[13]_PORT_A_data_out_reg[0];


--B1L96 is VGA_Controller:u1|oVGA_G[3]~113
B1L96 = GB4_q_a[13] & B1L114 & B1L115;


--GB4_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[14]_PORT_A_data_in = VCC;
GB4_q_a[14]_PORT_A_data_in_reg = DFFE(GB4_q_a[14]_PORT_A_data_in, GB4_q_a[14]_clock_0, , , GB4_q_a[14]_clock_enable_0);
GB4_q_a[14]_PORT_B_data_in = G1_mDATAOUT[14];
GB4_q_a[14]_PORT_B_data_in_reg = DFFE(GB4_q_a[14]_PORT_B_data_in, GB4_q_a[14]_clock_1, , , GB4_q_a[14]_clock_enable_1);
GB4_q_a[14]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[14]_PORT_A_address_reg = DFFE(GB4_q_a[14]_PORT_A_address, GB4_q_a[14]_clock_0, , , GB4_q_a[14]_clock_enable_0);
GB4_q_a[14]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[14]_PORT_B_address_reg = DFFE(GB4_q_a[14]_PORT_B_address, GB4_q_a[14]_clock_1, , , GB4_q_a[14]_clock_enable_1);
GB4_q_a[14]_PORT_A_write_enable = GND;
GB4_q_a[14]_PORT_A_write_enable_reg = DFFE(GB4_q_a[14]_PORT_A_write_enable, GB4_q_a[14]_clock_0, , , GB4_q_a[14]_clock_enable_0);
GB4_q_a[14]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[14]_PORT_B_write_enable_reg = DFFE(GB4_q_a[14]_PORT_B_write_enable, GB4_q_a[14]_clock_1, , , GB4_q_a[14]_clock_enable_1);
GB4_q_a[14]_clock_0 = CCD_MCLK;
GB4_q_a[14]_clock_1 = KB1__clk0;
GB4_q_a[14]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[14]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[14]_clear_1 = !C1_oRST_0;
GB4_q_a[14]_PORT_A_data_out = MEMORY(GB4_q_a[14]_PORT_A_data_in_reg, GB4_q_a[14]_PORT_B_data_in_reg, GB4_q_a[14]_PORT_A_address_reg, GB4_q_a[14]_PORT_B_address_reg, GB4_q_a[14]_PORT_A_write_enable_reg, GB4_q_a[14]_PORT_B_write_enable_reg, , , GB4_q_a[14]_clock_0, GB4_q_a[14]_clock_1, GB4_q_a[14]_clock_enable_0, GB4_q_a[14]_clock_enable_1, , GB4_q_a[14]_clear_1);
GB4_q_a[14]_PORT_A_data_out_reg = DFFE(GB4_q_a[14]_PORT_A_data_out, GB4_q_a[14]_clock_0, GB4_q_a[14]_clear_1, , GB4_q_a[14]_clock_enable_0);
GB4_q_a[14] = GB4_q_a[14]_PORT_A_data_out_reg[0];


--B1L97 is VGA_Controller:u1|oVGA_G[4]~114
B1L97 = GB4_q_a[14] & B1L114 & B1L115;


--GB3_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[10]_PORT_A_data_in = VCC;
GB3_q_a[10]_PORT_A_data_in_reg = DFFE(GB3_q_a[10]_PORT_A_data_in, GB3_q_a[10]_clock_0, , , GB3_q_a[10]_clock_enable_0);
GB3_q_a[10]_PORT_B_data_in = G1_mDATAOUT[10];
GB3_q_a[10]_PORT_B_data_in_reg = DFFE(GB3_q_a[10]_PORT_B_data_in, GB3_q_a[10]_clock_1, , , GB3_q_a[10]_clock_enable_1);
GB3_q_a[10]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[10]_PORT_A_address_reg = DFFE(GB3_q_a[10]_PORT_A_address, GB3_q_a[10]_clock_0, , , GB3_q_a[10]_clock_enable_0);
GB3_q_a[10]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[10]_PORT_B_address_reg = DFFE(GB3_q_a[10]_PORT_B_address, GB3_q_a[10]_clock_1, , , GB3_q_a[10]_clock_enable_1);
GB3_q_a[10]_PORT_A_write_enable = GND;
GB3_q_a[10]_PORT_A_write_enable_reg = DFFE(GB3_q_a[10]_PORT_A_write_enable, GB3_q_a[10]_clock_0, , , GB3_q_a[10]_clock_enable_0);
GB3_q_a[10]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[10]_PORT_B_write_enable_reg = DFFE(GB3_q_a[10]_PORT_B_write_enable, GB3_q_a[10]_clock_1, , , GB3_q_a[10]_clock_enable_1);
GB3_q_a[10]_clock_0 = CCD_MCLK;
GB3_q_a[10]_clock_1 = KB1__clk0;
GB3_q_a[10]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[10]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[10]_clear_1 = !C1_oRST_0;
GB3_q_a[10]_PORT_A_data_out = MEMORY(GB3_q_a[10]_PORT_A_data_in_reg, GB3_q_a[10]_PORT_B_data_in_reg, GB3_q_a[10]_PORT_A_address_reg, GB3_q_a[10]_PORT_B_address_reg, GB3_q_a[10]_PORT_A_write_enable_reg, GB3_q_a[10]_PORT_B_write_enable_reg, , , GB3_q_a[10]_clock_0, GB3_q_a[10]_clock_1, GB3_q_a[10]_clock_enable_0, GB3_q_a[10]_clock_enable_1, , GB3_q_a[10]_clear_1);
GB3_q_a[10]_PORT_A_data_out_reg = DFFE(GB3_q_a[10]_PORT_A_data_out, GB3_q_a[10]_clock_0, GB3_q_a[10]_clear_1, , GB3_q_a[10]_clock_enable_0);
GB3_q_a[10] = GB3_q_a[10]_PORT_A_data_out_reg[0];


--B1L98 is VGA_Controller:u1|oVGA_G[5]~115
B1L98 = GB3_q_a[10] & B1L114 & B1L115;


--GB3_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[11]_PORT_A_data_in = VCC;
GB3_q_a[11]_PORT_A_data_in_reg = DFFE(GB3_q_a[11]_PORT_A_data_in, GB3_q_a[11]_clock_0, , , GB3_q_a[11]_clock_enable_0);
GB3_q_a[11]_PORT_B_data_in = G1_mDATAOUT[11];
GB3_q_a[11]_PORT_B_data_in_reg = DFFE(GB3_q_a[11]_PORT_B_data_in, GB3_q_a[11]_clock_1, , , GB3_q_a[11]_clock_enable_1);
GB3_q_a[11]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[11]_PORT_A_address_reg = DFFE(GB3_q_a[11]_PORT_A_address, GB3_q_a[11]_clock_0, , , GB3_q_a[11]_clock_enable_0);
GB3_q_a[11]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[11]_PORT_B_address_reg = DFFE(GB3_q_a[11]_PORT_B_address, GB3_q_a[11]_clock_1, , , GB3_q_a[11]_clock_enable_1);
GB3_q_a[11]_PORT_A_write_enable = GND;
GB3_q_a[11]_PORT_A_write_enable_reg = DFFE(GB3_q_a[11]_PORT_A_write_enable, GB3_q_a[11]_clock_0, , , GB3_q_a[11]_clock_enable_0);
GB3_q_a[11]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[11]_PORT_B_write_enable_reg = DFFE(GB3_q_a[11]_PORT_B_write_enable, GB3_q_a[11]_clock_1, , , GB3_q_a[11]_clock_enable_1);
GB3_q_a[11]_clock_0 = CCD_MCLK;
GB3_q_a[11]_clock_1 = KB1__clk0;
GB3_q_a[11]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[11]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[11]_clear_1 = !C1_oRST_0;
GB3_q_a[11]_PORT_A_data_out = MEMORY(GB3_q_a[11]_PORT_A_data_in_reg, GB3_q_a[11]_PORT_B_data_in_reg, GB3_q_a[11]_PORT_A_address_reg, GB3_q_a[11]_PORT_B_address_reg, GB3_q_a[11]_PORT_A_write_enable_reg, GB3_q_a[11]_PORT_B_write_enable_reg, , , GB3_q_a[11]_clock_0, GB3_q_a[11]_clock_1, GB3_q_a[11]_clock_enable_0, GB3_q_a[11]_clock_enable_1, , GB3_q_a[11]_clear_1);
GB3_q_a[11]_PORT_A_data_out_reg = DFFE(GB3_q_a[11]_PORT_A_data_out, GB3_q_a[11]_clock_0, GB3_q_a[11]_clear_1, , GB3_q_a[11]_clock_enable_0);
GB3_q_a[11] = GB3_q_a[11]_PORT_A_data_out_reg[0];


--B1L99 is VGA_Controller:u1|oVGA_G[6]~116
B1L99 = GB3_q_a[11] & B1L114 & B1L115;


--GB3_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[12]_PORT_A_data_in = VCC;
GB3_q_a[12]_PORT_A_data_in_reg = DFFE(GB3_q_a[12]_PORT_A_data_in, GB3_q_a[12]_clock_0, , , GB3_q_a[12]_clock_enable_0);
GB3_q_a[12]_PORT_B_data_in = G1_mDATAOUT[12];
GB3_q_a[12]_PORT_B_data_in_reg = DFFE(GB3_q_a[12]_PORT_B_data_in, GB3_q_a[12]_clock_1, , , GB3_q_a[12]_clock_enable_1);
GB3_q_a[12]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[12]_PORT_A_address_reg = DFFE(GB3_q_a[12]_PORT_A_address, GB3_q_a[12]_clock_0, , , GB3_q_a[12]_clock_enable_0);
GB3_q_a[12]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[12]_PORT_B_address_reg = DFFE(GB3_q_a[12]_PORT_B_address, GB3_q_a[12]_clock_1, , , GB3_q_a[12]_clock_enable_1);
GB3_q_a[12]_PORT_A_write_enable = GND;
GB3_q_a[12]_PORT_A_write_enable_reg = DFFE(GB3_q_a[12]_PORT_A_write_enable, GB3_q_a[12]_clock_0, , , GB3_q_a[12]_clock_enable_0);
GB3_q_a[12]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[12]_PORT_B_write_enable_reg = DFFE(GB3_q_a[12]_PORT_B_write_enable, GB3_q_a[12]_clock_1, , , GB3_q_a[12]_clock_enable_1);
GB3_q_a[12]_clock_0 = CCD_MCLK;
GB3_q_a[12]_clock_1 = KB1__clk0;
GB3_q_a[12]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[12]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[12]_clear_1 = !C1_oRST_0;
GB3_q_a[12]_PORT_A_data_out = MEMORY(GB3_q_a[12]_PORT_A_data_in_reg, GB3_q_a[12]_PORT_B_data_in_reg, GB3_q_a[12]_PORT_A_address_reg, GB3_q_a[12]_PORT_B_address_reg, GB3_q_a[12]_PORT_A_write_enable_reg, GB3_q_a[12]_PORT_B_write_enable_reg, , , GB3_q_a[12]_clock_0, GB3_q_a[12]_clock_1, GB3_q_a[12]_clock_enable_0, GB3_q_a[12]_clock_enable_1, , GB3_q_a[12]_clear_1);
GB3_q_a[12]_PORT_A_data_out_reg = DFFE(GB3_q_a[12]_PORT_A_data_out, GB3_q_a[12]_clock_0, GB3_q_a[12]_clear_1, , GB3_q_a[12]_clock_enable_0);
GB3_q_a[12] = GB3_q_a[12]_PORT_A_data_out_reg[0];


--B1L100 is VGA_Controller:u1|oVGA_G[7]~117
B1L100 = GB3_q_a[12] & B1L114 & B1L115;


--GB3_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[13]_PORT_A_data_in = VCC;
GB3_q_a[13]_PORT_A_data_in_reg = DFFE(GB3_q_a[13]_PORT_A_data_in, GB3_q_a[13]_clock_0, , , GB3_q_a[13]_clock_enable_0);
GB3_q_a[13]_PORT_B_data_in = G1_mDATAOUT[13];
GB3_q_a[13]_PORT_B_data_in_reg = DFFE(GB3_q_a[13]_PORT_B_data_in, GB3_q_a[13]_clock_1, , , GB3_q_a[13]_clock_enable_1);
GB3_q_a[13]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[13]_PORT_A_address_reg = DFFE(GB3_q_a[13]_PORT_A_address, GB3_q_a[13]_clock_0, , , GB3_q_a[13]_clock_enable_0);
GB3_q_a[13]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[13]_PORT_B_address_reg = DFFE(GB3_q_a[13]_PORT_B_address, GB3_q_a[13]_clock_1, , , GB3_q_a[13]_clock_enable_1);
GB3_q_a[13]_PORT_A_write_enable = GND;
GB3_q_a[13]_PORT_A_write_enable_reg = DFFE(GB3_q_a[13]_PORT_A_write_enable, GB3_q_a[13]_clock_0, , , GB3_q_a[13]_clock_enable_0);
GB3_q_a[13]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[13]_PORT_B_write_enable_reg = DFFE(GB3_q_a[13]_PORT_B_write_enable, GB3_q_a[13]_clock_1, , , GB3_q_a[13]_clock_enable_1);
GB3_q_a[13]_clock_0 = CCD_MCLK;
GB3_q_a[13]_clock_1 = KB1__clk0;
GB3_q_a[13]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[13]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[13]_clear_1 = !C1_oRST_0;
GB3_q_a[13]_PORT_A_data_out = MEMORY(GB3_q_a[13]_PORT_A_data_in_reg, GB3_q_a[13]_PORT_B_data_in_reg, GB3_q_a[13]_PORT_A_address_reg, GB3_q_a[13]_PORT_B_address_reg, GB3_q_a[13]_PORT_A_write_enable_reg, GB3_q_a[13]_PORT_B_write_enable_reg, , , GB3_q_a[13]_clock_0, GB3_q_a[13]_clock_1, GB3_q_a[13]_clock_enable_0, GB3_q_a[13]_clock_enable_1, , GB3_q_a[13]_clear_1);
GB3_q_a[13]_PORT_A_data_out_reg = DFFE(GB3_q_a[13]_PORT_A_data_out, GB3_q_a[13]_clock_0, GB3_q_a[13]_clear_1, , GB3_q_a[13]_clock_enable_0);
GB3_q_a[13] = GB3_q_a[13]_PORT_A_data_out_reg[0];


--B1L101 is VGA_Controller:u1|oVGA_G[8]~118
B1L101 = GB3_q_a[13] & B1L114 & B1L115;


--GB3_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[14]_PORT_A_data_in = VCC;
GB3_q_a[14]_PORT_A_data_in_reg = DFFE(GB3_q_a[14]_PORT_A_data_in, GB3_q_a[14]_clock_0, , , GB3_q_a[14]_clock_enable_0);
GB3_q_a[14]_PORT_B_data_in = G1_mDATAOUT[14];
GB3_q_a[14]_PORT_B_data_in_reg = DFFE(GB3_q_a[14]_PORT_B_data_in, GB3_q_a[14]_clock_1, , , GB3_q_a[14]_clock_enable_1);
GB3_q_a[14]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[14]_PORT_A_address_reg = DFFE(GB3_q_a[14]_PORT_A_address, GB3_q_a[14]_clock_0, , , GB3_q_a[14]_clock_enable_0);
GB3_q_a[14]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[14]_PORT_B_address_reg = DFFE(GB3_q_a[14]_PORT_B_address, GB3_q_a[14]_clock_1, , , GB3_q_a[14]_clock_enable_1);
GB3_q_a[14]_PORT_A_write_enable = GND;
GB3_q_a[14]_PORT_A_write_enable_reg = DFFE(GB3_q_a[14]_PORT_A_write_enable, GB3_q_a[14]_clock_0, , , GB3_q_a[14]_clock_enable_0);
GB3_q_a[14]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[14]_PORT_B_write_enable_reg = DFFE(GB3_q_a[14]_PORT_B_write_enable, GB3_q_a[14]_clock_1, , , GB3_q_a[14]_clock_enable_1);
GB3_q_a[14]_clock_0 = CCD_MCLK;
GB3_q_a[14]_clock_1 = KB1__clk0;
GB3_q_a[14]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[14]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[14]_clear_1 = !C1_oRST_0;
GB3_q_a[14]_PORT_A_data_out = MEMORY(GB3_q_a[14]_PORT_A_data_in_reg, GB3_q_a[14]_PORT_B_data_in_reg, GB3_q_a[14]_PORT_A_address_reg, GB3_q_a[14]_PORT_B_address_reg, GB3_q_a[14]_PORT_A_write_enable_reg, GB3_q_a[14]_PORT_B_write_enable_reg, , , GB3_q_a[14]_clock_0, GB3_q_a[14]_clock_1, GB3_q_a[14]_clock_enable_0, GB3_q_a[14]_clock_enable_1, , GB3_q_a[14]_clear_1);
GB3_q_a[14]_PORT_A_data_out_reg = DFFE(GB3_q_a[14]_PORT_A_data_out, GB3_q_a[14]_clock_0, GB3_q_a[14]_clear_1, , GB3_q_a[14]_clock_enable_0);
GB3_q_a[14] = GB3_q_a[14]_PORT_A_data_out_reg[0];


--B1L102 is VGA_Controller:u1|oVGA_G[9]~119
B1L102 = GB3_q_a[14] & B1L114 & B1L115;


--GB3_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[0]_PORT_A_data_in = VCC;
GB3_q_a[0]_PORT_A_data_in_reg = DFFE(GB3_q_a[0]_PORT_A_data_in, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_data_in = G1_mDATAOUT[0];
GB3_q_a[0]_PORT_B_data_in_reg = DFFE(GB3_q_a[0]_PORT_B_data_in, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[0]_PORT_A_address_reg = DFFE(GB3_q_a[0]_PORT_A_address, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[0]_PORT_B_address_reg = DFFE(GB3_q_a[0]_PORT_B_address, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_write_enable = GND;
GB3_q_a[0]_PORT_A_write_enable_reg = DFFE(GB3_q_a[0]_PORT_A_write_enable, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[0]_PORT_B_write_enable_reg = DFFE(GB3_q_a[0]_PORT_B_write_enable, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_clock_0 = CCD_MCLK;
GB3_q_a[0]_clock_1 = KB1__clk0;
GB3_q_a[0]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[0]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[0]_clear_1 = !C1_oRST_0;
GB3_q_a[0]_PORT_A_data_out = MEMORY(GB3_q_a[0]_PORT_A_data_in_reg, GB3_q_a[0]_PORT_B_data_in_reg, GB3_q_a[0]_PORT_A_address_reg, GB3_q_a[0]_PORT_B_address_reg, GB3_q_a[0]_PORT_A_write_enable_reg, GB3_q_a[0]_PORT_B_write_enable_reg, , , GB3_q_a[0]_clock_0, GB3_q_a[0]_clock_1, GB3_q_a[0]_clock_enable_0, GB3_q_a[0]_clock_enable_1, , GB3_q_a[0]_clear_1);
GB3_q_a[0]_PORT_A_data_out_reg = DFFE(GB3_q_a[0]_PORT_A_data_out, GB3_q_a[0]_clock_0, GB3_q_a[0]_clear_1, , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0] = GB3_q_a[0]_PORT_A_data_out_reg[0];


--B1L83 is VGA_Controller:u1|oVGA_B[0]~110
B1L83 = GB3_q_a[0] & B1L114 & B1L115;


--GB3_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[1]_PORT_A_data_in = VCC;
GB3_q_a[1]_PORT_A_data_in_reg = DFFE(GB3_q_a[1]_PORT_A_data_in, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_data_in = G1_mDATAOUT[1];
GB3_q_a[1]_PORT_B_data_in_reg = DFFE(GB3_q_a[1]_PORT_B_data_in, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[1]_PORT_A_address_reg = DFFE(GB3_q_a[1]_PORT_A_address, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[1]_PORT_B_address_reg = DFFE(GB3_q_a[1]_PORT_B_address, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_write_enable = GND;
GB3_q_a[1]_PORT_A_write_enable_reg = DFFE(GB3_q_a[1]_PORT_A_write_enable, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[1]_PORT_B_write_enable_reg = DFFE(GB3_q_a[1]_PORT_B_write_enable, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_clock_0 = CCD_MCLK;
GB3_q_a[1]_clock_1 = KB1__clk0;
GB3_q_a[1]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[1]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[1]_clear_1 = !C1_oRST_0;
GB3_q_a[1]_PORT_A_data_out = MEMORY(GB3_q_a[1]_PORT_A_data_in_reg, GB3_q_a[1]_PORT_B_data_in_reg, GB3_q_a[1]_PORT_A_address_reg, GB3_q_a[1]_PORT_B_address_reg, GB3_q_a[1]_PORT_A_write_enable_reg, GB3_q_a[1]_PORT_B_write_enable_reg, , , GB3_q_a[1]_clock_0, GB3_q_a[1]_clock_1, GB3_q_a[1]_clock_enable_0, GB3_q_a[1]_clock_enable_1, , GB3_q_a[1]_clear_1);
GB3_q_a[1]_PORT_A_data_out_reg = DFFE(GB3_q_a[1]_PORT_A_data_out, GB3_q_a[1]_clock_0, GB3_q_a[1]_clear_1, , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1] = GB3_q_a[1]_PORT_A_data_out_reg[0];


--B1L84 is VGA_Controller:u1|oVGA_B[1]~111
B1L84 = GB3_q_a[1] & B1L114 & B1L115;


--GB3_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[2]_PORT_A_data_in = VCC;
GB3_q_a[2]_PORT_A_data_in_reg = DFFE(GB3_q_a[2]_PORT_A_data_in, GB3_q_a[2]_clock_0, , , GB3_q_a[2]_clock_enable_0);
GB3_q_a[2]_PORT_B_data_in = G1_mDATAOUT[2];
GB3_q_a[2]_PORT_B_data_in_reg = DFFE(GB3_q_a[2]_PORT_B_data_in, GB3_q_a[2]_clock_1, , , GB3_q_a[2]_clock_enable_1);
GB3_q_a[2]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[2]_PORT_A_address_reg = DFFE(GB3_q_a[2]_PORT_A_address, GB3_q_a[2]_clock_0, , , GB3_q_a[2]_clock_enable_0);
GB3_q_a[2]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[2]_PORT_B_address_reg = DFFE(GB3_q_a[2]_PORT_B_address, GB3_q_a[2]_clock_1, , , GB3_q_a[2]_clock_enable_1);
GB3_q_a[2]_PORT_A_write_enable = GND;
GB3_q_a[2]_PORT_A_write_enable_reg = DFFE(GB3_q_a[2]_PORT_A_write_enable, GB3_q_a[2]_clock_0, , , GB3_q_a[2]_clock_enable_0);
GB3_q_a[2]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[2]_PORT_B_write_enable_reg = DFFE(GB3_q_a[2]_PORT_B_write_enable, GB3_q_a[2]_clock_1, , , GB3_q_a[2]_clock_enable_1);
GB3_q_a[2]_clock_0 = CCD_MCLK;
GB3_q_a[2]_clock_1 = KB1__clk0;
GB3_q_a[2]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[2]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[2]_clear_1 = !C1_oRST_0;
GB3_q_a[2]_PORT_A_data_out = MEMORY(GB3_q_a[2]_PORT_A_data_in_reg, GB3_q_a[2]_PORT_B_data_in_reg, GB3_q_a[2]_PORT_A_address_reg, GB3_q_a[2]_PORT_B_address_reg, GB3_q_a[2]_PORT_A_write_enable_reg, GB3_q_a[2]_PORT_B_write_enable_reg, , , GB3_q_a[2]_clock_0, GB3_q_a[2]_clock_1, GB3_q_a[2]_clock_enable_0, GB3_q_a[2]_clock_enable_1, , GB3_q_a[2]_clear_1);
GB3_q_a[2]_PORT_A_data_out_reg = DFFE(GB3_q_a[2]_PORT_A_data_out, GB3_q_a[2]_clock_0, GB3_q_a[2]_clear_1, , GB3_q_a[2]_clock_enable_0);
GB3_q_a[2] = GB3_q_a[2]_PORT_A_data_out_reg[0];


--B1L85 is VGA_Controller:u1|oVGA_B[2]~112
B1L85 = GB3_q_a[2] & B1L114 & B1L115;


--GB3_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[3]_PORT_A_data_in = VCC;
GB3_q_a[3]_PORT_A_data_in_reg = DFFE(GB3_q_a[3]_PORT_A_data_in, GB3_q_a[3]_clock_0, , , GB3_q_a[3]_clock_enable_0);
GB3_q_a[3]_PORT_B_data_in = G1_mDATAOUT[3];
GB3_q_a[3]_PORT_B_data_in_reg = DFFE(GB3_q_a[3]_PORT_B_data_in, GB3_q_a[3]_clock_1, , , GB3_q_a[3]_clock_enable_1);
GB3_q_a[3]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[3]_PORT_A_address_reg = DFFE(GB3_q_a[3]_PORT_A_address, GB3_q_a[3]_clock_0, , , GB3_q_a[3]_clock_enable_0);
GB3_q_a[3]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[3]_PORT_B_address_reg = DFFE(GB3_q_a[3]_PORT_B_address, GB3_q_a[3]_clock_1, , , GB3_q_a[3]_clock_enable_1);
GB3_q_a[3]_PORT_A_write_enable = GND;
GB3_q_a[3]_PORT_A_write_enable_reg = DFFE(GB3_q_a[3]_PORT_A_write_enable, GB3_q_a[3]_clock_0, , , GB3_q_a[3]_clock_enable_0);
GB3_q_a[3]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[3]_PORT_B_write_enable_reg = DFFE(GB3_q_a[3]_PORT_B_write_enable, GB3_q_a[3]_clock_1, , , GB3_q_a[3]_clock_enable_1);
GB3_q_a[3]_clock_0 = CCD_MCLK;
GB3_q_a[3]_clock_1 = KB1__clk0;
GB3_q_a[3]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[3]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[3]_clear_1 = !C1_oRST_0;
GB3_q_a[3]_PORT_A_data_out = MEMORY(GB3_q_a[3]_PORT_A_data_in_reg, GB3_q_a[3]_PORT_B_data_in_reg, GB3_q_a[3]_PORT_A_address_reg, GB3_q_a[3]_PORT_B_address_reg, GB3_q_a[3]_PORT_A_write_enable_reg, GB3_q_a[3]_PORT_B_write_enable_reg, , , GB3_q_a[3]_clock_0, GB3_q_a[3]_clock_1, GB3_q_a[3]_clock_enable_0, GB3_q_a[3]_clock_enable_1, , GB3_q_a[3]_clear_1);
GB3_q_a[3]_PORT_A_data_out_reg = DFFE(GB3_q_a[3]_PORT_A_data_out, GB3_q_a[3]_clock_0, GB3_q_a[3]_clear_1, , GB3_q_a[3]_clock_enable_0);
GB3_q_a[3] = GB3_q_a[3]_PORT_A_data_out_reg[0];


--B1L86 is VGA_Controller:u1|oVGA_B[3]~113
B1L86 = GB3_q_a[3] & B1L114 & B1L115;


--GB3_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[4]_PORT_A_data_in = VCC;
GB3_q_a[4]_PORT_A_data_in_reg = DFFE(GB3_q_a[4]_PORT_A_data_in, GB3_q_a[4]_clock_0, , , GB3_q_a[4]_clock_enable_0);
GB3_q_a[4]_PORT_B_data_in = G1_mDATAOUT[4];
GB3_q_a[4]_PORT_B_data_in_reg = DFFE(GB3_q_a[4]_PORT_B_data_in, GB3_q_a[4]_clock_1, , , GB3_q_a[4]_clock_enable_1);
GB3_q_a[4]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[4]_PORT_A_address_reg = DFFE(GB3_q_a[4]_PORT_A_address, GB3_q_a[4]_clock_0, , , GB3_q_a[4]_clock_enable_0);
GB3_q_a[4]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[4]_PORT_B_address_reg = DFFE(GB3_q_a[4]_PORT_B_address, GB3_q_a[4]_clock_1, , , GB3_q_a[4]_clock_enable_1);
GB3_q_a[4]_PORT_A_write_enable = GND;
GB3_q_a[4]_PORT_A_write_enable_reg = DFFE(GB3_q_a[4]_PORT_A_write_enable, GB3_q_a[4]_clock_0, , , GB3_q_a[4]_clock_enable_0);
GB3_q_a[4]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[4]_PORT_B_write_enable_reg = DFFE(GB3_q_a[4]_PORT_B_write_enable, GB3_q_a[4]_clock_1, , , GB3_q_a[4]_clock_enable_1);
GB3_q_a[4]_clock_0 = CCD_MCLK;
GB3_q_a[4]_clock_1 = KB1__clk0;
GB3_q_a[4]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[4]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[4]_clear_1 = !C1_oRST_0;
GB3_q_a[4]_PORT_A_data_out = MEMORY(GB3_q_a[4]_PORT_A_data_in_reg, GB3_q_a[4]_PORT_B_data_in_reg, GB3_q_a[4]_PORT_A_address_reg, GB3_q_a[4]_PORT_B_address_reg, GB3_q_a[4]_PORT_A_write_enable_reg, GB3_q_a[4]_PORT_B_write_enable_reg, , , GB3_q_a[4]_clock_0, GB3_q_a[4]_clock_1, GB3_q_a[4]_clock_enable_0, GB3_q_a[4]_clock_enable_1, , GB3_q_a[4]_clear_1);
GB3_q_a[4]_PORT_A_data_out_reg = DFFE(GB3_q_a[4]_PORT_A_data_out, GB3_q_a[4]_clock_0, GB3_q_a[4]_clear_1, , GB3_q_a[4]_clock_enable_0);
GB3_q_a[4] = GB3_q_a[4]_PORT_A_data_out_reg[0];


--B1L87 is VGA_Controller:u1|oVGA_B[4]~114
B1L87 = GB3_q_a[4] & B1L114 & B1L115;


--GB3_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[5]_PORT_A_data_in = VCC;
GB3_q_a[5]_PORT_A_data_in_reg = DFFE(GB3_q_a[5]_PORT_A_data_in, GB3_q_a[5]_clock_0, , , GB3_q_a[5]_clock_enable_0);
GB3_q_a[5]_PORT_B_data_in = G1_mDATAOUT[5];
GB3_q_a[5]_PORT_B_data_in_reg = DFFE(GB3_q_a[5]_PORT_B_data_in, GB3_q_a[5]_clock_1, , , GB3_q_a[5]_clock_enable_1);
GB3_q_a[5]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[5]_PORT_A_address_reg = DFFE(GB3_q_a[5]_PORT_A_address, GB3_q_a[5]_clock_0, , , GB3_q_a[5]_clock_enable_0);
GB3_q_a[5]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[5]_PORT_B_address_reg = DFFE(GB3_q_a[5]_PORT_B_address, GB3_q_a[5]_clock_1, , , GB3_q_a[5]_clock_enable_1);
GB3_q_a[5]_PORT_A_write_enable = GND;
GB3_q_a[5]_PORT_A_write_enable_reg = DFFE(GB3_q_a[5]_PORT_A_write_enable, GB3_q_a[5]_clock_0, , , GB3_q_a[5]_clock_enable_0);
GB3_q_a[5]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[5]_PORT_B_write_enable_reg = DFFE(GB3_q_a[5]_PORT_B_write_enable, GB3_q_a[5]_clock_1, , , GB3_q_a[5]_clock_enable_1);
GB3_q_a[5]_clock_0 = CCD_MCLK;
GB3_q_a[5]_clock_1 = KB1__clk0;
GB3_q_a[5]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[5]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[5]_clear_1 = !C1_oRST_0;
GB3_q_a[5]_PORT_A_data_out = MEMORY(GB3_q_a[5]_PORT_A_data_in_reg, GB3_q_a[5]_PORT_B_data_in_reg, GB3_q_a[5]_PORT_A_address_reg, GB3_q_a[5]_PORT_B_address_reg, GB3_q_a[5]_PORT_A_write_enable_reg, GB3_q_a[5]_PORT_B_write_enable_reg, , , GB3_q_a[5]_clock_0, GB3_q_a[5]_clock_1, GB3_q_a[5]_clock_enable_0, GB3_q_a[5]_clock_enable_1, , GB3_q_a[5]_clear_1);
GB3_q_a[5]_PORT_A_data_out_reg = DFFE(GB3_q_a[5]_PORT_A_data_out, GB3_q_a[5]_clock_0, GB3_q_a[5]_clear_1, , GB3_q_a[5]_clock_enable_0);
GB3_q_a[5] = GB3_q_a[5]_PORT_A_data_out_reg[0];


--B1L88 is VGA_Controller:u1|oVGA_B[5]~115
B1L88 = GB3_q_a[5] & B1L114 & B1L115;


--GB3_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[6]_PORT_A_data_in = VCC;
GB3_q_a[6]_PORT_A_data_in_reg = DFFE(GB3_q_a[6]_PORT_A_data_in, GB3_q_a[6]_clock_0, , , GB3_q_a[6]_clock_enable_0);
GB3_q_a[6]_PORT_B_data_in = G1_mDATAOUT[6];
GB3_q_a[6]_PORT_B_data_in_reg = DFFE(GB3_q_a[6]_PORT_B_data_in, GB3_q_a[6]_clock_1, , , GB3_q_a[6]_clock_enable_1);
GB3_q_a[6]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[6]_PORT_A_address_reg = DFFE(GB3_q_a[6]_PORT_A_address, GB3_q_a[6]_clock_0, , , GB3_q_a[6]_clock_enable_0);
GB3_q_a[6]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[6]_PORT_B_address_reg = DFFE(GB3_q_a[6]_PORT_B_address, GB3_q_a[6]_clock_1, , , GB3_q_a[6]_clock_enable_1);
GB3_q_a[6]_PORT_A_write_enable = GND;
GB3_q_a[6]_PORT_A_write_enable_reg = DFFE(GB3_q_a[6]_PORT_A_write_enable, GB3_q_a[6]_clock_0, , , GB3_q_a[6]_clock_enable_0);
GB3_q_a[6]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[6]_PORT_B_write_enable_reg = DFFE(GB3_q_a[6]_PORT_B_write_enable, GB3_q_a[6]_clock_1, , , GB3_q_a[6]_clock_enable_1);
GB3_q_a[6]_clock_0 = CCD_MCLK;
GB3_q_a[6]_clock_1 = KB1__clk0;
GB3_q_a[6]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[6]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[6]_clear_1 = !C1_oRST_0;
GB3_q_a[6]_PORT_A_data_out = MEMORY(GB3_q_a[6]_PORT_A_data_in_reg, GB3_q_a[6]_PORT_B_data_in_reg, GB3_q_a[6]_PORT_A_address_reg, GB3_q_a[6]_PORT_B_address_reg, GB3_q_a[6]_PORT_A_write_enable_reg, GB3_q_a[6]_PORT_B_write_enable_reg, , , GB3_q_a[6]_clock_0, GB3_q_a[6]_clock_1, GB3_q_a[6]_clock_enable_0, GB3_q_a[6]_clock_enable_1, , GB3_q_a[6]_clear_1);
GB3_q_a[6]_PORT_A_data_out_reg = DFFE(GB3_q_a[6]_PORT_A_data_out, GB3_q_a[6]_clock_0, GB3_q_a[6]_clear_1, , GB3_q_a[6]_clock_enable_0);
GB3_q_a[6] = GB3_q_a[6]_PORT_A_data_out_reg[0];


--B1L89 is VGA_Controller:u1|oVGA_B[6]~116
B1L89 = GB3_q_a[6] & B1L114 & B1L115;


--GB3_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[7]_PORT_A_data_in = VCC;
GB3_q_a[7]_PORT_A_data_in_reg = DFFE(GB3_q_a[7]_PORT_A_data_in, GB3_q_a[7]_clock_0, , , GB3_q_a[7]_clock_enable_0);
GB3_q_a[7]_PORT_B_data_in = G1_mDATAOUT[7];
GB3_q_a[7]_PORT_B_data_in_reg = DFFE(GB3_q_a[7]_PORT_B_data_in, GB3_q_a[7]_clock_1, , , GB3_q_a[7]_clock_enable_1);
GB3_q_a[7]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[7]_PORT_A_address_reg = DFFE(GB3_q_a[7]_PORT_A_address, GB3_q_a[7]_clock_0, , , GB3_q_a[7]_clock_enable_0);
GB3_q_a[7]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[7]_PORT_B_address_reg = DFFE(GB3_q_a[7]_PORT_B_address, GB3_q_a[7]_clock_1, , , GB3_q_a[7]_clock_enable_1);
GB3_q_a[7]_PORT_A_write_enable = GND;
GB3_q_a[7]_PORT_A_write_enable_reg = DFFE(GB3_q_a[7]_PORT_A_write_enable, GB3_q_a[7]_clock_0, , , GB3_q_a[7]_clock_enable_0);
GB3_q_a[7]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[7]_PORT_B_write_enable_reg = DFFE(GB3_q_a[7]_PORT_B_write_enable, GB3_q_a[7]_clock_1, , , GB3_q_a[7]_clock_enable_1);
GB3_q_a[7]_clock_0 = CCD_MCLK;
GB3_q_a[7]_clock_1 = KB1__clk0;
GB3_q_a[7]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[7]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[7]_clear_1 = !C1_oRST_0;
GB3_q_a[7]_PORT_A_data_out = MEMORY(GB3_q_a[7]_PORT_A_data_in_reg, GB3_q_a[7]_PORT_B_data_in_reg, GB3_q_a[7]_PORT_A_address_reg, GB3_q_a[7]_PORT_B_address_reg, GB3_q_a[7]_PORT_A_write_enable_reg, GB3_q_a[7]_PORT_B_write_enable_reg, , , GB3_q_a[7]_clock_0, GB3_q_a[7]_clock_1, GB3_q_a[7]_clock_enable_0, GB3_q_a[7]_clock_enable_1, , GB3_q_a[7]_clear_1);
GB3_q_a[7]_PORT_A_data_out_reg = DFFE(GB3_q_a[7]_PORT_A_data_out, GB3_q_a[7]_clock_0, GB3_q_a[7]_clear_1, , GB3_q_a[7]_clock_enable_0);
GB3_q_a[7] = GB3_q_a[7]_PORT_A_data_out_reg[0];


--B1L90 is VGA_Controller:u1|oVGA_B[7]~117
B1L90 = GB3_q_a[7] & B1L114 & B1L115;


--GB3_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[8]_PORT_A_data_in = VCC;
GB3_q_a[8]_PORT_A_data_in_reg = DFFE(GB3_q_a[8]_PORT_A_data_in, GB3_q_a[8]_clock_0, , , GB3_q_a[8]_clock_enable_0);
GB3_q_a[8]_PORT_B_data_in = G1_mDATAOUT[8];
GB3_q_a[8]_PORT_B_data_in_reg = DFFE(GB3_q_a[8]_PORT_B_data_in, GB3_q_a[8]_clock_1, , , GB3_q_a[8]_clock_enable_1);
GB3_q_a[8]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[8]_PORT_A_address_reg = DFFE(GB3_q_a[8]_PORT_A_address, GB3_q_a[8]_clock_0, , , GB3_q_a[8]_clock_enable_0);
GB3_q_a[8]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[8]_PORT_B_address_reg = DFFE(GB3_q_a[8]_PORT_B_address, GB3_q_a[8]_clock_1, , , GB3_q_a[8]_clock_enable_1);
GB3_q_a[8]_PORT_A_write_enable = GND;
GB3_q_a[8]_PORT_A_write_enable_reg = DFFE(GB3_q_a[8]_PORT_A_write_enable, GB3_q_a[8]_clock_0, , , GB3_q_a[8]_clock_enable_0);
GB3_q_a[8]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[8]_PORT_B_write_enable_reg = DFFE(GB3_q_a[8]_PORT_B_write_enable, GB3_q_a[8]_clock_1, , , GB3_q_a[8]_clock_enable_1);
GB3_q_a[8]_clock_0 = CCD_MCLK;
GB3_q_a[8]_clock_1 = KB1__clk0;
GB3_q_a[8]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[8]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[8]_clear_1 = !C1_oRST_0;
GB3_q_a[8]_PORT_A_data_out = MEMORY(GB3_q_a[8]_PORT_A_data_in_reg, GB3_q_a[8]_PORT_B_data_in_reg, GB3_q_a[8]_PORT_A_address_reg, GB3_q_a[8]_PORT_B_address_reg, GB3_q_a[8]_PORT_A_write_enable_reg, GB3_q_a[8]_PORT_B_write_enable_reg, , , GB3_q_a[8]_clock_0, GB3_q_a[8]_clock_1, GB3_q_a[8]_clock_enable_0, GB3_q_a[8]_clock_enable_1, , GB3_q_a[8]_clear_1);
GB3_q_a[8]_PORT_A_data_out_reg = DFFE(GB3_q_a[8]_PORT_A_data_out, GB3_q_a[8]_clock_0, GB3_q_a[8]_clear_1, , GB3_q_a[8]_clock_enable_0);
GB3_q_a[8] = GB3_q_a[8]_PORT_A_data_out_reg[0];


--B1L91 is VGA_Controller:u1|oVGA_B[8]~118
B1L91 = GB3_q_a[8] & B1L114 & B1L115;


--GB3_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[9]_PORT_A_data_in = VCC;
GB3_q_a[9]_PORT_A_data_in_reg = DFFE(GB3_q_a[9]_PORT_A_data_in, GB3_q_a[9]_clock_0, , , GB3_q_a[9]_clock_enable_0);
GB3_q_a[9]_PORT_B_data_in = G1_mDATAOUT[9];
GB3_q_a[9]_PORT_B_data_in_reg = DFFE(GB3_q_a[9]_PORT_B_data_in, GB3_q_a[9]_clock_1, , , GB3_q_a[9]_clock_enable_1);
GB3_q_a[9]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[9]_PORT_A_address_reg = DFFE(GB3_q_a[9]_PORT_A_address, GB3_q_a[9]_clock_0, , , GB3_q_a[9]_clock_enable_0);
GB3_q_a[9]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[9]_PORT_B_address_reg = DFFE(GB3_q_a[9]_PORT_B_address, GB3_q_a[9]_clock_1, , , GB3_q_a[9]_clock_enable_1);
GB3_q_a[9]_PORT_A_write_enable = GND;
GB3_q_a[9]_PORT_A_write_enable_reg = DFFE(GB3_q_a[9]_PORT_A_write_enable, GB3_q_a[9]_clock_0, , , GB3_q_a[9]_clock_enable_0);
GB3_q_a[9]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[9]_PORT_B_write_enable_reg = DFFE(GB3_q_a[9]_PORT_B_write_enable, GB3_q_a[9]_clock_1, , , GB3_q_a[9]_clock_enable_1);
GB3_q_a[9]_clock_0 = CCD_MCLK;
GB3_q_a[9]_clock_1 = KB1__clk0;
GB3_q_a[9]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[9]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[9]_clear_1 = !C1_oRST_0;
GB3_q_a[9]_PORT_A_data_out = MEMORY(GB3_q_a[9]_PORT_A_data_in_reg, GB3_q_a[9]_PORT_B_data_in_reg, GB3_q_a[9]_PORT_A_address_reg, GB3_q_a[9]_PORT_B_address_reg, GB3_q_a[9]_PORT_A_write_enable_reg, GB3_q_a[9]_PORT_B_write_enable_reg, , , GB3_q_a[9]_clock_0, GB3_q_a[9]_clock_1, GB3_q_a[9]_clock_enable_0, GB3_q_a[9]_clock_enable_1, , GB3_q_a[9]_clear_1);
GB3_q_a[9]_PORT_A_data_out_reg = DFFE(GB3_q_a[9]_PORT_A_data_out, GB3_q_a[9]_clock_0, GB3_q_a[9]_clear_1, , GB3_q_a[9]_clock_enable_0);
GB3_q_a[9] = GB3_q_a[9]_PORT_A_data_out_reg[0];


--B1L92 is VGA_Controller:u1|oVGA_B[9]~119
B1L92 = GB3_q_a[9] & B1L114 & B1L115;


--D1L3 is CCD_Capture:u3|Frame_Cont[0]~1192
D1L3 = D1_Frame_Cont[0] $ VCC;

--D1L4 is CCD_Capture:u3|Frame_Cont[0]~1193
D1L4 = CARRY(D1_Frame_Cont[0]);


--C1_oRST_1 is Reset_Delay:u2|oRST_1
C1_oRST_1 = DFFEAS(C1L79, CLOCK_50, KEY[0],  ,  ,  ,  ,  ,  );


--D1_mSTART is CCD_Capture:u3|mSTART
D1_mSTART = DFFEAS(D1L183, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--rCCD_FVAL is rCCD_FVAL
rCCD_FVAL = DFFEAS(A1L192, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--D1_Pre_FVAL is CCD_Capture:u3|Pre_FVAL
D1_Pre_FVAL = DFFEAS(rCCD_FVAL, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1L167 is CCD_Capture:u3|always2~28
D1L167 = D1_mSTART & rCCD_FVAL & !D1_Pre_FVAL;


--D1L6 is CCD_Capture:u3|Frame_Cont[1]~1194
D1L6 = D1_Frame_Cont[1] & !D1L4 # !D1_Frame_Cont[1] & (D1L4 # GND);

--D1L7 is CCD_Capture:u3|Frame_Cont[1]~1195
D1L7 = CARRY(!D1L4 # !D1_Frame_Cont[1]);


--D1L9 is CCD_Capture:u3|Frame_Cont[2]~1196
D1L9 = D1_Frame_Cont[2] & (D1L7 $ GND) # !D1_Frame_Cont[2] & !D1L7 & VCC;

--D1L10 is CCD_Capture:u3|Frame_Cont[2]~1197
D1L10 = CARRY(D1_Frame_Cont[2] & !D1L7);


--D1L12 is CCD_Capture:u3|Frame_Cont[3]~1198
D1L12 = D1_Frame_Cont[3] & !D1L10 # !D1_Frame_Cont[3] & (D1L10 # GND);

--D1L13 is CCD_Capture:u3|Frame_Cont[3]~1199
D1L13 = CARRY(!D1L10 # !D1_Frame_Cont[3]);


--D1L15 is CCD_Capture:u3|Frame_Cont[4]~1200
D1L15 = D1_Frame_Cont[4] & (D1L13 $ GND) # !D1_Frame_Cont[4] & !D1L13 & VCC;

--D1L16 is CCD_Capture:u3|Frame_Cont[4]~1201
D1L16 = CARRY(D1_Frame_Cont[4] & !D1L13);


--D1L18 is CCD_Capture:u3|Frame_Cont[5]~1202
D1L18 = D1_Frame_Cont[5] & !D1L16 # !D1_Frame_Cont[5] & (D1L16 # GND);

--D1L19 is CCD_Capture:u3|Frame_Cont[5]~1203
D1L19 = CARRY(!D1L16 # !D1_Frame_Cont[5]);


--D1L21 is CCD_Capture:u3|Frame_Cont[6]~1204
D1L21 = D1_Frame_Cont[6] & (D1L19 $ GND) # !D1_Frame_Cont[6] & !D1L19 & VCC;

--D1L22 is CCD_Capture:u3|Frame_Cont[6]~1205
D1L22 = CARRY(D1_Frame_Cont[6] & !D1L19);


--D1L24 is CCD_Capture:u3|Frame_Cont[7]~1206
D1L24 = D1_Frame_Cont[7] & !D1L22 # !D1_Frame_Cont[7] & (D1L22 # GND);

--D1L25 is CCD_Capture:u3|Frame_Cont[7]~1207
D1L25 = CARRY(!D1L22 # !D1_Frame_Cont[7]);


--D1L27 is CCD_Capture:u3|Frame_Cont[8]~1208
D1L27 = D1_Frame_Cont[8] & (D1L25 $ GND) # !D1_Frame_Cont[8] & !D1L25 & VCC;

--D1L28 is CCD_Capture:u3|Frame_Cont[8]~1209
D1L28 = CARRY(D1_Frame_Cont[8] & !D1L25);


--D1L30 is CCD_Capture:u3|Frame_Cont[9]~1210
D1L30 = D1_Frame_Cont[9] & !D1L28 # !D1_Frame_Cont[9] & (D1L28 # GND);

--D1L31 is CCD_Capture:u3|Frame_Cont[9]~1211
D1L31 = CARRY(!D1L28 # !D1_Frame_Cont[9]);


--D1L33 is CCD_Capture:u3|Frame_Cont[10]~1212
D1L33 = D1_Frame_Cont[10] & (D1L31 $ GND) # !D1_Frame_Cont[10] & !D1L31 & VCC;

--D1L34 is CCD_Capture:u3|Frame_Cont[10]~1213
D1L34 = CARRY(D1_Frame_Cont[10] & !D1L31);


--D1L36 is CCD_Capture:u3|Frame_Cont[11]~1214
D1L36 = D1_Frame_Cont[11] & !D1L34 # !D1_Frame_Cont[11] & (D1L34 # GND);

--D1L37 is CCD_Capture:u3|Frame_Cont[11]~1215
D1L37 = CARRY(!D1L34 # !D1_Frame_Cont[11]);


--D1L39 is CCD_Capture:u3|Frame_Cont[12]~1216
D1L39 = D1_Frame_Cont[12] & (D1L37 $ GND) # !D1_Frame_Cont[12] & !D1L37 & VCC;

--D1L40 is CCD_Capture:u3|Frame_Cont[12]~1217
D1L40 = CARRY(D1_Frame_Cont[12] & !D1L37);


--D1L42 is CCD_Capture:u3|Frame_Cont[13]~1218
D1L42 = D1_Frame_Cont[13] & !D1L40 # !D1_Frame_Cont[13] & (D1L40 # GND);

--D1L43 is CCD_Capture:u3|Frame_Cont[13]~1219
D1L43 = CARRY(!D1L40 # !D1_Frame_Cont[13]);


--D1L45 is CCD_Capture:u3|Frame_Cont[14]~1220
D1L45 = D1_Frame_Cont[14] & (D1L43 $ GND) # !D1_Frame_Cont[14] & !D1L43 & VCC;

--D1L46 is CCD_Capture:u3|Frame_Cont[14]~1221
D1L46 = CARRY(D1_Frame_Cont[14] & !D1L43);


--D1L48 is CCD_Capture:u3|Frame_Cont[15]~1222
D1L48 = D1_Frame_Cont[15] & !D1L46 # !D1_Frame_Cont[15] & (D1L46 # GND);

--D1L49 is CCD_Capture:u3|Frame_Cont[15]~1223
D1L49 = CARRY(!D1L46 # !D1_Frame_Cont[15]);


--D1L51 is CCD_Capture:u3|Frame_Cont[16]~1224
D1L51 = D1_Frame_Cont[16] & (D1L49 $ GND) # !D1_Frame_Cont[16] & !D1L49 & VCC;

--D1L52 is CCD_Capture:u3|Frame_Cont[16]~1225
D1L52 = CARRY(D1_Frame_Cont[16] & !D1L49);


--D1L54 is CCD_Capture:u3|Frame_Cont[17]~1226
D1L54 = D1_Frame_Cont[17] & !D1L52 # !D1_Frame_Cont[17] & (D1L52 # GND);

--D1L55 is CCD_Capture:u3|Frame_Cont[17]~1227
D1L55 = CARRY(!D1L52 # !D1_Frame_Cont[17]);


--D1L57 is CCD_Capture:u3|Frame_Cont[18]~1228
D1L57 = D1_Frame_Cont[18] & (D1L55 $ GND) # !D1_Frame_Cont[18] & !D1L55 & VCC;

--D1L58 is CCD_Capture:u3|Frame_Cont[18]~1229
D1L58 = CARRY(D1_Frame_Cont[18] & !D1L55);


--D1L60 is CCD_Capture:u3|Frame_Cont[19]~1230
D1L60 = D1_Frame_Cont[19] & !D1L58 # !D1_Frame_Cont[19] & (D1L58 # GND);

--D1L61 is CCD_Capture:u3|Frame_Cont[19]~1231
D1L61 = CARRY(!D1L58 # !D1_Frame_Cont[19]);


--D1L63 is CCD_Capture:u3|Frame_Cont[20]~1232
D1L63 = D1_Frame_Cont[20] & (D1L61 $ GND) # !D1_Frame_Cont[20] & !D1L61 & VCC;

--D1L64 is CCD_Capture:u3|Frame_Cont[20]~1233
D1L64 = CARRY(D1_Frame_Cont[20] & !D1L61);


--D1L66 is CCD_Capture:u3|Frame_Cont[21]~1234
D1L66 = D1_Frame_Cont[21] & !D1L64 # !D1_Frame_Cont[21] & (D1L64 # GND);

--D1L67 is CCD_Capture:u3|Frame_Cont[21]~1235
D1L67 = CARRY(!D1L64 # !D1_Frame_Cont[21]);


--D1L69 is CCD_Capture:u3|Frame_Cont[22]~1236
D1L69 = D1_Frame_Cont[22] & (D1L67 $ GND) # !D1_Frame_Cont[22] & !D1L67 & VCC;

--D1L70 is CCD_Capture:u3|Frame_Cont[22]~1237
D1L70 = CARRY(D1_Frame_Cont[22] & !D1L67);


--D1L72 is CCD_Capture:u3|Frame_Cont[23]~1238
D1L72 = D1_Frame_Cont[23] & !D1L70 # !D1_Frame_Cont[23] & (D1L70 # GND);

--D1L73 is CCD_Capture:u3|Frame_Cont[23]~1239
D1L73 = CARRY(!D1L70 # !D1_Frame_Cont[23]);


--D1L75 is CCD_Capture:u3|Frame_Cont[24]~1240
D1L75 = D1_Frame_Cont[24] & (D1L73 $ GND) # !D1_Frame_Cont[24] & !D1L73 & VCC;

--D1L76 is CCD_Capture:u3|Frame_Cont[24]~1241
D1L76 = CARRY(D1_Frame_Cont[24] & !D1L73);


--D1L78 is CCD_Capture:u3|Frame_Cont[25]~1242
D1L78 = D1_Frame_Cont[25] & !D1L76 # !D1_Frame_Cont[25] & (D1L76 # GND);

--D1L79 is CCD_Capture:u3|Frame_Cont[25]~1243
D1L79 = CARRY(!D1L76 # !D1_Frame_Cont[25]);


--D1L81 is CCD_Capture:u3|Frame_Cont[26]~1244
D1L81 = D1_Frame_Cont[26] & (D1L79 $ GND) # !D1_Frame_Cont[26] & !D1L79 & VCC;

--D1L82 is CCD_Capture:u3|Frame_Cont[26]~1245
D1L82 = CARRY(D1_Frame_Cont[26] & !D1L79);


--D1L84 is CCD_Capture:u3|Frame_Cont[27]~1246
D1L84 = D1_Frame_Cont[27] & !D1L82 # !D1_Frame_Cont[27] & (D1L82 # GND);

--D1L85 is CCD_Capture:u3|Frame_Cont[27]~1247
D1L85 = CARRY(!D1L82 # !D1_Frame_Cont[27]);


--D1L87 is CCD_Capture:u3|Frame_Cont[28]~1248
D1L87 = D1_Frame_Cont[28] & (D1L85 $ GND) # !D1_Frame_Cont[28] & !D1L85 & VCC;

--D1L88 is CCD_Capture:u3|Frame_Cont[28]~1249
D1L88 = CARRY(D1_Frame_Cont[28] & !D1L85);


--D1L90 is CCD_Capture:u3|Frame_Cont[29]~1250
D1L90 = D1_Frame_Cont[29] & !D1L88 # !D1_Frame_Cont[29] & (D1L88 # GND);

--D1L91 is CCD_Capture:u3|Frame_Cont[29]~1251
D1L91 = CARRY(!D1L88 # !D1_Frame_Cont[29]);


--D1L93 is CCD_Capture:u3|Frame_Cont[30]~1252
D1L93 = D1_Frame_Cont[30] & (D1L91 $ GND) # !D1_Frame_Cont[30] & !D1L91 & VCC;

--D1L94 is CCD_Capture:u3|Frame_Cont[30]~1253
D1L94 = CARRY(D1_Frame_Cont[30] & !D1L91);


--D1L96 is CCD_Capture:u3|Frame_Cont[31]~1254
D1L96 = D1_Frame_Cont[31] $ D1L94;


--D1_X_Cont[8] is CCD_Capture:u3|X_Cont[8]
D1_X_Cont[8] = DFFEAS(D1L130, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[9] is CCD_Capture:u3|X_Cont[9]
D1_X_Cont[9] = DFFEAS(D1L133, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1L98 is CCD_Capture:u3|LessThan~137
D1L98 = !D1_X_Cont[8] & !D1_X_Cont[9];


--D1_X_Cont[0] is CCD_Capture:u3|X_Cont[0]
D1_X_Cont[0] = DFFEAS(D1L105, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[1] is CCD_Capture:u3|X_Cont[1]
D1_X_Cont[1] = DFFEAS(D1L109, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[2] is CCD_Capture:u3|X_Cont[2]
D1_X_Cont[2] = DFFEAS(D1L112, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[3] is CCD_Capture:u3|X_Cont[3]
D1_X_Cont[3] = DFFEAS(D1L115, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1L99 is CCD_Capture:u3|LessThan~138
D1L99 = !D1_X_Cont[3] # !D1_X_Cont[2] # !D1_X_Cont[1] # !D1_X_Cont[0];


--D1_X_Cont[4] is CCD_Capture:u3|X_Cont[4]
D1_X_Cont[4] = DFFEAS(D1L118, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[5] is CCD_Capture:u3|X_Cont[5]
D1_X_Cont[5] = DFFEAS(D1L121, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[6] is CCD_Capture:u3|X_Cont[6]
D1_X_Cont[6] = DFFEAS(D1L124, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[7] is CCD_Capture:u3|X_Cont[7]
D1_X_Cont[7] = DFFEAS(D1L127, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1L100 is CCD_Capture:u3|LessThan~139
D1L100 = !D1_X_Cont[7] # !D1_X_Cont[6] # !D1_X_Cont[5] # !D1_X_Cont[4];


--D1_X_Cont[10] is CCD_Capture:u3|X_Cont[10]
D1_X_Cont[10] = DFFEAS(D1L136, CCD_PIXCLK, C1_oRST_1,  , D1L166,  ,  , D1L107,  );


--D1L101 is CCD_Capture:u3|LessThan~140
D1L101 = D1L98 & (D1L99 # D1L100) # !D1_X_Cont[10];


--D1L140 is CCD_Capture:u3|Y_Cont[0]~822
D1L140 = D1L101 & D1_Y_Cont[0] & VCC # !D1L101 & (D1_Y_Cont[0] $ VCC);

--D1L141 is CCD_Capture:u3|Y_Cont[0]~823
D1L141 = CARRY(!D1L101 & D1_Y_Cont[0]);


--D1_mCCD_FVAL is CCD_Capture:u3|mCCD_FVAL
D1_mCCD_FVAL = DFFEAS(D1L180, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1_mCCD_LVAL is CCD_Capture:u3|mCCD_LVAL
D1_mCCD_LVAL = DFFEAS(rCCD_LVAL, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1L166 is CCD_Capture:u3|Y_Cont[10]~824
D1L166 = D1_mCCD_LVAL # !D1_mCCD_FVAL;


--D1L143 is CCD_Capture:u3|Y_Cont[1]~825
D1L143 = D1_Y_Cont[1] & !D1L141 # !D1_Y_Cont[1] & (D1L141 # GND);

--D1L144 is CCD_Capture:u3|Y_Cont[1]~826
D1L144 = CARRY(!D1L141 # !D1_Y_Cont[1]);


--D1L146 is CCD_Capture:u3|Y_Cont[2]~827
D1L146 = D1_Y_Cont[2] & (D1L144 $ GND) # !D1_Y_Cont[2] & !D1L144 & VCC;

--D1L147 is CCD_Capture:u3|Y_Cont[2]~828
D1L147 = CARRY(D1_Y_Cont[2] & !D1L144);


--D1L149 is CCD_Capture:u3|Y_Cont[3]~829
D1L149 = D1_Y_Cont[3] & !D1L147 # !D1_Y_Cont[3] & (D1L147 # GND);

--D1L150 is CCD_Capture:u3|Y_Cont[3]~830
D1L150 = CARRY(!D1L147 # !D1_Y_Cont[3]);


--D1L152 is CCD_Capture:u3|Y_Cont[4]~831
D1L152 = D1_Y_Cont[4] & (D1L150 $ GND) # !D1_Y_Cont[4] & !D1L150 & VCC;

--D1L153 is CCD_Capture:u3|Y_Cont[4]~832
D1L153 = CARRY(D1_Y_Cont[4] & !D1L150);


--D1L155 is CCD_Capture:u3|Y_Cont[5]~833
D1L155 = D1_Y_Cont[5] & !D1L153 # !D1_Y_Cont[5] & (D1L153 # GND);

--D1L156 is CCD_Capture:u3|Y_Cont[5]~834
D1L156 = CARRY(!D1L153 # !D1_Y_Cont[5]);


--D1L158 is CCD_Capture:u3|Y_Cont[6]~835
D1L158 = D1_Y_Cont[6] & (D1L156 $ GND) # !D1_Y_Cont[6] & !D1L156 & VCC;

--D1L159 is CCD_Capture:u3|Y_Cont[6]~836
D1L159 = CARRY(D1_Y_Cont[6] & !D1L156);


--D1L161 is CCD_Capture:u3|Y_Cont[7]~837
D1L161 = D1_Y_Cont[7] & !D1L159 # !D1_Y_Cont[7] & (D1L159 # GND);

--D1L162 is CCD_Capture:u3|Y_Cont[7]~838
D1L162 = CARRY(!D1L159 # !D1_Y_Cont[7]);


--D1L164 is CCD_Capture:u3|Y_Cont[8]~839
D1L164 = D1_Y_Cont[8] $ !D1L162;


--R1_SA[0] is Sdram_Control_4Port:u6|command:command1|SA[0]
R1_SA[0] = DFFEAS(R1L33, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_ST[2] is Sdram_Control_4Port:u6|ST[2]
G1_ST[2] = DFFEAS(G1L92, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_ST[0] is Sdram_Control_4Port:u6|ST[0]
G1_ST[0] = DFFEAS(G1L87, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_ST[9] is Sdram_Control_4Port:u6|ST[9]
G1_ST[9] = DFFEAS(G1L108, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_ST[7] is Sdram_Control_4Port:u6|ST[7]
G1_ST[7] = DFFEAS(G1L102, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_ST[6] is Sdram_Control_4Port:u6|ST[6]
G1_ST[6] = DFFEAS(G1L100, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_ST[5] is Sdram_Control_4Port:u6|ST[5]
G1_ST[5] = DFFEAS(G1L98, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L15 is Sdram_Control_4Port:u6|Equal~1115
G1L15 = !G1_ST[9] & !G1_ST[7] & !G1_ST[6] & !G1_ST[5];


--G1_ST[4] is Sdram_Control_4Port:u6|ST[4]
G1_ST[4] = DFFEAS(G1L96, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_ST[3] is Sdram_Control_4Port:u6|ST[3]
G1_ST[3] = DFFEAS(G1L94, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L16 is Sdram_Control_4Port:u6|Equal~1116
G1L16 = !G1_ST[4] & !G1_ST[3];


--G1_ST[8] is Sdram_Control_4Port:u6|ST[8]
G1_ST[8] = DFFEAS(G1L106, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_ST[1] is Sdram_Control_4Port:u6|ST[1]
G1_ST[1] = DFFEAS(G1L90, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L17 is Sdram_Control_4Port:u6|Equal~1117
G1L17 = G1L15 & G1L16 & G1_ST[8] & G1_ST[1];


--G1L72 is Sdram_Control_4Port:u6|SA~482
G1L72 = R1_SA[0] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_SA[1] is Sdram_Control_4Port:u6|command:command1|SA[1]
R1_SA[1] = DFFEAS(R1L34, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L73 is Sdram_Control_4Port:u6|SA~483
G1L73 = R1_SA[1] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_SA[2] is Sdram_Control_4Port:u6|command:command1|SA[2]
R1_SA[2] = DFFEAS(R1L35, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L74 is Sdram_Control_4Port:u6|SA~484
G1L74 = R1_SA[2] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_SA[3] is Sdram_Control_4Port:u6|command:command1|SA[3]
R1_SA[3] = DFFEAS(R1L36, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L75 is Sdram_Control_4Port:u6|SA~485
G1L75 = R1_SA[3] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_SA[4] is Sdram_Control_4Port:u6|command:command1|SA[4]
R1_SA[4] = DFFEAS(R1L37, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L76 is Sdram_Control_4Port:u6|SA~486
G1L76 = R1_SA[4] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_SA[5] is Sdram_Control_4Port:u6|command:command1|SA[5]
R1_SA[5] = DFFEAS(R1L38, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L77 is Sdram_Control_4Port:u6|SA~487
G1L77 = R1_SA[5] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_SA[6] is Sdram_Control_4Port:u6|command:command1|SA[6]
R1_SA[6] = DFFEAS(R1L39, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L78 is Sdram_Control_4Port:u6|SA~488
G1L78 = R1_SA[6] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_SA[7] is Sdram_Control_4Port:u6|command:command1|SA[7]
R1_SA[7] = DFFEAS(R1L40, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L79 is Sdram_Control_4Port:u6|SA~489
G1L79 = R1_SA[7] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_SA[8] is Sdram_Control_4Port:u6|command:command1|SA[8]
R1_SA[8] = DFFEAS(R1L41, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L80 is Sdram_Control_4Port:u6|SA~490
G1L80 = R1_SA[8] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_SA[9] is Sdram_Control_4Port:u6|command:command1|SA[9]
R1_SA[9] = DFFEAS(R1L42, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L81 is Sdram_Control_4Port:u6|SA~491
G1L81 = R1_SA[9] # G1_ST[0] & G1L17 & !G1_ST[2];


--R1_SA[10] is Sdram_Control_4Port:u6|command:command1|SA[10]
R1_SA[10] = DFFEAS(R1L43, KB1__clk0,  ,  ,  ,  ,  , R1_do_load_mode,  );


--G1L82 is Sdram_Control_4Port:u6|SA~492
G1L82 = R1_SA[10] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_SA[11] is Sdram_Control_4Port:u6|command:command1|SA[11]
R1_SA[11] = DFFEAS(R1L44, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L83 is Sdram_Control_4Port:u6|SA~493
G1L83 = R1_SA[11] & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--G1L18 is Sdram_Control_4Port:u6|Equal~1118
G1L18 = G1L15 & !G1_ST[4] & !G1_ST[3];


--G1L32 is Sdram_Control_4Port:u6|LessThan~1258
G1L32 = G1_ST[0] & G1_ST[1];


--G1L33 is Sdram_Control_4Port:u6|LessThan~1259
G1L33 = G1L18 & !G1_ST[2] & !G1_ST[8] & !G1L32;


--G1L19 is Sdram_Control_4Port:u6|Equal~1119
G1L19 = G1_ST[0] & G1L17 & !G1_ST[2];


--G1_Write is Sdram_Control_4Port:u6|Write
G1_Write = DFFEAS(G1L122, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_Read is Sdram_Control_4Port:u6|Read
G1_Read = DFFEAS(G1L58, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L14 is Sdram_Control_4Port:u6|DQM~82
G1L14 = G1L33 # G1_Write & G1L19 # !G1_Write & (!G1_Read);


--R1_WE_N is Sdram_Control_4Port:u6|command:command1|WE_N
R1_WE_N = DFFEAS(R1L47, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L112 is Sdram_Control_4Port:u6|WE_N~43
G1L112 = R1_WE_N & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_CAS_N is Sdram_Control_4Port:u6|command:command1|CAS_N
R1_CAS_N = DFFEAS(R1L7, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L5 is Sdram_Control_4Port:u6|CAS_N~9
G1L5 = R1_CAS_N # G1_ST[0] & G1L17 & !G1_ST[2];


--R1_RAS_N is Sdram_Control_4Port:u6|command:command1|RAS_N
R1_RAS_N = DFFEAS(R1L16, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L50 is Sdram_Control_4Port:u6|RAS_N~45
G1L50 = R1_RAS_N & (G1_ST[2] # !G1L17 # !G1_ST[0]);


--R1_CS_N[0] is Sdram_Control_4Port:u6|command:command1|CS_N[0]
R1_CS_N[0] = DFFEAS(R1L12, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_BA[0] is Sdram_Control_4Port:u6|command:command1|BA[0]
R1_BA[0] = DFFEAS(R1L4, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_BA[1] is Sdram_Control_4Port:u6|command:command1|BA[1]
R1_BA[1] = DFFEAS(R1L5, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--B1L2 is VGA_Controller:u1|Equal~116
B1L2 = !B1_H_Cont[8] & !B1_H_Cont[9];


--B1L42 is VGA_Controller:u1|LessThan~1091
B1L42 = B1_H_Cont[7] # B1_H_Cont[5] & B1_H_Cont[6] # !B1L2;


--C1_oRST_2 is Reset_Delay:u2|oRST_2
C1_oRST_2 = DFFEAS(C1L81, CLOCK_50, KEY[0],  ,  ,  ,  ,  ,  );


--B1_H_Cont[0] is VGA_Controller:u1|H_Cont[0]
B1_H_Cont[0] = DFFEAS(B1L8, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1_H_Cont[1] is VGA_Controller:u1|H_Cont[1]
B1_H_Cont[1] = DFFEAS(B1L11, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1L3 is VGA_Controller:u1|Equal~117
B1L3 = !B1_H_Cont[8] & !B1_H_Cont[9] & !B1_H_Cont[0] & !B1_H_Cont[1];


--B1_H_Cont[2] is VGA_Controller:u1|H_Cont[2]
B1_H_Cont[2] = DFFEAS(B1L14, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1_H_Cont[3] is VGA_Controller:u1|H_Cont[3]
B1_H_Cont[3] = DFFEAS(B1L17, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1L4 is VGA_Controller:u1|Equal~118
B1L4 = !B1_H_Cont[2] & !B1_H_Cont[3];


--B1L5 is VGA_Controller:u1|Equal~119
B1L5 = B1L1 & B1L3 & B1L4 & !B1_H_Cont[7];


--B1L117 is VGA_Controller:u1|oVGA_V_SYNC~174
B1L117 = B1L5 & (B1_V_Cont[9] # B1L41) # !B1L5 & B1_oVGA_V_SYNC;


--B1_oRequest is VGA_Controller:u1|oRequest
B1_oRequest = DFFEAS(B1L80, CCD_MCLK, C1_oRST_2,  ,  ,  ,  ,  ,  );


--X4_rdptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[7]
X4_rdptr_g[7] = DFFEAS(Z4_power_modified_counter_values[7], CCD_MCLK, C1_oRST_0,  , X4_valid_rdreq,  ,  ,  ,  );


--HB4_dffe7a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[7]
HB4_dffe7a[7] = DFFEAS(X4_delayed_wrptr_g[7], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4_rdptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0]
X4_rdptr_g[0] = DFFEAS(Z4_power_modified_counter_values[0], CCD_MCLK, C1_oRST_0,  , X4_valid_rdreq,  ,  ,  ,  );


--X4_rdptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2]
X4_rdptr_g[2] = DFFEAS(Z4_power_modified_counter_values[2], CCD_MCLK, C1_oRST_0,  , X4_valid_rdreq,  ,  ,  ,  );


--HB4_dffe7a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[2]
HB4_dffe7a[2] = DFFEAS(X4_delayed_wrptr_g[2], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--HB4_dffe7a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0]
HB4_dffe7a[0] = DFFEAS(X4_delayed_wrptr_g[0], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4L15 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~54
X4L15 = X4_rdptr_g[0] & HB4_dffe7a[0] & (X4_rdptr_g[2] $ !HB4_dffe7a[2]) # !X4_rdptr_g[0] & !HB4_dffe7a[0] & (X4_rdptr_g[2] $ !HB4_dffe7a[2]);


--X4_rdptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[6]
X4_rdptr_g[6] = DFFEAS(Z4_power_modified_counter_values[6], CCD_MCLK, C1_oRST_0,  , X4_valid_rdreq,  ,  ,  ,  );


--X4_rdptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[1]
X4_rdptr_g[1] = DFFEAS(Z4_power_modified_counter_values[1], CCD_MCLK, C1_oRST_0,  , X4_valid_rdreq,  ,  ,  ,  );


--HB4_dffe7a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1]
HB4_dffe7a[1] = DFFEAS(X4_delayed_wrptr_g[1], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--HB4_dffe7a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[6]
HB4_dffe7a[6] = DFFEAS(X4_delayed_wrptr_g[6], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~55
X4L16 = X4_rdptr_g[6] & HB4_dffe7a[6] & (X4_rdptr_g[1] $ !HB4_dffe7a[1]) # !X4_rdptr_g[6] & !HB4_dffe7a[6] & (X4_rdptr_g[1] $ !HB4_dffe7a[1]);


--X4_rdptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[3]
X4_rdptr_g[3] = DFFEAS(Z4_power_modified_counter_values[3], CCD_MCLK, C1_oRST_0,  , X4_valid_rdreq,  ,  ,  ,  );


--X4_rdptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8]
X4_rdptr_g[8] = DFFEAS(Z4_power_modified_counter_values[8], CCD_MCLK, C1_oRST_0,  , X4_valid_rdreq,  ,  ,  ,  );


--HB4_dffe7a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[8]
HB4_dffe7a[8] = DFFEAS(X4_delayed_wrptr_g[8], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--HB4_dffe7a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[3]
HB4_dffe7a[3] = DFFEAS(X4_delayed_wrptr_g[3], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4L17 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~56
X4L17 = X4_rdptr_g[3] & HB4_dffe7a[3] & (X4_rdptr_g[8] $ !HB4_dffe7a[8]) # !X4_rdptr_g[3] & !HB4_dffe7a[3] & (X4_rdptr_g[8] $ !HB4_dffe7a[8]);


--X4_rdptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[5]
X4_rdptr_g[5] = DFFEAS(Z4_power_modified_counter_values[5], CCD_MCLK, C1_oRST_0,  , X4_valid_rdreq,  ,  ,  ,  );


--X4_rdptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4]
X4_rdptr_g[4] = DFFEAS(Z4_power_modified_counter_values[4], CCD_MCLK, C1_oRST_0,  , X4_valid_rdreq,  ,  ,  ,  );


--HB4_dffe7a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4]
HB4_dffe7a[4] = DFFEAS(X4_delayed_wrptr_g[4], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--HB4_dffe7a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[5]
HB4_dffe7a[5] = DFFEAS(X4_delayed_wrptr_g[5], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4L18 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~57
X4L18 = X4_rdptr_g[5] & HB4_dffe7a[5] & (X4_rdptr_g[4] $ !HB4_dffe7a[4]) # !X4_rdptr_g[5] & !HB4_dffe7a[5] & (X4_rdptr_g[4] $ !HB4_dffe7a[4]);


--X4L19 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~58
X4L19 = X4L15 & X4L16 & X4L17 & X4L18;


--X4_valid_rdreq is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq
X4_valid_rdreq = B1_oRequest & (X4_rdptr_g[7] $ HB4_dffe7a[7] # !X4L19);


--X4_p0addr is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|p0addr
X4_p0addr = DFFEAS(VCC, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--X4_rdcnt_addr_ena is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdcnt_addr_ena
X4_rdcnt_addr_ena = X4_valid_rdreq # !X4_p0addr;


--G1_OUT_VALID is Sdram_Control_4Port:u6|OUT_VALID
G1_OUT_VALID = DFFEAS(G1L45, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_RD_MASK[1] is Sdram_Control_4Port:u6|RD_MASK[1]
G1_RD_MASK[1] = DFFEAS(G1L54, KB1__clk0,  ,  , G1L259,  ,  ,  ,  );


--JB4_dffe9a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[7]
JB4_dffe9a[7] = DFFEAS(X4_rdptr_g[7], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[7]
EB4_power_modified_counter_values[7] = DFFEAS(EB4_countera7, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4L1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|_~16
X4L1 = JB4_dffe9a[7] $ EB4_power_modified_counter_values[7];


--JB4_dffe9a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[2]
JB4_dffe9a[2] = DFFEAS(X4_rdptr_g[2], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[2]
EB4_power_modified_counter_values[2] = DFFEAS(EB4_countera2, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB4_dffe9a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[0]
JB4_dffe9a[0] = DFFEAS(X4_rdptr_g[0], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB4_counter_ffa[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|counter_ffa[0]
EB4_counter_ffa[0] = DFFEAS(EB4_countera0, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4L32 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~55
X4L32 = JB4_dffe9a[2] & EB4_power_modified_counter_values[2] & (JB4_dffe9a[0] $ EB4_counter_ffa[0]) # !JB4_dffe9a[2] & !EB4_power_modified_counter_values[2] & (JB4_dffe9a[0] $ EB4_counter_ffa[0]);


--JB4_dffe9a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[6]
JB4_dffe9a[6] = DFFEAS(X4_rdptr_g[6], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB4_dffe9a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[1]
JB4_dffe9a[1] = DFFEAS(X4_rdptr_g[1], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[1]
EB4_power_modified_counter_values[1] = DFFEAS(EB4_countera1, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[6]
EB4_power_modified_counter_values[6] = DFFEAS(EB4_countera6, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4L33 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~56
X4L33 = JB4_dffe9a[6] & EB4_power_modified_counter_values[6] & (JB4_dffe9a[1] $ !EB4_power_modified_counter_values[1]) # !JB4_dffe9a[6] & !EB4_power_modified_counter_values[6] & (JB4_dffe9a[1] $ !EB4_power_modified_counter_values[1]);


--JB4_dffe9a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[3]
JB4_dffe9a[3] = DFFEAS(X4_rdptr_g[3], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB4_dffe9a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[8]
JB4_dffe9a[8] = DFFEAS(X4_rdptr_g[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[8]
EB4_power_modified_counter_values[8] = DFFEAS(EB4_countera8, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[3]
EB4_power_modified_counter_values[3] = DFFEAS(EB4_countera3, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4L34 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~57
X4L34 = JB4_dffe9a[3] & EB4_power_modified_counter_values[3] & (JB4_dffe9a[8] $ !EB4_power_modified_counter_values[8]) # !JB4_dffe9a[3] & !EB4_power_modified_counter_values[3] & (JB4_dffe9a[8] $ !EB4_power_modified_counter_values[8]);


--JB4_dffe9a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5]
JB4_dffe9a[5] = DFFEAS(X4_rdptr_g[5], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB4_dffe9a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[4]
JB4_dffe9a[4] = DFFEAS(X4_rdptr_g[4], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[4]
EB4_power_modified_counter_values[4] = DFFEAS(EB4_countera4, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[5]
EB4_power_modified_counter_values[5] = DFFEAS(EB4_countera5, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4L35 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~58
X4L35 = JB4_dffe9a[5] & EB4_power_modified_counter_values[5] & (JB4_dffe9a[4] $ !EB4_power_modified_counter_values[4]) # !JB4_dffe9a[5] & !EB4_power_modified_counter_values[5] & (JB4_dffe9a[4] $ !EB4_power_modified_counter_values[4]);


--X4L36 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~59
X4L36 = X4L32 & X4L33 & X4L34 & X4L35;


--X4_valid_wrreq is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_wrreq
X4_valid_wrreq = G1_OUT_VALID & G1_RD_MASK[1] & (X4L1 # !X4L36);


--C1_oRST_0 is Reset_Delay:u2|oRST_0
C1_oRST_0 = DFFEAS(C1L77, CLOCK_50, KEY[0],  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[0]
Z4_power_modified_counter_values[0] = DFFEAS(Z4_countera0, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[1]
Z4_power_modified_counter_values[1] = DFFEAS(Z4_countera1, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[2]
Z4_power_modified_counter_values[2] = DFFEAS(Z4_countera2, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[3]
Z4_power_modified_counter_values[3] = DFFEAS(Z4_countera3, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[4]
Z4_power_modified_counter_values[4] = DFFEAS(Z4_countera4, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[5]
Z4_power_modified_counter_values[5] = DFFEAS(Z4_countera5, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[6]
Z4_power_modified_counter_values[6] = DFFEAS(Z4_countera6, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[7]
Z4_power_modified_counter_values[7] = DFFEAS(Z4_countera7, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8]
Z4_power_modified_counter_values[8] = DFFEAS(Z4_countera8, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[0] is Sdram_Control_4Port:u6|mDATAOUT[0]
G1_mDATAOUT[0] = DFFEAS(A1L34, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--X4_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]
X4_wrptr_g[0] = DFFEAS(X4L39, KB1__clk0, C1_oRST_0,  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[1]
X4_wrptr_g[1] = DFFEAS(EB4_power_modified_counter_values[1], KB1__clk0, C1_oRST_0,  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2]
X4_wrptr_g[2] = DFFEAS(EB4_power_modified_counter_values[2], KB1__clk0, C1_oRST_0,  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[3]
X4_wrptr_g[3] = DFFEAS(EB4_power_modified_counter_values[3], KB1__clk0, C1_oRST_0,  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[4]
X4_wrptr_g[4] = DFFEAS(EB4_power_modified_counter_values[4], KB1__clk0, C1_oRST_0,  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5]
X4_wrptr_g[5] = DFFEAS(EB4_power_modified_counter_values[5], KB1__clk0, C1_oRST_0,  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6]
X4_wrptr_g[6] = DFFEAS(EB4_power_modified_counter_values[6], KB1__clk0, C1_oRST_0,  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[7]
X4_wrptr_g[7] = DFFEAS(EB4_power_modified_counter_values[7], KB1__clk0, C1_oRST_0,  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8]
X4_wrptr_g[8] = DFFEAS(EB4_power_modified_counter_values[8], KB1__clk0, C1_oRST_0,  , X4_valid_wrreq,  ,  ,  ,  );


--B1_V_Cont[0] is VGA_Controller:u1|V_Cont[0]
B1_V_Cont[0] = DFFEAS(B1L50, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1L50 is VGA_Controller:u1|V_Cont[0]~900
B1L50 = B1_V_Cont[0] $ VCC;

--B1L51 is VGA_Controller:u1|V_Cont[0]~901
B1L51 = CARRY(B1_V_Cont[0]);


--B1L53 is VGA_Controller:u1|V_Cont[1]~902
B1L53 = B1_V_Cont[1] & !B1L51 # !B1_V_Cont[1] & (B1L51 # GND);

--B1L54 is VGA_Controller:u1|V_Cont[1]~903
B1L54 = CARRY(!B1L51 # !B1_V_Cont[1]);


--B1L56 is VGA_Controller:u1|V_Cont[2]~904
B1L56 = B1_V_Cont[2] & (B1L54 $ GND) # !B1_V_Cont[2] & !B1L54 & VCC;

--B1L57 is VGA_Controller:u1|V_Cont[2]~905
B1L57 = CARRY(B1_V_Cont[2] & !B1L54);


--B1L59 is VGA_Controller:u1|V_Cont[3]~906
B1L59 = B1_V_Cont[3] & !B1L57 # !B1_V_Cont[3] & (B1L57 # GND);

--B1L60 is VGA_Controller:u1|V_Cont[3]~907
B1L60 = CARRY(!B1L57 # !B1_V_Cont[3]);


--B1L62 is VGA_Controller:u1|V_Cont[4]~908
B1L62 = B1_V_Cont[4] & (B1L60 $ GND) # !B1_V_Cont[4] & !B1L60 & VCC;

--B1L63 is VGA_Controller:u1|V_Cont[4]~909
B1L63 = CARRY(B1_V_Cont[4] & !B1L60);


--B1L65 is VGA_Controller:u1|V_Cont[5]~910
B1L65 = B1_V_Cont[5] & !B1L63 # !B1_V_Cont[5] & (B1L63 # GND);

--B1L66 is VGA_Controller:u1|V_Cont[5]~911
B1L66 = CARRY(!B1L63 # !B1_V_Cont[5]);


--B1L68 is VGA_Controller:u1|V_Cont[6]~912
B1L68 = B1_V_Cont[6] & (B1L66 $ GND) # !B1_V_Cont[6] & !B1L66 & VCC;

--B1L69 is VGA_Controller:u1|V_Cont[6]~913
B1L69 = CARRY(B1_V_Cont[6] & !B1L66);


--B1L43 is VGA_Controller:u1|LessThan~1092
B1L43 = !B1_V_Cont[5] & !B1_V_Cont[6] & !B1_V_Cont[7] & !B1_V_Cont[8];


--B1L44 is VGA_Controller:u1|LessThan~1093
B1L44 = !B1_V_Cont[1] & !B1_V_Cont[0] # !B1_V_Cont[3] # !B1_V_Cont[2];


--B1L45 is VGA_Controller:u1|LessThan~1094
B1L45 = B1_V_Cont[9] & (B1_V_Cont[4] # !B1L44 # !B1L43);


--B1L71 is VGA_Controller:u1|V_Cont[7]~914
B1L71 = B1_V_Cont[7] & !B1L69 # !B1_V_Cont[7] & (B1L69 # GND);

--B1L72 is VGA_Controller:u1|V_Cont[7]~915
B1L72 = CARRY(!B1L69 # !B1_V_Cont[7]);


--B1L74 is VGA_Controller:u1|V_Cont[8]~916
B1L74 = B1_V_Cont[8] & (B1L72 $ GND) # !B1_V_Cont[8] & !B1L72 & VCC;

--B1L75 is VGA_Controller:u1|V_Cont[8]~917
B1L75 = CARRY(B1_V_Cont[8] & !B1L72);


--B1L77 is VGA_Controller:u1|V_Cont[9]~918
B1L77 = B1_V_Cont[9] $ B1L75;


--B1L8 is VGA_Controller:u1|H_Cont[0]~246
B1L8 = B1_H_Cont[0] $ VCC;

--B1L9 is VGA_Controller:u1|H_Cont[0]~247
B1L9 = CARRY(B1_H_Cont[0]);


--B1L11 is VGA_Controller:u1|H_Cont[1]~248
B1L11 = B1_H_Cont[1] & !B1L9 # !B1_H_Cont[1] & (B1L9 # GND);

--B1L12 is VGA_Controller:u1|H_Cont[1]~249
B1L12 = CARRY(!B1L9 # !B1_H_Cont[1]);


--B1L14 is VGA_Controller:u1|H_Cont[2]~250
B1L14 = B1_H_Cont[2] & (B1L12 $ GND) # !B1_H_Cont[2] & !B1L12 & VCC;

--B1L15 is VGA_Controller:u1|H_Cont[2]~251
B1L15 = CARRY(B1_H_Cont[2] & !B1L12);


--B1L17 is VGA_Controller:u1|H_Cont[3]~252
B1L17 = B1_H_Cont[3] & !B1L15 # !B1_H_Cont[3] & (B1L15 # GND);

--B1L18 is VGA_Controller:u1|H_Cont[3]~253
B1L18 = CARRY(!B1L15 # !B1_H_Cont[3]);


--B1L20 is VGA_Controller:u1|H_Cont[4]~254
B1L20 = B1_H_Cont[4] & (B1L18 $ GND) # !B1_H_Cont[4] & !B1L18 & VCC;

--B1L21 is VGA_Controller:u1|H_Cont[4]~255
B1L21 = CARRY(B1_H_Cont[4] & !B1L18);


--B1L26 is VGA_Controller:u1|H_Cont[6]~256
B1L26 = !B1_H_Cont[5] & !B1_H_Cont[6];


--B1L46 is VGA_Controller:u1|LessThan~1095
B1L46 = B1_H_Cont[8] & B1_H_Cont[9] & (B1_H_Cont[7] # !B1L26);


--B1L23 is VGA_Controller:u1|H_Cont[5]~257
B1L23 = B1_H_Cont[5] & !B1L21 # !B1_H_Cont[5] & (B1L21 # GND);

--B1L24 is VGA_Controller:u1|H_Cont[5]~258
B1L24 = CARRY(!B1L21 # !B1_H_Cont[5]);


--B1L27 is VGA_Controller:u1|H_Cont[6]~259
B1L27 = B1_H_Cont[6] & (B1L24 $ GND) # !B1_H_Cont[6] & !B1L24 & VCC;

--B1L28 is VGA_Controller:u1|H_Cont[6]~260
B1L28 = CARRY(B1_H_Cont[6] & !B1L24);


--B1L30 is VGA_Controller:u1|H_Cont[7]~261
B1L30 = B1_H_Cont[7] & !B1L28 # !B1_H_Cont[7] & (B1L28 # GND);

--B1L31 is VGA_Controller:u1|H_Cont[7]~262
B1L31 = CARRY(!B1L28 # !B1_H_Cont[7]);


--B1L33 is VGA_Controller:u1|H_Cont[8]~263
B1L33 = B1_H_Cont[8] & (B1L31 $ GND) # !B1_H_Cont[8] & !B1L31 & VCC;

--B1L34 is VGA_Controller:u1|H_Cont[8]~264
B1L34 = CARRY(B1_H_Cont[8] & !B1L31);


--B1L36 is VGA_Controller:u1|H_Cont[9]~265
B1L36 = B1_H_Cont[9] $ B1L34;


--G1_mDATAOUT[1] is Sdram_Control_4Port:u6|mDATAOUT[1]
G1_mDATAOUT[1] = DFFEAS(A1L36, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[2] is Sdram_Control_4Port:u6|mDATAOUT[2]
G1_mDATAOUT[2] = DFFEAS(A1L38, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[3] is Sdram_Control_4Port:u6|mDATAOUT[3]
G1_mDATAOUT[3] = DFFEAS(A1L40, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[4] is Sdram_Control_4Port:u6|mDATAOUT[4]
G1_mDATAOUT[4] = DFFEAS(A1L42, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[5] is Sdram_Control_4Port:u6|mDATAOUT[5]
G1_mDATAOUT[5] = DFFEAS(A1L44, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[6] is Sdram_Control_4Port:u6|mDATAOUT[6]
G1_mDATAOUT[6] = DFFEAS(A1L46, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[7] is Sdram_Control_4Port:u6|mDATAOUT[7]
G1_mDATAOUT[7] = DFFEAS(A1L48, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[8] is Sdram_Control_4Port:u6|mDATAOUT[8]
G1_mDATAOUT[8] = DFFEAS(A1L50, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[9] is Sdram_Control_4Port:u6|mDATAOUT[9]
G1_mDATAOUT[9] = DFFEAS(A1L52, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[10] is Sdram_Control_4Port:u6|mDATAOUT[10]
G1_mDATAOUT[10] = DFFEAS(A1L54, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[11] is Sdram_Control_4Port:u6|mDATAOUT[11]
G1_mDATAOUT[11] = DFFEAS(A1L56, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[12] is Sdram_Control_4Port:u6|mDATAOUT[12]
G1_mDATAOUT[12] = DFFEAS(A1L58, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[13] is Sdram_Control_4Port:u6|mDATAOUT[13]
G1_mDATAOUT[13] = DFFEAS(A1L60, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[14] is Sdram_Control_4Port:u6|mDATAOUT[14]
G1_mDATAOUT[14] = DFFEAS(A1L62, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--X3_rdptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[7]
X3_rdptr_g[7] = DFFEAS(Z3_power_modified_counter_values[7], CCD_MCLK, C1_oRST_0,  , X3_valid_rdreq,  ,  ,  ,  );


--HB3_dffe7a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[7]
HB3_dffe7a[7] = DFFEAS(X3_delayed_wrptr_g[7], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3_rdptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0]
X3_rdptr_g[0] = DFFEAS(Z3_power_modified_counter_values[0], CCD_MCLK, C1_oRST_0,  , X3_valid_rdreq,  ,  ,  ,  );


--X3_rdptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2]
X3_rdptr_g[2] = DFFEAS(Z3_power_modified_counter_values[2], CCD_MCLK, C1_oRST_0,  , X3_valid_rdreq,  ,  ,  ,  );


--HB3_dffe7a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[2]
HB3_dffe7a[2] = DFFEAS(X3_delayed_wrptr_g[2], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--HB3_dffe7a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0]
HB3_dffe7a[0] = DFFEAS(X3_delayed_wrptr_g[0], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3L13 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~54
X3L13 = X3_rdptr_g[0] & HB3_dffe7a[0] & (X3_rdptr_g[2] $ !HB3_dffe7a[2]) # !X3_rdptr_g[0] & !HB3_dffe7a[0] & (X3_rdptr_g[2] $ !HB3_dffe7a[2]);


--X3_rdptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[6]
X3_rdptr_g[6] = DFFEAS(Z3_power_modified_counter_values[6], CCD_MCLK, C1_oRST_0,  , X3_valid_rdreq,  ,  ,  ,  );


--X3_rdptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[1]
X3_rdptr_g[1] = DFFEAS(Z3_power_modified_counter_values[1], CCD_MCLK, C1_oRST_0,  , X3_valid_rdreq,  ,  ,  ,  );


--HB3_dffe7a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1]
HB3_dffe7a[1] = DFFEAS(X3_delayed_wrptr_g[1], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--HB3_dffe7a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[6]
HB3_dffe7a[6] = DFFEAS(X3_delayed_wrptr_g[6], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~55
X3L14 = X3_rdptr_g[6] & HB3_dffe7a[6] & (X3_rdptr_g[1] $ !HB3_dffe7a[1]) # !X3_rdptr_g[6] & !HB3_dffe7a[6] & (X3_rdptr_g[1] $ !HB3_dffe7a[1]);


--X3_rdptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[3]
X3_rdptr_g[3] = DFFEAS(Z3_power_modified_counter_values[3], CCD_MCLK, C1_oRST_0,  , X3_valid_rdreq,  ,  ,  ,  );


--X3_rdptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8]
X3_rdptr_g[8] = DFFEAS(Z3_power_modified_counter_values[8], CCD_MCLK, C1_oRST_0,  , X3_valid_rdreq,  ,  ,  ,  );


--HB3_dffe7a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[8]
HB3_dffe7a[8] = DFFEAS(X3_delayed_wrptr_g[8], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--HB3_dffe7a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[3]
HB3_dffe7a[3] = DFFEAS(X3_delayed_wrptr_g[3], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3L15 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~56
X3L15 = X3_rdptr_g[3] & HB3_dffe7a[3] & (X3_rdptr_g[8] $ !HB3_dffe7a[8]) # !X3_rdptr_g[3] & !HB3_dffe7a[3] & (X3_rdptr_g[8] $ !HB3_dffe7a[8]);


--X3_rdptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[5]
X3_rdptr_g[5] = DFFEAS(Z3_power_modified_counter_values[5], CCD_MCLK, C1_oRST_0,  , X3_valid_rdreq,  ,  ,  ,  );


--X3_rdptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4]
X3_rdptr_g[4] = DFFEAS(Z3_power_modified_counter_values[4], CCD_MCLK, C1_oRST_0,  , X3_valid_rdreq,  ,  ,  ,  );


--HB3_dffe7a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4]
HB3_dffe7a[4] = DFFEAS(X3_delayed_wrptr_g[4], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--HB3_dffe7a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[5]
HB3_dffe7a[5] = DFFEAS(X3_delayed_wrptr_g[5], CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~57
X3L16 = X3_rdptr_g[5] & HB3_dffe7a[5] & (X3_rdptr_g[4] $ !HB3_dffe7a[4]) # !X3_rdptr_g[5] & !HB3_dffe7a[5] & (X3_rdptr_g[4] $ !HB3_dffe7a[4]);


--X3L17 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~58
X3L17 = X3L13 & X3L14 & X3L15 & X3L16;


--X3_valid_rdreq is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq
X3_valid_rdreq = B1_oRequest & (X3_rdptr_g[7] $ HB3_dffe7a[7] # !X3L17);


--X3_rdcnt_addr_ena is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdcnt_addr_ena
X3_rdcnt_addr_ena = X3_valid_rdreq # !X4_p0addr;


--G1_RD_MASK[0] is Sdram_Control_4Port:u6|RD_MASK[0]
G1_RD_MASK[0] = DFFEAS(G1L55, KB1__clk0,  ,  , G1L259,  ,  ,  ,  );


--JB3_dffe9a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[7]
JB3_dffe9a[7] = DFFEAS(X3_rdptr_g[7], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[7]
EB3_power_modified_counter_values[7] = DFFEAS(EB3_countera7, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3L1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|_~16
X3L1 = JB3_dffe9a[7] $ EB3_power_modified_counter_values[7];


--JB3_dffe9a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[2]
JB3_dffe9a[2] = DFFEAS(X3_rdptr_g[2], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[2]
EB3_power_modified_counter_values[2] = DFFEAS(EB3_countera2, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB3_dffe9a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[0]
JB3_dffe9a[0] = DFFEAS(X3_rdptr_g[0], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB3_counter_ffa[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|counter_ffa[0]
EB3_counter_ffa[0] = DFFEAS(EB3_countera0, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3L30 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~55
X3L30 = JB3_dffe9a[2] & EB3_power_modified_counter_values[2] & (JB3_dffe9a[0] $ EB3_counter_ffa[0]) # !JB3_dffe9a[2] & !EB3_power_modified_counter_values[2] & (JB3_dffe9a[0] $ EB3_counter_ffa[0]);


--JB3_dffe9a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[6]
JB3_dffe9a[6] = DFFEAS(X3_rdptr_g[6], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB3_dffe9a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[1]
JB3_dffe9a[1] = DFFEAS(X3_rdptr_g[1], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[1]
EB3_power_modified_counter_values[1] = DFFEAS(EB3_countera1, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[6]
EB3_power_modified_counter_values[6] = DFFEAS(EB3_countera6, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3L31 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~56
X3L31 = JB3_dffe9a[6] & EB3_power_modified_counter_values[6] & (JB3_dffe9a[1] $ !EB3_power_modified_counter_values[1]) # !JB3_dffe9a[6] & !EB3_power_modified_counter_values[6] & (JB3_dffe9a[1] $ !EB3_power_modified_counter_values[1]);


--JB3_dffe9a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[3]
JB3_dffe9a[3] = DFFEAS(X3_rdptr_g[3], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB3_dffe9a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[8]
JB3_dffe9a[8] = DFFEAS(X3_rdptr_g[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[8]
EB3_power_modified_counter_values[8] = DFFEAS(EB3_countera8, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[3]
EB3_power_modified_counter_values[3] = DFFEAS(EB3_countera3, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3L32 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~57
X3L32 = JB3_dffe9a[3] & EB3_power_modified_counter_values[3] & (JB3_dffe9a[8] $ !EB3_power_modified_counter_values[8]) # !JB3_dffe9a[3] & !EB3_power_modified_counter_values[3] & (JB3_dffe9a[8] $ !EB3_power_modified_counter_values[8]);


--JB3_dffe9a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5]
JB3_dffe9a[5] = DFFEAS(X3_rdptr_g[5], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB3_dffe9a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[4]
JB3_dffe9a[4] = DFFEAS(X3_rdptr_g[4], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[4]
EB3_power_modified_counter_values[4] = DFFEAS(EB3_countera4, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[5]
EB3_power_modified_counter_values[5] = DFFEAS(EB3_countera5, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3L33 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~58
X3L33 = JB3_dffe9a[5] & EB3_power_modified_counter_values[5] & (JB3_dffe9a[4] $ !EB3_power_modified_counter_values[4]) # !JB3_dffe9a[5] & !EB3_power_modified_counter_values[5] & (JB3_dffe9a[4] $ !EB3_power_modified_counter_values[4]);


--X3L34 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~59
X3L34 = X3L30 & X3L31 & X3L32 & X3L33;


--X3_valid_wrreq is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_wrreq
X3_valid_wrreq = G1_OUT_VALID & G1_RD_MASK[0] & (X3L1 # !X3L34);


--Z3_power_modified_counter_values[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[0]
Z3_power_modified_counter_values[0] = DFFEAS(Z3_countera0, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[1]
Z3_power_modified_counter_values[1] = DFFEAS(Z3_countera1, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[2]
Z3_power_modified_counter_values[2] = DFFEAS(Z3_countera2, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[3]
Z3_power_modified_counter_values[3] = DFFEAS(Z3_countera3, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[4]
Z3_power_modified_counter_values[4] = DFFEAS(Z3_countera4, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[5]
Z3_power_modified_counter_values[5] = DFFEAS(Z3_countera5, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[6]
Z3_power_modified_counter_values[6] = DFFEAS(Z3_countera6, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[7]
Z3_power_modified_counter_values[7] = DFFEAS(Z3_countera7, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8]
Z3_power_modified_counter_values[8] = DFFEAS(Z3_countera8, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--X3_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]
X3_wrptr_g[0] = DFFEAS(X3L37, KB1__clk0, C1_oRST_0,  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[1]
X3_wrptr_g[1] = DFFEAS(EB3_power_modified_counter_values[1], KB1__clk0, C1_oRST_0,  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2]
X3_wrptr_g[2] = DFFEAS(EB3_power_modified_counter_values[2], KB1__clk0, C1_oRST_0,  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[3]
X3_wrptr_g[3] = DFFEAS(EB3_power_modified_counter_values[3], KB1__clk0, C1_oRST_0,  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[4]
X3_wrptr_g[4] = DFFEAS(EB3_power_modified_counter_values[4], KB1__clk0, C1_oRST_0,  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5]
X3_wrptr_g[5] = DFFEAS(EB3_power_modified_counter_values[5], KB1__clk0, C1_oRST_0,  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6]
X3_wrptr_g[6] = DFFEAS(EB3_power_modified_counter_values[6], KB1__clk0, C1_oRST_0,  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[7]
X3_wrptr_g[7] = DFFEAS(EB3_power_modified_counter_values[7], KB1__clk0, C1_oRST_0,  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8]
X3_wrptr_g[8] = DFFEAS(EB3_power_modified_counter_values[8], KB1__clk0, C1_oRST_0,  , X3_valid_wrreq,  ,  ,  ,  );


--C1_Cont[21] is Reset_Delay:u2|Cont[21]
C1_Cont[21] = DFFEAS(C1L66, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[20] is Reset_Delay:u2|Cont[20]
C1_Cont[20] = DFFEAS(C1L63, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[0] is Reset_Delay:u2|Cont[0]
C1_Cont[0] = DFFEAS(C1L3, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[1] is Reset_Delay:u2|Cont[1]
C1_Cont[1] = DFFEAS(C1L6, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1L68 is Reset_Delay:u2|Equal~199
C1L68 = C1_Cont[0] & C1_Cont[1];


--C1_Cont[2] is Reset_Delay:u2|Cont[2]
C1_Cont[2] = DFFEAS(C1L9, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[3] is Reset_Delay:u2|Cont[3]
C1_Cont[3] = DFFEAS(C1L12, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[4] is Reset_Delay:u2|Cont[4]
C1_Cont[4] = DFFEAS(C1L15, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[5] is Reset_Delay:u2|Cont[5]
C1_Cont[5] = DFFEAS(C1L18, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[6] is Reset_Delay:u2|Cont[6]
C1_Cont[6] = DFFEAS(C1L21, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[7] is Reset_Delay:u2|Cont[7]
C1_Cont[7] = DFFEAS(C1L24, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1L69 is Reset_Delay:u2|Equal~200
C1L69 = C1_Cont[4] & C1_Cont[5] & C1_Cont[6] & C1_Cont[7];


--C1L70 is Reset_Delay:u2|Equal~201
C1L70 = C1L68 & C1_Cont[2] & C1_Cont[3] & C1L69;


--C1_Cont[8] is Reset_Delay:u2|Cont[8]
C1_Cont[8] = DFFEAS(C1L27, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[9] is Reset_Delay:u2|Cont[9]
C1_Cont[9] = DFFEAS(C1L30, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[10] is Reset_Delay:u2|Cont[10]
C1_Cont[10] = DFFEAS(C1L33, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[11] is Reset_Delay:u2|Cont[11]
C1_Cont[11] = DFFEAS(C1L36, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1L71 is Reset_Delay:u2|Equal~202
C1L71 = C1_Cont[8] & C1_Cont[9] & C1_Cont[10] & C1_Cont[11];


--C1_Cont[12] is Reset_Delay:u2|Cont[12]
C1_Cont[12] = DFFEAS(C1L39, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[13] is Reset_Delay:u2|Cont[13]
C1_Cont[13] = DFFEAS(C1L42, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[14] is Reset_Delay:u2|Cont[14]
C1_Cont[14] = DFFEAS(C1L45, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[15] is Reset_Delay:u2|Cont[15]
C1_Cont[15] = DFFEAS(C1L48, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1L72 is Reset_Delay:u2|Equal~203
C1L72 = C1_Cont[12] & C1_Cont[13] & C1_Cont[14] & C1_Cont[15];


--C1_Cont[16] is Reset_Delay:u2|Cont[16]
C1_Cont[16] = DFFEAS(C1L51, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[17] is Reset_Delay:u2|Cont[17]
C1_Cont[17] = DFFEAS(C1L54, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[18] is Reset_Delay:u2|Cont[18]
C1_Cont[18] = DFFEAS(C1L57, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[19] is Reset_Delay:u2|Cont[19]
C1_Cont[19] = DFFEAS(C1L60, CLOCK_50, KEY[0],  , C1L75,  ,  ,  ,  );


--C1L73 is Reset_Delay:u2|Equal~204
C1L73 = C1_Cont[16] & C1_Cont[17] & C1_Cont[18] & C1_Cont[19];


--C1L74 is Reset_Delay:u2|Equal~205
C1L74 = C1L70 & C1L71 & C1L72 & C1L73;


--C1L79 is Reset_Delay:u2|oRST_1~54
C1L79 = C1_oRST_1 # C1_Cont[21] & (C1_Cont[20] # C1L74);


--D1L183 is CCD_Capture:u3|mSTART~27
D1L183 = KEY[2] & (D1_mSTART # !KEY[3]);


--D1L105 is CCD_Capture:u3|X_Cont[0]~934
D1L105 = D1_X_Cont[0] $ VCC;

--D1L106 is CCD_Capture:u3|X_Cont[0]~935
D1L106 = CARRY(D1_X_Cont[0]);


--D1L109 is CCD_Capture:u3|X_Cont[1]~936
D1L109 = D1_X_Cont[1] & !D1L106 # !D1_X_Cont[1] & (D1L106 # GND);

--D1L110 is CCD_Capture:u3|X_Cont[1]~937
D1L110 = CARRY(!D1L106 # !D1_X_Cont[1]);


--D1L112 is CCD_Capture:u3|X_Cont[2]~938
D1L112 = D1_X_Cont[2] & (D1L110 $ GND) # !D1_X_Cont[2] & !D1L110 & VCC;

--D1L113 is CCD_Capture:u3|X_Cont[2]~939
D1L113 = CARRY(D1_X_Cont[2] & !D1L110);


--D1L115 is CCD_Capture:u3|X_Cont[3]~940
D1L115 = D1_X_Cont[3] & !D1L113 # !D1_X_Cont[3] & (D1L113 # GND);

--D1L116 is CCD_Capture:u3|X_Cont[3]~941
D1L116 = CARRY(!D1L113 # !D1_X_Cont[3]);


--D1L118 is CCD_Capture:u3|X_Cont[4]~942
D1L118 = D1_X_Cont[4] & (D1L116 $ GND) # !D1_X_Cont[4] & !D1L116 & VCC;

--D1L119 is CCD_Capture:u3|X_Cont[4]~943
D1L119 = CARRY(D1_X_Cont[4] & !D1L116);


--D1L121 is CCD_Capture:u3|X_Cont[5]~944
D1L121 = D1_X_Cont[5] & !D1L119 # !D1_X_Cont[5] & (D1L119 # GND);

--D1L122 is CCD_Capture:u3|X_Cont[5]~945
D1L122 = CARRY(!D1L119 # !D1_X_Cont[5]);


--D1L124 is CCD_Capture:u3|X_Cont[6]~946
D1L124 = D1_X_Cont[6] & (D1L122 $ GND) # !D1_X_Cont[6] & !D1L122 & VCC;

--D1L125 is CCD_Capture:u3|X_Cont[6]~947
D1L125 = CARRY(D1_X_Cont[6] & !D1L122);


--D1L127 is CCD_Capture:u3|X_Cont[7]~948
D1L127 = D1_X_Cont[7] & !D1L125 # !D1_X_Cont[7] & (D1L125 # GND);

--D1L128 is CCD_Capture:u3|X_Cont[7]~949
D1L128 = CARRY(!D1L125 # !D1_X_Cont[7]);


--D1L130 is CCD_Capture:u3|X_Cont[8]~950
D1L130 = D1_X_Cont[8] & (D1L128 $ GND) # !D1_X_Cont[8] & !D1L128 & VCC;

--D1L131 is CCD_Capture:u3|X_Cont[8]~951
D1L131 = CARRY(D1_X_Cont[8] & !D1L128);


--D1L107 is CCD_Capture:u3|X_Cont[0]~952
D1L107 = !D1_mCCD_FVAL # !D1L101;


--D1L133 is CCD_Capture:u3|X_Cont[9]~953
D1L133 = D1_X_Cont[9] & !D1L131 # !D1_X_Cont[9] & (D1L131 # GND);

--D1L134 is CCD_Capture:u3|X_Cont[9]~954
D1L134 = CARRY(!D1L131 # !D1_X_Cont[9]);


--D1L136 is CCD_Capture:u3|X_Cont[10]~955
D1L136 = D1_X_Cont[10] $ !D1L134;


--D1L180 is CCD_Capture:u3|mCCD_FVAL~40
D1L180 = D1_mCCD_FVAL & (rCCD_FVAL # !D1_Pre_FVAL) # !D1_mCCD_FVAL & rCCD_FVAL & D1_mSTART & !D1_Pre_FVAL;


--rCCD_LVAL is rCCD_LVAL
rCCD_LVAL = DFFEAS(A1L190, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--R1_do_load_mode is Sdram_Control_4Port:u6|command:command1|do_load_mode
R1_do_load_mode = DFFEAS(R1L50, KB1__clk0,  ,  ,  ,  ,  , S1_INIT_REQ,  );


--S1_SADDR[8] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[8]
S1_SADDR[8] = DFFEAS(G1_mADDR[8], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_do_writea is Sdram_Control_4Port:u6|command:command1|do_writea
R1_do_writea = DFFEAS(R1L86, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_do_reada is Sdram_Control_4Port:u6|command:command1|do_reada
R1_do_reada = DFFEAS(R1L81, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L33 is Sdram_Control_4Port:u6|command:command1|SA~489
R1L33 = R1_do_load_mode # S1_SADDR[8] & (R1_do_writea # R1_do_reada);


--G1L20 is Sdram_Control_4Port:u6|Equal~1120
G1L20 = G1L15 & G1L16 & !G1_ST[2] & !G1_ST[8];


--G1L21 is Sdram_Control_4Port:u6|Equal~1121
G1L21 = G1_ST[8] & G1_ST[1];


--G1L22 is Sdram_Control_4Port:u6|Equal~1122
G1L22 = G1_ST[2] & G1L15 & G1L16 & G1L21;


--G1L89 is Sdram_Control_4Port:u6|ST[1]~2688
G1L89 = G1_ST[0] & (!G1L22) # !G1_ST[0] & (G1_ST[1] # !G1L20);


--G1L123 is Sdram_Control_4Port:u6|add~2849
G1L123 = G1_ST[0] $ VCC;

--G1L124 is Sdram_Control_4Port:u6|add~2850
G1L124 = CARRY(G1_ST[0]);


--G1L125 is Sdram_Control_4Port:u6|add~2851
G1L125 = G1_ST[1] & !G1L124 # !G1_ST[1] & (G1L124 # GND);

--G1L126 is Sdram_Control_4Port:u6|add~2852
G1L126 = CARRY(!G1L124 # !G1_ST[1]);


--G1L127 is Sdram_Control_4Port:u6|add~2853
G1L127 = G1_ST[2] & (G1L126 $ GND) # !G1_ST[2] & !G1L126 & VCC;

--G1L128 is Sdram_Control_4Port:u6|add~2854
G1L128 = CARRY(G1_ST[2] & !G1L126);


--G1L23 is Sdram_Control_4Port:u6|Equal~1123
G1L23 = G1_ST[0] & G1L20 & !G1_ST[1];


--G1L24 is Sdram_Control_4Port:u6|Equal~1124
G1L24 = G1L20 & !G1_ST[0] & !G1_ST[1];


--G1_Pre_RD is Sdram_Control_4Port:u6|Pre_RD
G1_Pre_RD = DFFEAS(G1_mRD, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_Pre_WR is Sdram_Control_4Port:u6|Pre_WR
G1_Pre_WR = DFFEAS(G1_mWR, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mWR is Sdram_Control_4Port:u6|mWR
G1_mWR = DFFEAS(G1L266, KB1__clk0,  ,  , G1L115,  ,  ,  ,  );


--G1_mRD is Sdram_Control_4Port:u6|mRD
G1_mRD = DFFEAS(G1L260, KB1__clk0,  ,  , G1L259,  ,  ,  ,  );


--G1L104 is Sdram_Control_4Port:u6|ST[8]~2689
G1L104 = G1_Pre_RD & (G1_Pre_WR # !G1_mWR) # !G1_Pre_RD & !G1_mRD & (G1_Pre_WR # !G1_mWR);


--S1_CMD_ACK is Sdram_Control_4Port:u6|control_interface:control1|CMD_ACK
S1_CMD_ACK = DFFEAS(S1L51, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L105 is Sdram_Control_4Port:u6|ST[8]~2690
G1L105 = G1L24 & (G1L104 # G1L23 & !S1_CMD_ACK) # !G1L24 & (G1L23 & !S1_CMD_ACK);


--G1L92 is Sdram_Control_4Port:u6|ST[2]~2691
G1L92 = G1L89 & G1L127 & !G1L23 & !G1L105;


--G1L86 is Sdram_Control_4Port:u6|ST[0]~2692
G1L86 = G1L24 # G1L123 & (!G1L22 # !G1_ST[0]);


--G1L87 is Sdram_Control_4Port:u6|ST[0]~2693
G1L87 = G1L105 & G1_ST[0] # !G1L105 & (G1L86 & !G1L23);


--G1L129 is Sdram_Control_4Port:u6|add~2855
G1L129 = G1_ST[3] & !G1L128 # !G1_ST[3] & (G1L128 # GND);

--G1L130 is Sdram_Control_4Port:u6|add~2856
G1L130 = CARRY(!G1L128 # !G1_ST[3]);


--G1L131 is Sdram_Control_4Port:u6|add~2857
G1L131 = G1_ST[4] & (G1L130 $ GND) # !G1_ST[4] & !G1L130 & VCC;

--G1L132 is Sdram_Control_4Port:u6|add~2858
G1L132 = CARRY(G1_ST[4] & !G1L130);


--G1L133 is Sdram_Control_4Port:u6|add~2859
G1L133 = G1_ST[5] & !G1L132 # !G1_ST[5] & (G1L132 # GND);

--G1L134 is Sdram_Control_4Port:u6|add~2860
G1L134 = CARRY(!G1L132 # !G1_ST[5]);


--G1L135 is Sdram_Control_4Port:u6|add~2861
G1L135 = G1_ST[6] & (G1L134 $ GND) # !G1_ST[6] & !G1L134 & VCC;

--G1L136 is Sdram_Control_4Port:u6|add~2862
G1L136 = CARRY(G1_ST[6] & !G1L134);


--G1L137 is Sdram_Control_4Port:u6|add~2863
G1L137 = G1_ST[7] & !G1L136 # !G1_ST[7] & (G1L136 # GND);

--G1L138 is Sdram_Control_4Port:u6|add~2864
G1L138 = CARRY(!G1L136 # !G1_ST[7]);


--G1L139 is Sdram_Control_4Port:u6|add~2865
G1L139 = G1_ST[8] & (G1L138 $ GND) # !G1_ST[8] & !G1L138 & VCC;

--G1L140 is Sdram_Control_4Port:u6|add~2866
G1L140 = CARRY(G1_ST[8] & !G1L138);


--G1L141 is Sdram_Control_4Port:u6|add~2867
G1L141 = G1_ST[9] $ G1L140;


--G1L108 is Sdram_Control_4Port:u6|ST[9]~2694
G1L108 = G1L141 & G1L89 & !G1L23 & !G1L105;


--G1L102 is Sdram_Control_4Port:u6|ST[7]~2695
G1L102 = G1L89 & G1L137 & !G1L23 & !G1L105;


--G1L100 is Sdram_Control_4Port:u6|ST[6]~2696
G1L100 = G1L89 & G1L135 & !G1L23 & !G1L105;


--G1L98 is Sdram_Control_4Port:u6|ST[5]~2697
G1L98 = G1L89 & G1L133 & !G1L23 & !G1L105;


--G1L96 is Sdram_Control_4Port:u6|ST[4]~2698
G1L96 = G1L89 & G1L131 & !G1L23 & !G1L105;


--G1L94 is Sdram_Control_4Port:u6|ST[3]~2699
G1L94 = G1L89 & G1L129 & !G1L23 & !G1L105;


--G1L106 is Sdram_Control_4Port:u6|ST[8]~2700
G1L106 = G1L89 & G1L139 & !G1L23 & !G1L105;


--G1L90 is Sdram_Control_4Port:u6|ST[1]~2701
G1L90 = !G1L105 & (G1L23 # G1L89 & G1L125);


--S1_SADDR[9] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[9]
S1_SADDR[9] = DFFEAS(G1_mADDR[9], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L34 is Sdram_Control_4Port:u6|command:command1|SA~490
R1L34 = R1_do_load_mode # S1_SADDR[9] & (R1_do_writea # R1_do_reada);


--S1_SADDR[10] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[10]
S1_SADDR[10] = DFFEAS(G1_mADDR[10], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L35 is Sdram_Control_4Port:u6|command:command1|SA~491
R1L35 = R1_do_load_mode # S1_SADDR[10] & (R1_do_writea # R1_do_reada);


--S1_SADDR[11] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[11]
S1_SADDR[11] = DFFEAS(G1_mADDR[11], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L36 is Sdram_Control_4Port:u6|command:command1|SA~492
R1L36 = S1_SADDR[11] & !R1_do_load_mode & (R1_do_writea # R1_do_reada);


--S1_SADDR[12] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[12]
S1_SADDR[12] = DFFEAS(G1_mADDR[12], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L37 is Sdram_Control_4Port:u6|command:command1|SA~493
R1L37 = R1_do_load_mode # S1_SADDR[12] & (R1_do_writea # R1_do_reada);


--S1_SADDR[13] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[13]
S1_SADDR[13] = DFFEAS(G1_mADDR[13], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L38 is Sdram_Control_4Port:u6|command:command1|SA~494
R1L38 = R1_do_load_mode # S1_SADDR[13] & (R1_do_writea # R1_do_reada);


--S1_SADDR[14] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[14]
S1_SADDR[14] = DFFEAS(G1_mADDR[14], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L39 is Sdram_Control_4Port:u6|command:command1|SA~495
R1L39 = S1_SADDR[14] & !R1_do_load_mode & (R1_do_writea # R1_do_reada);


--S1_SADDR[15] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[15]
S1_SADDR[15] = DFFEAS(G1_mADDR[15], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L40 is Sdram_Control_4Port:u6|command:command1|SA~496
R1L40 = S1_SADDR[15] & !R1_do_load_mode & (R1_do_writea # R1_do_reada);


--S1_SADDR[16] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[16]
S1_SADDR[16] = DFFEAS(G1_mADDR[16], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L41 is Sdram_Control_4Port:u6|command:command1|SA~497
R1L41 = S1_SADDR[16] & !R1_do_load_mode & (R1_do_writea # R1_do_reada);


--S1_SADDR[17] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[17]
S1_SADDR[17] = DFFEAS(G1_mADDR[17], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L42 is Sdram_Control_4Port:u6|command:command1|SA~498
R1L42 = S1_SADDR[17] & !R1_do_load_mode & (R1_do_writea # R1_do_reada);


--R1L57 is Sdram_Control_4Port:u6|command:command1|always4~0
R1L57 = R1_do_writea # R1_do_reada;


--S1_SADDR[18] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[18]
S1_SADDR[18] = DFFEAS(G1_mADDR[18], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_do_precharge is Sdram_Control_4Port:u6|command:command1|do_precharge
R1_do_precharge = DFFEAS(R1L53, KB1__clk0,  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1_do_rw is Sdram_Control_4Port:u6|command:command1|do_rw
R1_do_rw = DFFEAS(R1L84, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L43 is Sdram_Control_4Port:u6|command:command1|SA~499
R1L43 = R1L57 & S1_SADDR[18] & !R1_do_precharge & !R1_do_rw;


--S1_SADDR[19] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[19]
S1_SADDR[19] = DFFEAS(G1_mADDR[19], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L44 is Sdram_Control_4Port:u6|command:command1|SA~500
R1L44 = S1_SADDR[19] & !R1_do_load_mode & (R1_do_writea # R1_do_reada);


--G1L25 is Sdram_Control_4Port:u6|Equal~1125
G1L25 = G1_mRD & !G1_Pre_RD;


--G1L57 is Sdram_Control_4Port:u6|Read~463
G1L57 = G1L20 & G1L25 & !G1_ST[0] & !G1_ST[1];


--G1L120 is Sdram_Control_4Port:u6|Write~320
G1L120 = G1_Write & !G1L57 & (G1_ST[0] # !G1L22);


--G1L121 is Sdram_Control_4Port:u6|Write~321
G1L121 = G1L24 & G1_mWR & !G1_Pre_WR;


--G1L122 is Sdram_Control_4Port:u6|Write~322
G1L122 = G1L120 # G1L121 & !G1_Write & !G1L25;


--G1L26 is Sdram_Control_4Port:u6|Equal~1126
G1L26 = !G1L21 # !G1L18 # !G1_ST[2] # !G1_ST[0];


--G1L58 is Sdram_Control_4Port:u6|Read~464
G1L58 = G1_Read & (G1L26 $ (!G1L57 & G1L121)) # !G1_Read & G1L57;


--R1_do_refresh is Sdram_Control_4Port:u6|command:command1|do_refresh
R1_do_refresh = DFFEAS(R1L55, KB1__clk0,  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1L109 is Sdram_Control_4Port:u6|command:command1|rw_flag~24
R1L109 = !R1_do_load_mode & !R1_do_precharge;


--R1_rw_flag is Sdram_Control_4Port:u6|command:command1|rw_flag
R1_rw_flag = DFFEAS(R1L110, KB1__clk0,  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1L46 is Sdram_Control_4Port:u6|command:command1|WE_N~73
R1L46 = R1_do_rw & !R1_do_writea & !R1_do_reada;


--R1L47 is Sdram_Control_4Port:u6|command:command1|WE_N~74
R1L47 = R1_do_refresh # R1L109 & (R1_rw_flag # !R1L46);


--R1L7 is Sdram_Control_4Port:u6|command:command1|CAS_N~114
R1L7 = !R1_do_refresh & (R1_do_precharge # !R1_do_load_mode & !R1L46);


--R1_oe4 is Sdram_Control_4Port:u6|command:command1|oe4
R1_oe4 = DFFEAS(R1L93, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L15 is Sdram_Control_4Port:u6|command:command1|RAS_N~164
R1L15 = R1_do_precharge & (R1_rw_flag # R1_oe4);


--R1L16 is Sdram_Control_4Port:u6|command:command1|RAS_N~165
R1L16 = !R1_do_refresh & (R1L15 # R1L109 & !R1L57);


--S1_SADDR[22] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[22]
S1_SADDR[22] = DFFEAS(G1_mADDR[22], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_do_initial is Sdram_Control_4Port:u6|command:command1|do_initial
R1_do_initial = DFFEAS(S1_INIT_REQ, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L12 is Sdram_Control_4Port:u6|command:command1|CS_N~22
R1L12 = R1L109 & S1_SADDR[22] & !R1_do_refresh & !R1_do_initial;


--S1_SADDR[20] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[20]
S1_SADDR[20] = DFFEAS(G1_mADDR[20], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L4 is Sdram_Control_4Port:u6|command:command1|BA~32
R1L4 = S1_SADDR[20] & !R1_do_load_mode & !R1_do_precharge;


--S1_SADDR[21] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[21]
S1_SADDR[21] = DFFEAS(G1_mADDR[21], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L5 is Sdram_Control_4Port:u6|command:command1|BA~33
R1L5 = S1_SADDR[21] & !R1_do_load_mode & !R1_do_precharge;


--C1L81 is Reset_Delay:u2|oRST_2~15
C1L81 = C1_oRST_2 # C1_Cont[21] & C1_Cont[20] & C1L74;


--B1L47 is VGA_Controller:u1|LessThan~1096
B1L47 = B1L1 & (!B1_H_Cont[3] # !B1_H_Cont[2] # !B1_H_Cont[1]);


--B1L79 is VGA_Controller:u1|always0~225
B1L79 = B1_H_Cont[8] & (B1L47 & !B1_H_Cont[7] # !B1_H_Cont[9]) # !B1_H_Cont[8] & (B1_H_Cont[9] # !B1L47 & B1_H_Cont[7]);


--B1L80 is VGA_Controller:u1|always0~226
B1L80 = B1L114 & B1L79;


--X4_delayed_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7]
X4_delayed_wrptr_g[7] = DFFEAS(X4_wrptr_g[7], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[2]
X4_delayed_wrptr_g[2] = DFFEAS(X4_wrptr_g[2], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0]
X4_delayed_wrptr_g[0] = DFFEAS(X4_wrptr_g[0], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[1]
X4_delayed_wrptr_g[1] = DFFEAS(X4_wrptr_g[1], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6]
X4_delayed_wrptr_g[6] = DFFEAS(X4_wrptr_g[6], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[8]
X4_delayed_wrptr_g[8] = DFFEAS(X4_wrptr_g[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3]
X4_delayed_wrptr_g[3] = DFFEAS(X4_wrptr_g[3], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[4]
X4_delayed_wrptr_g[4] = DFFEAS(X4_wrptr_g[4], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5]
X4_delayed_wrptr_g[5] = DFFEAS(X4_wrptr_g[5], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X4_rdaclr is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdaclr
X4_rdaclr = DFFEAS(VCC, !CCD_MCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--G1L27 is Sdram_Control_4Port:u6|Equal~1127
G1L27 = G1_ST[2] & G1L18 & G1L32 & !G1_ST[8];


--G1L45 is Sdram_Control_4Port:u6|OUT_VALID~138
G1L45 = G1_Read & (G1L27 # G1_OUT_VALID & G1L26) # !G1_Read & G1_OUT_VALID;


--CB11_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[8]
CB11_dffe5a[8] = DFFEAS(JB3_dffe9a[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[8]
X3_delayed_wrptr_g[8] = DFFEAS(X3_wrptr_g[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB12_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[7]
CB12_dffe5a[7] = DFFEAS(AB11_xor7, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB11_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[7]
CB11_dffe5a[7] = DFFEAS(AB12_xor7, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB12_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[6]
CB12_dffe5a[6] = DFFEAS(AB11_xor6, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB11_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]
CB11_dffe5a[6] = DFFEAS(AB12_xor6, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB12_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[5]
CB12_dffe5a[5] = DFFEAS(AB11_xor5, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB11_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[5]
CB11_dffe5a[5] = DFFEAS(AB12_xor5, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB12_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4]
CB12_dffe5a[4] = DFFEAS(AB11_xor4, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB11_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]
CB11_dffe5a[4] = DFFEAS(AB12_xor4, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB12_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]
CB12_dffe5a[3] = DFFEAS(AB11_xor3, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB11_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3]
CB11_dffe5a[3] = DFFEAS(AB12_xor3, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB12_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2]
CB12_dffe5a[2] = DFFEAS(AB11_xor2, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB11_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2]
CB11_dffe5a[2] = DFFEAS(AB12_xor2, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB12_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]
CB12_dffe5a[1] = DFFEAS(AB11_xor1, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB11_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[1]
CB11_dffe5a[1] = DFFEAS(AB12_xor1, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB12_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[0]
CB12_dffe5a[0] = DFFEAS(AB11_xor0, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB11_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[0]
CB11_dffe5a[0] = DFFEAS(AB12_xor0, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--BB6L2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~260
BB6L2 = CARRY(CB12_dffe5a[0] # !CB11_dffe5a[0]);


--BB6L4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~262
BB6L4 = CARRY(CB12_dffe5a[1] & CB11_dffe5a[1] & !BB6L2 # !CB12_dffe5a[1] & (CB11_dffe5a[1] # !BB6L2));


--BB6L6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~264
BB6L6 = CARRY(CB12_dffe5a[2] & (!BB6L4 # !CB11_dffe5a[2]) # !CB12_dffe5a[2] & !CB11_dffe5a[2] & !BB6L4);


--BB6L8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~266
BB6L8 = CARRY(CB12_dffe5a[3] & CB11_dffe5a[3] & !BB6L6 # !CB12_dffe5a[3] & (CB11_dffe5a[3] # !BB6L6));


--BB6L10 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~268
BB6L10 = CARRY(CB12_dffe5a[4] & (!BB6L8 # !CB11_dffe5a[4]) # !CB12_dffe5a[4] & !CB11_dffe5a[4] & !BB6L8);


--BB6L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~270
BB6L12 = CARRY(CB12_dffe5a[5] & CB11_dffe5a[5] & !BB6L10 # !CB12_dffe5a[5] & (CB11_dffe5a[5] # !BB6L10));


--BB6L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~272
BB6L14 = CARRY(CB12_dffe5a[6] & (!BB6L12 # !CB11_dffe5a[6]) # !CB12_dffe5a[6] & !CB11_dffe5a[6] & !BB6L12);


--BB6L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~274
BB6L16 = CARRY(CB12_dffe5a[7] & CB11_dffe5a[7] & !BB6L14 # !CB12_dffe5a[7] & (CB11_dffe5a[7] # !BB6L14));


--BB6L17 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~275
BB6L17 = CB11_dffe5a[8] $ X3_delayed_wrptr_g[8] $ !BB6L16;


--CB2_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[8]
CB2_dffe5a[8] = DFFEAS(HB1_dffe7a[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB1_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[8]
CB1_dffe5a[8] = DFFEAS(X1_rdptr_g[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB2_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[7]
CB2_dffe5a[7] = DFFEAS(AB2_xor7, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB1_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[7]
CB1_dffe5a[7] = DFFEAS(AB1_xor7, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB2_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[6]
CB2_dffe5a[6] = DFFEAS(AB2_xor6, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB1_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[6]
CB1_dffe5a[6] = DFFEAS(AB1_xor6, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB2_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[5]
CB2_dffe5a[5] = DFFEAS(AB2_xor5, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB1_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[5]
CB1_dffe5a[5] = DFFEAS(AB1_xor5, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB2_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[4]
CB2_dffe5a[4] = DFFEAS(AB2_xor4, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB1_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[4]
CB1_dffe5a[4] = DFFEAS(AB1_xor4, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB2_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[3]
CB2_dffe5a[3] = DFFEAS(AB2_xor3, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB1_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[3]
CB1_dffe5a[3] = DFFEAS(AB1_xor3, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB2_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[2]
CB2_dffe5a[2] = DFFEAS(AB2_xor2, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB1_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[2]
CB1_dffe5a[2] = DFFEAS(AB1_xor2, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB2_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[1]
CB2_dffe5a[1] = DFFEAS(AB2_xor1, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB1_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[1]
CB1_dffe5a[1] = DFFEAS(AB1_xor1, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB2_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[0]
CB2_dffe5a[0] = DFFEAS(AB2_xor0, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB1_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[0]
CB1_dffe5a[0] = DFFEAS(AB1_xor0, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--BB1L2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~274
BB1L2 = CARRY(CB2_dffe5a[0] # !CB1_dffe5a[0]);


--BB1L4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~276
BB1L4 = CARRY(CB2_dffe5a[1] & CB1_dffe5a[1] & !BB1L2 # !CB2_dffe5a[1] & (CB1_dffe5a[1] # !BB1L2));


--BB1L6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~278
BB1L6 = CARRY(CB2_dffe5a[2] & (!BB1L4 # !CB1_dffe5a[2]) # !CB2_dffe5a[2] & !CB1_dffe5a[2] & !BB1L4);


--BB1L8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~280
BB1L8 = CARRY(CB2_dffe5a[3] & CB1_dffe5a[3] & !BB1L6 # !CB2_dffe5a[3] & (CB1_dffe5a[3] # !BB1L6));


--BB1L10 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~282
BB1L10 = CARRY(CB2_dffe5a[4] & (!BB1L8 # !CB1_dffe5a[4]) # !CB2_dffe5a[4] & !CB1_dffe5a[4] & !BB1L8);


--BB1L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~284
BB1L12 = CARRY(CB2_dffe5a[5] & CB1_dffe5a[5] & !BB1L10 # !CB2_dffe5a[5] & (CB1_dffe5a[5] # !BB1L10));


--BB1L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~286
BB1L14 = CARRY(CB2_dffe5a[6] & (!BB1L12 # !CB1_dffe5a[6]) # !CB2_dffe5a[6] & !CB1_dffe5a[6] & !BB1L12);


--BB1L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~288
BB1L16 = CARRY(CB2_dffe5a[7] & CB1_dffe5a[7] & !BB1L14 # !CB2_dffe5a[7] & (CB1_dffe5a[7] # !BB1L14));


--BB1L17 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~289
BB1L17 = CB2_dffe5a[8] $ CB1_dffe5a[8] $ BB1L16;


--G1_mRD_DONE is Sdram_Control_4Port:u6|mRD_DONE
G1_mRD_DONE = DFFEAS(G1L254, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--CB6_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[8]
CB6_dffe5a[8] = DFFEAS(HB2_dffe7a[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB5_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[8]
CB5_dffe5a[8] = DFFEAS(X2_rdptr_g[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB6_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[7]
CB6_dffe5a[7] = DFFEAS(AB6_xor7, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB5_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[7]
CB5_dffe5a[7] = DFFEAS(AB5_xor7, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB6_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[6]
CB6_dffe5a[6] = DFFEAS(AB6_xor6, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB5_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[6]
CB5_dffe5a[6] = DFFEAS(AB5_xor6, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB6_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[5]
CB6_dffe5a[5] = DFFEAS(AB6_xor5, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB5_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[5]
CB5_dffe5a[5] = DFFEAS(AB5_xor5, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB6_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[4]
CB6_dffe5a[4] = DFFEAS(AB6_xor4, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB5_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[4]
CB5_dffe5a[4] = DFFEAS(AB5_xor4, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB6_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[3]
CB6_dffe5a[3] = DFFEAS(AB6_xor3, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB5_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[3]
CB5_dffe5a[3] = DFFEAS(AB5_xor3, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB6_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[2]
CB6_dffe5a[2] = DFFEAS(AB6_xor2, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB5_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[2]
CB5_dffe5a[2] = DFFEAS(AB5_xor2, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB6_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[1]
CB6_dffe5a[1] = DFFEAS(AB6_xor1, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB5_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[1]
CB5_dffe5a[1] = DFFEAS(AB5_xor1, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB6_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[0]
CB6_dffe5a[0] = DFFEAS(AB6_xor0, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB5_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[0]
CB5_dffe5a[0] = DFFEAS(AB5_xor0, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--BB3L2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~267
BB3L2 = CARRY(CB6_dffe5a[0] # !CB5_dffe5a[0]);


--BB3L4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~269
BB3L4 = CARRY(CB6_dffe5a[1] & CB5_dffe5a[1] & !BB3L2 # !CB6_dffe5a[1] & (CB5_dffe5a[1] # !BB3L2));


--BB3L6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~271
BB3L6 = CARRY(CB6_dffe5a[2] & (!BB3L4 # !CB5_dffe5a[2]) # !CB6_dffe5a[2] & !CB5_dffe5a[2] & !BB3L4);


--BB3L8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~273
BB3L8 = CARRY(CB6_dffe5a[3] & CB5_dffe5a[3] & !BB3L6 # !CB6_dffe5a[3] & (CB5_dffe5a[3] # !BB3L6));


--BB3L10 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~275
BB3L10 = CARRY(CB6_dffe5a[4] & (!BB3L8 # !CB5_dffe5a[4]) # !CB6_dffe5a[4] & !CB5_dffe5a[4] & !BB3L8);


--BB3L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~277
BB3L12 = CARRY(CB6_dffe5a[5] & CB5_dffe5a[5] & !BB3L10 # !CB6_dffe5a[5] & (CB5_dffe5a[5] # !BB3L10));


--BB3L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~279
BB3L14 = CARRY(CB6_dffe5a[6] & (!BB3L12 # !CB5_dffe5a[6]) # !CB6_dffe5a[6] & !CB5_dffe5a[6] & !BB3L12);


--BB3L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~281
BB3L16 = CARRY(CB6_dffe5a[7] & CB5_dffe5a[7] & !BB3L14 # !CB6_dffe5a[7] & (CB5_dffe5a[7] # !BB3L14));


--BB3L17 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~282
BB3L17 = CB6_dffe5a[8] $ CB5_dffe5a[8] $ !BB3L16;


--G1L54 is Sdram_Control_4Port:u6|RD_MASK~98
G1L54 = !BB6L17 & !BB1L17 & !G1_mRD_DONE & BB3L17;


--CB15_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[8]
CB15_dffe5a[8] = DFFEAS(JB4_dffe9a[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB16_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[7]
CB16_dffe5a[7] = DFFEAS(AB15_xor7, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB15_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[7]
CB15_dffe5a[7] = DFFEAS(AB16_xor7, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB16_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[6]
CB16_dffe5a[6] = DFFEAS(AB15_xor6, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB15_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]
CB15_dffe5a[6] = DFFEAS(AB16_xor6, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB16_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[5]
CB16_dffe5a[5] = DFFEAS(AB15_xor5, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB15_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[5]
CB15_dffe5a[5] = DFFEAS(AB16_xor5, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB16_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4]
CB16_dffe5a[4] = DFFEAS(AB15_xor4, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB15_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]
CB15_dffe5a[4] = DFFEAS(AB16_xor4, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB16_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]
CB16_dffe5a[3] = DFFEAS(AB15_xor3, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB15_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3]
CB15_dffe5a[3] = DFFEAS(AB16_xor3, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB16_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2]
CB16_dffe5a[2] = DFFEAS(AB15_xor2, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB15_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2]
CB15_dffe5a[2] = DFFEAS(AB16_xor2, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB16_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]
CB16_dffe5a[1] = DFFEAS(AB15_xor1, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB15_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[1]
CB15_dffe5a[1] = DFFEAS(AB16_xor1, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB16_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[0]
CB16_dffe5a[0] = DFFEAS(AB15_xor0, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--CB15_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[0]
CB15_dffe5a[0] = DFFEAS(AB16_xor0, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--BB8L2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~331
BB8L2 = CARRY(CB16_dffe5a[0] # !CB15_dffe5a[0]);


--BB8L4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~333
BB8L4 = CARRY(CB16_dffe5a[1] & CB15_dffe5a[1] & !BB8L2 # !CB16_dffe5a[1] & (CB15_dffe5a[1] # !BB8L2));


--BB8L6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~335
BB8L6 = CARRY(CB16_dffe5a[2] & (!BB8L4 # !CB15_dffe5a[2]) # !CB16_dffe5a[2] & !CB15_dffe5a[2] & !BB8L4);


--BB8L8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~337
BB8L8 = CARRY(CB16_dffe5a[3] & CB15_dffe5a[3] & !BB8L6 # !CB16_dffe5a[3] & (CB15_dffe5a[3] # !BB8L6));


--BB8L10 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~339
BB8L10 = CARRY(CB16_dffe5a[4] & (!BB8L8 # !CB15_dffe5a[4]) # !CB16_dffe5a[4] & !CB15_dffe5a[4] & !BB8L8);


--BB8L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~341
BB8L12 = CARRY(CB16_dffe5a[5] & CB15_dffe5a[5] & !BB8L10 # !CB16_dffe5a[5] & (CB15_dffe5a[5] # !BB8L10));


--BB8L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~343
BB8L14 = CARRY(CB16_dffe5a[6] & (!BB8L12 # !CB15_dffe5a[6]) # !CB16_dffe5a[6] & !CB15_dffe5a[6] & !BB8L12);


--BB8L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~345
BB8L16 = CARRY(CB16_dffe5a[7] & CB15_dffe5a[7] & !BB8L14 # !CB16_dffe5a[7] & (CB15_dffe5a[7] # !BB8L14));


--BB8L17 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~346
BB8L17 = CB15_dffe5a[8] $ X4_delayed_wrptr_g[8] $ BB8L16;


--BB8L19 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~348
BB8L19 = BB3L17 & BB8L17 & !BB6L17 & !BB1L17;


--G1L255 is Sdram_Control_4Port:u6|mRD~732
G1L255 = G1_RD_MASK[1] # G1_RD_MASK[0] # G1_mWR # !C1_oRST_0;


--G1_WR_MASK[1] is Sdram_Control_4Port:u6|WR_MASK[1]
G1_WR_MASK[1] = DFFEAS(G1L117, KB1__clk0,  ,  , G1L115,  ,  ,  ,  );


--G1_WR_MASK[0] is Sdram_Control_4Port:u6|WR_MASK[0]
G1_WR_MASK[0] = DFFEAS(G1L118, KB1__clk0,  ,  , G1L115,  ,  ,  ,  );


--G1L256 is Sdram_Control_4Port:u6|mRD~733
G1L256 = G1_mRD # G1_WR_MASK[1] # G1_WR_MASK[0];


--G1L257 is Sdram_Control_4Port:u6|mRD~734
G1L257 = BB8L19 # G1L255 # G1L256;


--G1L258 is Sdram_Control_4Port:u6|mRD~735
G1L258 = !G1_ST[0] & !G1_ST[1] & !G1L257 & G1L20;


--G1L259 is Sdram_Control_4Port:u6|mRD~736
G1L259 = G1L258 # G1_mRD_DONE;


--EB4_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity_ff
EB4_parity_ff = DFFEAS(EB4_parity, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB4_parity is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity
EB4_parity = X4_valid_wrreq & !EB4_parity_ff # !X4_valid_wrreq & EB4_parity_ff & VCC;

--EB4L31 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity~COUT
EB4L31 = CARRY(X4_valid_wrreq & !EB4_parity_ff);


--EB4_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0
EB4_countera0 = X4_valid_wrreq & (EB4L31 $ (GND # !EB4_counter_ffa[0])) # !X4_valid_wrreq & (EB4_counter_ffa[0] # GND);

--EB4L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0~COUT
EB4L12 = CARRY(!EB4L31 # !X4_valid_wrreq);


--EB4_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1
EB4_countera1 = EB4L12 & (EB4_power_modified_counter_values[1] & VCC) # !EB4L12 & (EB4_counter_ffa[0] $ (!EB4_power_modified_counter_values[1] & VCC));

--EB4L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1~COUT
EB4L14 = CARRY(EB4_counter_ffa[0] & !EB4L12);


--EB4_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2
EB4_countera2 = EB4L14 & (EB4_power_modified_counter_values[1] $ (EB4_power_modified_counter_values[2] & VCC)) # !EB4L14 & (EB4_power_modified_counter_values[2] # GND);

--EB4L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2~COUT
EB4L16 = CARRY(EB4_power_modified_counter_values[1] # !EB4L14);


--EB4_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3
EB4_countera3 = EB4L16 & (EB4_power_modified_counter_values[3] & VCC) # !EB4L16 & (EB4_power_modified_counter_values[2] $ (EB4_power_modified_counter_values[3] # GND));

--EB4L18 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3~COUT
EB4L18 = CARRY(!EB4_power_modified_counter_values[2] & !EB4L16);


--EB4_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4
EB4_countera4 = EB4L18 & (EB4_power_modified_counter_values[3] $ (EB4_power_modified_counter_values[4] & VCC)) # !EB4L18 & (EB4_power_modified_counter_values[4] # GND);

--EB4L20 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4~COUT
EB4L20 = CARRY(EB4_power_modified_counter_values[3] # !EB4L18);


--EB4_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5
EB4_countera5 = EB4L20 & (EB4_power_modified_counter_values[5] & VCC) # !EB4L20 & (EB4_power_modified_counter_values[4] $ (EB4_power_modified_counter_values[5] # GND));

--EB4L22 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5~COUT
EB4L22 = CARRY(!EB4_power_modified_counter_values[4] & !EB4L20);


--EB4_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6
EB4_countera6 = EB4L22 & (EB4_power_modified_counter_values[5] $ (EB4_power_modified_counter_values[6] & VCC)) # !EB4L22 & (EB4_power_modified_counter_values[6] # GND);

--EB4L24 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6~COUT
EB4L24 = CARRY(EB4_power_modified_counter_values[5] # !EB4L22);


--EB4_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7
EB4_countera7 = EB4L24 & (EB4_power_modified_counter_values[7] & VCC) # !EB4L24 & (EB4_power_modified_counter_values[6] $ (EB4_power_modified_counter_values[7] # GND));

--EB4L26 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7~COUT
EB4L26 = CARRY(!EB4_power_modified_counter_values[6] & !EB4L24);


--EB4_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera8
EB4_countera8 = EB4_power_modified_counter_values[8] $ EB4L26;


--C1L77 is Reset_Delay:u2|oRST_0~31
C1L77 = C1_oRST_0 # C1_Cont[21] # C1_Cont[20] & C1L74;


--Z4_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity_ff
Z4_parity_ff = DFFEAS(Z4_parity, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z4_parity is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity
Z4_parity = X4_rdcnt_addr_ena & (Z4_parity_ff $ VCC) # !X4_rdcnt_addr_ena & Z4_parity_ff & VCC;

--Z4L31 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity~COUT
Z4L31 = CARRY(X4_rdcnt_addr_ena & Z4_parity_ff);


--Z4_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0
Z4_countera0 = X4_rdcnt_addr_ena & (Z4L31 $ (GND # !Z4_power_modified_counter_values[0])) # !X4_rdcnt_addr_ena & (Z4_power_modified_counter_values[0] # GND);

--Z4L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0~COUT
Z4L12 = CARRY(!Z4L31 # !X4_rdcnt_addr_ena);


--Z4_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1
Z4_countera1 = Z4L12 & (Z4_power_modified_counter_values[1] & VCC) # !Z4L12 & (Z4_power_modified_counter_values[0] $ (Z4_power_modified_counter_values[1] # GND));

--Z4L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1~COUT
Z4L14 = CARRY(!Z4_power_modified_counter_values[0] & !Z4L12);


--Z4_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2
Z4_countera2 = Z4L14 & (Z4_power_modified_counter_values[1] $ (Z4_power_modified_counter_values[2] & VCC)) # !Z4L14 & (Z4_power_modified_counter_values[2] # GND);

--Z4L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2~COUT
Z4L16 = CARRY(Z4_power_modified_counter_values[1] # !Z4L14);


--Z4_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3
Z4_countera3 = Z4L16 & (Z4_power_modified_counter_values[3] & VCC) # !Z4L16 & (Z4_power_modified_counter_values[2] $ (Z4_power_modified_counter_values[3] # GND));

--Z4L18 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3~COUT
Z4L18 = CARRY(!Z4_power_modified_counter_values[2] & !Z4L16);


--Z4_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4
Z4_countera4 = Z4L18 & (Z4_power_modified_counter_values[3] $ (Z4_power_modified_counter_values[4] & VCC)) # !Z4L18 & (Z4_power_modified_counter_values[4] # GND);

--Z4L20 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4~COUT
Z4L20 = CARRY(Z4_power_modified_counter_values[3] # !Z4L18);


--Z4_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5
Z4_countera5 = Z4L20 & (Z4_power_modified_counter_values[5] & VCC) # !Z4L20 & (Z4_power_modified_counter_values[4] $ (Z4_power_modified_counter_values[5] # GND));

--Z4L22 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5~COUT
Z4L22 = CARRY(!Z4_power_modified_counter_values[4] & !Z4L20);


--Z4_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6
Z4_countera6 = Z4L22 & (Z4_power_modified_counter_values[5] $ (Z4_power_modified_counter_values[6] & VCC)) # !Z4L22 & (Z4_power_modified_counter_values[6] # GND);

--Z4L24 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6~COUT
Z4L24 = CARRY(Z4_power_modified_counter_values[5] # !Z4L22);


--Z4_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7
Z4_countera7 = Z4L24 & (Z4_power_modified_counter_values[7] & VCC) # !Z4L24 & (Z4_power_modified_counter_values[6] $ (Z4_power_modified_counter_values[7] # GND));

--Z4L26 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7~COUT
Z4L26 = CARRY(!Z4_power_modified_counter_values[6] & !Z4L24);


--Z4_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera8
Z4_countera8 = Z4_power_modified_counter_values[8] $ Z4L26;


--X3_delayed_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7]
X3_delayed_wrptr_g[7] = DFFEAS(X3_wrptr_g[7], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[2]
X3_delayed_wrptr_g[2] = DFFEAS(X3_wrptr_g[2], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0]
X3_delayed_wrptr_g[0] = DFFEAS(X3_wrptr_g[0], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[1]
X3_delayed_wrptr_g[1] = DFFEAS(X3_wrptr_g[1], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6]
X3_delayed_wrptr_g[6] = DFFEAS(X3_wrptr_g[6], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3]
X3_delayed_wrptr_g[3] = DFFEAS(X3_wrptr_g[3], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[4]
X3_delayed_wrptr_g[4] = DFFEAS(X3_wrptr_g[4], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5]
X3_delayed_wrptr_g[5] = DFFEAS(X3_wrptr_g[5], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--G1L55 is Sdram_Control_4Port:u6|RD_MASK~99
G1L55 = BB6L17 & BB3L17 & !BB1L17 & !G1_mRD_DONE;


--EB3_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity_ff
EB3_parity_ff = DFFEAS(EB3_parity, KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB3_parity is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity
EB3_parity = X3_valid_wrreq & !EB3_parity_ff # !X3_valid_wrreq & EB3_parity_ff & VCC;

--EB3L31 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity~COUT
EB3L31 = CARRY(X3_valid_wrreq & !EB3_parity_ff);


--EB3_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0
EB3_countera0 = X3_valid_wrreq & (EB3L31 $ (GND # !EB3_counter_ffa[0])) # !X3_valid_wrreq & (EB3_counter_ffa[0] # GND);

--EB3L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0~COUT
EB3L12 = CARRY(!EB3L31 # !X3_valid_wrreq);


--EB3_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1
EB3_countera1 = EB3L12 & (EB3_power_modified_counter_values[1] & VCC) # !EB3L12 & (EB3_counter_ffa[0] $ (!EB3_power_modified_counter_values[1] & VCC));

--EB3L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1~COUT
EB3L14 = CARRY(EB3_counter_ffa[0] & !EB3L12);


--EB3_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2
EB3_countera2 = EB3L14 & (EB3_power_modified_counter_values[1] $ (EB3_power_modified_counter_values[2] & VCC)) # !EB3L14 & (EB3_power_modified_counter_values[2] # GND);

--EB3L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2~COUT
EB3L16 = CARRY(EB3_power_modified_counter_values[1] # !EB3L14);


--EB3_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3
EB3_countera3 = EB3L16 & (EB3_power_modified_counter_values[3] & VCC) # !EB3L16 & (EB3_power_modified_counter_values[2] $ (EB3_power_modified_counter_values[3] # GND));

--EB3L18 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3~COUT
EB3L18 = CARRY(!EB3_power_modified_counter_values[2] & !EB3L16);


--EB3_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4
EB3_countera4 = EB3L18 & (EB3_power_modified_counter_values[3] $ (EB3_power_modified_counter_values[4] & VCC)) # !EB3L18 & (EB3_power_modified_counter_values[4] # GND);

--EB3L20 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4~COUT
EB3L20 = CARRY(EB3_power_modified_counter_values[3] # !EB3L18);


--EB3_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5
EB3_countera5 = EB3L20 & (EB3_power_modified_counter_values[5] & VCC) # !EB3L20 & (EB3_power_modified_counter_values[4] $ (EB3_power_modified_counter_values[5] # GND));

--EB3L22 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5~COUT
EB3L22 = CARRY(!EB3_power_modified_counter_values[4] & !EB3L20);


--EB3_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6
EB3_countera6 = EB3L22 & (EB3_power_modified_counter_values[5] $ (EB3_power_modified_counter_values[6] & VCC)) # !EB3L22 & (EB3_power_modified_counter_values[6] # GND);

--EB3L24 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6~COUT
EB3L24 = CARRY(EB3_power_modified_counter_values[5] # !EB3L22);


--EB3_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7
EB3_countera7 = EB3L24 & (EB3_power_modified_counter_values[7] & VCC) # !EB3L24 & (EB3_power_modified_counter_values[6] $ (EB3_power_modified_counter_values[7] # GND));

--EB3L26 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7~COUT
EB3L26 = CARRY(!EB3_power_modified_counter_values[6] & !EB3L24);


--EB3_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera8
EB3_countera8 = EB3_power_modified_counter_values[8] $ EB3L26;


--Z3_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity_ff
Z3_parity_ff = DFFEAS(Z3_parity, CCD_MCLK, X4_rdaclr,  ,  ,  ,  ,  ,  );


--Z3_parity is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity
Z3_parity = X3_rdcnt_addr_ena & (Z3_parity_ff $ VCC) # !X3_rdcnt_addr_ena & Z3_parity_ff & VCC;

--Z3L31 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity~COUT
Z3L31 = CARRY(X3_rdcnt_addr_ena & Z3_parity_ff);


--Z3_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0
Z3_countera0 = X3_rdcnt_addr_ena & (Z3L31 $ (GND # !Z3_power_modified_counter_values[0])) # !X3_rdcnt_addr_ena & (Z3_power_modified_counter_values[0] # GND);

--Z3L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0~COUT
Z3L12 = CARRY(!Z3L31 # !X3_rdcnt_addr_ena);


--Z3_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1
Z3_countera1 = Z3L12 & (Z3_power_modified_counter_values[1] & VCC) # !Z3L12 & (Z3_power_modified_counter_values[0] $ (Z3_power_modified_counter_values[1] # GND));

--Z3L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1~COUT
Z3L14 = CARRY(!Z3_power_modified_counter_values[0] & !Z3L12);


--Z3_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2
Z3_countera2 = Z3L14 & (Z3_power_modified_counter_values[1] $ (Z3_power_modified_counter_values[2] & VCC)) # !Z3L14 & (Z3_power_modified_counter_values[2] # GND);

--Z3L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2~COUT
Z3L16 = CARRY(Z3_power_modified_counter_values[1] # !Z3L14);


--Z3_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3
Z3_countera3 = Z3L16 & (Z3_power_modified_counter_values[3] & VCC) # !Z3L16 & (Z3_power_modified_counter_values[2] $ (Z3_power_modified_counter_values[3] # GND));

--Z3L18 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3~COUT
Z3L18 = CARRY(!Z3_power_modified_counter_values[2] & !Z3L16);


--Z3_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4
Z3_countera4 = Z3L18 & (Z3_power_modified_counter_values[3] $ (Z3_power_modified_counter_values[4] & VCC)) # !Z3L18 & (Z3_power_modified_counter_values[4] # GND);

--Z3L20 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4~COUT
Z3L20 = CARRY(Z3_power_modified_counter_values[3] # !Z3L18);


--Z3_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5
Z3_countera5 = Z3L20 & (Z3_power_modified_counter_values[5] & VCC) # !Z3L20 & (Z3_power_modified_counter_values[4] $ (Z3_power_modified_counter_values[5] # GND));

--Z3L22 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5~COUT
Z3L22 = CARRY(!Z3_power_modified_counter_values[4] & !Z3L20);


--Z3_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6
Z3_countera6 = Z3L22 & (Z3_power_modified_counter_values[5] $ (Z3_power_modified_counter_values[6] & VCC)) # !Z3L22 & (Z3_power_modified_counter_values[6] # GND);

--Z3L24 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6~COUT
Z3L24 = CARRY(Z3_power_modified_counter_values[5] # !Z3L22);


--Z3_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7
Z3_countera7 = Z3L24 & (Z3_power_modified_counter_values[7] & VCC) # !Z3L24 & (Z3_power_modified_counter_values[6] $ (Z3_power_modified_counter_values[7] # GND));

--Z3L26 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7~COUT
Z3L26 = CARRY(!Z3_power_modified_counter_values[6] & !Z3L24);


--Z3_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera8
Z3_countera8 = Z3_power_modified_counter_values[8] $ Z3L26;


--GB1_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[0]_PORT_A_data_in = VCC;
GB1_q_a[0]_PORT_A_data_in_reg = DFFE(GB1_q_a[0]_PORT_A_data_in, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_data_in = PB3_q_b[0];
GB1_q_a[0]_PORT_B_data_in_reg = DFFE(GB1_q_a[0]_PORT_B_data_in, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[0]_PORT_B_address_reg = DFFE(GB1_q_a[0]_PORT_B_address, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_write_enable = GND;
GB1_q_a[0]_PORT_A_write_enable_reg = DFFE(GB1_q_a[0]_PORT_A_write_enable, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[0]_PORT_B_write_enable_reg = DFFE(GB1_q_a[0]_PORT_B_write_enable, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_clock_0 = KB1__clk0;
GB1_q_a[0]_clock_1 = CCD_PIXCLK;
GB1_q_a[0]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[0]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[0]_clear_1 = !C1_oRST_0;
GB1_q_a[0]_PORT_A_data_out = MEMORY(GB1_q_a[0]_PORT_A_data_in_reg, GB1_q_a[0]_PORT_B_data_in_reg, GB1_q_a[0]_PORT_A_address_reg, GB1_q_a[0]_PORT_B_address_reg, GB1_q_a[0]_PORT_A_write_enable_reg, GB1_q_a[0]_PORT_B_write_enable_reg, , , GB1_q_a[0]_clock_0, GB1_q_a[0]_clock_1, GB1_q_a[0]_clock_enable_0, GB1_q_a[0]_clock_enable_1, , GB1_q_a[0]_clear_1);
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, GB1_q_a[0]_clear_1, , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0] = GB1_q_a[0]_PORT_A_data_out_reg[0];


--GB2_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[0]_PORT_A_data_in = VCC;
GB2_q_a[0]_PORT_A_data_in_reg = DFFE(GB2_q_a[0]_PORT_A_data_in, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_data_in = PB1_q_b[0];
GB2_q_a[0]_PORT_B_data_in_reg = DFFE(GB2_q_a[0]_PORT_B_data_in, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[0]_PORT_A_address_reg = DFFE(GB2_q_a[0]_PORT_A_address, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[0]_PORT_B_address_reg = DFFE(GB2_q_a[0]_PORT_B_address, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_write_enable = GND;
GB2_q_a[0]_PORT_A_write_enable_reg = DFFE(GB2_q_a[0]_PORT_A_write_enable, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[0]_PORT_B_write_enable_reg = DFFE(GB2_q_a[0]_PORT_B_write_enable, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_clock_0 = KB1__clk0;
GB2_q_a[0]_clock_1 = CCD_PIXCLK;
GB2_q_a[0]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[0]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[0]_clear_1 = !C1_oRST_0;
GB2_q_a[0]_PORT_A_data_out = MEMORY(GB2_q_a[0]_PORT_A_data_in_reg, GB2_q_a[0]_PORT_B_data_in_reg, GB2_q_a[0]_PORT_A_address_reg, GB2_q_a[0]_PORT_B_address_reg, GB2_q_a[0]_PORT_A_write_enable_reg, GB2_q_a[0]_PORT_B_write_enable_reg, , , GB2_q_a[0]_clock_0, GB2_q_a[0]_clock_1, GB2_q_a[0]_clock_enable_0, GB2_q_a[0]_clock_enable_1, , GB2_q_a[0]_clear_1);
GB2_q_a[0]_PORT_A_data_out_reg = DFFE(GB2_q_a[0]_PORT_A_data_out, GB2_q_a[0]_clock_0, GB2_q_a[0]_clear_1, , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0] = GB2_q_a[0]_PORT_A_data_out_reg[0];


--G1L220 is Sdram_Control_4Port:u6|mDATAIN[0]~160
G1L220 = G1_WR_MASK[0] & GB1_q_a[0] # !G1_WR_MASK[0] & (GB2_q_a[0]);


--R1_OE is Sdram_Control_4Port:u6|command:command1|OE
R1_OE = DFFEAS(R1_oe4, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--GB1_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[1]_PORT_A_data_in = VCC;
GB1_q_a[1]_PORT_A_data_in_reg = DFFE(GB1_q_a[1]_PORT_A_data_in, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_data_in = PB3_q_b[1];
GB1_q_a[1]_PORT_B_data_in_reg = DFFE(GB1_q_a[1]_PORT_B_data_in, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[1]_PORT_B_address_reg = DFFE(GB1_q_a[1]_PORT_B_address, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_write_enable = GND;
GB1_q_a[1]_PORT_A_write_enable_reg = DFFE(GB1_q_a[1]_PORT_A_write_enable, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[1]_PORT_B_write_enable_reg = DFFE(GB1_q_a[1]_PORT_B_write_enable, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_clock_0 = KB1__clk0;
GB1_q_a[1]_clock_1 = CCD_PIXCLK;
GB1_q_a[1]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[1]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[1]_clear_1 = !C1_oRST_0;
GB1_q_a[1]_PORT_A_data_out = MEMORY(GB1_q_a[1]_PORT_A_data_in_reg, GB1_q_a[1]_PORT_B_data_in_reg, GB1_q_a[1]_PORT_A_address_reg, GB1_q_a[1]_PORT_B_address_reg, GB1_q_a[1]_PORT_A_write_enable_reg, GB1_q_a[1]_PORT_B_write_enable_reg, , , GB1_q_a[1]_clock_0, GB1_q_a[1]_clock_1, GB1_q_a[1]_clock_enable_0, GB1_q_a[1]_clock_enable_1, , GB1_q_a[1]_clear_1);
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, GB1_q_a[1]_clear_1, , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1] = GB1_q_a[1]_PORT_A_data_out_reg[0];


--GB2_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[1]_PORT_A_data_in = VCC;
GB2_q_a[1]_PORT_A_data_in_reg = DFFE(GB2_q_a[1]_PORT_A_data_in, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_data_in = PB1_q_b[1];
GB2_q_a[1]_PORT_B_data_in_reg = DFFE(GB2_q_a[1]_PORT_B_data_in, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[1]_PORT_A_address_reg = DFFE(GB2_q_a[1]_PORT_A_address, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[1]_PORT_B_address_reg = DFFE(GB2_q_a[1]_PORT_B_address, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_write_enable = GND;
GB2_q_a[1]_PORT_A_write_enable_reg = DFFE(GB2_q_a[1]_PORT_A_write_enable, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[1]_PORT_B_write_enable_reg = DFFE(GB2_q_a[1]_PORT_B_write_enable, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_clock_0 = KB1__clk0;
GB2_q_a[1]_clock_1 = CCD_PIXCLK;
GB2_q_a[1]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[1]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[1]_clear_1 = !C1_oRST_0;
GB2_q_a[1]_PORT_A_data_out = MEMORY(GB2_q_a[1]_PORT_A_data_in_reg, GB2_q_a[1]_PORT_B_data_in_reg, GB2_q_a[1]_PORT_A_address_reg, GB2_q_a[1]_PORT_B_address_reg, GB2_q_a[1]_PORT_A_write_enable_reg, GB2_q_a[1]_PORT_B_write_enable_reg, , , GB2_q_a[1]_clock_0, GB2_q_a[1]_clock_1, GB2_q_a[1]_clock_enable_0, GB2_q_a[1]_clock_enable_1, , GB2_q_a[1]_clear_1);
GB2_q_a[1]_PORT_A_data_out_reg = DFFE(GB2_q_a[1]_PORT_A_data_out, GB2_q_a[1]_clock_0, GB2_q_a[1]_clear_1, , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1] = GB2_q_a[1]_PORT_A_data_out_reg[0];


--G1L221 is Sdram_Control_4Port:u6|mDATAIN[1]~161
G1L221 = G1_WR_MASK[0] & GB1_q_a[1] # !G1_WR_MASK[0] & (GB2_q_a[1]);


--GB1_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[2]_PORT_A_data_in = VCC;
GB1_q_a[2]_PORT_A_data_in_reg = DFFE(GB1_q_a[2]_PORT_A_data_in, GB1_q_a[2]_clock_0, , , GB1_q_a[2]_clock_enable_0);
GB1_q_a[2]_PORT_B_data_in = PB3_q_b[2];
GB1_q_a[2]_PORT_B_data_in_reg = DFFE(GB1_q_a[2]_PORT_B_data_in, GB1_q_a[2]_clock_1, , , GB1_q_a[2]_clock_enable_1);
GB1_q_a[2]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[2]_PORT_A_address_reg = DFFE(GB1_q_a[2]_PORT_A_address, GB1_q_a[2]_clock_0, , , GB1_q_a[2]_clock_enable_0);
GB1_q_a[2]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[2]_PORT_B_address_reg = DFFE(GB1_q_a[2]_PORT_B_address, GB1_q_a[2]_clock_1, , , GB1_q_a[2]_clock_enable_1);
GB1_q_a[2]_PORT_A_write_enable = GND;
GB1_q_a[2]_PORT_A_write_enable_reg = DFFE(GB1_q_a[2]_PORT_A_write_enable, GB1_q_a[2]_clock_0, , , GB1_q_a[2]_clock_enable_0);
GB1_q_a[2]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[2]_PORT_B_write_enable_reg = DFFE(GB1_q_a[2]_PORT_B_write_enable, GB1_q_a[2]_clock_1, , , GB1_q_a[2]_clock_enable_1);
GB1_q_a[2]_clock_0 = KB1__clk0;
GB1_q_a[2]_clock_1 = CCD_PIXCLK;
GB1_q_a[2]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[2]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[2]_clear_1 = !C1_oRST_0;
GB1_q_a[2]_PORT_A_data_out = MEMORY(GB1_q_a[2]_PORT_A_data_in_reg, GB1_q_a[2]_PORT_B_data_in_reg, GB1_q_a[2]_PORT_A_address_reg, GB1_q_a[2]_PORT_B_address_reg, GB1_q_a[2]_PORT_A_write_enable_reg, GB1_q_a[2]_PORT_B_write_enable_reg, , , GB1_q_a[2]_clock_0, GB1_q_a[2]_clock_1, GB1_q_a[2]_clock_enable_0, GB1_q_a[2]_clock_enable_1, , GB1_q_a[2]_clear_1);
GB1_q_a[2]_PORT_A_data_out_reg = DFFE(GB1_q_a[2]_PORT_A_data_out, GB1_q_a[2]_clock_0, GB1_q_a[2]_clear_1, , GB1_q_a[2]_clock_enable_0);
GB1_q_a[2] = GB1_q_a[2]_PORT_A_data_out_reg[0];


--GB2_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[2]_PORT_A_data_in = VCC;
GB2_q_a[2]_PORT_A_data_in_reg = DFFE(GB2_q_a[2]_PORT_A_data_in, GB2_q_a[2]_clock_0, , , GB2_q_a[2]_clock_enable_0);
GB2_q_a[2]_PORT_B_data_in = PB1_q_b[2];
GB2_q_a[2]_PORT_B_data_in_reg = DFFE(GB2_q_a[2]_PORT_B_data_in, GB2_q_a[2]_clock_1, , , GB2_q_a[2]_clock_enable_1);
GB2_q_a[2]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[2]_PORT_A_address_reg = DFFE(GB2_q_a[2]_PORT_A_address, GB2_q_a[2]_clock_0, , , GB2_q_a[2]_clock_enable_0);
GB2_q_a[2]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[2]_PORT_B_address_reg = DFFE(GB2_q_a[2]_PORT_B_address, GB2_q_a[2]_clock_1, , , GB2_q_a[2]_clock_enable_1);
GB2_q_a[2]_PORT_A_write_enable = GND;
GB2_q_a[2]_PORT_A_write_enable_reg = DFFE(GB2_q_a[2]_PORT_A_write_enable, GB2_q_a[2]_clock_0, , , GB2_q_a[2]_clock_enable_0);
GB2_q_a[2]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[2]_PORT_B_write_enable_reg = DFFE(GB2_q_a[2]_PORT_B_write_enable, GB2_q_a[2]_clock_1, , , GB2_q_a[2]_clock_enable_1);
GB2_q_a[2]_clock_0 = KB1__clk0;
GB2_q_a[2]_clock_1 = CCD_PIXCLK;
GB2_q_a[2]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[2]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[2]_clear_1 = !C1_oRST_0;
GB2_q_a[2]_PORT_A_data_out = MEMORY(GB2_q_a[2]_PORT_A_data_in_reg, GB2_q_a[2]_PORT_B_data_in_reg, GB2_q_a[2]_PORT_A_address_reg, GB2_q_a[2]_PORT_B_address_reg, GB2_q_a[2]_PORT_A_write_enable_reg, GB2_q_a[2]_PORT_B_write_enable_reg, , , GB2_q_a[2]_clock_0, GB2_q_a[2]_clock_1, GB2_q_a[2]_clock_enable_0, GB2_q_a[2]_clock_enable_1, , GB2_q_a[2]_clear_1);
GB2_q_a[2]_PORT_A_data_out_reg = DFFE(GB2_q_a[2]_PORT_A_data_out, GB2_q_a[2]_clock_0, GB2_q_a[2]_clear_1, , GB2_q_a[2]_clock_enable_0);
GB2_q_a[2] = GB2_q_a[2]_PORT_A_data_out_reg[0];


--G1L222 is Sdram_Control_4Port:u6|mDATAIN[2]~162
G1L222 = G1_WR_MASK[0] & GB1_q_a[2] # !G1_WR_MASK[0] & (GB2_q_a[2]);


--GB1_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[3]_PORT_A_data_in = VCC;
GB1_q_a[3]_PORT_A_data_in_reg = DFFE(GB1_q_a[3]_PORT_A_data_in, GB1_q_a[3]_clock_0, , , GB1_q_a[3]_clock_enable_0);
GB1_q_a[3]_PORT_B_data_in = PB3_q_b[3];
GB1_q_a[3]_PORT_B_data_in_reg = DFFE(GB1_q_a[3]_PORT_B_data_in, GB1_q_a[3]_clock_1, , , GB1_q_a[3]_clock_enable_1);
GB1_q_a[3]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[3]_PORT_A_address_reg = DFFE(GB1_q_a[3]_PORT_A_address, GB1_q_a[3]_clock_0, , , GB1_q_a[3]_clock_enable_0);
GB1_q_a[3]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[3]_PORT_B_address_reg = DFFE(GB1_q_a[3]_PORT_B_address, GB1_q_a[3]_clock_1, , , GB1_q_a[3]_clock_enable_1);
GB1_q_a[3]_PORT_A_write_enable = GND;
GB1_q_a[3]_PORT_A_write_enable_reg = DFFE(GB1_q_a[3]_PORT_A_write_enable, GB1_q_a[3]_clock_0, , , GB1_q_a[3]_clock_enable_0);
GB1_q_a[3]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[3]_PORT_B_write_enable_reg = DFFE(GB1_q_a[3]_PORT_B_write_enable, GB1_q_a[3]_clock_1, , , GB1_q_a[3]_clock_enable_1);
GB1_q_a[3]_clock_0 = KB1__clk0;
GB1_q_a[3]_clock_1 = CCD_PIXCLK;
GB1_q_a[3]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[3]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[3]_clear_1 = !C1_oRST_0;
GB1_q_a[3]_PORT_A_data_out = MEMORY(GB1_q_a[3]_PORT_A_data_in_reg, GB1_q_a[3]_PORT_B_data_in_reg, GB1_q_a[3]_PORT_A_address_reg, GB1_q_a[3]_PORT_B_address_reg, GB1_q_a[3]_PORT_A_write_enable_reg, GB1_q_a[3]_PORT_B_write_enable_reg, , , GB1_q_a[3]_clock_0, GB1_q_a[3]_clock_1, GB1_q_a[3]_clock_enable_0, GB1_q_a[3]_clock_enable_1, , GB1_q_a[3]_clear_1);
GB1_q_a[3]_PORT_A_data_out_reg = DFFE(GB1_q_a[3]_PORT_A_data_out, GB1_q_a[3]_clock_0, GB1_q_a[3]_clear_1, , GB1_q_a[3]_clock_enable_0);
GB1_q_a[3] = GB1_q_a[3]_PORT_A_data_out_reg[0];


--GB2_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[3]_PORT_A_data_in = VCC;
GB2_q_a[3]_PORT_A_data_in_reg = DFFE(GB2_q_a[3]_PORT_A_data_in, GB2_q_a[3]_clock_0, , , GB2_q_a[3]_clock_enable_0);
GB2_q_a[3]_PORT_B_data_in = PB1_q_b[3];
GB2_q_a[3]_PORT_B_data_in_reg = DFFE(GB2_q_a[3]_PORT_B_data_in, GB2_q_a[3]_clock_1, , , GB2_q_a[3]_clock_enable_1);
GB2_q_a[3]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[3]_PORT_A_address_reg = DFFE(GB2_q_a[3]_PORT_A_address, GB2_q_a[3]_clock_0, , , GB2_q_a[3]_clock_enable_0);
GB2_q_a[3]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[3]_PORT_B_address_reg = DFFE(GB2_q_a[3]_PORT_B_address, GB2_q_a[3]_clock_1, , , GB2_q_a[3]_clock_enable_1);
GB2_q_a[3]_PORT_A_write_enable = GND;
GB2_q_a[3]_PORT_A_write_enable_reg = DFFE(GB2_q_a[3]_PORT_A_write_enable, GB2_q_a[3]_clock_0, , , GB2_q_a[3]_clock_enable_0);
GB2_q_a[3]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[3]_PORT_B_write_enable_reg = DFFE(GB2_q_a[3]_PORT_B_write_enable, GB2_q_a[3]_clock_1, , , GB2_q_a[3]_clock_enable_1);
GB2_q_a[3]_clock_0 = KB1__clk0;
GB2_q_a[3]_clock_1 = CCD_PIXCLK;
GB2_q_a[3]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[3]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[3]_clear_1 = !C1_oRST_0;
GB2_q_a[3]_PORT_A_data_out = MEMORY(GB2_q_a[3]_PORT_A_data_in_reg, GB2_q_a[3]_PORT_B_data_in_reg, GB2_q_a[3]_PORT_A_address_reg, GB2_q_a[3]_PORT_B_address_reg, GB2_q_a[3]_PORT_A_write_enable_reg, GB2_q_a[3]_PORT_B_write_enable_reg, , , GB2_q_a[3]_clock_0, GB2_q_a[3]_clock_1, GB2_q_a[3]_clock_enable_0, GB2_q_a[3]_clock_enable_1, , GB2_q_a[3]_clear_1);
GB2_q_a[3]_PORT_A_data_out_reg = DFFE(GB2_q_a[3]_PORT_A_data_out, GB2_q_a[3]_clock_0, GB2_q_a[3]_clear_1, , GB2_q_a[3]_clock_enable_0);
GB2_q_a[3] = GB2_q_a[3]_PORT_A_data_out_reg[0];


--G1L223 is Sdram_Control_4Port:u6|mDATAIN[3]~163
G1L223 = G1_WR_MASK[0] & GB1_q_a[3] # !G1_WR_MASK[0] & (GB2_q_a[3]);


--GB1_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[4]_PORT_A_data_in = VCC;
GB1_q_a[4]_PORT_A_data_in_reg = DFFE(GB1_q_a[4]_PORT_A_data_in, GB1_q_a[4]_clock_0, , , GB1_q_a[4]_clock_enable_0);
GB1_q_a[4]_PORT_B_data_in = PB3_q_b[4];
GB1_q_a[4]_PORT_B_data_in_reg = DFFE(GB1_q_a[4]_PORT_B_data_in, GB1_q_a[4]_clock_1, , , GB1_q_a[4]_clock_enable_1);
GB1_q_a[4]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[4]_PORT_A_address_reg = DFFE(GB1_q_a[4]_PORT_A_address, GB1_q_a[4]_clock_0, , , GB1_q_a[4]_clock_enable_0);
GB1_q_a[4]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[4]_PORT_B_address_reg = DFFE(GB1_q_a[4]_PORT_B_address, GB1_q_a[4]_clock_1, , , GB1_q_a[4]_clock_enable_1);
GB1_q_a[4]_PORT_A_write_enable = GND;
GB1_q_a[4]_PORT_A_write_enable_reg = DFFE(GB1_q_a[4]_PORT_A_write_enable, GB1_q_a[4]_clock_0, , , GB1_q_a[4]_clock_enable_0);
GB1_q_a[4]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[4]_PORT_B_write_enable_reg = DFFE(GB1_q_a[4]_PORT_B_write_enable, GB1_q_a[4]_clock_1, , , GB1_q_a[4]_clock_enable_1);
GB1_q_a[4]_clock_0 = KB1__clk0;
GB1_q_a[4]_clock_1 = CCD_PIXCLK;
GB1_q_a[4]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[4]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[4]_clear_1 = !C1_oRST_0;
GB1_q_a[4]_PORT_A_data_out = MEMORY(GB1_q_a[4]_PORT_A_data_in_reg, GB1_q_a[4]_PORT_B_data_in_reg, GB1_q_a[4]_PORT_A_address_reg, GB1_q_a[4]_PORT_B_address_reg, GB1_q_a[4]_PORT_A_write_enable_reg, GB1_q_a[4]_PORT_B_write_enable_reg, , , GB1_q_a[4]_clock_0, GB1_q_a[4]_clock_1, GB1_q_a[4]_clock_enable_0, GB1_q_a[4]_clock_enable_1, , GB1_q_a[4]_clear_1);
GB1_q_a[4]_PORT_A_data_out_reg = DFFE(GB1_q_a[4]_PORT_A_data_out, GB1_q_a[4]_clock_0, GB1_q_a[4]_clear_1, , GB1_q_a[4]_clock_enable_0);
GB1_q_a[4] = GB1_q_a[4]_PORT_A_data_out_reg[0];


--GB2_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[4]_PORT_A_data_in = VCC;
GB2_q_a[4]_PORT_A_data_in_reg = DFFE(GB2_q_a[4]_PORT_A_data_in, GB2_q_a[4]_clock_0, , , GB2_q_a[4]_clock_enable_0);
GB2_q_a[4]_PORT_B_data_in = PB1_q_b[4];
GB2_q_a[4]_PORT_B_data_in_reg = DFFE(GB2_q_a[4]_PORT_B_data_in, GB2_q_a[4]_clock_1, , , GB2_q_a[4]_clock_enable_1);
GB2_q_a[4]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[4]_PORT_A_address_reg = DFFE(GB2_q_a[4]_PORT_A_address, GB2_q_a[4]_clock_0, , , GB2_q_a[4]_clock_enable_0);
GB2_q_a[4]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[4]_PORT_B_address_reg = DFFE(GB2_q_a[4]_PORT_B_address, GB2_q_a[4]_clock_1, , , GB2_q_a[4]_clock_enable_1);
GB2_q_a[4]_PORT_A_write_enable = GND;
GB2_q_a[4]_PORT_A_write_enable_reg = DFFE(GB2_q_a[4]_PORT_A_write_enable, GB2_q_a[4]_clock_0, , , GB2_q_a[4]_clock_enable_0);
GB2_q_a[4]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[4]_PORT_B_write_enable_reg = DFFE(GB2_q_a[4]_PORT_B_write_enable, GB2_q_a[4]_clock_1, , , GB2_q_a[4]_clock_enable_1);
GB2_q_a[4]_clock_0 = KB1__clk0;
GB2_q_a[4]_clock_1 = CCD_PIXCLK;
GB2_q_a[4]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[4]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[4]_clear_1 = !C1_oRST_0;
GB2_q_a[4]_PORT_A_data_out = MEMORY(GB2_q_a[4]_PORT_A_data_in_reg, GB2_q_a[4]_PORT_B_data_in_reg, GB2_q_a[4]_PORT_A_address_reg, GB2_q_a[4]_PORT_B_address_reg, GB2_q_a[4]_PORT_A_write_enable_reg, GB2_q_a[4]_PORT_B_write_enable_reg, , , GB2_q_a[4]_clock_0, GB2_q_a[4]_clock_1, GB2_q_a[4]_clock_enable_0, GB2_q_a[4]_clock_enable_1, , GB2_q_a[4]_clear_1);
GB2_q_a[4]_PORT_A_data_out_reg = DFFE(GB2_q_a[4]_PORT_A_data_out, GB2_q_a[4]_clock_0, GB2_q_a[4]_clear_1, , GB2_q_a[4]_clock_enable_0);
GB2_q_a[4] = GB2_q_a[4]_PORT_A_data_out_reg[0];


--G1L224 is Sdram_Control_4Port:u6|mDATAIN[4]~164
G1L224 = G1_WR_MASK[0] & GB1_q_a[4] # !G1_WR_MASK[0] & (GB2_q_a[4]);


--GB1_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[5]_PORT_A_data_in = VCC;
GB1_q_a[5]_PORT_A_data_in_reg = DFFE(GB1_q_a[5]_PORT_A_data_in, GB1_q_a[5]_clock_0, , , GB1_q_a[5]_clock_enable_0);
GB1_q_a[5]_PORT_B_data_in = PB3_q_b[5];
GB1_q_a[5]_PORT_B_data_in_reg = DFFE(GB1_q_a[5]_PORT_B_data_in, GB1_q_a[5]_clock_1, , , GB1_q_a[5]_clock_enable_1);
GB1_q_a[5]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[5]_PORT_A_address_reg = DFFE(GB1_q_a[5]_PORT_A_address, GB1_q_a[5]_clock_0, , , GB1_q_a[5]_clock_enable_0);
GB1_q_a[5]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[5]_PORT_B_address_reg = DFFE(GB1_q_a[5]_PORT_B_address, GB1_q_a[5]_clock_1, , , GB1_q_a[5]_clock_enable_1);
GB1_q_a[5]_PORT_A_write_enable = GND;
GB1_q_a[5]_PORT_A_write_enable_reg = DFFE(GB1_q_a[5]_PORT_A_write_enable, GB1_q_a[5]_clock_0, , , GB1_q_a[5]_clock_enable_0);
GB1_q_a[5]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[5]_PORT_B_write_enable_reg = DFFE(GB1_q_a[5]_PORT_B_write_enable, GB1_q_a[5]_clock_1, , , GB1_q_a[5]_clock_enable_1);
GB1_q_a[5]_clock_0 = KB1__clk0;
GB1_q_a[5]_clock_1 = CCD_PIXCLK;
GB1_q_a[5]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[5]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[5]_clear_1 = !C1_oRST_0;
GB1_q_a[5]_PORT_A_data_out = MEMORY(GB1_q_a[5]_PORT_A_data_in_reg, GB1_q_a[5]_PORT_B_data_in_reg, GB1_q_a[5]_PORT_A_address_reg, GB1_q_a[5]_PORT_B_address_reg, GB1_q_a[5]_PORT_A_write_enable_reg, GB1_q_a[5]_PORT_B_write_enable_reg, , , GB1_q_a[5]_clock_0, GB1_q_a[5]_clock_1, GB1_q_a[5]_clock_enable_0, GB1_q_a[5]_clock_enable_1, , GB1_q_a[5]_clear_1);
GB1_q_a[5]_PORT_A_data_out_reg = DFFE(GB1_q_a[5]_PORT_A_data_out, GB1_q_a[5]_clock_0, GB1_q_a[5]_clear_1, , GB1_q_a[5]_clock_enable_0);
GB1_q_a[5] = GB1_q_a[5]_PORT_A_data_out_reg[0];


--GB2_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[5]_PORT_A_data_in = VCC;
GB2_q_a[5]_PORT_A_data_in_reg = DFFE(GB2_q_a[5]_PORT_A_data_in, GB2_q_a[5]_clock_0, , , GB2_q_a[5]_clock_enable_0);
GB2_q_a[5]_PORT_B_data_in = PB1_q_b[5];
GB2_q_a[5]_PORT_B_data_in_reg = DFFE(GB2_q_a[5]_PORT_B_data_in, GB2_q_a[5]_clock_1, , , GB2_q_a[5]_clock_enable_1);
GB2_q_a[5]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[5]_PORT_A_address_reg = DFFE(GB2_q_a[5]_PORT_A_address, GB2_q_a[5]_clock_0, , , GB2_q_a[5]_clock_enable_0);
GB2_q_a[5]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[5]_PORT_B_address_reg = DFFE(GB2_q_a[5]_PORT_B_address, GB2_q_a[5]_clock_1, , , GB2_q_a[5]_clock_enable_1);
GB2_q_a[5]_PORT_A_write_enable = GND;
GB2_q_a[5]_PORT_A_write_enable_reg = DFFE(GB2_q_a[5]_PORT_A_write_enable, GB2_q_a[5]_clock_0, , , GB2_q_a[5]_clock_enable_0);
GB2_q_a[5]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[5]_PORT_B_write_enable_reg = DFFE(GB2_q_a[5]_PORT_B_write_enable, GB2_q_a[5]_clock_1, , , GB2_q_a[5]_clock_enable_1);
GB2_q_a[5]_clock_0 = KB1__clk0;
GB2_q_a[5]_clock_1 = CCD_PIXCLK;
GB2_q_a[5]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[5]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[5]_clear_1 = !C1_oRST_0;
GB2_q_a[5]_PORT_A_data_out = MEMORY(GB2_q_a[5]_PORT_A_data_in_reg, GB2_q_a[5]_PORT_B_data_in_reg, GB2_q_a[5]_PORT_A_address_reg, GB2_q_a[5]_PORT_B_address_reg, GB2_q_a[5]_PORT_A_write_enable_reg, GB2_q_a[5]_PORT_B_write_enable_reg, , , GB2_q_a[5]_clock_0, GB2_q_a[5]_clock_1, GB2_q_a[5]_clock_enable_0, GB2_q_a[5]_clock_enable_1, , GB2_q_a[5]_clear_1);
GB2_q_a[5]_PORT_A_data_out_reg = DFFE(GB2_q_a[5]_PORT_A_data_out, GB2_q_a[5]_clock_0, GB2_q_a[5]_clear_1, , GB2_q_a[5]_clock_enable_0);
GB2_q_a[5] = GB2_q_a[5]_PORT_A_data_out_reg[0];


--G1L225 is Sdram_Control_4Port:u6|mDATAIN[5]~165
G1L225 = G1_WR_MASK[0] & GB1_q_a[5] # !G1_WR_MASK[0] & (GB2_q_a[5]);


--GB1_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[6]_PORT_A_data_in = VCC;
GB1_q_a[6]_PORT_A_data_in_reg = DFFE(GB1_q_a[6]_PORT_A_data_in, GB1_q_a[6]_clock_0, , , GB1_q_a[6]_clock_enable_0);
GB1_q_a[6]_PORT_B_data_in = PB3_q_b[6];
GB1_q_a[6]_PORT_B_data_in_reg = DFFE(GB1_q_a[6]_PORT_B_data_in, GB1_q_a[6]_clock_1, , , GB1_q_a[6]_clock_enable_1);
GB1_q_a[6]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[6]_PORT_A_address_reg = DFFE(GB1_q_a[6]_PORT_A_address, GB1_q_a[6]_clock_0, , , GB1_q_a[6]_clock_enable_0);
GB1_q_a[6]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[6]_PORT_B_address_reg = DFFE(GB1_q_a[6]_PORT_B_address, GB1_q_a[6]_clock_1, , , GB1_q_a[6]_clock_enable_1);
GB1_q_a[6]_PORT_A_write_enable = GND;
GB1_q_a[6]_PORT_A_write_enable_reg = DFFE(GB1_q_a[6]_PORT_A_write_enable, GB1_q_a[6]_clock_0, , , GB1_q_a[6]_clock_enable_0);
GB1_q_a[6]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[6]_PORT_B_write_enable_reg = DFFE(GB1_q_a[6]_PORT_B_write_enable, GB1_q_a[6]_clock_1, , , GB1_q_a[6]_clock_enable_1);
GB1_q_a[6]_clock_0 = KB1__clk0;
GB1_q_a[6]_clock_1 = CCD_PIXCLK;
GB1_q_a[6]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[6]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[6]_clear_1 = !C1_oRST_0;
GB1_q_a[6]_PORT_A_data_out = MEMORY(GB1_q_a[6]_PORT_A_data_in_reg, GB1_q_a[6]_PORT_B_data_in_reg, GB1_q_a[6]_PORT_A_address_reg, GB1_q_a[6]_PORT_B_address_reg, GB1_q_a[6]_PORT_A_write_enable_reg, GB1_q_a[6]_PORT_B_write_enable_reg, , , GB1_q_a[6]_clock_0, GB1_q_a[6]_clock_1, GB1_q_a[6]_clock_enable_0, GB1_q_a[6]_clock_enable_1, , GB1_q_a[6]_clear_1);
GB1_q_a[6]_PORT_A_data_out_reg = DFFE(GB1_q_a[6]_PORT_A_data_out, GB1_q_a[6]_clock_0, GB1_q_a[6]_clear_1, , GB1_q_a[6]_clock_enable_0);
GB1_q_a[6] = GB1_q_a[6]_PORT_A_data_out_reg[0];


--GB2_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[6]_PORT_A_data_in = VCC;
GB2_q_a[6]_PORT_A_data_in_reg = DFFE(GB2_q_a[6]_PORT_A_data_in, GB2_q_a[6]_clock_0, , , GB2_q_a[6]_clock_enable_0);
GB2_q_a[6]_PORT_B_data_in = PB1_q_b[6];
GB2_q_a[6]_PORT_B_data_in_reg = DFFE(GB2_q_a[6]_PORT_B_data_in, GB2_q_a[6]_clock_1, , , GB2_q_a[6]_clock_enable_1);
GB2_q_a[6]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[6]_PORT_A_address_reg = DFFE(GB2_q_a[6]_PORT_A_address, GB2_q_a[6]_clock_0, , , GB2_q_a[6]_clock_enable_0);
GB2_q_a[6]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[6]_PORT_B_address_reg = DFFE(GB2_q_a[6]_PORT_B_address, GB2_q_a[6]_clock_1, , , GB2_q_a[6]_clock_enable_1);
GB2_q_a[6]_PORT_A_write_enable = GND;
GB2_q_a[6]_PORT_A_write_enable_reg = DFFE(GB2_q_a[6]_PORT_A_write_enable, GB2_q_a[6]_clock_0, , , GB2_q_a[6]_clock_enable_0);
GB2_q_a[6]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[6]_PORT_B_write_enable_reg = DFFE(GB2_q_a[6]_PORT_B_write_enable, GB2_q_a[6]_clock_1, , , GB2_q_a[6]_clock_enable_1);
GB2_q_a[6]_clock_0 = KB1__clk0;
GB2_q_a[6]_clock_1 = CCD_PIXCLK;
GB2_q_a[6]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[6]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[6]_clear_1 = !C1_oRST_0;
GB2_q_a[6]_PORT_A_data_out = MEMORY(GB2_q_a[6]_PORT_A_data_in_reg, GB2_q_a[6]_PORT_B_data_in_reg, GB2_q_a[6]_PORT_A_address_reg, GB2_q_a[6]_PORT_B_address_reg, GB2_q_a[6]_PORT_A_write_enable_reg, GB2_q_a[6]_PORT_B_write_enable_reg, , , GB2_q_a[6]_clock_0, GB2_q_a[6]_clock_1, GB2_q_a[6]_clock_enable_0, GB2_q_a[6]_clock_enable_1, , GB2_q_a[6]_clear_1);
GB2_q_a[6]_PORT_A_data_out_reg = DFFE(GB2_q_a[6]_PORT_A_data_out, GB2_q_a[6]_clock_0, GB2_q_a[6]_clear_1, , GB2_q_a[6]_clock_enable_0);
GB2_q_a[6] = GB2_q_a[6]_PORT_A_data_out_reg[0];


--G1L226 is Sdram_Control_4Port:u6|mDATAIN[6]~166
G1L226 = G1_WR_MASK[0] & GB1_q_a[6] # !G1_WR_MASK[0] & (GB2_q_a[6]);


--GB1_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[7]_PORT_A_data_in = VCC;
GB1_q_a[7]_PORT_A_data_in_reg = DFFE(GB1_q_a[7]_PORT_A_data_in, GB1_q_a[7]_clock_0, , , GB1_q_a[7]_clock_enable_0);
GB1_q_a[7]_PORT_B_data_in = PB3_q_b[7];
GB1_q_a[7]_PORT_B_data_in_reg = DFFE(GB1_q_a[7]_PORT_B_data_in, GB1_q_a[7]_clock_1, , , GB1_q_a[7]_clock_enable_1);
GB1_q_a[7]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[7]_PORT_A_address_reg = DFFE(GB1_q_a[7]_PORT_A_address, GB1_q_a[7]_clock_0, , , GB1_q_a[7]_clock_enable_0);
GB1_q_a[7]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[7]_PORT_B_address_reg = DFFE(GB1_q_a[7]_PORT_B_address, GB1_q_a[7]_clock_1, , , GB1_q_a[7]_clock_enable_1);
GB1_q_a[7]_PORT_A_write_enable = GND;
GB1_q_a[7]_PORT_A_write_enable_reg = DFFE(GB1_q_a[7]_PORT_A_write_enable, GB1_q_a[7]_clock_0, , , GB1_q_a[7]_clock_enable_0);
GB1_q_a[7]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[7]_PORT_B_write_enable_reg = DFFE(GB1_q_a[7]_PORT_B_write_enable, GB1_q_a[7]_clock_1, , , GB1_q_a[7]_clock_enable_1);
GB1_q_a[7]_clock_0 = KB1__clk0;
GB1_q_a[7]_clock_1 = CCD_PIXCLK;
GB1_q_a[7]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[7]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[7]_clear_1 = !C1_oRST_0;
GB1_q_a[7]_PORT_A_data_out = MEMORY(GB1_q_a[7]_PORT_A_data_in_reg, GB1_q_a[7]_PORT_B_data_in_reg, GB1_q_a[7]_PORT_A_address_reg, GB1_q_a[7]_PORT_B_address_reg, GB1_q_a[7]_PORT_A_write_enable_reg, GB1_q_a[7]_PORT_B_write_enable_reg, , , GB1_q_a[7]_clock_0, GB1_q_a[7]_clock_1, GB1_q_a[7]_clock_enable_0, GB1_q_a[7]_clock_enable_1, , GB1_q_a[7]_clear_1);
GB1_q_a[7]_PORT_A_data_out_reg = DFFE(GB1_q_a[7]_PORT_A_data_out, GB1_q_a[7]_clock_0, GB1_q_a[7]_clear_1, , GB1_q_a[7]_clock_enable_0);
GB1_q_a[7] = GB1_q_a[7]_PORT_A_data_out_reg[0];


--GB2_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[7]_PORT_A_data_in = VCC;
GB2_q_a[7]_PORT_A_data_in_reg = DFFE(GB2_q_a[7]_PORT_A_data_in, GB2_q_a[7]_clock_0, , , GB2_q_a[7]_clock_enable_0);
GB2_q_a[7]_PORT_B_data_in = PB1_q_b[7];
GB2_q_a[7]_PORT_B_data_in_reg = DFFE(GB2_q_a[7]_PORT_B_data_in, GB2_q_a[7]_clock_1, , , GB2_q_a[7]_clock_enable_1);
GB2_q_a[7]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[7]_PORT_A_address_reg = DFFE(GB2_q_a[7]_PORT_A_address, GB2_q_a[7]_clock_0, , , GB2_q_a[7]_clock_enable_0);
GB2_q_a[7]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[7]_PORT_B_address_reg = DFFE(GB2_q_a[7]_PORT_B_address, GB2_q_a[7]_clock_1, , , GB2_q_a[7]_clock_enable_1);
GB2_q_a[7]_PORT_A_write_enable = GND;
GB2_q_a[7]_PORT_A_write_enable_reg = DFFE(GB2_q_a[7]_PORT_A_write_enable, GB2_q_a[7]_clock_0, , , GB2_q_a[7]_clock_enable_0);
GB2_q_a[7]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[7]_PORT_B_write_enable_reg = DFFE(GB2_q_a[7]_PORT_B_write_enable, GB2_q_a[7]_clock_1, , , GB2_q_a[7]_clock_enable_1);
GB2_q_a[7]_clock_0 = KB1__clk0;
GB2_q_a[7]_clock_1 = CCD_PIXCLK;
GB2_q_a[7]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[7]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[7]_clear_1 = !C1_oRST_0;
GB2_q_a[7]_PORT_A_data_out = MEMORY(GB2_q_a[7]_PORT_A_data_in_reg, GB2_q_a[7]_PORT_B_data_in_reg, GB2_q_a[7]_PORT_A_address_reg, GB2_q_a[7]_PORT_B_address_reg, GB2_q_a[7]_PORT_A_write_enable_reg, GB2_q_a[7]_PORT_B_write_enable_reg, , , GB2_q_a[7]_clock_0, GB2_q_a[7]_clock_1, GB2_q_a[7]_clock_enable_0, GB2_q_a[7]_clock_enable_1, , GB2_q_a[7]_clear_1);
GB2_q_a[7]_PORT_A_data_out_reg = DFFE(GB2_q_a[7]_PORT_A_data_out, GB2_q_a[7]_clock_0, GB2_q_a[7]_clear_1, , GB2_q_a[7]_clock_enable_0);
GB2_q_a[7] = GB2_q_a[7]_PORT_A_data_out_reg[0];


--G1L227 is Sdram_Control_4Port:u6|mDATAIN[7]~167
G1L227 = G1_WR_MASK[0] & GB1_q_a[7] # !G1_WR_MASK[0] & (GB2_q_a[7]);


--GB1_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[8]_PORT_A_data_in = VCC;
GB1_q_a[8]_PORT_A_data_in_reg = DFFE(GB1_q_a[8]_PORT_A_data_in, GB1_q_a[8]_clock_0, , , GB1_q_a[8]_clock_enable_0);
GB1_q_a[8]_PORT_B_data_in = PB3_q_b[8];
GB1_q_a[8]_PORT_B_data_in_reg = DFFE(GB1_q_a[8]_PORT_B_data_in, GB1_q_a[8]_clock_1, , , GB1_q_a[8]_clock_enable_1);
GB1_q_a[8]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[8]_PORT_A_address_reg = DFFE(GB1_q_a[8]_PORT_A_address, GB1_q_a[8]_clock_0, , , GB1_q_a[8]_clock_enable_0);
GB1_q_a[8]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[8]_PORT_B_address_reg = DFFE(GB1_q_a[8]_PORT_B_address, GB1_q_a[8]_clock_1, , , GB1_q_a[8]_clock_enable_1);
GB1_q_a[8]_PORT_A_write_enable = GND;
GB1_q_a[8]_PORT_A_write_enable_reg = DFFE(GB1_q_a[8]_PORT_A_write_enable, GB1_q_a[8]_clock_0, , , GB1_q_a[8]_clock_enable_0);
GB1_q_a[8]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[8]_PORT_B_write_enable_reg = DFFE(GB1_q_a[8]_PORT_B_write_enable, GB1_q_a[8]_clock_1, , , GB1_q_a[8]_clock_enable_1);
GB1_q_a[8]_clock_0 = KB1__clk0;
GB1_q_a[8]_clock_1 = CCD_PIXCLK;
GB1_q_a[8]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[8]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[8]_clear_1 = !C1_oRST_0;
GB1_q_a[8]_PORT_A_data_out = MEMORY(GB1_q_a[8]_PORT_A_data_in_reg, GB1_q_a[8]_PORT_B_data_in_reg, GB1_q_a[8]_PORT_A_address_reg, GB1_q_a[8]_PORT_B_address_reg, GB1_q_a[8]_PORT_A_write_enable_reg, GB1_q_a[8]_PORT_B_write_enable_reg, , , GB1_q_a[8]_clock_0, GB1_q_a[8]_clock_1, GB1_q_a[8]_clock_enable_0, GB1_q_a[8]_clock_enable_1, , GB1_q_a[8]_clear_1);
GB1_q_a[8]_PORT_A_data_out_reg = DFFE(GB1_q_a[8]_PORT_A_data_out, GB1_q_a[8]_clock_0, GB1_q_a[8]_clear_1, , GB1_q_a[8]_clock_enable_0);
GB1_q_a[8] = GB1_q_a[8]_PORT_A_data_out_reg[0];


--GB2_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[8]_PORT_A_data_in = VCC;
GB2_q_a[8]_PORT_A_data_in_reg = DFFE(GB2_q_a[8]_PORT_A_data_in, GB2_q_a[8]_clock_0, , , GB2_q_a[8]_clock_enable_0);
GB2_q_a[8]_PORT_B_data_in = PB1_q_b[8];
GB2_q_a[8]_PORT_B_data_in_reg = DFFE(GB2_q_a[8]_PORT_B_data_in, GB2_q_a[8]_clock_1, , , GB2_q_a[8]_clock_enable_1);
GB2_q_a[8]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[8]_PORT_A_address_reg = DFFE(GB2_q_a[8]_PORT_A_address, GB2_q_a[8]_clock_0, , , GB2_q_a[8]_clock_enable_0);
GB2_q_a[8]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[8]_PORT_B_address_reg = DFFE(GB2_q_a[8]_PORT_B_address, GB2_q_a[8]_clock_1, , , GB2_q_a[8]_clock_enable_1);
GB2_q_a[8]_PORT_A_write_enable = GND;
GB2_q_a[8]_PORT_A_write_enable_reg = DFFE(GB2_q_a[8]_PORT_A_write_enable, GB2_q_a[8]_clock_0, , , GB2_q_a[8]_clock_enable_0);
GB2_q_a[8]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[8]_PORT_B_write_enable_reg = DFFE(GB2_q_a[8]_PORT_B_write_enable, GB2_q_a[8]_clock_1, , , GB2_q_a[8]_clock_enable_1);
GB2_q_a[8]_clock_0 = KB1__clk0;
GB2_q_a[8]_clock_1 = CCD_PIXCLK;
GB2_q_a[8]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[8]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[8]_clear_1 = !C1_oRST_0;
GB2_q_a[8]_PORT_A_data_out = MEMORY(GB2_q_a[8]_PORT_A_data_in_reg, GB2_q_a[8]_PORT_B_data_in_reg, GB2_q_a[8]_PORT_A_address_reg, GB2_q_a[8]_PORT_B_address_reg, GB2_q_a[8]_PORT_A_write_enable_reg, GB2_q_a[8]_PORT_B_write_enable_reg, , , GB2_q_a[8]_clock_0, GB2_q_a[8]_clock_1, GB2_q_a[8]_clock_enable_0, GB2_q_a[8]_clock_enable_1, , GB2_q_a[8]_clear_1);
GB2_q_a[8]_PORT_A_data_out_reg = DFFE(GB2_q_a[8]_PORT_A_data_out, GB2_q_a[8]_clock_0, GB2_q_a[8]_clear_1, , GB2_q_a[8]_clock_enable_0);
GB2_q_a[8] = GB2_q_a[8]_PORT_A_data_out_reg[0];


--G1L228 is Sdram_Control_4Port:u6|mDATAIN[8]~168
G1L228 = G1_WR_MASK[0] & GB1_q_a[8] # !G1_WR_MASK[0] & (GB2_q_a[8]);


--GB1_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[9]_PORT_A_data_in = VCC;
GB1_q_a[9]_PORT_A_data_in_reg = DFFE(GB1_q_a[9]_PORT_A_data_in, GB1_q_a[9]_clock_0, , , GB1_q_a[9]_clock_enable_0);
GB1_q_a[9]_PORT_B_data_in = PB3_q_b[9];
GB1_q_a[9]_PORT_B_data_in_reg = DFFE(GB1_q_a[9]_PORT_B_data_in, GB1_q_a[9]_clock_1, , , GB1_q_a[9]_clock_enable_1);
GB1_q_a[9]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[9]_PORT_A_address_reg = DFFE(GB1_q_a[9]_PORT_A_address, GB1_q_a[9]_clock_0, , , GB1_q_a[9]_clock_enable_0);
GB1_q_a[9]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[9]_PORT_B_address_reg = DFFE(GB1_q_a[9]_PORT_B_address, GB1_q_a[9]_clock_1, , , GB1_q_a[9]_clock_enable_1);
GB1_q_a[9]_PORT_A_write_enable = GND;
GB1_q_a[9]_PORT_A_write_enable_reg = DFFE(GB1_q_a[9]_PORT_A_write_enable, GB1_q_a[9]_clock_0, , , GB1_q_a[9]_clock_enable_0);
GB1_q_a[9]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[9]_PORT_B_write_enable_reg = DFFE(GB1_q_a[9]_PORT_B_write_enable, GB1_q_a[9]_clock_1, , , GB1_q_a[9]_clock_enable_1);
GB1_q_a[9]_clock_0 = KB1__clk0;
GB1_q_a[9]_clock_1 = CCD_PIXCLK;
GB1_q_a[9]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[9]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[9]_clear_1 = !C1_oRST_0;
GB1_q_a[9]_PORT_A_data_out = MEMORY(GB1_q_a[9]_PORT_A_data_in_reg, GB1_q_a[9]_PORT_B_data_in_reg, GB1_q_a[9]_PORT_A_address_reg, GB1_q_a[9]_PORT_B_address_reg, GB1_q_a[9]_PORT_A_write_enable_reg, GB1_q_a[9]_PORT_B_write_enable_reg, , , GB1_q_a[9]_clock_0, GB1_q_a[9]_clock_1, GB1_q_a[9]_clock_enable_0, GB1_q_a[9]_clock_enable_1, , GB1_q_a[9]_clear_1);
GB1_q_a[9]_PORT_A_data_out_reg = DFFE(GB1_q_a[9]_PORT_A_data_out, GB1_q_a[9]_clock_0, GB1_q_a[9]_clear_1, , GB1_q_a[9]_clock_enable_0);
GB1_q_a[9] = GB1_q_a[9]_PORT_A_data_out_reg[0];


--GB2_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[9]_PORT_A_data_in = VCC;
GB2_q_a[9]_PORT_A_data_in_reg = DFFE(GB2_q_a[9]_PORT_A_data_in, GB2_q_a[9]_clock_0, , , GB2_q_a[9]_clock_enable_0);
GB2_q_a[9]_PORT_B_data_in = PB1_q_b[9];
GB2_q_a[9]_PORT_B_data_in_reg = DFFE(GB2_q_a[9]_PORT_B_data_in, GB2_q_a[9]_clock_1, , , GB2_q_a[9]_clock_enable_1);
GB2_q_a[9]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[9]_PORT_A_address_reg = DFFE(GB2_q_a[9]_PORT_A_address, GB2_q_a[9]_clock_0, , , GB2_q_a[9]_clock_enable_0);
GB2_q_a[9]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[9]_PORT_B_address_reg = DFFE(GB2_q_a[9]_PORT_B_address, GB2_q_a[9]_clock_1, , , GB2_q_a[9]_clock_enable_1);
GB2_q_a[9]_PORT_A_write_enable = GND;
GB2_q_a[9]_PORT_A_write_enable_reg = DFFE(GB2_q_a[9]_PORT_A_write_enable, GB2_q_a[9]_clock_0, , , GB2_q_a[9]_clock_enable_0);
GB2_q_a[9]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[9]_PORT_B_write_enable_reg = DFFE(GB2_q_a[9]_PORT_B_write_enable, GB2_q_a[9]_clock_1, , , GB2_q_a[9]_clock_enable_1);
GB2_q_a[9]_clock_0 = KB1__clk0;
GB2_q_a[9]_clock_1 = CCD_PIXCLK;
GB2_q_a[9]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[9]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[9]_clear_1 = !C1_oRST_0;
GB2_q_a[9]_PORT_A_data_out = MEMORY(GB2_q_a[9]_PORT_A_data_in_reg, GB2_q_a[9]_PORT_B_data_in_reg, GB2_q_a[9]_PORT_A_address_reg, GB2_q_a[9]_PORT_B_address_reg, GB2_q_a[9]_PORT_A_write_enable_reg, GB2_q_a[9]_PORT_B_write_enable_reg, , , GB2_q_a[9]_clock_0, GB2_q_a[9]_clock_1, GB2_q_a[9]_clock_enable_0, GB2_q_a[9]_clock_enable_1, , GB2_q_a[9]_clear_1);
GB2_q_a[9]_PORT_A_data_out_reg = DFFE(GB2_q_a[9]_PORT_A_data_out, GB2_q_a[9]_clock_0, GB2_q_a[9]_clear_1, , GB2_q_a[9]_clock_enable_0);
GB2_q_a[9] = GB2_q_a[9]_PORT_A_data_out_reg[0];


--G1L229 is Sdram_Control_4Port:u6|mDATAIN[9]~169
G1L229 = G1_WR_MASK[0] & GB1_q_a[9] # !G1_WR_MASK[0] & (GB2_q_a[9]);


--GB1_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[10]_PORT_A_data_in = VCC;
GB1_q_a[10]_PORT_A_data_in_reg = DFFE(GB1_q_a[10]_PORT_A_data_in, GB1_q_a[10]_clock_0, , , GB1_q_a[10]_clock_enable_0);
GB1_q_a[10]_PORT_B_data_in = PB2_q_b[5];
GB1_q_a[10]_PORT_B_data_in_reg = DFFE(GB1_q_a[10]_PORT_B_data_in, GB1_q_a[10]_clock_1, , , GB1_q_a[10]_clock_enable_1);
GB1_q_a[10]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[10]_PORT_A_address_reg = DFFE(GB1_q_a[10]_PORT_A_address, GB1_q_a[10]_clock_0, , , GB1_q_a[10]_clock_enable_0);
GB1_q_a[10]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[10]_PORT_B_address_reg = DFFE(GB1_q_a[10]_PORT_B_address, GB1_q_a[10]_clock_1, , , GB1_q_a[10]_clock_enable_1);
GB1_q_a[10]_PORT_A_write_enable = GND;
GB1_q_a[10]_PORT_A_write_enable_reg = DFFE(GB1_q_a[10]_PORT_A_write_enable, GB1_q_a[10]_clock_0, , , GB1_q_a[10]_clock_enable_0);
GB1_q_a[10]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[10]_PORT_B_write_enable_reg = DFFE(GB1_q_a[10]_PORT_B_write_enable, GB1_q_a[10]_clock_1, , , GB1_q_a[10]_clock_enable_1);
GB1_q_a[10]_clock_0 = KB1__clk0;
GB1_q_a[10]_clock_1 = CCD_PIXCLK;
GB1_q_a[10]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[10]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[10]_clear_1 = !C1_oRST_0;
GB1_q_a[10]_PORT_A_data_out = MEMORY(GB1_q_a[10]_PORT_A_data_in_reg, GB1_q_a[10]_PORT_B_data_in_reg, GB1_q_a[10]_PORT_A_address_reg, GB1_q_a[10]_PORT_B_address_reg, GB1_q_a[10]_PORT_A_write_enable_reg, GB1_q_a[10]_PORT_B_write_enable_reg, , , GB1_q_a[10]_clock_0, GB1_q_a[10]_clock_1, GB1_q_a[10]_clock_enable_0, GB1_q_a[10]_clock_enable_1, , GB1_q_a[10]_clear_1);
GB1_q_a[10]_PORT_A_data_out_reg = DFFE(GB1_q_a[10]_PORT_A_data_out, GB1_q_a[10]_clock_0, GB1_q_a[10]_clear_1, , GB1_q_a[10]_clock_enable_0);
GB1_q_a[10] = GB1_q_a[10]_PORT_A_data_out_reg[0];


--GB2_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[10]_PORT_A_data_in = VCC;
GB2_q_a[10]_PORT_A_data_in_reg = DFFE(GB2_q_a[10]_PORT_A_data_in, GB2_q_a[10]_clock_0, , , GB2_q_a[10]_clock_enable_0);
GB2_q_a[10]_PORT_B_data_in = PB2_q_b[0];
GB2_q_a[10]_PORT_B_data_in_reg = DFFE(GB2_q_a[10]_PORT_B_data_in, GB2_q_a[10]_clock_1, , , GB2_q_a[10]_clock_enable_1);
GB2_q_a[10]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[10]_PORT_A_address_reg = DFFE(GB2_q_a[10]_PORT_A_address, GB2_q_a[10]_clock_0, , , GB2_q_a[10]_clock_enable_0);
GB2_q_a[10]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[10]_PORT_B_address_reg = DFFE(GB2_q_a[10]_PORT_B_address, GB2_q_a[10]_clock_1, , , GB2_q_a[10]_clock_enable_1);
GB2_q_a[10]_PORT_A_write_enable = GND;
GB2_q_a[10]_PORT_A_write_enable_reg = DFFE(GB2_q_a[10]_PORT_A_write_enable, GB2_q_a[10]_clock_0, , , GB2_q_a[10]_clock_enable_0);
GB2_q_a[10]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[10]_PORT_B_write_enable_reg = DFFE(GB2_q_a[10]_PORT_B_write_enable, GB2_q_a[10]_clock_1, , , GB2_q_a[10]_clock_enable_1);
GB2_q_a[10]_clock_0 = KB1__clk0;
GB2_q_a[10]_clock_1 = CCD_PIXCLK;
GB2_q_a[10]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[10]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[10]_clear_1 = !C1_oRST_0;
GB2_q_a[10]_PORT_A_data_out = MEMORY(GB2_q_a[10]_PORT_A_data_in_reg, GB2_q_a[10]_PORT_B_data_in_reg, GB2_q_a[10]_PORT_A_address_reg, GB2_q_a[10]_PORT_B_address_reg, GB2_q_a[10]_PORT_A_write_enable_reg, GB2_q_a[10]_PORT_B_write_enable_reg, , , GB2_q_a[10]_clock_0, GB2_q_a[10]_clock_1, GB2_q_a[10]_clock_enable_0, GB2_q_a[10]_clock_enable_1, , GB2_q_a[10]_clear_1);
GB2_q_a[10]_PORT_A_data_out_reg = DFFE(GB2_q_a[10]_PORT_A_data_out, GB2_q_a[10]_clock_0, GB2_q_a[10]_clear_1, , GB2_q_a[10]_clock_enable_0);
GB2_q_a[10] = GB2_q_a[10]_PORT_A_data_out_reg[0];


--G1L230 is Sdram_Control_4Port:u6|mDATAIN[10]~170
G1L230 = G1_WR_MASK[0] & GB1_q_a[10] # !G1_WR_MASK[0] & (GB2_q_a[10]);


--GB1_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[11]_PORT_A_data_in = VCC;
GB1_q_a[11]_PORT_A_data_in_reg = DFFE(GB1_q_a[11]_PORT_A_data_in, GB1_q_a[11]_clock_0, , , GB1_q_a[11]_clock_enable_0);
GB1_q_a[11]_PORT_B_data_in = PB2_q_b[6];
GB1_q_a[11]_PORT_B_data_in_reg = DFFE(GB1_q_a[11]_PORT_B_data_in, GB1_q_a[11]_clock_1, , , GB1_q_a[11]_clock_enable_1);
GB1_q_a[11]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[11]_PORT_A_address_reg = DFFE(GB1_q_a[11]_PORT_A_address, GB1_q_a[11]_clock_0, , , GB1_q_a[11]_clock_enable_0);
GB1_q_a[11]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[11]_PORT_B_address_reg = DFFE(GB1_q_a[11]_PORT_B_address, GB1_q_a[11]_clock_1, , , GB1_q_a[11]_clock_enable_1);
GB1_q_a[11]_PORT_A_write_enable = GND;
GB1_q_a[11]_PORT_A_write_enable_reg = DFFE(GB1_q_a[11]_PORT_A_write_enable, GB1_q_a[11]_clock_0, , , GB1_q_a[11]_clock_enable_0);
GB1_q_a[11]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[11]_PORT_B_write_enable_reg = DFFE(GB1_q_a[11]_PORT_B_write_enable, GB1_q_a[11]_clock_1, , , GB1_q_a[11]_clock_enable_1);
GB1_q_a[11]_clock_0 = KB1__clk0;
GB1_q_a[11]_clock_1 = CCD_PIXCLK;
GB1_q_a[11]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[11]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[11]_clear_1 = !C1_oRST_0;
GB1_q_a[11]_PORT_A_data_out = MEMORY(GB1_q_a[11]_PORT_A_data_in_reg, GB1_q_a[11]_PORT_B_data_in_reg, GB1_q_a[11]_PORT_A_address_reg, GB1_q_a[11]_PORT_B_address_reg, GB1_q_a[11]_PORT_A_write_enable_reg, GB1_q_a[11]_PORT_B_write_enable_reg, , , GB1_q_a[11]_clock_0, GB1_q_a[11]_clock_1, GB1_q_a[11]_clock_enable_0, GB1_q_a[11]_clock_enable_1, , GB1_q_a[11]_clear_1);
GB1_q_a[11]_PORT_A_data_out_reg = DFFE(GB1_q_a[11]_PORT_A_data_out, GB1_q_a[11]_clock_0, GB1_q_a[11]_clear_1, , GB1_q_a[11]_clock_enable_0);
GB1_q_a[11] = GB1_q_a[11]_PORT_A_data_out_reg[0];


--GB2_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[11]_PORT_A_data_in = VCC;
GB2_q_a[11]_PORT_A_data_in_reg = DFFE(GB2_q_a[11]_PORT_A_data_in, GB2_q_a[11]_clock_0, , , GB2_q_a[11]_clock_enable_0);
GB2_q_a[11]_PORT_B_data_in = PB2_q_b[1];
GB2_q_a[11]_PORT_B_data_in_reg = DFFE(GB2_q_a[11]_PORT_B_data_in, GB2_q_a[11]_clock_1, , , GB2_q_a[11]_clock_enable_1);
GB2_q_a[11]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[11]_PORT_A_address_reg = DFFE(GB2_q_a[11]_PORT_A_address, GB2_q_a[11]_clock_0, , , GB2_q_a[11]_clock_enable_0);
GB2_q_a[11]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[11]_PORT_B_address_reg = DFFE(GB2_q_a[11]_PORT_B_address, GB2_q_a[11]_clock_1, , , GB2_q_a[11]_clock_enable_1);
GB2_q_a[11]_PORT_A_write_enable = GND;
GB2_q_a[11]_PORT_A_write_enable_reg = DFFE(GB2_q_a[11]_PORT_A_write_enable, GB2_q_a[11]_clock_0, , , GB2_q_a[11]_clock_enable_0);
GB2_q_a[11]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[11]_PORT_B_write_enable_reg = DFFE(GB2_q_a[11]_PORT_B_write_enable, GB2_q_a[11]_clock_1, , , GB2_q_a[11]_clock_enable_1);
GB2_q_a[11]_clock_0 = KB1__clk0;
GB2_q_a[11]_clock_1 = CCD_PIXCLK;
GB2_q_a[11]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[11]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[11]_clear_1 = !C1_oRST_0;
GB2_q_a[11]_PORT_A_data_out = MEMORY(GB2_q_a[11]_PORT_A_data_in_reg, GB2_q_a[11]_PORT_B_data_in_reg, GB2_q_a[11]_PORT_A_address_reg, GB2_q_a[11]_PORT_B_address_reg, GB2_q_a[11]_PORT_A_write_enable_reg, GB2_q_a[11]_PORT_B_write_enable_reg, , , GB2_q_a[11]_clock_0, GB2_q_a[11]_clock_1, GB2_q_a[11]_clock_enable_0, GB2_q_a[11]_clock_enable_1, , GB2_q_a[11]_clear_1);
GB2_q_a[11]_PORT_A_data_out_reg = DFFE(GB2_q_a[11]_PORT_A_data_out, GB2_q_a[11]_clock_0, GB2_q_a[11]_clear_1, , GB2_q_a[11]_clock_enable_0);
GB2_q_a[11] = GB2_q_a[11]_PORT_A_data_out_reg[0];


--G1L231 is Sdram_Control_4Port:u6|mDATAIN[11]~171
G1L231 = G1_WR_MASK[0] & GB1_q_a[11] # !G1_WR_MASK[0] & (GB2_q_a[11]);


--GB1_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[12]_PORT_A_data_in = VCC;
GB1_q_a[12]_PORT_A_data_in_reg = DFFE(GB1_q_a[12]_PORT_A_data_in, GB1_q_a[12]_clock_0, , , GB1_q_a[12]_clock_enable_0);
GB1_q_a[12]_PORT_B_data_in = PB2_q_b[7];
GB1_q_a[12]_PORT_B_data_in_reg = DFFE(GB1_q_a[12]_PORT_B_data_in, GB1_q_a[12]_clock_1, , , GB1_q_a[12]_clock_enable_1);
GB1_q_a[12]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[12]_PORT_A_address_reg = DFFE(GB1_q_a[12]_PORT_A_address, GB1_q_a[12]_clock_0, , , GB1_q_a[12]_clock_enable_0);
GB1_q_a[12]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[12]_PORT_B_address_reg = DFFE(GB1_q_a[12]_PORT_B_address, GB1_q_a[12]_clock_1, , , GB1_q_a[12]_clock_enable_1);
GB1_q_a[12]_PORT_A_write_enable = GND;
GB1_q_a[12]_PORT_A_write_enable_reg = DFFE(GB1_q_a[12]_PORT_A_write_enable, GB1_q_a[12]_clock_0, , , GB1_q_a[12]_clock_enable_0);
GB1_q_a[12]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[12]_PORT_B_write_enable_reg = DFFE(GB1_q_a[12]_PORT_B_write_enable, GB1_q_a[12]_clock_1, , , GB1_q_a[12]_clock_enable_1);
GB1_q_a[12]_clock_0 = KB1__clk0;
GB1_q_a[12]_clock_1 = CCD_PIXCLK;
GB1_q_a[12]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[12]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[12]_clear_1 = !C1_oRST_0;
GB1_q_a[12]_PORT_A_data_out = MEMORY(GB1_q_a[12]_PORT_A_data_in_reg, GB1_q_a[12]_PORT_B_data_in_reg, GB1_q_a[12]_PORT_A_address_reg, GB1_q_a[12]_PORT_B_address_reg, GB1_q_a[12]_PORT_A_write_enable_reg, GB1_q_a[12]_PORT_B_write_enable_reg, , , GB1_q_a[12]_clock_0, GB1_q_a[12]_clock_1, GB1_q_a[12]_clock_enable_0, GB1_q_a[12]_clock_enable_1, , GB1_q_a[12]_clear_1);
GB1_q_a[12]_PORT_A_data_out_reg = DFFE(GB1_q_a[12]_PORT_A_data_out, GB1_q_a[12]_clock_0, GB1_q_a[12]_clear_1, , GB1_q_a[12]_clock_enable_0);
GB1_q_a[12] = GB1_q_a[12]_PORT_A_data_out_reg[0];


--GB2_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[12]_PORT_A_data_in = VCC;
GB2_q_a[12]_PORT_A_data_in_reg = DFFE(GB2_q_a[12]_PORT_A_data_in, GB2_q_a[12]_clock_0, , , GB2_q_a[12]_clock_enable_0);
GB2_q_a[12]_PORT_B_data_in = PB2_q_b[2];
GB2_q_a[12]_PORT_B_data_in_reg = DFFE(GB2_q_a[12]_PORT_B_data_in, GB2_q_a[12]_clock_1, , , GB2_q_a[12]_clock_enable_1);
GB2_q_a[12]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[12]_PORT_A_address_reg = DFFE(GB2_q_a[12]_PORT_A_address, GB2_q_a[12]_clock_0, , , GB2_q_a[12]_clock_enable_0);
GB2_q_a[12]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[12]_PORT_B_address_reg = DFFE(GB2_q_a[12]_PORT_B_address, GB2_q_a[12]_clock_1, , , GB2_q_a[12]_clock_enable_1);
GB2_q_a[12]_PORT_A_write_enable = GND;
GB2_q_a[12]_PORT_A_write_enable_reg = DFFE(GB2_q_a[12]_PORT_A_write_enable, GB2_q_a[12]_clock_0, , , GB2_q_a[12]_clock_enable_0);
GB2_q_a[12]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[12]_PORT_B_write_enable_reg = DFFE(GB2_q_a[12]_PORT_B_write_enable, GB2_q_a[12]_clock_1, , , GB2_q_a[12]_clock_enable_1);
GB2_q_a[12]_clock_0 = KB1__clk0;
GB2_q_a[12]_clock_1 = CCD_PIXCLK;
GB2_q_a[12]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[12]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[12]_clear_1 = !C1_oRST_0;
GB2_q_a[12]_PORT_A_data_out = MEMORY(GB2_q_a[12]_PORT_A_data_in_reg, GB2_q_a[12]_PORT_B_data_in_reg, GB2_q_a[12]_PORT_A_address_reg, GB2_q_a[12]_PORT_B_address_reg, GB2_q_a[12]_PORT_A_write_enable_reg, GB2_q_a[12]_PORT_B_write_enable_reg, , , GB2_q_a[12]_clock_0, GB2_q_a[12]_clock_1, GB2_q_a[12]_clock_enable_0, GB2_q_a[12]_clock_enable_1, , GB2_q_a[12]_clear_1);
GB2_q_a[12]_PORT_A_data_out_reg = DFFE(GB2_q_a[12]_PORT_A_data_out, GB2_q_a[12]_clock_0, GB2_q_a[12]_clear_1, , GB2_q_a[12]_clock_enable_0);
GB2_q_a[12] = GB2_q_a[12]_PORT_A_data_out_reg[0];


--G1L232 is Sdram_Control_4Port:u6|mDATAIN[12]~172
G1L232 = G1_WR_MASK[0] & GB1_q_a[12] # !G1_WR_MASK[0] & (GB2_q_a[12]);


--GB1_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[13]_PORT_A_data_in = VCC;
GB1_q_a[13]_PORT_A_data_in_reg = DFFE(GB1_q_a[13]_PORT_A_data_in, GB1_q_a[13]_clock_0, , , GB1_q_a[13]_clock_enable_0);
GB1_q_a[13]_PORT_B_data_in = PB2_q_b[8];
GB1_q_a[13]_PORT_B_data_in_reg = DFFE(GB1_q_a[13]_PORT_B_data_in, GB1_q_a[13]_clock_1, , , GB1_q_a[13]_clock_enable_1);
GB1_q_a[13]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[13]_PORT_A_address_reg = DFFE(GB1_q_a[13]_PORT_A_address, GB1_q_a[13]_clock_0, , , GB1_q_a[13]_clock_enable_0);
GB1_q_a[13]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[13]_PORT_B_address_reg = DFFE(GB1_q_a[13]_PORT_B_address, GB1_q_a[13]_clock_1, , , GB1_q_a[13]_clock_enable_1);
GB1_q_a[13]_PORT_A_write_enable = GND;
GB1_q_a[13]_PORT_A_write_enable_reg = DFFE(GB1_q_a[13]_PORT_A_write_enable, GB1_q_a[13]_clock_0, , , GB1_q_a[13]_clock_enable_0);
GB1_q_a[13]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[13]_PORT_B_write_enable_reg = DFFE(GB1_q_a[13]_PORT_B_write_enable, GB1_q_a[13]_clock_1, , , GB1_q_a[13]_clock_enable_1);
GB1_q_a[13]_clock_0 = KB1__clk0;
GB1_q_a[13]_clock_1 = CCD_PIXCLK;
GB1_q_a[13]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[13]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[13]_clear_1 = !C1_oRST_0;
GB1_q_a[13]_PORT_A_data_out = MEMORY(GB1_q_a[13]_PORT_A_data_in_reg, GB1_q_a[13]_PORT_B_data_in_reg, GB1_q_a[13]_PORT_A_address_reg, GB1_q_a[13]_PORT_B_address_reg, GB1_q_a[13]_PORT_A_write_enable_reg, GB1_q_a[13]_PORT_B_write_enable_reg, , , GB1_q_a[13]_clock_0, GB1_q_a[13]_clock_1, GB1_q_a[13]_clock_enable_0, GB1_q_a[13]_clock_enable_1, , GB1_q_a[13]_clear_1);
GB1_q_a[13]_PORT_A_data_out_reg = DFFE(GB1_q_a[13]_PORT_A_data_out, GB1_q_a[13]_clock_0, GB1_q_a[13]_clear_1, , GB1_q_a[13]_clock_enable_0);
GB1_q_a[13] = GB1_q_a[13]_PORT_A_data_out_reg[0];


--GB2_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[13]_PORT_A_data_in = VCC;
GB2_q_a[13]_PORT_A_data_in_reg = DFFE(GB2_q_a[13]_PORT_A_data_in, GB2_q_a[13]_clock_0, , , GB2_q_a[13]_clock_enable_0);
GB2_q_a[13]_PORT_B_data_in = PB2_q_b[3];
GB2_q_a[13]_PORT_B_data_in_reg = DFFE(GB2_q_a[13]_PORT_B_data_in, GB2_q_a[13]_clock_1, , , GB2_q_a[13]_clock_enable_1);
GB2_q_a[13]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[13]_PORT_A_address_reg = DFFE(GB2_q_a[13]_PORT_A_address, GB2_q_a[13]_clock_0, , , GB2_q_a[13]_clock_enable_0);
GB2_q_a[13]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[13]_PORT_B_address_reg = DFFE(GB2_q_a[13]_PORT_B_address, GB2_q_a[13]_clock_1, , , GB2_q_a[13]_clock_enable_1);
GB2_q_a[13]_PORT_A_write_enable = GND;
GB2_q_a[13]_PORT_A_write_enable_reg = DFFE(GB2_q_a[13]_PORT_A_write_enable, GB2_q_a[13]_clock_0, , , GB2_q_a[13]_clock_enable_0);
GB2_q_a[13]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[13]_PORT_B_write_enable_reg = DFFE(GB2_q_a[13]_PORT_B_write_enable, GB2_q_a[13]_clock_1, , , GB2_q_a[13]_clock_enable_1);
GB2_q_a[13]_clock_0 = KB1__clk0;
GB2_q_a[13]_clock_1 = CCD_PIXCLK;
GB2_q_a[13]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[13]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[13]_clear_1 = !C1_oRST_0;
GB2_q_a[13]_PORT_A_data_out = MEMORY(GB2_q_a[13]_PORT_A_data_in_reg, GB2_q_a[13]_PORT_B_data_in_reg, GB2_q_a[13]_PORT_A_address_reg, GB2_q_a[13]_PORT_B_address_reg, GB2_q_a[13]_PORT_A_write_enable_reg, GB2_q_a[13]_PORT_B_write_enable_reg, , , GB2_q_a[13]_clock_0, GB2_q_a[13]_clock_1, GB2_q_a[13]_clock_enable_0, GB2_q_a[13]_clock_enable_1, , GB2_q_a[13]_clear_1);
GB2_q_a[13]_PORT_A_data_out_reg = DFFE(GB2_q_a[13]_PORT_A_data_out, GB2_q_a[13]_clock_0, GB2_q_a[13]_clear_1, , GB2_q_a[13]_clock_enable_0);
GB2_q_a[13] = GB2_q_a[13]_PORT_A_data_out_reg[0];


--G1L233 is Sdram_Control_4Port:u6|mDATAIN[13]~173
G1L233 = G1_WR_MASK[0] & GB1_q_a[13] # !G1_WR_MASK[0] & (GB2_q_a[13]);


--GB1_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[14]_PORT_A_data_in = VCC;
GB1_q_a[14]_PORT_A_data_in_reg = DFFE(GB1_q_a[14]_PORT_A_data_in, GB1_q_a[14]_clock_0, , , GB1_q_a[14]_clock_enable_0);
GB1_q_a[14]_PORT_B_data_in = PB2_q_b[9];
GB1_q_a[14]_PORT_B_data_in_reg = DFFE(GB1_q_a[14]_PORT_B_data_in, GB1_q_a[14]_clock_1, , , GB1_q_a[14]_clock_enable_1);
GB1_q_a[14]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[14]_PORT_A_address_reg = DFFE(GB1_q_a[14]_PORT_A_address, GB1_q_a[14]_clock_0, , , GB1_q_a[14]_clock_enable_0);
GB1_q_a[14]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[14]_PORT_B_address_reg = DFFE(GB1_q_a[14]_PORT_B_address, GB1_q_a[14]_clock_1, , , GB1_q_a[14]_clock_enable_1);
GB1_q_a[14]_PORT_A_write_enable = GND;
GB1_q_a[14]_PORT_A_write_enable_reg = DFFE(GB1_q_a[14]_PORT_A_write_enable, GB1_q_a[14]_clock_0, , , GB1_q_a[14]_clock_enable_0);
GB1_q_a[14]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[14]_PORT_B_write_enable_reg = DFFE(GB1_q_a[14]_PORT_B_write_enable, GB1_q_a[14]_clock_1, , , GB1_q_a[14]_clock_enable_1);
GB1_q_a[14]_clock_0 = KB1__clk0;
GB1_q_a[14]_clock_1 = CCD_PIXCLK;
GB1_q_a[14]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[14]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[14]_clear_1 = !C1_oRST_0;
GB1_q_a[14]_PORT_A_data_out = MEMORY(GB1_q_a[14]_PORT_A_data_in_reg, GB1_q_a[14]_PORT_B_data_in_reg, GB1_q_a[14]_PORT_A_address_reg, GB1_q_a[14]_PORT_B_address_reg, GB1_q_a[14]_PORT_A_write_enable_reg, GB1_q_a[14]_PORT_B_write_enable_reg, , , GB1_q_a[14]_clock_0, GB1_q_a[14]_clock_1, GB1_q_a[14]_clock_enable_0, GB1_q_a[14]_clock_enable_1, , GB1_q_a[14]_clear_1);
GB1_q_a[14]_PORT_A_data_out_reg = DFFE(GB1_q_a[14]_PORT_A_data_out, GB1_q_a[14]_clock_0, GB1_q_a[14]_clear_1, , GB1_q_a[14]_clock_enable_0);
GB1_q_a[14] = GB1_q_a[14]_PORT_A_data_out_reg[0];


--GB2_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[14]_PORT_A_data_in = VCC;
GB2_q_a[14]_PORT_A_data_in_reg = DFFE(GB2_q_a[14]_PORT_A_data_in, GB2_q_a[14]_clock_0, , , GB2_q_a[14]_clock_enable_0);
GB2_q_a[14]_PORT_B_data_in = PB2_q_b[4];
GB2_q_a[14]_PORT_B_data_in_reg = DFFE(GB2_q_a[14]_PORT_B_data_in, GB2_q_a[14]_clock_1, , , GB2_q_a[14]_clock_enable_1);
GB2_q_a[14]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[14]_PORT_A_address_reg = DFFE(GB2_q_a[14]_PORT_A_address, GB2_q_a[14]_clock_0, , , GB2_q_a[14]_clock_enable_0);
GB2_q_a[14]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[14]_PORT_B_address_reg = DFFE(GB2_q_a[14]_PORT_B_address, GB2_q_a[14]_clock_1, , , GB2_q_a[14]_clock_enable_1);
GB2_q_a[14]_PORT_A_write_enable = GND;
GB2_q_a[14]_PORT_A_write_enable_reg = DFFE(GB2_q_a[14]_PORT_A_write_enable, GB2_q_a[14]_clock_0, , , GB2_q_a[14]_clock_enable_0);
GB2_q_a[14]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[14]_PORT_B_write_enable_reg = DFFE(GB2_q_a[14]_PORT_B_write_enable, GB2_q_a[14]_clock_1, , , GB2_q_a[14]_clock_enable_1);
GB2_q_a[14]_clock_0 = KB1__clk0;
GB2_q_a[14]_clock_1 = CCD_PIXCLK;
GB2_q_a[14]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[14]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[14]_clear_1 = !C1_oRST_0;
GB2_q_a[14]_PORT_A_data_out = MEMORY(GB2_q_a[14]_PORT_A_data_in_reg, GB2_q_a[14]_PORT_B_data_in_reg, GB2_q_a[14]_PORT_A_address_reg, GB2_q_a[14]_PORT_B_address_reg, GB2_q_a[14]_PORT_A_write_enable_reg, GB2_q_a[14]_PORT_B_write_enable_reg, , , GB2_q_a[14]_clock_0, GB2_q_a[14]_clock_1, GB2_q_a[14]_clock_enable_0, GB2_q_a[14]_clock_enable_1, , GB2_q_a[14]_clear_1);
GB2_q_a[14]_PORT_A_data_out_reg = DFFE(GB2_q_a[14]_PORT_A_data_out, GB2_q_a[14]_clock_0, GB2_q_a[14]_clear_1, , GB2_q_a[14]_clock_enable_0);
GB2_q_a[14] = GB2_q_a[14]_PORT_A_data_out_reg[0];


--G1L234 is Sdram_Control_4Port:u6|mDATAIN[14]~174
G1L234 = G1_WR_MASK[0] & GB1_q_a[14] # !G1_WR_MASK[0] & (GB2_q_a[14]);


--GB1_q_a[15] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[15]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[15]_PORT_A_data_in = VCC;
GB1_q_a[15]_PORT_A_data_in_reg = DFFE(GB1_q_a[15]_PORT_A_data_in, GB1_q_a[15]_clock_0, , , GB1_q_a[15]_clock_enable_0);
GB1_q_a[15]_PORT_B_data_in = ~GND;
GB1_q_a[15]_PORT_B_data_in_reg = DFFE(GB1_q_a[15]_PORT_B_data_in, GB1_q_a[15]_clock_1, , , GB1_q_a[15]_clock_enable_1);
GB1_q_a[15]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[15]_PORT_A_address_reg = DFFE(GB1_q_a[15]_PORT_A_address, GB1_q_a[15]_clock_0, , , GB1_q_a[15]_clock_enable_0);
GB1_q_a[15]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[15]_PORT_B_address_reg = DFFE(GB1_q_a[15]_PORT_B_address, GB1_q_a[15]_clock_1, , , GB1_q_a[15]_clock_enable_1);
GB1_q_a[15]_PORT_A_write_enable = GND;
GB1_q_a[15]_PORT_A_write_enable_reg = DFFE(GB1_q_a[15]_PORT_A_write_enable, GB1_q_a[15]_clock_0, , , GB1_q_a[15]_clock_enable_0);
GB1_q_a[15]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[15]_PORT_B_write_enable_reg = DFFE(GB1_q_a[15]_PORT_B_write_enable, GB1_q_a[15]_clock_1, , , GB1_q_a[15]_clock_enable_1);
GB1_q_a[15]_clock_0 = KB1__clk0;
GB1_q_a[15]_clock_1 = CCD_PIXCLK;
GB1_q_a[15]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[15]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[15]_clear_1 = !C1_oRST_0;
GB1_q_a[15]_PORT_A_data_out = MEMORY(GB1_q_a[15]_PORT_A_data_in_reg, GB1_q_a[15]_PORT_B_data_in_reg, GB1_q_a[15]_PORT_A_address_reg, GB1_q_a[15]_PORT_B_address_reg, GB1_q_a[15]_PORT_A_write_enable_reg, GB1_q_a[15]_PORT_B_write_enable_reg, , , GB1_q_a[15]_clock_0, GB1_q_a[15]_clock_1, GB1_q_a[15]_clock_enable_0, GB1_q_a[15]_clock_enable_1, , GB1_q_a[15]_clear_1);
GB1_q_a[15]_PORT_A_data_out_reg = DFFE(GB1_q_a[15]_PORT_A_data_out, GB1_q_a[15]_clock_0, GB1_q_a[15]_clear_1, , GB1_q_a[15]_clock_enable_0);
GB1_q_a[15] = GB1_q_a[15]_PORT_A_data_out_reg[0];


--GB2_q_a[15] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[15]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[15]_PORT_A_data_in = VCC;
GB2_q_a[15]_PORT_A_data_in_reg = DFFE(GB2_q_a[15]_PORT_A_data_in, GB2_q_a[15]_clock_0, , , GB2_q_a[15]_clock_enable_0);
GB2_q_a[15]_PORT_B_data_in = ~GND;
GB2_q_a[15]_PORT_B_data_in_reg = DFFE(GB2_q_a[15]_PORT_B_data_in, GB2_q_a[15]_clock_1, , , GB2_q_a[15]_clock_enable_1);
GB2_q_a[15]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[15]_PORT_A_address_reg = DFFE(GB2_q_a[15]_PORT_A_address, GB2_q_a[15]_clock_0, , , GB2_q_a[15]_clock_enable_0);
GB2_q_a[15]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[15]_PORT_B_address_reg = DFFE(GB2_q_a[15]_PORT_B_address, GB2_q_a[15]_clock_1, , , GB2_q_a[15]_clock_enable_1);
GB2_q_a[15]_PORT_A_write_enable = GND;
GB2_q_a[15]_PORT_A_write_enable_reg = DFFE(GB2_q_a[15]_PORT_A_write_enable, GB2_q_a[15]_clock_0, , , GB2_q_a[15]_clock_enable_0);
GB2_q_a[15]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[15]_PORT_B_write_enable_reg = DFFE(GB2_q_a[15]_PORT_B_write_enable, GB2_q_a[15]_clock_1, , , GB2_q_a[15]_clock_enable_1);
GB2_q_a[15]_clock_0 = KB1__clk0;
GB2_q_a[15]_clock_1 = CCD_PIXCLK;
GB2_q_a[15]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[15]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[15]_clear_1 = !C1_oRST_0;
GB2_q_a[15]_PORT_A_data_out = MEMORY(GB2_q_a[15]_PORT_A_data_in_reg, GB2_q_a[15]_PORT_B_data_in_reg, GB2_q_a[15]_PORT_A_address_reg, GB2_q_a[15]_PORT_B_address_reg, GB2_q_a[15]_PORT_A_write_enable_reg, GB2_q_a[15]_PORT_B_write_enable_reg, , , GB2_q_a[15]_clock_0, GB2_q_a[15]_clock_1, GB2_q_a[15]_clock_enable_0, GB2_q_a[15]_clock_enable_1, , GB2_q_a[15]_clear_1);
GB2_q_a[15]_PORT_A_data_out_reg = DFFE(GB2_q_a[15]_PORT_A_data_out, GB2_q_a[15]_clock_0, GB2_q_a[15]_clear_1, , GB2_q_a[15]_clock_enable_0);
GB2_q_a[15] = GB2_q_a[15]_PORT_A_data_out_reg[0];


--G1L235 is Sdram_Control_4Port:u6|mDATAIN[15]~175
G1L235 = G1_WR_MASK[0] & GB1_q_a[15] # !G1_WR_MASK[0] & (GB2_q_a[15]);


--LB1L44Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~reg0
LB1L44Q = DFFEAS(LB1L42, H1_mI2C_CTRL_CLK, KEY[1],  ,  , VCC,  ,  , !H1_mI2C_GO);


--LB1L50Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~reg0
LB1L50Q = DFFEAS(LB1L48, H1_mI2C_CTRL_CLK, KEY[1],  ,  , VCC,  ,  , !H1_mI2C_GO);


--LB1L53Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~reg0
LB1L53Q = DFFEAS(LB1L51, H1_mI2C_CTRL_CLK, KEY[1],  ,  , VCC,  ,  , !H1_mI2C_GO);


--LB1L47Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~reg0
LB1L47Q = DFFEAS(LB1L45, H1_mI2C_CTRL_CLK, KEY[1],  ,  , VCC,  ,  , !H1_mI2C_GO);


--LB1L15 is I2C_CCD_Config:u7|I2C_Controller:u0|I2C_SCLK~253
LB1L15 = LB1L44Q # LB1L50Q # LB1L53Q # LB1L47Q;


--LB1L56Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~reg0
LB1L56Q = DFFEAS(LB1L54, H1_mI2C_CTRL_CLK, KEY[1],  ,  , VCC,  ,  , !H1_mI2C_GO);


--LB1L16 is I2C_CCD_Config:u7|I2C_Controller:u0|I2C_SCLK~254
LB1L16 = LB1L56Q & (!LB1L53Q # !LB1L50Q) # !LB1L56Q & LB1L15;


--LB1L59Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[5]~reg0
LB1L59Q = DFFEAS(LB1L57, H1_mI2C_CTRL_CLK, KEY[1],  ,  , VCC,  ,  , !H1_mI2C_GO);


--H1_mI2C_CTRL_CLK is I2C_CCD_Config:u7|mI2C_CTRL_CLK
H1_mI2C_CTRL_CLK = DFFEAS(H1L92, CLOCK_50, KEY[1],  ,  ,  ,  ,  ,  );


--LB1_SCLK is I2C_CCD_Config:u7|I2C_Controller:u0|SCLK
LB1_SCLK = DFFEAS(LB1L23, H1_mI2C_CTRL_CLK, KEY[1],  ,  ,  ,  ,  ,  );


--LB1L17 is I2C_CCD_Config:u7|I2C_Controller:u0|I2C_SCLK~255
LB1L17 = LB1L16 & LB1L59Q & !H1_mI2C_CTRL_CLK # !LB1_SCLK;


--LB1L25Q is I2C_CCD_Config:u7|I2C_Controller:u0|SDO~reg0
LB1L25Q = DFFEAS(LB1L77, H1_mI2C_CTRL_CLK, KEY[1],  ,  ,  ,  ,  ,  );


--C1L3 is Reset_Delay:u2|Cont[0]~1196
C1L3 = C1_Cont[0] $ VCC;

--C1L4 is Reset_Delay:u2|Cont[0]~1197
C1L4 = CARRY(C1_Cont[0]);


--C1L6 is Reset_Delay:u2|Cont[1]~1198
C1L6 = C1_Cont[1] & !C1L4 # !C1_Cont[1] & (C1L4 # GND);

--C1L7 is Reset_Delay:u2|Cont[1]~1199
C1L7 = CARRY(!C1L4 # !C1_Cont[1]);


--C1L9 is Reset_Delay:u2|Cont[2]~1200
C1L9 = C1_Cont[2] & (C1L7 $ GND) # !C1_Cont[2] & !C1L7 & VCC;

--C1L10 is Reset_Delay:u2|Cont[2]~1201
C1L10 = CARRY(C1_Cont[2] & !C1L7);


--C1L12 is Reset_Delay:u2|Cont[3]~1202
C1L12 = C1_Cont[3] & !C1L10 # !C1_Cont[3] & (C1L10 # GND);

--C1L13 is Reset_Delay:u2|Cont[3]~1203
C1L13 = CARRY(!C1L10 # !C1_Cont[3]);


--C1L15 is Reset_Delay:u2|Cont[4]~1204
C1L15 = C1_Cont[4] & (C1L13 $ GND) # !C1_Cont[4] & !C1L13 & VCC;

--C1L16 is Reset_Delay:u2|Cont[4]~1205
C1L16 = CARRY(C1_Cont[4] & !C1L13);


--C1L18 is Reset_Delay:u2|Cont[5]~1206
C1L18 = C1_Cont[5] & !C1L16 # !C1_Cont[5] & (C1L16 # GND);

--C1L19 is Reset_Delay:u2|Cont[5]~1207
C1L19 = CARRY(!C1L16 # !C1_Cont[5]);


--C1L21 is Reset_Delay:u2|Cont[6]~1208
C1L21 = C1_Cont[6] & (C1L19 $ GND) # !C1_Cont[6] & !C1L19 & VCC;

--C1L22 is Reset_Delay:u2|Cont[6]~1209
C1L22 = CARRY(C1_Cont[6] & !C1L19);


--C1L24 is Reset_Delay:u2|Cont[7]~1210
C1L24 = C1_Cont[7] & !C1L22 # !C1_Cont[7] & (C1L22 # GND);

--C1L25 is Reset_Delay:u2|Cont[7]~1211
C1L25 = CARRY(!C1L22 # !C1_Cont[7]);


--C1L27 is Reset_Delay:u2|Cont[8]~1212
C1L27 = C1_Cont[8] & (C1L25 $ GND) # !C1_Cont[8] & !C1L25 & VCC;

--C1L28 is Reset_Delay:u2|Cont[8]~1213
C1L28 = CARRY(C1_Cont[8] & !C1L25);


--C1L30 is Reset_Delay:u2|Cont[9]~1214
C1L30 = C1_Cont[9] & !C1L28 # !C1_Cont[9] & (C1L28 # GND);

--C1L31 is Reset_Delay:u2|Cont[9]~1215
C1L31 = CARRY(!C1L28 # !C1_Cont[9]);


--C1L33 is Reset_Delay:u2|Cont[10]~1216
C1L33 = C1_Cont[10] & (C1L31 $ GND) # !C1_Cont[10] & !C1L31 & VCC;

--C1L34 is Reset_Delay:u2|Cont[10]~1217
C1L34 = CARRY(C1_Cont[10] & !C1L31);


--C1L36 is Reset_Delay:u2|Cont[11]~1218
C1L36 = C1_Cont[11] & !C1L34 # !C1_Cont[11] & (C1L34 # GND);

--C1L37 is Reset_Delay:u2|Cont[11]~1219
C1L37 = CARRY(!C1L34 # !C1_Cont[11]);


--C1L39 is Reset_Delay:u2|Cont[12]~1220
C1L39 = C1_Cont[12] & (C1L37 $ GND) # !C1_Cont[12] & !C1L37 & VCC;

--C1L40 is Reset_Delay:u2|Cont[12]~1221
C1L40 = CARRY(C1_Cont[12] & !C1L37);


--C1L42 is Reset_Delay:u2|Cont[13]~1222
C1L42 = C1_Cont[13] & !C1L40 # !C1_Cont[13] & (C1L40 # GND);

--C1L43 is Reset_Delay:u2|Cont[13]~1223
C1L43 = CARRY(!C1L40 # !C1_Cont[13]);


--C1L45 is Reset_Delay:u2|Cont[14]~1224
C1L45 = C1_Cont[14] & (C1L43 $ GND) # !C1_Cont[14] & !C1L43 & VCC;

--C1L46 is Reset_Delay:u2|Cont[14]~1225
C1L46 = CARRY(C1_Cont[14] & !C1L43);


--C1L48 is Reset_Delay:u2|Cont[15]~1226
C1L48 = C1_Cont[15] & !C1L46 # !C1_Cont[15] & (C1L46 # GND);

--C1L49 is Reset_Delay:u2|Cont[15]~1227
C1L49 = CARRY(!C1L46 # !C1_Cont[15]);


--C1L51 is Reset_Delay:u2|Cont[16]~1228
C1L51 = C1_Cont[16] & (C1L49 $ GND) # !C1_Cont[16] & !C1L49 & VCC;

--C1L52 is Reset_Delay:u2|Cont[16]~1229
C1L52 = CARRY(C1_Cont[16] & !C1L49);


--C1L54 is Reset_Delay:u2|Cont[17]~1230
C1L54 = C1_Cont[17] & !C1L52 # !C1_Cont[17] & (C1L52 # GND);

--C1L55 is Reset_Delay:u2|Cont[17]~1231
C1L55 = CARRY(!C1L52 # !C1_Cont[17]);


--C1L57 is Reset_Delay:u2|Cont[18]~1232
C1L57 = C1_Cont[18] & (C1L55 $ GND) # !C1_Cont[18] & !C1L55 & VCC;

--C1L58 is Reset_Delay:u2|Cont[18]~1233
C1L58 = CARRY(C1_Cont[18] & !C1L55);


--C1L60 is Reset_Delay:u2|Cont[19]~1234
C1L60 = C1_Cont[19] & !C1L58 # !C1_Cont[19] & (C1L58 # GND);

--C1L61 is Reset_Delay:u2|Cont[19]~1235
C1L61 = CARRY(!C1L58 # !C1_Cont[19]);


--C1L63 is Reset_Delay:u2|Cont[20]~1236
C1L63 = C1_Cont[20] & (C1L61 $ GND) # !C1_Cont[20] & !C1L61 & VCC;

--C1L64 is Reset_Delay:u2|Cont[20]~1237
C1L64 = CARRY(C1_Cont[20] & !C1L61);


--C1L66 is Reset_Delay:u2|Cont[21]~1238
C1L66 = C1_Cont[21] $ C1L64;


--C1L75 is Reset_Delay:u2|Equal~206
C1L75 = !C1L74 # !C1_Cont[20] # !C1_Cont[21];


--S1_LOAD_MODE is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE
S1_LOAD_MODE = DFFEAS(S1L16, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_command_done is Sdram_Control_4Port:u6|command:command1|command_done
R1_command_done = DFFEAS(R1L76, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L50 is Sdram_Control_4Port:u6|command:command1|always0~155
R1L50 = S1_LOAD_MODE & !R1_do_load_mode & !R1_command_done;


--S1_INIT_REQ is Sdram_Control_4Port:u6|control_interface:control1|INIT_REQ
S1_INIT_REQ = DFFEAS(S1L19, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_mADDR[8] is Sdram_Control_4Port:u6|mADDR[8]
G1_mADDR[8] = DFFEAS(G1L191, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--S1_WRITEA is Sdram_Control_4Port:u6|control_interface:control1|WRITEA
S1_WRITEA = DFFEAS(S1L2, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1_rp_done is Sdram_Control_4Port:u6|command:command1|rp_done
R1_rp_done = DFFEAS(R1L95, KB1__clk0,  ,  , R1L99,  ,  ,  ,  );


--R1L51 is Sdram_Control_4Port:u6|command:command1|always0~156
R1L51 = !R1_command_done & !R1_rp_done;


--S1_REF_REQ is Sdram_Control_4Port:u6|control_interface:control1|REF_REQ
S1_REF_REQ = DFFEAS(S1L32, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L49 is Sdram_Control_4Port:u6|command:command1|always0~13
R1L49 = S1_WRITEA & R1L51 & !R1_do_writea & !S1_REF_REQ;


--R1L86 is Sdram_Control_4Port:u6|command:command1|do_writea~38
R1L86 = R1L49 & !S1_INIT_REQ;


--S1_READA is Sdram_Control_4Port:u6|control_interface:control1|READA
S1_READA = DFFEAS(S1L8, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L52 is Sdram_Control_4Port:u6|command:command1|always0~157
R1L52 = !R1_do_reada & !R1_command_done & !R1_rp_done;


--R1L81 is Sdram_Control_4Port:u6|command:command1|do_reada~36
R1L81 = S1_READA & R1L52 & !S1_INIT_REQ & !S1_REF_REQ;


--G1_mWR_DONE is Sdram_Control_4Port:u6|mWR_DONE
G1_mWR_DONE = DFFEAS(G1L265, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1L266 is Sdram_Control_4Port:u6|mWR~611
G1L266 = !G1_mWR_DONE & (BB1L17 # !BB3L17);


--G1L115 is Sdram_Control_4Port:u6|WR_MASK[0]~150
G1L115 = G1L258 # G1_mWR_DONE;


--G1L260 is Sdram_Control_4Port:u6|mRD~737
G1L260 = BB3L17 & !BB1L17 & !G1_mRD_DONE;


--R1_CM_ACK is Sdram_Control_4Port:u6|command:command1|CM_ACK
R1_CM_ACK = DFFEAS(R1L9, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--S1L51 is Sdram_Control_4Port:u6|control_interface:control1|always1~0
S1L51 = R1_CM_ACK & !S1_CMD_ACK;


--G1_mADDR[9] is Sdram_Control_4Port:u6|mADDR[9]
G1_mADDR[9] = DFFEAS(G1L193, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[10] is Sdram_Control_4Port:u6|mADDR[10]
G1_mADDR[10] = DFFEAS(G1L195, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[11] is Sdram_Control_4Port:u6|mADDR[11]
G1_mADDR[11] = DFFEAS(G1L197, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[12] is Sdram_Control_4Port:u6|mADDR[12]
G1_mADDR[12] = DFFEAS(G1L199, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[13] is Sdram_Control_4Port:u6|mADDR[13]
G1_mADDR[13] = DFFEAS(G1L201, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[14] is Sdram_Control_4Port:u6|mADDR[14]
G1_mADDR[14] = DFFEAS(G1L203, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[15] is Sdram_Control_4Port:u6|mADDR[15]
G1_mADDR[15] = DFFEAS(G1L205, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[16] is Sdram_Control_4Port:u6|mADDR[16]
G1_mADDR[16] = DFFEAS(G1L207, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[17] is Sdram_Control_4Port:u6|mADDR[17]
G1_mADDR[17] = DFFEAS(G1L209, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[18] is Sdram_Control_4Port:u6|mADDR[18]
G1_mADDR[18] = DFFEAS(G1L211, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--S1_PRECHARGE is Sdram_Control_4Port:u6|control_interface:control1|PRECHARGE
S1_PRECHARGE = DFFEAS(S1L27, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L53 is Sdram_Control_4Port:u6|command:command1|always0~158
R1L53 = S1_PRECHARGE & !R1_do_precharge & !R1_command_done;


--R1_rw_shift[0] is Sdram_Control_4Port:u6|command:command1|rw_shift[0]
R1_rw_shift[0] = DFFEAS(R1L114, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L84 is Sdram_Control_4Port:u6|command:command1|do_rw~49
R1L84 = R1_do_writea & R1_do_rw # !R1_do_writea & (R1_do_reada & R1_do_rw # !R1_do_reada & (R1_rw_shift[0]));


--G1_mADDR[19] is Sdram_Control_4Port:u6|mADDR[19]
G1_mADDR[19] = DFFEAS(G1L213, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--R1L54 is Sdram_Control_4Port:u6|command:command1|always0~159
R1L54 = !R1_do_writea & !R1_do_refresh;


--S1_REFRESH is Sdram_Control_4Port:u6|control_interface:control1|REFRESH
S1_REFRESH = DFFEAS(S1L30, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L55 is Sdram_Control_4Port:u6|command:command1|always0~160
R1L55 = R1L52 & R1L54 & (S1_REF_REQ # S1_REFRESH);


--R1L110 is Sdram_Control_4Port:u6|command:command1|rw_flag~25
R1L110 = R1_do_reada # R1_rw_flag & R1L109 & R1L54;


--R1L92 is Sdram_Control_4Port:u6|command:command1|oe4~33
R1L92 = !R1_do_reada & !R1_do_precharge & !R1_do_refresh & !R1_do_initial;


--G1_PM_STOP is Sdram_Control_4Port:u6|PM_STOP
G1_PM_STOP = DFFEAS(G1L19, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L93 is Sdram_Control_4Port:u6|command:command1|oe4~34
R1L93 = R1_do_writea # R1_oe4 & R1L92 & !G1_PM_STOP;


--G1_mADDR[22] is Sdram_Control_4Port:u6|mADDR[22]
G1_mADDR[22] = DFFEAS(G1L215, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[20] is Sdram_Control_4Port:u6|mADDR[20]
G1_mADDR[20] = DFFEAS(G1L217, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--G1_mADDR[21] is Sdram_Control_4Port:u6|mADDR[21]
G1_mADDR[21] = DFFEAS(G1L219, KB1__clk0,  ,  , G1L258,  ,  ,  ,  );


--AB11_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor7
AB11_xor7 = X3_wrptr_g[7] $ X3_wrptr_g[8];


--AB12_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor7
AB12_xor7 = JB3_dffe9a[8] $ JB3_dffe9a[7];


--AB11_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor6
AB11_xor6 = X3_wrptr_g[6] $ X3_wrptr_g[7] $ X3_wrptr_g[8];


--AB12_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor6
AB12_xor6 = JB3_dffe9a[6] $ JB3_dffe9a[8] $ JB3_dffe9a[7];


--AB11_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor5
AB11_xor5 = X3_wrptr_g[5] $ X3_wrptr_g[6] $ X3_wrptr_g[7] $ X3_wrptr_g[8];


--AB12_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor5
AB12_xor5 = JB3_dffe9a[6] $ JB3_dffe9a[8] $ JB3_dffe9a[5] $ JB3_dffe9a[7];


--AB11_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor4
AB11_xor4 = X3_wrptr_g[4] $ AB11_xor5;


--AB12_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor4
AB12_xor4 = JB3_dffe9a[4] $ AB12_xor5;


--AB11_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor3
AB11_xor3 = X3_wrptr_g[3] $ X3_wrptr_g[4] $ AB11_xor5;


--AB12_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor3
AB12_xor3 = JB3_dffe9a[3] $ JB3_dffe9a[4] $ AB12_xor5;


--AB11_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor2
AB11_xor2 = X3_wrptr_g[2] $ X3_wrptr_g[3] $ X3_wrptr_g[4] $ AB11_xor5;


--AB12_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor2
AB12_xor2 = JB3_dffe9a[2] $ JB3_dffe9a[3] $ JB3_dffe9a[4] $ AB12_xor5;


--AB11_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor1
AB11_xor1 = X3_wrptr_g[1] $ AB11_xor2;


--AB12_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor1
AB12_xor1 = JB3_dffe9a[1] $ AB12_xor2;


--AB11_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor0
AB11_xor0 = X3_wrptr_g[0] $ X3_wrptr_g[1] $ AB11_xor2;


--AB12_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor0
AB12_xor0 = JB3_dffe9a[0] $ JB3_dffe9a[1] $ AB12_xor2;


--HB1_dffe7a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[8]
HB1_dffe7a[8] = DFFEAS(X1_delayed_wrptr_g[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1_rdptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8]
X1_rdptr_g[8] = DFFEAS(Z1_power_modified_counter_values[8], KB1__clk0, C1_oRST_0,  , X1_valid_rdreq,  ,  ,  ,  );


--HB1_dffe7a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[7]
HB1_dffe7a[7] = DFFEAS(X1_delayed_wrptr_g[7], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB2_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor7
AB2_xor7 = HB1_dffe7a[8] $ HB1_dffe7a[7];


--X1_rdptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[7]
X1_rdptr_g[7] = DFFEAS(Z1_power_modified_counter_values[7], KB1__clk0, C1_oRST_0,  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor7
AB1_xor7 = X1_rdptr_g[8] $ X1_rdptr_g[7];


--HB1_dffe7a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[6]
HB1_dffe7a[6] = DFFEAS(X1_delayed_wrptr_g[6], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB2_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor6
AB2_xor6 = HB1_dffe7a[8] $ HB1_dffe7a[7] $ HB1_dffe7a[6];


--X1_rdptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[6]
X1_rdptr_g[6] = DFFEAS(Z1_power_modified_counter_values[6], KB1__clk0, C1_oRST_0,  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor6
AB1_xor6 = X1_rdptr_g[8] $ X1_rdptr_g[7] $ X1_rdptr_g[6];


--HB1_dffe7a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[5]
HB1_dffe7a[5] = DFFEAS(X1_delayed_wrptr_g[5], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB2_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor5
AB2_xor5 = HB1_dffe7a[8] $ HB1_dffe7a[7] $ HB1_dffe7a[6] $ HB1_dffe7a[5];


--X1_rdptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[5]
X1_rdptr_g[5] = DFFEAS(Z1_power_modified_counter_values[5], KB1__clk0, C1_oRST_0,  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor5
AB1_xor5 = X1_rdptr_g[8] $ X1_rdptr_g[7] $ X1_rdptr_g[6] $ X1_rdptr_g[5];


--HB1_dffe7a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4]
HB1_dffe7a[4] = DFFEAS(X1_delayed_wrptr_g[4], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB2_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor4
AB2_xor4 = AB2_xor5 $ HB1_dffe7a[4];


--X1_rdptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4]
X1_rdptr_g[4] = DFFEAS(Z1_power_modified_counter_values[4], KB1__clk0, C1_oRST_0,  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor4
AB1_xor4 = AB1_xor5 $ X1_rdptr_g[4];


--HB1_dffe7a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[3]
HB1_dffe7a[3] = DFFEAS(X1_delayed_wrptr_g[3], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB2_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor3
AB2_xor3 = AB2_xor5 $ HB1_dffe7a[4] $ HB1_dffe7a[3];


--X1_rdptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[3]
X1_rdptr_g[3] = DFFEAS(Z1_power_modified_counter_values[3], KB1__clk0, C1_oRST_0,  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor3
AB1_xor3 = AB1_xor5 $ X1_rdptr_g[4] $ X1_rdptr_g[3];


--HB1_dffe7a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[2]
HB1_dffe7a[2] = DFFEAS(X1_delayed_wrptr_g[2], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB2_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor2
AB2_xor2 = AB2_xor5 $ HB1_dffe7a[4] $ HB1_dffe7a[3] $ HB1_dffe7a[2];


--X1_rdptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2]
X1_rdptr_g[2] = DFFEAS(Z1_power_modified_counter_values[2], KB1__clk0, C1_oRST_0,  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor2
AB1_xor2 = AB1_xor5 $ X1_rdptr_g[4] $ X1_rdptr_g[3] $ X1_rdptr_g[2];


--HB1_dffe7a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1]
HB1_dffe7a[1] = DFFEAS(X1_delayed_wrptr_g[1], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB2_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor1
AB2_xor1 = AB2_xor2 $ HB1_dffe7a[1];


--X1_rdptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[1]
X1_rdptr_g[1] = DFFEAS(Z1_power_modified_counter_values[1], KB1__clk0, C1_oRST_0,  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor1
AB1_xor1 = AB1_xor2 $ X1_rdptr_g[1];


--HB1_dffe7a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0]
HB1_dffe7a[0] = DFFEAS(X1_delayed_wrptr_g[0], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB2_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor0
AB2_xor0 = AB2_xor2 $ HB1_dffe7a[1] $ HB1_dffe7a[0];


--X1_rdptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0]
X1_rdptr_g[0] = DFFEAS(Z1_power_modified_counter_values[0], KB1__clk0, C1_oRST_0,  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor0
AB1_xor0 = AB1_xor2 $ X1_rdptr_g[1] $ X1_rdptr_g[0];


--G1L254 is Sdram_Control_4Port:u6|mRD_DONE~77
G1L254 = G1_Read & (G1_mRD_DONE # !G1L26 & !G1L27);


--HB2_dffe7a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[8]
HB2_dffe7a[8] = DFFEAS(X2_delayed_wrptr_g[8], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2_rdptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8]
X2_rdptr_g[8] = DFFEAS(Z2_power_modified_counter_values[8], KB1__clk0, C1_oRST_0,  , X2_valid_rdreq,  ,  ,  ,  );


--HB2_dffe7a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[7]
HB2_dffe7a[7] = DFFEAS(X2_delayed_wrptr_g[7], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB6_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor7
AB6_xor7 = HB2_dffe7a[8] $ HB2_dffe7a[7];


--X2_rdptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[7]
X2_rdptr_g[7] = DFFEAS(Z2_power_modified_counter_values[7], KB1__clk0, C1_oRST_0,  , X2_valid_rdreq,  ,  ,  ,  );


--AB5_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor7
AB5_xor7 = X2_rdptr_g[8] $ X2_rdptr_g[7];


--HB2_dffe7a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[6]
HB2_dffe7a[6] = DFFEAS(X2_delayed_wrptr_g[6], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB6_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor6
AB6_xor6 = HB2_dffe7a[8] $ HB2_dffe7a[7] $ HB2_dffe7a[6];


--X2_rdptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[6]
X2_rdptr_g[6] = DFFEAS(Z2_power_modified_counter_values[6], KB1__clk0, C1_oRST_0,  , X2_valid_rdreq,  ,  ,  ,  );


--AB5_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor6
AB5_xor6 = X2_rdptr_g[8] $ X2_rdptr_g[7] $ X2_rdptr_g[6];


--HB2_dffe7a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[5]
HB2_dffe7a[5] = DFFEAS(X2_delayed_wrptr_g[5], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB6_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor5
AB6_xor5 = HB2_dffe7a[8] $ HB2_dffe7a[7] $ HB2_dffe7a[6] $ HB2_dffe7a[5];


--X2_rdptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[5]
X2_rdptr_g[5] = DFFEAS(Z2_power_modified_counter_values[5], KB1__clk0, C1_oRST_0,  , X2_valid_rdreq,  ,  ,  ,  );


--AB5_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor5
AB5_xor5 = X2_rdptr_g[8] $ X2_rdptr_g[7] $ X2_rdptr_g[6] $ X2_rdptr_g[5];


--HB2_dffe7a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4]
HB2_dffe7a[4] = DFFEAS(X2_delayed_wrptr_g[4], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB6_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor4
AB6_xor4 = AB6_xor5 $ HB2_dffe7a[4];


--X2_rdptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4]
X2_rdptr_g[4] = DFFEAS(Z2_power_modified_counter_values[4], KB1__clk0, C1_oRST_0,  , X2_valid_rdreq,  ,  ,  ,  );


--AB5_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor4
AB5_xor4 = AB5_xor5 $ X2_rdptr_g[4];


--HB2_dffe7a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[3]
HB2_dffe7a[3] = DFFEAS(X2_delayed_wrptr_g[3], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB6_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor3
AB6_xor3 = AB6_xor5 $ HB2_dffe7a[4] $ HB2_dffe7a[3];


--X2_rdptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[3]
X2_rdptr_g[3] = DFFEAS(Z2_power_modified_counter_values[3], KB1__clk0, C1_oRST_0,  , X2_valid_rdreq,  ,  ,  ,  );


--AB5_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor3
AB5_xor3 = AB5_xor5 $ X2_rdptr_g[4] $ X2_rdptr_g[3];


--HB2_dffe7a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[2]
HB2_dffe7a[2] = DFFEAS(X2_delayed_wrptr_g[2], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB6_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor2
AB6_xor2 = AB6_xor5 $ HB2_dffe7a[4] $ HB2_dffe7a[3] $ HB2_dffe7a[2];


--X2_rdptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2]
X2_rdptr_g[2] = DFFEAS(Z2_power_modified_counter_values[2], KB1__clk0, C1_oRST_0,  , X2_valid_rdreq,  ,  ,  ,  );


--AB5_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor2
AB5_xor2 = AB5_xor5 $ X2_rdptr_g[4] $ X2_rdptr_g[3] $ X2_rdptr_g[2];


--HB2_dffe7a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1]
HB2_dffe7a[1] = DFFEAS(X2_delayed_wrptr_g[1], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB6_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor1
AB6_xor1 = AB6_xor2 $ HB2_dffe7a[1];


--X2_rdptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[1]
X2_rdptr_g[1] = DFFEAS(Z2_power_modified_counter_values[1], KB1__clk0, C1_oRST_0,  , X2_valid_rdreq,  ,  ,  ,  );


--AB5_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor1
AB5_xor1 = AB5_xor2 $ X2_rdptr_g[1];


--HB2_dffe7a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0]
HB2_dffe7a[0] = DFFEAS(X2_delayed_wrptr_g[0], KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--AB6_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor0
AB6_xor0 = AB6_xor2 $ HB2_dffe7a[1] $ HB2_dffe7a[0];


--X2_rdptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0]
X2_rdptr_g[0] = DFFEAS(Z2_power_modified_counter_values[0], KB1__clk0, C1_oRST_0,  , X2_valid_rdreq,  ,  ,  ,  );


--AB5_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor0
AB5_xor0 = AB5_xor2 $ X2_rdptr_g[1] $ X2_rdptr_g[0];


--AB15_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor7
AB15_xor7 = X4_wrptr_g[7] $ X4_wrptr_g[8];


--AB16_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor7
AB16_xor7 = JB4_dffe9a[8] $ JB4_dffe9a[7];


--AB15_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor6
AB15_xor6 = X4_wrptr_g[6] $ X4_wrptr_g[7] $ X4_wrptr_g[8];


--AB16_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor6
AB16_xor6 = JB4_dffe9a[6] $ JB4_dffe9a[8] $ JB4_dffe9a[7];


--AB15_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor5
AB15_xor5 = X4_wrptr_g[5] $ X4_wrptr_g[6] $ X4_wrptr_g[7] $ X4_wrptr_g[8];


--AB16_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor5
AB16_xor5 = JB4_dffe9a[6] $ JB4_dffe9a[8] $ JB4_dffe9a[5] $ JB4_dffe9a[7];


--AB15_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor4
AB15_xor4 = X4_wrptr_g[4] $ AB15_xor5;


--AB16_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor4
AB16_xor4 = JB4_dffe9a[4] $ AB16_xor5;


--AB15_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor3
AB15_xor3 = X4_wrptr_g[3] $ X4_wrptr_g[4] $ AB15_xor5;


--AB16_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor3
AB16_xor3 = JB4_dffe9a[3] $ JB4_dffe9a[4] $ AB16_xor5;


--AB15_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor2
AB15_xor2 = X4_wrptr_g[2] $ X4_wrptr_g[3] $ X4_wrptr_g[4] $ AB15_xor5;


--AB16_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor2
AB16_xor2 = JB4_dffe9a[2] $ JB4_dffe9a[3] $ JB4_dffe9a[4] $ AB16_xor5;


--AB15_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor1
AB15_xor1 = X4_wrptr_g[1] $ AB15_xor2;


--AB16_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor1
AB16_xor1 = JB4_dffe9a[1] $ AB16_xor2;


--AB15_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor0
AB15_xor0 = X4_wrptr_g[0] $ X4_wrptr_g[1] $ AB15_xor2;


--AB16_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor0
AB16_xor0 = JB4_dffe9a[0] $ JB4_dffe9a[1] $ AB16_xor2;


--G1L117 is Sdram_Control_4Port:u6|WR_MASK~151
G1L117 = !BB1L17 & !BB3L17 & !G1_mWR_DONE;


--G1L118 is Sdram_Control_4Port:u6|WR_MASK~152
G1L118 = BB1L17 & !G1_mWR_DONE;


--G1_IN_REQ is Sdram_Control_4Port:u6|IN_REQ
G1_IN_REQ = DFFEAS(G1L31, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--X1L1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|_~7
X1L1 = HB1_dffe7a[7] $ X1_rdptr_g[7];


--X1L13 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~55
X1L13 = HB1_dffe7a[2] & X1_rdptr_g[2] & (HB1_dffe7a[0] $ !X1_rdptr_g[0]) # !HB1_dffe7a[2] & !X1_rdptr_g[2] & (HB1_dffe7a[0] $ !X1_rdptr_g[0]);


--X1L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~56
X1L14 = HB1_dffe7a[6] & X1_rdptr_g[6] & (HB1_dffe7a[1] $ !X1_rdptr_g[1]) # !HB1_dffe7a[6] & !X1_rdptr_g[6] & (HB1_dffe7a[1] $ !X1_rdptr_g[1]);


--X1L15 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~57
X1L15 = HB1_dffe7a[8] & X1_rdptr_g[8] & (HB1_dffe7a[3] $ !X1_rdptr_g[3]) # !HB1_dffe7a[8] & !X1_rdptr_g[8] & (HB1_dffe7a[3] $ !X1_rdptr_g[3]);


--X1L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~58
X1L16 = HB1_dffe7a[5] & X1_rdptr_g[5] & (HB1_dffe7a[4] $ !X1_rdptr_g[4]) # !HB1_dffe7a[5] & !X1_rdptr_g[5] & (HB1_dffe7a[4] $ !X1_rdptr_g[4]);


--X1L17 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~59
X1L17 = X1L13 & X1L14 & X1L15 & X1L16;


--X1_valid_rdreq is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq
X1_valid_rdreq = G1_WR_MASK[0] & G1_IN_REQ & (X1L1 # !X1L17);


--X2_p0addr is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|p0addr
X2_p0addr = DFFEAS(VCC, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--X1_rdcnt_addr_ena is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdcnt_addr_ena
X1_rdcnt_addr_ena = X1_valid_rdreq # !X2_p0addr;


--J1_mCCD_DVAL is Mirror_Col:u8|mCCD_DVAL
J1_mCCD_DVAL = DFFEAS(E1_mDVAL, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--JB1_dffe9a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[7]
JB1_dffe9a[7] = DFFEAS(X1_rdptr_g[7], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[7]
EB1_power_modified_counter_values[7] = DFFEAS(EB1_countera7, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB1_dffe9a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[2]
JB1_dffe9a[2] = DFFEAS(X1_rdptr_g[2], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[2]
EB1_power_modified_counter_values[2] = DFFEAS(EB1_countera2, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB1_dffe9a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[0]
JB1_dffe9a[0] = DFFEAS(X1_rdptr_g[0], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB1_counter_ffa[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|counter_ffa[0]
EB1_counter_ffa[0] = DFFEAS(EB1_countera0, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1L30 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~54
X1L30 = JB1_dffe9a[2] & EB1_power_modified_counter_values[2] & (JB1_dffe9a[0] $ EB1_counter_ffa[0]) # !JB1_dffe9a[2] & !EB1_power_modified_counter_values[2] & (JB1_dffe9a[0] $ EB1_counter_ffa[0]);


--JB1_dffe9a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[6]
JB1_dffe9a[6] = DFFEAS(X1_rdptr_g[6], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB1_dffe9a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[1]
JB1_dffe9a[1] = DFFEAS(X1_rdptr_g[1], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[1]
EB1_power_modified_counter_values[1] = DFFEAS(EB1_countera1, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[6]
EB1_power_modified_counter_values[6] = DFFEAS(EB1_countera6, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1L31 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~55
X1L31 = JB1_dffe9a[6] & EB1_power_modified_counter_values[6] & (JB1_dffe9a[1] $ !EB1_power_modified_counter_values[1]) # !JB1_dffe9a[6] & !EB1_power_modified_counter_values[6] & (JB1_dffe9a[1] $ !EB1_power_modified_counter_values[1]);


--JB1_dffe9a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[3]
JB1_dffe9a[3] = DFFEAS(X1_rdptr_g[3], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB1_dffe9a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[8]
JB1_dffe9a[8] = DFFEAS(X1_rdptr_g[8], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[8]
EB1_power_modified_counter_values[8] = DFFEAS(EB1_countera8, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[3]
EB1_power_modified_counter_values[3] = DFFEAS(EB1_countera3, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1L32 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~56
X1L32 = JB1_dffe9a[3] & EB1_power_modified_counter_values[3] & (JB1_dffe9a[8] $ !EB1_power_modified_counter_values[8]) # !JB1_dffe9a[3] & !EB1_power_modified_counter_values[3] & (JB1_dffe9a[8] $ !EB1_power_modified_counter_values[8]);


--JB1_dffe9a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5]
JB1_dffe9a[5] = DFFEAS(X1_rdptr_g[5], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB1_dffe9a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[4]
JB1_dffe9a[4] = DFFEAS(X1_rdptr_g[4], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[4]
EB1_power_modified_counter_values[4] = DFFEAS(EB1_countera4, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[5]
EB1_power_modified_counter_values[5] = DFFEAS(EB1_countera5, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1L33 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~57
X1L33 = JB1_dffe9a[5] & EB1_power_modified_counter_values[5] & (JB1_dffe9a[4] $ !EB1_power_modified_counter_values[4]) # !JB1_dffe9a[5] & !EB1_power_modified_counter_values[5] & (JB1_dffe9a[4] $ !EB1_power_modified_counter_values[4]);


--X1L34 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~58
X1L34 = X1L30 & X1L31 & X1L32 & X1L33;


--X1_valid_wrreq is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_wrreq
X1_valid_wrreq = J1_mCCD_DVAL & (JB1_dffe9a[7] $ EB1_power_modified_counter_values[7] # !X1L34);


--Z1_power_modified_counter_values[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[0]
Z1_power_modified_counter_values[0] = DFFEAS(Z1_countera0, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[1]
Z1_power_modified_counter_values[1] = DFFEAS(Z1_countera1, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[2]
Z1_power_modified_counter_values[2] = DFFEAS(Z1_countera2, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[3]
Z1_power_modified_counter_values[3] = DFFEAS(Z1_countera3, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[4]
Z1_power_modified_counter_values[4] = DFFEAS(Z1_countera4, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[5]
Z1_power_modified_counter_values[5] = DFFEAS(Z1_countera5, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[6]
Z1_power_modified_counter_values[6] = DFFEAS(Z1_countera6, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[7]
Z1_power_modified_counter_values[7] = DFFEAS(Z1_countera7, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8]
Z1_power_modified_counter_values[8] = DFFEAS(Z1_countera8, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--PB3_q_b[0] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB3_q_b[0]_PORT_A_data_in = E1_mCCD_B[0];
PB3_q_b[0]_PORT_A_data_in_reg = DFFE(PB3_q_b[0]_PORT_A_data_in, PB3_q_b[0]_clock_0, , , PB3_q_b[0]_clock_enable_0);
PB3_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB3_q_b[0]_PORT_A_address_reg = DFFE(PB3_q_b[0]_PORT_A_address, PB3_q_b[0]_clock_0, , , PB3_q_b[0]_clock_enable_0);
PB3_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB3_q_b[0]_PORT_B_address_reg = DFFE(PB3_q_b[0]_PORT_B_address, PB3_q_b[0]_clock_1, , , );
PB3_q_b[0]_PORT_A_write_enable = VCC;
PB3_q_b[0]_PORT_A_write_enable_reg = DFFE(PB3_q_b[0]_PORT_A_write_enable, PB3_q_b[0]_clock_0, , , PB3_q_b[0]_clock_enable_0);
PB3_q_b[0]_PORT_B_read_enable = VCC;
PB3_q_b[0]_PORT_B_read_enable_reg = DFFE(PB3_q_b[0]_PORT_B_read_enable, PB3_q_b[0]_clock_1, , , );
PB3_q_b[0]_clock_0 = CCD_PIXCLK;
PB3_q_b[0]_clock_1 = CCD_PIXCLK;
PB3_q_b[0]_clock_enable_0 = E1_mDVAL;
PB3_q_b[0]_PORT_B_data_out = MEMORY(PB3_q_b[0]_PORT_A_data_in_reg, , PB3_q_b[0]_PORT_A_address_reg, PB3_q_b[0]_PORT_B_address_reg, PB3_q_b[0]_PORT_A_write_enable_reg, PB3_q_b[0]_PORT_B_read_enable_reg, , , PB3_q_b[0]_clock_0, PB3_q_b[0]_clock_1, PB3_q_b[0]_clock_enable_0, , , );
PB3_q_b[0]_PORT_B_data_out_reg = DFFE(PB3_q_b[0]_PORT_B_data_out, PB3_q_b[0]_clock_1, , , );
PB3_q_b[0] = PB3_q_b[0]_PORT_B_data_out_reg[0];


--X1_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]
X1_wrptr_g[0] = DFFEAS(X1L37, CCD_PIXCLK, C1_oRST_0,  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[1]
X1_wrptr_g[1] = DFFEAS(EB1_power_modified_counter_values[1], CCD_PIXCLK, C1_oRST_0,  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2]
X1_wrptr_g[2] = DFFEAS(EB1_power_modified_counter_values[2], CCD_PIXCLK, C1_oRST_0,  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[3]
X1_wrptr_g[3] = DFFEAS(EB1_power_modified_counter_values[3], CCD_PIXCLK, C1_oRST_0,  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[4]
X1_wrptr_g[4] = DFFEAS(EB1_power_modified_counter_values[4], CCD_PIXCLK, C1_oRST_0,  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5]
X1_wrptr_g[5] = DFFEAS(EB1_power_modified_counter_values[5], CCD_PIXCLK, C1_oRST_0,  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6]
X1_wrptr_g[6] = DFFEAS(EB1_power_modified_counter_values[6], CCD_PIXCLK, C1_oRST_0,  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[7]
X1_wrptr_g[7] = DFFEAS(EB1_power_modified_counter_values[7], CCD_PIXCLK, C1_oRST_0,  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8]
X1_wrptr_g[8] = DFFEAS(EB1_power_modified_counter_values[8], CCD_PIXCLK, C1_oRST_0,  , X1_valid_wrreq,  ,  ,  ,  );


--X2L1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|_~7
X2L1 = HB2_dffe7a[7] $ X2_rdptr_g[7];


--X2L15 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~55
X2L15 = HB2_dffe7a[2] & X2_rdptr_g[2] & (HB2_dffe7a[0] $ !X2_rdptr_g[0]) # !HB2_dffe7a[2] & !X2_rdptr_g[2] & (HB2_dffe7a[0] $ !X2_rdptr_g[0]);


--X2L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~56
X2L16 = HB2_dffe7a[6] & X2_rdptr_g[6] & (HB2_dffe7a[1] $ !X2_rdptr_g[1]) # !HB2_dffe7a[6] & !X2_rdptr_g[6] & (HB2_dffe7a[1] $ !X2_rdptr_g[1]);


--X2L17 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~57
X2L17 = HB2_dffe7a[8] & X2_rdptr_g[8] & (HB2_dffe7a[3] $ !X2_rdptr_g[3]) # !HB2_dffe7a[8] & !X2_rdptr_g[8] & (HB2_dffe7a[3] $ !X2_rdptr_g[3]);


--X2L18 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~58
X2L18 = HB2_dffe7a[5] & X2_rdptr_g[5] & (HB2_dffe7a[4] $ !X2_rdptr_g[4]) # !HB2_dffe7a[5] & !X2_rdptr_g[5] & (HB2_dffe7a[4] $ !X2_rdptr_g[4]);


--X2L19 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~59
X2L19 = X2L15 & X2L16 & X2L17 & X2L18;


--X2_valid_rdreq is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq
X2_valid_rdreq = G1_WR_MASK[1] & G1_IN_REQ & (X2L1 # !X2L19);


--X2_rdcnt_addr_ena is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdcnt_addr_ena
X2_rdcnt_addr_ena = X2_valid_rdreq # !X2_p0addr;


--JB2_dffe9a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[7]
JB2_dffe9a[7] = DFFEAS(X2_rdptr_g[7], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[7]
EB2_power_modified_counter_values[7] = DFFEAS(EB2_countera7, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB2_dffe9a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[2]
JB2_dffe9a[2] = DFFEAS(X2_rdptr_g[2], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[2]
EB2_power_modified_counter_values[2] = DFFEAS(EB2_countera2, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB2_dffe9a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[0]
JB2_dffe9a[0] = DFFEAS(X2_rdptr_g[0], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB2_counter_ffa[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|counter_ffa[0]
EB2_counter_ffa[0] = DFFEAS(EB2_countera0, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2L32 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~54
X2L32 = JB2_dffe9a[2] & EB2_power_modified_counter_values[2] & (JB2_dffe9a[0] $ EB2_counter_ffa[0]) # !JB2_dffe9a[2] & !EB2_power_modified_counter_values[2] & (JB2_dffe9a[0] $ EB2_counter_ffa[0]);


--JB2_dffe9a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[6]
JB2_dffe9a[6] = DFFEAS(X2_rdptr_g[6], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB2_dffe9a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[1]
JB2_dffe9a[1] = DFFEAS(X2_rdptr_g[1], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[1]
EB2_power_modified_counter_values[1] = DFFEAS(EB2_countera1, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[6]
EB2_power_modified_counter_values[6] = DFFEAS(EB2_countera6, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2L33 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~55
X2L33 = JB2_dffe9a[6] & EB2_power_modified_counter_values[6] & (JB2_dffe9a[1] $ !EB2_power_modified_counter_values[1]) # !JB2_dffe9a[6] & !EB2_power_modified_counter_values[6] & (JB2_dffe9a[1] $ !EB2_power_modified_counter_values[1]);


--JB2_dffe9a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[3]
JB2_dffe9a[3] = DFFEAS(X2_rdptr_g[3], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB2_dffe9a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[8]
JB2_dffe9a[8] = DFFEAS(X2_rdptr_g[8], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[8]
EB2_power_modified_counter_values[8] = DFFEAS(EB2_countera8, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[3]
EB2_power_modified_counter_values[3] = DFFEAS(EB2_countera3, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2L34 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~56
X2L34 = JB2_dffe9a[3] & EB2_power_modified_counter_values[3] & (JB2_dffe9a[8] $ !EB2_power_modified_counter_values[8]) # !JB2_dffe9a[3] & !EB2_power_modified_counter_values[3] & (JB2_dffe9a[8] $ !EB2_power_modified_counter_values[8]);


--JB2_dffe9a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5]
JB2_dffe9a[5] = DFFEAS(X2_rdptr_g[5], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--JB2_dffe9a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[4]
JB2_dffe9a[4] = DFFEAS(X2_rdptr_g[4], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[4]
EB2_power_modified_counter_values[4] = DFFEAS(EB2_countera4, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[5]
EB2_power_modified_counter_values[5] = DFFEAS(EB2_countera5, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2L35 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~57
X2L35 = JB2_dffe9a[5] & EB2_power_modified_counter_values[5] & (JB2_dffe9a[4] $ !EB2_power_modified_counter_values[4]) # !JB2_dffe9a[5] & !EB2_power_modified_counter_values[5] & (JB2_dffe9a[4] $ !EB2_power_modified_counter_values[4]);


--X2L36 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~58
X2L36 = X2L32 & X2L33 & X2L34 & X2L35;


--X2_valid_wrreq is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_wrreq
X2_valid_wrreq = J1_mCCD_DVAL & (JB2_dffe9a[7] $ EB2_power_modified_counter_values[7] # !X2L36);


--Z2_power_modified_counter_values[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[0]
Z2_power_modified_counter_values[0] = DFFEAS(Z2_countera0, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[1]
Z2_power_modified_counter_values[1] = DFFEAS(Z2_countera1, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[2]
Z2_power_modified_counter_values[2] = DFFEAS(Z2_countera2, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[3]
Z2_power_modified_counter_values[3] = DFFEAS(Z2_countera3, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[4]
Z2_power_modified_counter_values[4] = DFFEAS(Z2_countera4, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[5]
Z2_power_modified_counter_values[5] = DFFEAS(Z2_countera5, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[6]
Z2_power_modified_counter_values[6] = DFFEAS(Z2_countera6, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[7]
Z2_power_modified_counter_values[7] = DFFEAS(Z2_countera7, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8]
Z2_power_modified_counter_values[8] = DFFEAS(Z2_countera8, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--PB1_q_b[0] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[0]_PORT_A_data_in = E1_mCCD_R[0];
PB1_q_b[0]_PORT_A_data_in_reg = DFFE(PB1_q_b[0]_PORT_A_data_in, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[0]_PORT_A_address_reg = DFFE(PB1_q_b[0]_PORT_A_address, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[0]_PORT_B_address_reg = DFFE(PB1_q_b[0]_PORT_B_address, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0]_PORT_A_write_enable = VCC;
PB1_q_b[0]_PORT_A_write_enable_reg = DFFE(PB1_q_b[0]_PORT_A_write_enable, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_B_read_enable = VCC;
PB1_q_b[0]_PORT_B_read_enable_reg = DFFE(PB1_q_b[0]_PORT_B_read_enable, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0]_clock_0 = CCD_PIXCLK;
PB1_q_b[0]_clock_1 = CCD_PIXCLK;
PB1_q_b[0]_clock_enable_0 = E1_mDVAL;
PB1_q_b[0]_PORT_B_data_out = MEMORY(PB1_q_b[0]_PORT_A_data_in_reg, , PB1_q_b[0]_PORT_A_address_reg, PB1_q_b[0]_PORT_B_address_reg, PB1_q_b[0]_PORT_A_write_enable_reg, PB1_q_b[0]_PORT_B_read_enable_reg, , , PB1_q_b[0]_clock_0, PB1_q_b[0]_clock_1, PB1_q_b[0]_clock_enable_0, , , );
PB1_q_b[0]_PORT_B_data_out_reg = DFFE(PB1_q_b[0]_PORT_B_data_out, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0] = PB1_q_b[0]_PORT_B_data_out_reg[0];


--X2_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]
X2_wrptr_g[0] = DFFEAS(X2L39, CCD_PIXCLK, C1_oRST_0,  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[1]
X2_wrptr_g[1] = DFFEAS(EB2_power_modified_counter_values[1], CCD_PIXCLK, C1_oRST_0,  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2]
X2_wrptr_g[2] = DFFEAS(EB2_power_modified_counter_values[2], CCD_PIXCLK, C1_oRST_0,  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[3]
X2_wrptr_g[3] = DFFEAS(EB2_power_modified_counter_values[3], CCD_PIXCLK, C1_oRST_0,  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[4]
X2_wrptr_g[4] = DFFEAS(EB2_power_modified_counter_values[4], CCD_PIXCLK, C1_oRST_0,  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5]
X2_wrptr_g[5] = DFFEAS(EB2_power_modified_counter_values[5], CCD_PIXCLK, C1_oRST_0,  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6]
X2_wrptr_g[6] = DFFEAS(EB2_power_modified_counter_values[6], CCD_PIXCLK, C1_oRST_0,  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[7]
X2_wrptr_g[7] = DFFEAS(EB2_power_modified_counter_values[7], CCD_PIXCLK, C1_oRST_0,  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8]
X2_wrptr_g[8] = DFFEAS(EB2_power_modified_counter_values[8], CCD_PIXCLK, C1_oRST_0,  , X2_valid_wrreq,  ,  ,  ,  );


--PB3_q_b[1] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB3_q_b[1]_PORT_A_data_in = E1_mCCD_B[1];
PB3_q_b[1]_PORT_A_data_in_reg = DFFE(PB3_q_b[1]_PORT_A_data_in, PB3_q_b[1]_clock_0, , , PB3_q_b[1]_clock_enable_0);
PB3_q_b[1]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB3_q_b[1]_PORT_A_address_reg = DFFE(PB3_q_b[1]_PORT_A_address, PB3_q_b[1]_clock_0, , , PB3_q_b[1]_clock_enable_0);
PB3_q_b[1]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB3_q_b[1]_PORT_B_address_reg = DFFE(PB3_q_b[1]_PORT_B_address, PB3_q_b[1]_clock_1, , , );
PB3_q_b[1]_PORT_A_write_enable = VCC;
PB3_q_b[1]_PORT_A_write_enable_reg = DFFE(PB3_q_b[1]_PORT_A_write_enable, PB3_q_b[1]_clock_0, , , PB3_q_b[1]_clock_enable_0);
PB3_q_b[1]_PORT_B_read_enable = VCC;
PB3_q_b[1]_PORT_B_read_enable_reg = DFFE(PB3_q_b[1]_PORT_B_read_enable, PB3_q_b[1]_clock_1, , , );
PB3_q_b[1]_clock_0 = CCD_PIXCLK;
PB3_q_b[1]_clock_1 = CCD_PIXCLK;
PB3_q_b[1]_clock_enable_0 = E1_mDVAL;
PB3_q_b[1]_PORT_B_data_out = MEMORY(PB3_q_b[1]_PORT_A_data_in_reg, , PB3_q_b[1]_PORT_A_address_reg, PB3_q_b[1]_PORT_B_address_reg, PB3_q_b[1]_PORT_A_write_enable_reg, PB3_q_b[1]_PORT_B_read_enable_reg, , , PB3_q_b[1]_clock_0, PB3_q_b[1]_clock_1, PB3_q_b[1]_clock_enable_0, , , );
PB3_q_b[1]_PORT_B_data_out_reg = DFFE(PB3_q_b[1]_PORT_B_data_out, PB3_q_b[1]_clock_1, , , );
PB3_q_b[1] = PB3_q_b[1]_PORT_B_data_out_reg[0];


--PB1_q_b[1] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[1]_PORT_A_data_in = E1_mCCD_R[1];
PB1_q_b[1]_PORT_A_data_in_reg = DFFE(PB1_q_b[1]_PORT_A_data_in, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[1]_PORT_A_address_reg = DFFE(PB1_q_b[1]_PORT_A_address, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[1]_PORT_B_address_reg = DFFE(PB1_q_b[1]_PORT_B_address, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1]_PORT_A_write_enable = VCC;
PB1_q_b[1]_PORT_A_write_enable_reg = DFFE(PB1_q_b[1]_PORT_A_write_enable, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_B_read_enable = VCC;
PB1_q_b[1]_PORT_B_read_enable_reg = DFFE(PB1_q_b[1]_PORT_B_read_enable, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1]_clock_0 = CCD_PIXCLK;
PB1_q_b[1]_clock_1 = CCD_PIXCLK;
PB1_q_b[1]_clock_enable_0 = E1_mDVAL;
PB1_q_b[1]_PORT_B_data_out = MEMORY(PB1_q_b[1]_PORT_A_data_in_reg, , PB1_q_b[1]_PORT_A_address_reg, PB1_q_b[1]_PORT_B_address_reg, PB1_q_b[1]_PORT_A_write_enable_reg, PB1_q_b[1]_PORT_B_read_enable_reg, , , PB1_q_b[1]_clock_0, PB1_q_b[1]_clock_1, PB1_q_b[1]_clock_enable_0, , , );
PB1_q_b[1]_PORT_B_data_out_reg = DFFE(PB1_q_b[1]_PORT_B_data_out, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1] = PB1_q_b[1]_PORT_B_data_out_reg[0];


--PB3_q_b[2] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB3_q_b[2]_PORT_A_data_in = E1_mCCD_B[2];
PB3_q_b[2]_PORT_A_data_in_reg = DFFE(PB3_q_b[2]_PORT_A_data_in, PB3_q_b[2]_clock_0, , , PB3_q_b[2]_clock_enable_0);
PB3_q_b[2]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB3_q_b[2]_PORT_A_address_reg = DFFE(PB3_q_b[2]_PORT_A_address, PB3_q_b[2]_clock_0, , , PB3_q_b[2]_clock_enable_0);
PB3_q_b[2]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB3_q_b[2]_PORT_B_address_reg = DFFE(PB3_q_b[2]_PORT_B_address, PB3_q_b[2]_clock_1, , , );
PB3_q_b[2]_PORT_A_write_enable = VCC;
PB3_q_b[2]_PORT_A_write_enable_reg = DFFE(PB3_q_b[2]_PORT_A_write_enable, PB3_q_b[2]_clock_0, , , PB3_q_b[2]_clock_enable_0);
PB3_q_b[2]_PORT_B_read_enable = VCC;
PB3_q_b[2]_PORT_B_read_enable_reg = DFFE(PB3_q_b[2]_PORT_B_read_enable, PB3_q_b[2]_clock_1, , , );
PB3_q_b[2]_clock_0 = CCD_PIXCLK;
PB3_q_b[2]_clock_1 = CCD_PIXCLK;
PB3_q_b[2]_clock_enable_0 = E1_mDVAL;
PB3_q_b[2]_PORT_B_data_out = MEMORY(PB3_q_b[2]_PORT_A_data_in_reg, , PB3_q_b[2]_PORT_A_address_reg, PB3_q_b[2]_PORT_B_address_reg, PB3_q_b[2]_PORT_A_write_enable_reg, PB3_q_b[2]_PORT_B_read_enable_reg, , , PB3_q_b[2]_clock_0, PB3_q_b[2]_clock_1, PB3_q_b[2]_clock_enable_0, , , );
PB3_q_b[2]_PORT_B_data_out_reg = DFFE(PB3_q_b[2]_PORT_B_data_out, PB3_q_b[2]_clock_1, , , );
PB3_q_b[2] = PB3_q_b[2]_PORT_B_data_out_reg[0];


--PB1_q_b[2] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[2]_PORT_A_data_in = E1_mCCD_R[2];
PB1_q_b[2]_PORT_A_data_in_reg = DFFE(PB1_q_b[2]_PORT_A_data_in, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[2]_PORT_A_address_reg = DFFE(PB1_q_b[2]_PORT_A_address, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[2]_PORT_B_address_reg = DFFE(PB1_q_b[2]_PORT_B_address, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2]_PORT_A_write_enable = VCC;
PB1_q_b[2]_PORT_A_write_enable_reg = DFFE(PB1_q_b[2]_PORT_A_write_enable, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_B_read_enable = VCC;
PB1_q_b[2]_PORT_B_read_enable_reg = DFFE(PB1_q_b[2]_PORT_B_read_enable, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2]_clock_0 = CCD_PIXCLK;
PB1_q_b[2]_clock_1 = CCD_PIXCLK;
PB1_q_b[2]_clock_enable_0 = E1_mDVAL;
PB1_q_b[2]_PORT_B_data_out = MEMORY(PB1_q_b[2]_PORT_A_data_in_reg, , PB1_q_b[2]_PORT_A_address_reg, PB1_q_b[2]_PORT_B_address_reg, PB1_q_b[2]_PORT_A_write_enable_reg, PB1_q_b[2]_PORT_B_read_enable_reg, , , PB1_q_b[2]_clock_0, PB1_q_b[2]_clock_1, PB1_q_b[2]_clock_enable_0, , , );
PB1_q_b[2]_PORT_B_data_out_reg = DFFE(PB1_q_b[2]_PORT_B_data_out, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2] = PB1_q_b[2]_PORT_B_data_out_reg[0];


--PB3_q_b[3] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB3_q_b[3]_PORT_A_data_in = E1_mCCD_B[3];
PB3_q_b[3]_PORT_A_data_in_reg = DFFE(PB3_q_b[3]_PORT_A_data_in, PB3_q_b[3]_clock_0, , , PB3_q_b[3]_clock_enable_0);
PB3_q_b[3]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB3_q_b[3]_PORT_A_address_reg = DFFE(PB3_q_b[3]_PORT_A_address, PB3_q_b[3]_clock_0, , , PB3_q_b[3]_clock_enable_0);
PB3_q_b[3]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB3_q_b[3]_PORT_B_address_reg = DFFE(PB3_q_b[3]_PORT_B_address, PB3_q_b[3]_clock_1, , , );
PB3_q_b[3]_PORT_A_write_enable = VCC;
PB3_q_b[3]_PORT_A_write_enable_reg = DFFE(PB3_q_b[3]_PORT_A_write_enable, PB3_q_b[3]_clock_0, , , PB3_q_b[3]_clock_enable_0);
PB3_q_b[3]_PORT_B_read_enable = VCC;
PB3_q_b[3]_PORT_B_read_enable_reg = DFFE(PB3_q_b[3]_PORT_B_read_enable, PB3_q_b[3]_clock_1, , , );
PB3_q_b[3]_clock_0 = CCD_PIXCLK;
PB3_q_b[3]_clock_1 = CCD_PIXCLK;
PB3_q_b[3]_clock_enable_0 = E1_mDVAL;
PB3_q_b[3]_PORT_B_data_out = MEMORY(PB3_q_b[3]_PORT_A_data_in_reg, , PB3_q_b[3]_PORT_A_address_reg, PB3_q_b[3]_PORT_B_address_reg, PB3_q_b[3]_PORT_A_write_enable_reg, PB3_q_b[3]_PORT_B_read_enable_reg, , , PB3_q_b[3]_clock_0, PB3_q_b[3]_clock_1, PB3_q_b[3]_clock_enable_0, , , );
PB3_q_b[3]_PORT_B_data_out_reg = DFFE(PB3_q_b[3]_PORT_B_data_out, PB3_q_b[3]_clock_1, , , );
PB3_q_b[3] = PB3_q_b[3]_PORT_B_data_out_reg[0];


--PB1_q_b[3] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[3]_PORT_A_data_in = E1_mCCD_R[3];
PB1_q_b[3]_PORT_A_data_in_reg = DFFE(PB1_q_b[3]_PORT_A_data_in, PB1_q_b[3]_clock_0, , , PB1_q_b[3]_clock_enable_0);
PB1_q_b[3]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[3]_PORT_A_address_reg = DFFE(PB1_q_b[3]_PORT_A_address, PB1_q_b[3]_clock_0, , , PB1_q_b[3]_clock_enable_0);
PB1_q_b[3]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[3]_PORT_B_address_reg = DFFE(PB1_q_b[3]_PORT_B_address, PB1_q_b[3]_clock_1, , , );
PB1_q_b[3]_PORT_A_write_enable = VCC;
PB1_q_b[3]_PORT_A_write_enable_reg = DFFE(PB1_q_b[3]_PORT_A_write_enable, PB1_q_b[3]_clock_0, , , PB1_q_b[3]_clock_enable_0);
PB1_q_b[3]_PORT_B_read_enable = VCC;
PB1_q_b[3]_PORT_B_read_enable_reg = DFFE(PB1_q_b[3]_PORT_B_read_enable, PB1_q_b[3]_clock_1, , , );
PB1_q_b[3]_clock_0 = CCD_PIXCLK;
PB1_q_b[3]_clock_1 = CCD_PIXCLK;
PB1_q_b[3]_clock_enable_0 = E1_mDVAL;
PB1_q_b[3]_PORT_B_data_out = MEMORY(PB1_q_b[3]_PORT_A_data_in_reg, , PB1_q_b[3]_PORT_A_address_reg, PB1_q_b[3]_PORT_B_address_reg, PB1_q_b[3]_PORT_A_write_enable_reg, PB1_q_b[3]_PORT_B_read_enable_reg, , , PB1_q_b[3]_clock_0, PB1_q_b[3]_clock_1, PB1_q_b[3]_clock_enable_0, , , );
PB1_q_b[3]_PORT_B_data_out_reg = DFFE(PB1_q_b[3]_PORT_B_data_out, PB1_q_b[3]_clock_1, , , );
PB1_q_b[3] = PB1_q_b[3]_PORT_B_data_out_reg[0];


--PB3_q_b[4] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB3_q_b[4]_PORT_A_data_in = E1_mCCD_B[4];
PB3_q_b[4]_PORT_A_data_in_reg = DFFE(PB3_q_b[4]_PORT_A_data_in, PB3_q_b[4]_clock_0, , , PB3_q_b[4]_clock_enable_0);
PB3_q_b[4]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB3_q_b[4]_PORT_A_address_reg = DFFE(PB3_q_b[4]_PORT_A_address, PB3_q_b[4]_clock_0, , , PB3_q_b[4]_clock_enable_0);
PB3_q_b[4]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB3_q_b[4]_PORT_B_address_reg = DFFE(PB3_q_b[4]_PORT_B_address, PB3_q_b[4]_clock_1, , , );
PB3_q_b[4]_PORT_A_write_enable = VCC;
PB3_q_b[4]_PORT_A_write_enable_reg = DFFE(PB3_q_b[4]_PORT_A_write_enable, PB3_q_b[4]_clock_0, , , PB3_q_b[4]_clock_enable_0);
PB3_q_b[4]_PORT_B_read_enable = VCC;
PB3_q_b[4]_PORT_B_read_enable_reg = DFFE(PB3_q_b[4]_PORT_B_read_enable, PB3_q_b[4]_clock_1, , , );
PB3_q_b[4]_clock_0 = CCD_PIXCLK;
PB3_q_b[4]_clock_1 = CCD_PIXCLK;
PB3_q_b[4]_clock_enable_0 = E1_mDVAL;
PB3_q_b[4]_PORT_B_data_out = MEMORY(PB3_q_b[4]_PORT_A_data_in_reg, , PB3_q_b[4]_PORT_A_address_reg, PB3_q_b[4]_PORT_B_address_reg, PB3_q_b[4]_PORT_A_write_enable_reg, PB3_q_b[4]_PORT_B_read_enable_reg, , , PB3_q_b[4]_clock_0, PB3_q_b[4]_clock_1, PB3_q_b[4]_clock_enable_0, , , );
PB3_q_b[4]_PORT_B_data_out_reg = DFFE(PB3_q_b[4]_PORT_B_data_out, PB3_q_b[4]_clock_1, , , );
PB3_q_b[4] = PB3_q_b[4]_PORT_B_data_out_reg[0];


--PB1_q_b[4] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[4]_PORT_A_data_in = E1_mCCD_R[4];
PB1_q_b[4]_PORT_A_data_in_reg = DFFE(PB1_q_b[4]_PORT_A_data_in, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[4]_PORT_A_address_reg = DFFE(PB1_q_b[4]_PORT_A_address, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[4]_PORT_B_address_reg = DFFE(PB1_q_b[4]_PORT_B_address, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4]_PORT_A_write_enable = VCC;
PB1_q_b[4]_PORT_A_write_enable_reg = DFFE(PB1_q_b[4]_PORT_A_write_enable, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_B_read_enable = VCC;
PB1_q_b[4]_PORT_B_read_enable_reg = DFFE(PB1_q_b[4]_PORT_B_read_enable, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4]_clock_0 = CCD_PIXCLK;
PB1_q_b[4]_clock_1 = CCD_PIXCLK;
PB1_q_b[4]_clock_enable_0 = E1_mDVAL;
PB1_q_b[4]_PORT_B_data_out = MEMORY(PB1_q_b[4]_PORT_A_data_in_reg, , PB1_q_b[4]_PORT_A_address_reg, PB1_q_b[4]_PORT_B_address_reg, PB1_q_b[4]_PORT_A_write_enable_reg, PB1_q_b[4]_PORT_B_read_enable_reg, , , PB1_q_b[4]_clock_0, PB1_q_b[4]_clock_1, PB1_q_b[4]_clock_enable_0, , , );
PB1_q_b[4]_PORT_B_data_out_reg = DFFE(PB1_q_b[4]_PORT_B_data_out, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4] = PB1_q_b[4]_PORT_B_data_out_reg[0];


--PB3_q_b[5] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB3_q_b[5]_PORT_A_data_in = E1_mCCD_B[5];
PB3_q_b[5]_PORT_A_data_in_reg = DFFE(PB3_q_b[5]_PORT_A_data_in, PB3_q_b[5]_clock_0, , , PB3_q_b[5]_clock_enable_0);
PB3_q_b[5]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB3_q_b[5]_PORT_A_address_reg = DFFE(PB3_q_b[5]_PORT_A_address, PB3_q_b[5]_clock_0, , , PB3_q_b[5]_clock_enable_0);
PB3_q_b[5]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB3_q_b[5]_PORT_B_address_reg = DFFE(PB3_q_b[5]_PORT_B_address, PB3_q_b[5]_clock_1, , , );
PB3_q_b[5]_PORT_A_write_enable = VCC;
PB3_q_b[5]_PORT_A_write_enable_reg = DFFE(PB3_q_b[5]_PORT_A_write_enable, PB3_q_b[5]_clock_0, , , PB3_q_b[5]_clock_enable_0);
PB3_q_b[5]_PORT_B_read_enable = VCC;
PB3_q_b[5]_PORT_B_read_enable_reg = DFFE(PB3_q_b[5]_PORT_B_read_enable, PB3_q_b[5]_clock_1, , , );
PB3_q_b[5]_clock_0 = CCD_PIXCLK;
PB3_q_b[5]_clock_1 = CCD_PIXCLK;
PB3_q_b[5]_clock_enable_0 = E1_mDVAL;
PB3_q_b[5]_PORT_B_data_out = MEMORY(PB3_q_b[5]_PORT_A_data_in_reg, , PB3_q_b[5]_PORT_A_address_reg, PB3_q_b[5]_PORT_B_address_reg, PB3_q_b[5]_PORT_A_write_enable_reg, PB3_q_b[5]_PORT_B_read_enable_reg, , , PB3_q_b[5]_clock_0, PB3_q_b[5]_clock_1, PB3_q_b[5]_clock_enable_0, , , );
PB3_q_b[5]_PORT_B_data_out_reg = DFFE(PB3_q_b[5]_PORT_B_data_out, PB3_q_b[5]_clock_1, , , );
PB3_q_b[5] = PB3_q_b[5]_PORT_B_data_out_reg[0];


--PB1_q_b[5] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[5]_PORT_A_data_in = E1_mCCD_R[5];
PB1_q_b[5]_PORT_A_data_in_reg = DFFE(PB1_q_b[5]_PORT_A_data_in, PB1_q_b[5]_clock_0, , , PB1_q_b[5]_clock_enable_0);
PB1_q_b[5]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[5]_PORT_A_address_reg = DFFE(PB1_q_b[5]_PORT_A_address, PB1_q_b[5]_clock_0, , , PB1_q_b[5]_clock_enable_0);
PB1_q_b[5]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[5]_PORT_B_address_reg = DFFE(PB1_q_b[5]_PORT_B_address, PB1_q_b[5]_clock_1, , , );
PB1_q_b[5]_PORT_A_write_enable = VCC;
PB1_q_b[5]_PORT_A_write_enable_reg = DFFE(PB1_q_b[5]_PORT_A_write_enable, PB1_q_b[5]_clock_0, , , PB1_q_b[5]_clock_enable_0);
PB1_q_b[5]_PORT_B_read_enable = VCC;
PB1_q_b[5]_PORT_B_read_enable_reg = DFFE(PB1_q_b[5]_PORT_B_read_enable, PB1_q_b[5]_clock_1, , , );
PB1_q_b[5]_clock_0 = CCD_PIXCLK;
PB1_q_b[5]_clock_1 = CCD_PIXCLK;
PB1_q_b[5]_clock_enable_0 = E1_mDVAL;
PB1_q_b[5]_PORT_B_data_out = MEMORY(PB1_q_b[5]_PORT_A_data_in_reg, , PB1_q_b[5]_PORT_A_address_reg, PB1_q_b[5]_PORT_B_address_reg, PB1_q_b[5]_PORT_A_write_enable_reg, PB1_q_b[5]_PORT_B_read_enable_reg, , , PB1_q_b[5]_clock_0, PB1_q_b[5]_clock_1, PB1_q_b[5]_clock_enable_0, , , );
PB1_q_b[5]_PORT_B_data_out_reg = DFFE(PB1_q_b[5]_PORT_B_data_out, PB1_q_b[5]_clock_1, , , );
PB1_q_b[5] = PB1_q_b[5]_PORT_B_data_out_reg[0];


--PB3_q_b[6] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB3_q_b[6]_PORT_A_data_in = E1_mCCD_B[6];
PB3_q_b[6]_PORT_A_data_in_reg = DFFE(PB3_q_b[6]_PORT_A_data_in, PB3_q_b[6]_clock_0, , , PB3_q_b[6]_clock_enable_0);
PB3_q_b[6]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB3_q_b[6]_PORT_A_address_reg = DFFE(PB3_q_b[6]_PORT_A_address, PB3_q_b[6]_clock_0, , , PB3_q_b[6]_clock_enable_0);
PB3_q_b[6]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB3_q_b[6]_PORT_B_address_reg = DFFE(PB3_q_b[6]_PORT_B_address, PB3_q_b[6]_clock_1, , , );
PB3_q_b[6]_PORT_A_write_enable = VCC;
PB3_q_b[6]_PORT_A_write_enable_reg = DFFE(PB3_q_b[6]_PORT_A_write_enable, PB3_q_b[6]_clock_0, , , PB3_q_b[6]_clock_enable_0);
PB3_q_b[6]_PORT_B_read_enable = VCC;
PB3_q_b[6]_PORT_B_read_enable_reg = DFFE(PB3_q_b[6]_PORT_B_read_enable, PB3_q_b[6]_clock_1, , , );
PB3_q_b[6]_clock_0 = CCD_PIXCLK;
PB3_q_b[6]_clock_1 = CCD_PIXCLK;
PB3_q_b[6]_clock_enable_0 = E1_mDVAL;
PB3_q_b[6]_PORT_B_data_out = MEMORY(PB3_q_b[6]_PORT_A_data_in_reg, , PB3_q_b[6]_PORT_A_address_reg, PB3_q_b[6]_PORT_B_address_reg, PB3_q_b[6]_PORT_A_write_enable_reg, PB3_q_b[6]_PORT_B_read_enable_reg, , , PB3_q_b[6]_clock_0, PB3_q_b[6]_clock_1, PB3_q_b[6]_clock_enable_0, , , );
PB3_q_b[6]_PORT_B_data_out_reg = DFFE(PB3_q_b[6]_PORT_B_data_out, PB3_q_b[6]_clock_1, , , );
PB3_q_b[6] = PB3_q_b[6]_PORT_B_data_out_reg[0];


--PB1_q_b[6] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[6]_PORT_A_data_in = E1_mCCD_R[6];
PB1_q_b[6]_PORT_A_data_in_reg = DFFE(PB1_q_b[6]_PORT_A_data_in, PB1_q_b[6]_clock_0, , , PB1_q_b[6]_clock_enable_0);
PB1_q_b[6]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[6]_PORT_A_address_reg = DFFE(PB1_q_b[6]_PORT_A_address, PB1_q_b[6]_clock_0, , , PB1_q_b[6]_clock_enable_0);
PB1_q_b[6]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[6]_PORT_B_address_reg = DFFE(PB1_q_b[6]_PORT_B_address, PB1_q_b[6]_clock_1, , , );
PB1_q_b[6]_PORT_A_write_enable = VCC;
PB1_q_b[6]_PORT_A_write_enable_reg = DFFE(PB1_q_b[6]_PORT_A_write_enable, PB1_q_b[6]_clock_0, , , PB1_q_b[6]_clock_enable_0);
PB1_q_b[6]_PORT_B_read_enable = VCC;
PB1_q_b[6]_PORT_B_read_enable_reg = DFFE(PB1_q_b[6]_PORT_B_read_enable, PB1_q_b[6]_clock_1, , , );
PB1_q_b[6]_clock_0 = CCD_PIXCLK;
PB1_q_b[6]_clock_1 = CCD_PIXCLK;
PB1_q_b[6]_clock_enable_0 = E1_mDVAL;
PB1_q_b[6]_PORT_B_data_out = MEMORY(PB1_q_b[6]_PORT_A_data_in_reg, , PB1_q_b[6]_PORT_A_address_reg, PB1_q_b[6]_PORT_B_address_reg, PB1_q_b[6]_PORT_A_write_enable_reg, PB1_q_b[6]_PORT_B_read_enable_reg, , , PB1_q_b[6]_clock_0, PB1_q_b[6]_clock_1, PB1_q_b[6]_clock_enable_0, , , );
PB1_q_b[6]_PORT_B_data_out_reg = DFFE(PB1_q_b[6]_PORT_B_data_out, PB1_q_b[6]_clock_1, , , );
PB1_q_b[6] = PB1_q_b[6]_PORT_B_data_out_reg[0];


--PB3_q_b[7] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB3_q_b[7]_PORT_A_data_in = E1_mCCD_B[7];
PB3_q_b[7]_PORT_A_data_in_reg = DFFE(PB3_q_b[7]_PORT_A_data_in, PB3_q_b[7]_clock_0, , , PB3_q_b[7]_clock_enable_0);
PB3_q_b[7]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB3_q_b[7]_PORT_A_address_reg = DFFE(PB3_q_b[7]_PORT_A_address, PB3_q_b[7]_clock_0, , , PB3_q_b[7]_clock_enable_0);
PB3_q_b[7]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB3_q_b[7]_PORT_B_address_reg = DFFE(PB3_q_b[7]_PORT_B_address, PB3_q_b[7]_clock_1, , , );
PB3_q_b[7]_PORT_A_write_enable = VCC;
PB3_q_b[7]_PORT_A_write_enable_reg = DFFE(PB3_q_b[7]_PORT_A_write_enable, PB3_q_b[7]_clock_0, , , PB3_q_b[7]_clock_enable_0);
PB3_q_b[7]_PORT_B_read_enable = VCC;
PB3_q_b[7]_PORT_B_read_enable_reg = DFFE(PB3_q_b[7]_PORT_B_read_enable, PB3_q_b[7]_clock_1, , , );
PB3_q_b[7]_clock_0 = CCD_PIXCLK;
PB3_q_b[7]_clock_1 = CCD_PIXCLK;
PB3_q_b[7]_clock_enable_0 = E1_mDVAL;
PB3_q_b[7]_PORT_B_data_out = MEMORY(PB3_q_b[7]_PORT_A_data_in_reg, , PB3_q_b[7]_PORT_A_address_reg, PB3_q_b[7]_PORT_B_address_reg, PB3_q_b[7]_PORT_A_write_enable_reg, PB3_q_b[7]_PORT_B_read_enable_reg, , , PB3_q_b[7]_clock_0, PB3_q_b[7]_clock_1, PB3_q_b[7]_clock_enable_0, , , );
PB3_q_b[7]_PORT_B_data_out_reg = DFFE(PB3_q_b[7]_PORT_B_data_out, PB3_q_b[7]_clock_1, , , );
PB3_q_b[7] = PB3_q_b[7]_PORT_B_data_out_reg[0];


--PB1_q_b[7] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[7]_PORT_A_data_in = E1_mCCD_R[7];
PB1_q_b[7]_PORT_A_data_in_reg = DFFE(PB1_q_b[7]_PORT_A_data_in, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[7]_PORT_A_address_reg = DFFE(PB1_q_b[7]_PORT_A_address, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[7]_PORT_B_address_reg = DFFE(PB1_q_b[7]_PORT_B_address, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7]_PORT_A_write_enable = VCC;
PB1_q_b[7]_PORT_A_write_enable_reg = DFFE(PB1_q_b[7]_PORT_A_write_enable, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_B_read_enable = VCC;
PB1_q_b[7]_PORT_B_read_enable_reg = DFFE(PB1_q_b[7]_PORT_B_read_enable, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7]_clock_0 = CCD_PIXCLK;
PB1_q_b[7]_clock_1 = CCD_PIXCLK;
PB1_q_b[7]_clock_enable_0 = E1_mDVAL;
PB1_q_b[7]_PORT_B_data_out = MEMORY(PB1_q_b[7]_PORT_A_data_in_reg, , PB1_q_b[7]_PORT_A_address_reg, PB1_q_b[7]_PORT_B_address_reg, PB1_q_b[7]_PORT_A_write_enable_reg, PB1_q_b[7]_PORT_B_read_enable_reg, , , PB1_q_b[7]_clock_0, PB1_q_b[7]_clock_1, PB1_q_b[7]_clock_enable_0, , , );
PB1_q_b[7]_PORT_B_data_out_reg = DFFE(PB1_q_b[7]_PORT_B_data_out, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7] = PB1_q_b[7]_PORT_B_data_out_reg[0];


--PB3_q_b[8] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB3_q_b[8]_PORT_A_data_in = E1_mCCD_B[8];
PB3_q_b[8]_PORT_A_data_in_reg = DFFE(PB3_q_b[8]_PORT_A_data_in, PB3_q_b[8]_clock_0, , , PB3_q_b[8]_clock_enable_0);
PB3_q_b[8]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB3_q_b[8]_PORT_A_address_reg = DFFE(PB3_q_b[8]_PORT_A_address, PB3_q_b[8]_clock_0, , , PB3_q_b[8]_clock_enable_0);
PB3_q_b[8]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB3_q_b[8]_PORT_B_address_reg = DFFE(PB3_q_b[8]_PORT_B_address, PB3_q_b[8]_clock_1, , , );
PB3_q_b[8]_PORT_A_write_enable = VCC;
PB3_q_b[8]_PORT_A_write_enable_reg = DFFE(PB3_q_b[8]_PORT_A_write_enable, PB3_q_b[8]_clock_0, , , PB3_q_b[8]_clock_enable_0);
PB3_q_b[8]_PORT_B_read_enable = VCC;
PB3_q_b[8]_PORT_B_read_enable_reg = DFFE(PB3_q_b[8]_PORT_B_read_enable, PB3_q_b[8]_clock_1, , , );
PB3_q_b[8]_clock_0 = CCD_PIXCLK;
PB3_q_b[8]_clock_1 = CCD_PIXCLK;
PB3_q_b[8]_clock_enable_0 = E1_mDVAL;
PB3_q_b[8]_PORT_B_data_out = MEMORY(PB3_q_b[8]_PORT_A_data_in_reg, , PB3_q_b[8]_PORT_A_address_reg, PB3_q_b[8]_PORT_B_address_reg, PB3_q_b[8]_PORT_A_write_enable_reg, PB3_q_b[8]_PORT_B_read_enable_reg, , , PB3_q_b[8]_clock_0, PB3_q_b[8]_clock_1, PB3_q_b[8]_clock_enable_0, , , );
PB3_q_b[8]_PORT_B_data_out_reg = DFFE(PB3_q_b[8]_PORT_B_data_out, PB3_q_b[8]_clock_1, , , );
PB3_q_b[8] = PB3_q_b[8]_PORT_B_data_out_reg[0];


--PB1_q_b[8] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[8]_PORT_A_data_in = E1_mCCD_R[8];
PB1_q_b[8]_PORT_A_data_in_reg = DFFE(PB1_q_b[8]_PORT_A_data_in, PB1_q_b[8]_clock_0, , , PB1_q_b[8]_clock_enable_0);
PB1_q_b[8]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[8]_PORT_A_address_reg = DFFE(PB1_q_b[8]_PORT_A_address, PB1_q_b[8]_clock_0, , , PB1_q_b[8]_clock_enable_0);
PB1_q_b[8]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[8]_PORT_B_address_reg = DFFE(PB1_q_b[8]_PORT_B_address, PB1_q_b[8]_clock_1, , , );
PB1_q_b[8]_PORT_A_write_enable = VCC;
PB1_q_b[8]_PORT_A_write_enable_reg = DFFE(PB1_q_b[8]_PORT_A_write_enable, PB1_q_b[8]_clock_0, , , PB1_q_b[8]_clock_enable_0);
PB1_q_b[8]_PORT_B_read_enable = VCC;
PB1_q_b[8]_PORT_B_read_enable_reg = DFFE(PB1_q_b[8]_PORT_B_read_enable, PB1_q_b[8]_clock_1, , , );
PB1_q_b[8]_clock_0 = CCD_PIXCLK;
PB1_q_b[8]_clock_1 = CCD_PIXCLK;
PB1_q_b[8]_clock_enable_0 = E1_mDVAL;
PB1_q_b[8]_PORT_B_data_out = MEMORY(PB1_q_b[8]_PORT_A_data_in_reg, , PB1_q_b[8]_PORT_A_address_reg, PB1_q_b[8]_PORT_B_address_reg, PB1_q_b[8]_PORT_A_write_enable_reg, PB1_q_b[8]_PORT_B_read_enable_reg, , , PB1_q_b[8]_clock_0, PB1_q_b[8]_clock_1, PB1_q_b[8]_clock_enable_0, , , );
PB1_q_b[8]_PORT_B_data_out_reg = DFFE(PB1_q_b[8]_PORT_B_data_out, PB1_q_b[8]_clock_1, , , );
PB1_q_b[8] = PB1_q_b[8]_PORT_B_data_out_reg[0];


--PB3_q_b[9] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB3_q_b[9]_PORT_A_data_in = E1_mCCD_B[9];
PB3_q_b[9]_PORT_A_data_in_reg = DFFE(PB3_q_b[9]_PORT_A_data_in, PB3_q_b[9]_clock_0, , , PB3_q_b[9]_clock_enable_0);
PB3_q_b[9]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB3_q_b[9]_PORT_A_address_reg = DFFE(PB3_q_b[9]_PORT_A_address, PB3_q_b[9]_clock_0, , , PB3_q_b[9]_clock_enable_0);
PB3_q_b[9]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB3_q_b[9]_PORT_B_address_reg = DFFE(PB3_q_b[9]_PORT_B_address, PB3_q_b[9]_clock_1, , , );
PB3_q_b[9]_PORT_A_write_enable = VCC;
PB3_q_b[9]_PORT_A_write_enable_reg = DFFE(PB3_q_b[9]_PORT_A_write_enable, PB3_q_b[9]_clock_0, , , PB3_q_b[9]_clock_enable_0);
PB3_q_b[9]_PORT_B_read_enable = VCC;
PB3_q_b[9]_PORT_B_read_enable_reg = DFFE(PB3_q_b[9]_PORT_B_read_enable, PB3_q_b[9]_clock_1, , , );
PB3_q_b[9]_clock_0 = CCD_PIXCLK;
PB3_q_b[9]_clock_1 = CCD_PIXCLK;
PB3_q_b[9]_clock_enable_0 = E1_mDVAL;
PB3_q_b[9]_PORT_B_data_out = MEMORY(PB3_q_b[9]_PORT_A_data_in_reg, , PB3_q_b[9]_PORT_A_address_reg, PB3_q_b[9]_PORT_B_address_reg, PB3_q_b[9]_PORT_A_write_enable_reg, PB3_q_b[9]_PORT_B_read_enable_reg, , , PB3_q_b[9]_clock_0, PB3_q_b[9]_clock_1, PB3_q_b[9]_clock_enable_0, , , );
PB3_q_b[9]_PORT_B_data_out_reg = DFFE(PB3_q_b[9]_PORT_B_data_out, PB3_q_b[9]_clock_1, , , );
PB3_q_b[9] = PB3_q_b[9]_PORT_B_data_out_reg[0];


--PB1_q_b[9] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[9]_PORT_A_data_in = E1_mCCD_R[9];
PB1_q_b[9]_PORT_A_data_in_reg = DFFE(PB1_q_b[9]_PORT_A_data_in, PB1_q_b[9]_clock_0, , , PB1_q_b[9]_clock_enable_0);
PB1_q_b[9]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[9]_PORT_A_address_reg = DFFE(PB1_q_b[9]_PORT_A_address, PB1_q_b[9]_clock_0, , , PB1_q_b[9]_clock_enable_0);
PB1_q_b[9]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[9]_PORT_B_address_reg = DFFE(PB1_q_b[9]_PORT_B_address, PB1_q_b[9]_clock_1, , , );
PB1_q_b[9]_PORT_A_write_enable = VCC;
PB1_q_b[9]_PORT_A_write_enable_reg = DFFE(PB1_q_b[9]_PORT_A_write_enable, PB1_q_b[9]_clock_0, , , PB1_q_b[9]_clock_enable_0);
PB1_q_b[9]_PORT_B_read_enable = VCC;
PB1_q_b[9]_PORT_B_read_enable_reg = DFFE(PB1_q_b[9]_PORT_B_read_enable, PB1_q_b[9]_clock_1, , , );
PB1_q_b[9]_clock_0 = CCD_PIXCLK;
PB1_q_b[9]_clock_1 = CCD_PIXCLK;
PB1_q_b[9]_clock_enable_0 = E1_mDVAL;
PB1_q_b[9]_PORT_B_data_out = MEMORY(PB1_q_b[9]_PORT_A_data_in_reg, , PB1_q_b[9]_PORT_A_address_reg, PB1_q_b[9]_PORT_B_address_reg, PB1_q_b[9]_PORT_A_write_enable_reg, PB1_q_b[9]_PORT_B_read_enable_reg, , , PB1_q_b[9]_clock_0, PB1_q_b[9]_clock_1, PB1_q_b[9]_clock_enable_0, , , );
PB1_q_b[9]_PORT_B_data_out_reg = DFFE(PB1_q_b[9]_PORT_B_data_out, PB1_q_b[9]_clock_1, , , );
PB1_q_b[9] = PB1_q_b[9]_PORT_B_data_out_reg[0];


--PB2_q_b[5] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[5]_PORT_A_data_in = E1_mCCD_G[6];
PB2_q_b[5]_PORT_A_data_in_reg = DFFE(PB2_q_b[5]_PORT_A_data_in, PB2_q_b[5]_clock_0, , , PB2_q_b[5]_clock_enable_0);
PB2_q_b[5]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[5]_PORT_A_address_reg = DFFE(PB2_q_b[5]_PORT_A_address, PB2_q_b[5]_clock_0, , , PB2_q_b[5]_clock_enable_0);
PB2_q_b[5]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[5]_PORT_B_address_reg = DFFE(PB2_q_b[5]_PORT_B_address, PB2_q_b[5]_clock_1, , , );
PB2_q_b[5]_PORT_A_write_enable = VCC;
PB2_q_b[5]_PORT_A_write_enable_reg = DFFE(PB2_q_b[5]_PORT_A_write_enable, PB2_q_b[5]_clock_0, , , PB2_q_b[5]_clock_enable_0);
PB2_q_b[5]_PORT_B_read_enable = VCC;
PB2_q_b[5]_PORT_B_read_enable_reg = DFFE(PB2_q_b[5]_PORT_B_read_enable, PB2_q_b[5]_clock_1, , , );
PB2_q_b[5]_clock_0 = CCD_PIXCLK;
PB2_q_b[5]_clock_1 = CCD_PIXCLK;
PB2_q_b[5]_clock_enable_0 = E1_mDVAL;
PB2_q_b[5]_PORT_B_data_out = MEMORY(PB2_q_b[5]_PORT_A_data_in_reg, , PB2_q_b[5]_PORT_A_address_reg, PB2_q_b[5]_PORT_B_address_reg, PB2_q_b[5]_PORT_A_write_enable_reg, PB2_q_b[5]_PORT_B_read_enable_reg, , , PB2_q_b[5]_clock_0, PB2_q_b[5]_clock_1, PB2_q_b[5]_clock_enable_0, , , );
PB2_q_b[5]_PORT_B_data_out_reg = DFFE(PB2_q_b[5]_PORT_B_data_out, PB2_q_b[5]_clock_1, , , );
PB2_q_b[5] = PB2_q_b[5]_PORT_B_data_out_reg[0];


--PB2_q_b[0] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[0]_PORT_A_data_in = E1_mCCD_G[1];
PB2_q_b[0]_PORT_A_data_in_reg = DFFE(PB2_q_b[0]_PORT_A_data_in, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[0]_PORT_A_address_reg = DFFE(PB2_q_b[0]_PORT_A_address, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[0]_PORT_B_address_reg = DFFE(PB2_q_b[0]_PORT_B_address, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0]_PORT_A_write_enable = VCC;
PB2_q_b[0]_PORT_A_write_enable_reg = DFFE(PB2_q_b[0]_PORT_A_write_enable, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_B_read_enable = VCC;
PB2_q_b[0]_PORT_B_read_enable_reg = DFFE(PB2_q_b[0]_PORT_B_read_enable, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0]_clock_0 = CCD_PIXCLK;
PB2_q_b[0]_clock_1 = CCD_PIXCLK;
PB2_q_b[0]_clock_enable_0 = E1_mDVAL;
PB2_q_b[0]_PORT_B_data_out = MEMORY(PB2_q_b[0]_PORT_A_data_in_reg, , PB2_q_b[0]_PORT_A_address_reg, PB2_q_b[0]_PORT_B_address_reg, PB2_q_b[0]_PORT_A_write_enable_reg, PB2_q_b[0]_PORT_B_read_enable_reg, , , PB2_q_b[0]_clock_0, PB2_q_b[0]_clock_1, PB2_q_b[0]_clock_enable_0, , , );
PB2_q_b[0]_PORT_B_data_out_reg = DFFE(PB2_q_b[0]_PORT_B_data_out, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0] = PB2_q_b[0]_PORT_B_data_out_reg[0];


--PB2_q_b[6] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[6]_PORT_A_data_in = E1_mCCD_G[7];
PB2_q_b[6]_PORT_A_data_in_reg = DFFE(PB2_q_b[6]_PORT_A_data_in, PB2_q_b[6]_clock_0, , , PB2_q_b[6]_clock_enable_0);
PB2_q_b[6]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[6]_PORT_A_address_reg = DFFE(PB2_q_b[6]_PORT_A_address, PB2_q_b[6]_clock_0, , , PB2_q_b[6]_clock_enable_0);
PB2_q_b[6]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[6]_PORT_B_address_reg = DFFE(PB2_q_b[6]_PORT_B_address, PB2_q_b[6]_clock_1, , , );
PB2_q_b[6]_PORT_A_write_enable = VCC;
PB2_q_b[6]_PORT_A_write_enable_reg = DFFE(PB2_q_b[6]_PORT_A_write_enable, PB2_q_b[6]_clock_0, , , PB2_q_b[6]_clock_enable_0);
PB2_q_b[6]_PORT_B_read_enable = VCC;
PB2_q_b[6]_PORT_B_read_enable_reg = DFFE(PB2_q_b[6]_PORT_B_read_enable, PB2_q_b[6]_clock_1, , , );
PB2_q_b[6]_clock_0 = CCD_PIXCLK;
PB2_q_b[6]_clock_1 = CCD_PIXCLK;
PB2_q_b[6]_clock_enable_0 = E1_mDVAL;
PB2_q_b[6]_PORT_B_data_out = MEMORY(PB2_q_b[6]_PORT_A_data_in_reg, , PB2_q_b[6]_PORT_A_address_reg, PB2_q_b[6]_PORT_B_address_reg, PB2_q_b[6]_PORT_A_write_enable_reg, PB2_q_b[6]_PORT_B_read_enable_reg, , , PB2_q_b[6]_clock_0, PB2_q_b[6]_clock_1, PB2_q_b[6]_clock_enable_0, , , );
PB2_q_b[6]_PORT_B_data_out_reg = DFFE(PB2_q_b[6]_PORT_B_data_out, PB2_q_b[6]_clock_1, , , );
PB2_q_b[6] = PB2_q_b[6]_PORT_B_data_out_reg[0];


--PB2_q_b[1] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[1]_PORT_A_data_in = E1_mCCD_G[2];
PB2_q_b[1]_PORT_A_data_in_reg = DFFE(PB2_q_b[1]_PORT_A_data_in, PB2_q_b[1]_clock_0, , , PB2_q_b[1]_clock_enable_0);
PB2_q_b[1]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[1]_PORT_A_address_reg = DFFE(PB2_q_b[1]_PORT_A_address, PB2_q_b[1]_clock_0, , , PB2_q_b[1]_clock_enable_0);
PB2_q_b[1]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[1]_PORT_B_address_reg = DFFE(PB2_q_b[1]_PORT_B_address, PB2_q_b[1]_clock_1, , , );
PB2_q_b[1]_PORT_A_write_enable = VCC;
PB2_q_b[1]_PORT_A_write_enable_reg = DFFE(PB2_q_b[1]_PORT_A_write_enable, PB2_q_b[1]_clock_0, , , PB2_q_b[1]_clock_enable_0);
PB2_q_b[1]_PORT_B_read_enable = VCC;
PB2_q_b[1]_PORT_B_read_enable_reg = DFFE(PB2_q_b[1]_PORT_B_read_enable, PB2_q_b[1]_clock_1, , , );
PB2_q_b[1]_clock_0 = CCD_PIXCLK;
PB2_q_b[1]_clock_1 = CCD_PIXCLK;
PB2_q_b[1]_clock_enable_0 = E1_mDVAL;
PB2_q_b[1]_PORT_B_data_out = MEMORY(PB2_q_b[1]_PORT_A_data_in_reg, , PB2_q_b[1]_PORT_A_address_reg, PB2_q_b[1]_PORT_B_address_reg, PB2_q_b[1]_PORT_A_write_enable_reg, PB2_q_b[1]_PORT_B_read_enable_reg, , , PB2_q_b[1]_clock_0, PB2_q_b[1]_clock_1, PB2_q_b[1]_clock_enable_0, , , );
PB2_q_b[1]_PORT_B_data_out_reg = DFFE(PB2_q_b[1]_PORT_B_data_out, PB2_q_b[1]_clock_1, , , );
PB2_q_b[1] = PB2_q_b[1]_PORT_B_data_out_reg[0];


--PB2_q_b[7] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[7]_PORT_A_data_in = E1_mCCD_G[8];
PB2_q_b[7]_PORT_A_data_in_reg = DFFE(PB2_q_b[7]_PORT_A_data_in, PB2_q_b[7]_clock_0, , , PB2_q_b[7]_clock_enable_0);
PB2_q_b[7]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[7]_PORT_A_address_reg = DFFE(PB2_q_b[7]_PORT_A_address, PB2_q_b[7]_clock_0, , , PB2_q_b[7]_clock_enable_0);
PB2_q_b[7]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[7]_PORT_B_address_reg = DFFE(PB2_q_b[7]_PORT_B_address, PB2_q_b[7]_clock_1, , , );
PB2_q_b[7]_PORT_A_write_enable = VCC;
PB2_q_b[7]_PORT_A_write_enable_reg = DFFE(PB2_q_b[7]_PORT_A_write_enable, PB2_q_b[7]_clock_0, , , PB2_q_b[7]_clock_enable_0);
PB2_q_b[7]_PORT_B_read_enable = VCC;
PB2_q_b[7]_PORT_B_read_enable_reg = DFFE(PB2_q_b[7]_PORT_B_read_enable, PB2_q_b[7]_clock_1, , , );
PB2_q_b[7]_clock_0 = CCD_PIXCLK;
PB2_q_b[7]_clock_1 = CCD_PIXCLK;
PB2_q_b[7]_clock_enable_0 = E1_mDVAL;
PB2_q_b[7]_PORT_B_data_out = MEMORY(PB2_q_b[7]_PORT_A_data_in_reg, , PB2_q_b[7]_PORT_A_address_reg, PB2_q_b[7]_PORT_B_address_reg, PB2_q_b[7]_PORT_A_write_enable_reg, PB2_q_b[7]_PORT_B_read_enable_reg, , , PB2_q_b[7]_clock_0, PB2_q_b[7]_clock_1, PB2_q_b[7]_clock_enable_0, , , );
PB2_q_b[7]_PORT_B_data_out_reg = DFFE(PB2_q_b[7]_PORT_B_data_out, PB2_q_b[7]_clock_1, , , );
PB2_q_b[7] = PB2_q_b[7]_PORT_B_data_out_reg[0];


--PB2_q_b[2] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[2]_PORT_A_data_in = E1_mCCD_G[3];
PB2_q_b[2]_PORT_A_data_in_reg = DFFE(PB2_q_b[2]_PORT_A_data_in, PB2_q_b[2]_clock_0, , , PB2_q_b[2]_clock_enable_0);
PB2_q_b[2]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[2]_PORT_A_address_reg = DFFE(PB2_q_b[2]_PORT_A_address, PB2_q_b[2]_clock_0, , , PB2_q_b[2]_clock_enable_0);
PB2_q_b[2]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[2]_PORT_B_address_reg = DFFE(PB2_q_b[2]_PORT_B_address, PB2_q_b[2]_clock_1, , , );
PB2_q_b[2]_PORT_A_write_enable = VCC;
PB2_q_b[2]_PORT_A_write_enable_reg = DFFE(PB2_q_b[2]_PORT_A_write_enable, PB2_q_b[2]_clock_0, , , PB2_q_b[2]_clock_enable_0);
PB2_q_b[2]_PORT_B_read_enable = VCC;
PB2_q_b[2]_PORT_B_read_enable_reg = DFFE(PB2_q_b[2]_PORT_B_read_enable, PB2_q_b[2]_clock_1, , , );
PB2_q_b[2]_clock_0 = CCD_PIXCLK;
PB2_q_b[2]_clock_1 = CCD_PIXCLK;
PB2_q_b[2]_clock_enable_0 = E1_mDVAL;
PB2_q_b[2]_PORT_B_data_out = MEMORY(PB2_q_b[2]_PORT_A_data_in_reg, , PB2_q_b[2]_PORT_A_address_reg, PB2_q_b[2]_PORT_B_address_reg, PB2_q_b[2]_PORT_A_write_enable_reg, PB2_q_b[2]_PORT_B_read_enable_reg, , , PB2_q_b[2]_clock_0, PB2_q_b[2]_clock_1, PB2_q_b[2]_clock_enable_0, , , );
PB2_q_b[2]_PORT_B_data_out_reg = DFFE(PB2_q_b[2]_PORT_B_data_out, PB2_q_b[2]_clock_1, , , );
PB2_q_b[2] = PB2_q_b[2]_PORT_B_data_out_reg[0];


--PB2_q_b[8] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[8]_PORT_A_data_in = E1_mCCD_G[9];
PB2_q_b[8]_PORT_A_data_in_reg = DFFE(PB2_q_b[8]_PORT_A_data_in, PB2_q_b[8]_clock_0, , , PB2_q_b[8]_clock_enable_0);
PB2_q_b[8]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[8]_PORT_A_address_reg = DFFE(PB2_q_b[8]_PORT_A_address, PB2_q_b[8]_clock_0, , , PB2_q_b[8]_clock_enable_0);
PB2_q_b[8]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[8]_PORT_B_address_reg = DFFE(PB2_q_b[8]_PORT_B_address, PB2_q_b[8]_clock_1, , , );
PB2_q_b[8]_PORT_A_write_enable = VCC;
PB2_q_b[8]_PORT_A_write_enable_reg = DFFE(PB2_q_b[8]_PORT_A_write_enable, PB2_q_b[8]_clock_0, , , PB2_q_b[8]_clock_enable_0);
PB2_q_b[8]_PORT_B_read_enable = VCC;
PB2_q_b[8]_PORT_B_read_enable_reg = DFFE(PB2_q_b[8]_PORT_B_read_enable, PB2_q_b[8]_clock_1, , , );
PB2_q_b[8]_clock_0 = CCD_PIXCLK;
PB2_q_b[8]_clock_1 = CCD_PIXCLK;
PB2_q_b[8]_clock_enable_0 = E1_mDVAL;
PB2_q_b[8]_PORT_B_data_out = MEMORY(PB2_q_b[8]_PORT_A_data_in_reg, , PB2_q_b[8]_PORT_A_address_reg, PB2_q_b[8]_PORT_B_address_reg, PB2_q_b[8]_PORT_A_write_enable_reg, PB2_q_b[8]_PORT_B_read_enable_reg, , , PB2_q_b[8]_clock_0, PB2_q_b[8]_clock_1, PB2_q_b[8]_clock_enable_0, , , );
PB2_q_b[8]_PORT_B_data_out_reg = DFFE(PB2_q_b[8]_PORT_B_data_out, PB2_q_b[8]_clock_1, , , );
PB2_q_b[8] = PB2_q_b[8]_PORT_B_data_out_reg[0];


--PB2_q_b[3] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[3]_PORT_A_data_in = E1_mCCD_G[4];
PB2_q_b[3]_PORT_A_data_in_reg = DFFE(PB2_q_b[3]_PORT_A_data_in, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[3]_PORT_A_address_reg = DFFE(PB2_q_b[3]_PORT_A_address, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[3]_PORT_B_address_reg = DFFE(PB2_q_b[3]_PORT_B_address, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3]_PORT_A_write_enable = VCC;
PB2_q_b[3]_PORT_A_write_enable_reg = DFFE(PB2_q_b[3]_PORT_A_write_enable, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_B_read_enable = VCC;
PB2_q_b[3]_PORT_B_read_enable_reg = DFFE(PB2_q_b[3]_PORT_B_read_enable, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3]_clock_0 = CCD_PIXCLK;
PB2_q_b[3]_clock_1 = CCD_PIXCLK;
PB2_q_b[3]_clock_enable_0 = E1_mDVAL;
PB2_q_b[3]_PORT_B_data_out = MEMORY(PB2_q_b[3]_PORT_A_data_in_reg, , PB2_q_b[3]_PORT_A_address_reg, PB2_q_b[3]_PORT_B_address_reg, PB2_q_b[3]_PORT_A_write_enable_reg, PB2_q_b[3]_PORT_B_read_enable_reg, , , PB2_q_b[3]_clock_0, PB2_q_b[3]_clock_1, PB2_q_b[3]_clock_enable_0, , , );
PB2_q_b[3]_PORT_B_data_out_reg = DFFE(PB2_q_b[3]_PORT_B_data_out, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3] = PB2_q_b[3]_PORT_B_data_out_reg[0];


--PB2_q_b[9] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[9]_PORT_A_data_in = E1_mCCD_G[10];
PB2_q_b[9]_PORT_A_data_in_reg = DFFE(PB2_q_b[9]_PORT_A_data_in, PB2_q_b[9]_clock_0, , , PB2_q_b[9]_clock_enable_0);
PB2_q_b[9]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[9]_PORT_A_address_reg = DFFE(PB2_q_b[9]_PORT_A_address, PB2_q_b[9]_clock_0, , , PB2_q_b[9]_clock_enable_0);
PB2_q_b[9]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[9]_PORT_B_address_reg = DFFE(PB2_q_b[9]_PORT_B_address, PB2_q_b[9]_clock_1, , , );
PB2_q_b[9]_PORT_A_write_enable = VCC;
PB2_q_b[9]_PORT_A_write_enable_reg = DFFE(PB2_q_b[9]_PORT_A_write_enable, PB2_q_b[9]_clock_0, , , PB2_q_b[9]_clock_enable_0);
PB2_q_b[9]_PORT_B_read_enable = VCC;
PB2_q_b[9]_PORT_B_read_enable_reg = DFFE(PB2_q_b[9]_PORT_B_read_enable, PB2_q_b[9]_clock_1, , , );
PB2_q_b[9]_clock_0 = CCD_PIXCLK;
PB2_q_b[9]_clock_1 = CCD_PIXCLK;
PB2_q_b[9]_clock_enable_0 = E1_mDVAL;
PB2_q_b[9]_PORT_B_data_out = MEMORY(PB2_q_b[9]_PORT_A_data_in_reg, , PB2_q_b[9]_PORT_A_address_reg, PB2_q_b[9]_PORT_B_address_reg, PB2_q_b[9]_PORT_A_write_enable_reg, PB2_q_b[9]_PORT_B_read_enable_reg, , , PB2_q_b[9]_clock_0, PB2_q_b[9]_clock_1, PB2_q_b[9]_clock_enable_0, , , );
PB2_q_b[9]_PORT_B_data_out_reg = DFFE(PB2_q_b[9]_PORT_B_data_out, PB2_q_b[9]_clock_1, , , );
PB2_q_b[9] = PB2_q_b[9]_PORT_B_data_out_reg[0];


--PB2_q_b[4] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 640, Port A Width: 1, Port B Depth: 640, Port B Width: 1
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[4]_PORT_A_data_in = E1_mCCD_G[5];
PB2_q_b[4]_PORT_A_data_in_reg = DFFE(PB2_q_b[4]_PORT_A_data_in, PB2_q_b[4]_clock_0, , , PB2_q_b[4]_clock_enable_0);
PB2_q_b[4]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[4]_PORT_A_address_reg = DFFE(PB2_q_b[4]_PORT_A_address, PB2_q_b[4]_clock_0, , , PB2_q_b[4]_clock_enable_0);
PB2_q_b[4]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[4]_PORT_B_address_reg = DFFE(PB2_q_b[4]_PORT_B_address, PB2_q_b[4]_clock_1, , , );
PB2_q_b[4]_PORT_A_write_enable = VCC;
PB2_q_b[4]_PORT_A_write_enable_reg = DFFE(PB2_q_b[4]_PORT_A_write_enable, PB2_q_b[4]_clock_0, , , PB2_q_b[4]_clock_enable_0);
PB2_q_b[4]_PORT_B_read_enable = VCC;
PB2_q_b[4]_PORT_B_read_enable_reg = DFFE(PB2_q_b[4]_PORT_B_read_enable, PB2_q_b[4]_clock_1, , , );
PB2_q_b[4]_clock_0 = CCD_PIXCLK;
PB2_q_b[4]_clock_1 = CCD_PIXCLK;
PB2_q_b[4]_clock_enable_0 = E1_mDVAL;
PB2_q_b[4]_PORT_B_data_out = MEMORY(PB2_q_b[4]_PORT_A_data_in_reg, , PB2_q_b[4]_PORT_A_address_reg, PB2_q_b[4]_PORT_B_address_reg, PB2_q_b[4]_PORT_A_write_enable_reg, PB2_q_b[4]_PORT_B_read_enable_reg, , , PB2_q_b[4]_clock_0, PB2_q_b[4]_clock_1, PB2_q_b[4]_clock_enable_0, , , );
PB2_q_b[4]_PORT_B_data_out_reg = DFFE(PB2_q_b[4]_PORT_B_data_out, PB2_q_b[4]_clock_1, , , );
PB2_q_b[4] = PB2_q_b[4]_PORT_B_data_out_reg[0];


--LB1L60 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1081
LB1L60 = !LB1L56Q & !LB1L50Q & !LB1L53Q & !LB1L47Q;


--LB1L18 is I2C_CCD_Config:u7|I2C_Controller:u0|LessThan~163
LB1L18 = LB1L44Q # LB1L59Q # !LB1L60;


--LB1L42 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~302
LB1L42 = LB1L18 & !LB1L44Q # !LB1L18 & LB1L44Q & VCC;

--LB1L43 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~303
LB1L43 = CARRY(LB1L18 & !LB1L44Q);


--H1_mI2C_GO is I2C_CCD_Config:u7|mI2C_GO
H1_mI2C_GO = DFFEAS(H1L39, H1_mI2C_CTRL_CLK, KEY[1],  , H1L38,  ,  ,  ,  );


--LB1L45 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~304
LB1L45 = LB1L47Q & (GND # !LB1L43) # !LB1L47Q & (LB1L43 $ GND);

--LB1L46 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~305
LB1L46 = CARRY(LB1L47Q # !LB1L43);


--LB1L48 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~306
LB1L48 = LB1L50Q & LB1L46 & VCC # !LB1L50Q & !LB1L46;

--LB1L49 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~307
LB1L49 = CARRY(!LB1L50Q & !LB1L46);


--LB1L51 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~308
LB1L51 = LB1L53Q & (GND # !LB1L49) # !LB1L53Q & (LB1L49 $ GND);

--LB1L52 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~309
LB1L52 = CARRY(LB1L53Q # !LB1L49);


--LB1L54 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~310
LB1L54 = LB1L56Q & LB1L52 & VCC # !LB1L56Q & !LB1L52;

--LB1L55 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~311
LB1L55 = CARRY(!LB1L56Q & !LB1L52);


--LB1L57 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[5]~312
LB1L57 = LB1L59Q $ LB1L55;


--H1_mI2C_CLK_DIV[12] is I2C_CCD_Config:u7|mI2C_CLK_DIV[12]
H1_mI2C_CLK_DIV[12] = DFFEAS(H1L80, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[13] is I2C_CCD_Config:u7|mI2C_CLK_DIV[13]
H1_mI2C_CLK_DIV[13] = DFFEAS(H1L83, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[14] is I2C_CCD_Config:u7|mI2C_CLK_DIV[14]
H1_mI2C_CLK_DIV[14] = DFFEAS(H1L86, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[15] is I2C_CCD_Config:u7|mI2C_CLK_DIV[15]
H1_mI2C_CLK_DIV[15] = DFFEAS(H1L89, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1L32 is I2C_CCD_Config:u7|LessThan~303
H1L32 = !H1_mI2C_CLK_DIV[12] & !H1_mI2C_CLK_DIV[13] & !H1_mI2C_CLK_DIV[14] & !H1_mI2C_CLK_DIV[15];


--H1_mI2C_CLK_DIV[2] is I2C_CCD_Config:u7|mI2C_CLK_DIV[2]
H1_mI2C_CLK_DIV[2] = DFFEAS(H1L50, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[3] is I2C_CCD_Config:u7|mI2C_CLK_DIV[3]
H1_mI2C_CLK_DIV[3] = DFFEAS(H1L53, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[4] is I2C_CCD_Config:u7|mI2C_CLK_DIV[4]
H1_mI2C_CLK_DIV[4] = DFFEAS(H1L56, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[5] is I2C_CCD_Config:u7|mI2C_CLK_DIV[5]
H1_mI2C_CLK_DIV[5] = DFFEAS(H1L59, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1L33 is I2C_CCD_Config:u7|LessThan~304
H1L33 = !H1_mI2C_CLK_DIV[2] & !H1_mI2C_CLK_DIV[3] & !H1_mI2C_CLK_DIV[4] & !H1_mI2C_CLK_DIV[5];


--H1_mI2C_CLK_DIV[6] is I2C_CCD_Config:u7|mI2C_CLK_DIV[6]
H1_mI2C_CLK_DIV[6] = DFFEAS(H1L62, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[7] is I2C_CCD_Config:u7|mI2C_CLK_DIV[7]
H1_mI2C_CLK_DIV[7] = DFFEAS(H1L65, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[8] is I2C_CCD_Config:u7|mI2C_CLK_DIV[8]
H1_mI2C_CLK_DIV[8] = DFFEAS(H1L68, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1L34 is I2C_CCD_Config:u7|LessThan~305
H1L34 = H1L33 # !H1_mI2C_CLK_DIV[8] # !H1_mI2C_CLK_DIV[7] # !H1_mI2C_CLK_DIV[6];


--H1_mI2C_CLK_DIV[9] is I2C_CCD_Config:u7|mI2C_CLK_DIV[9]
H1_mI2C_CLK_DIV[9] = DFFEAS(H1L71, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[10] is I2C_CCD_Config:u7|mI2C_CLK_DIV[10]
H1_mI2C_CLK_DIV[10] = DFFEAS(H1L74, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1L35 is I2C_CCD_Config:u7|LessThan~306
H1L35 = !H1_mI2C_CLK_DIV[9] & !H1_mI2C_CLK_DIV[10];


--H1_mI2C_CLK_DIV[11] is I2C_CCD_Config:u7|mI2C_CLK_DIV[11]
H1_mI2C_CLK_DIV[11] = DFFEAS(H1L77, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1L36 is I2C_CCD_Config:u7|LessThan~307
H1L36 = H1_mI2C_CLK_DIV[11] & (!H1L35 # !H1L34) # !H1L32;


--H1L92 is I2C_CCD_Config:u7|mI2C_CTRL_CLK~79
H1L92 = H1_mI2C_CTRL_CLK $ H1L36;


--LB1L20 is I2C_CCD_Config:u7|I2C_Controller:u0|SCLK~145
LB1L20 = LB1L47Q & !LB1L53Q # !LB1L47Q & (LB1L50Q);


--LB1L21 is I2C_CCD_Config:u7|I2C_Controller:u0|SCLK~146
LB1L21 = LB1L56Q & (!LB1L20 # !LB1L53Q # !LB1L44Q) # !LB1L56Q & (LB1L53Q # LB1L20);


--LB1L41 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[15]~777
LB1L41 = LB1L56Q & LB1L50Q & LB1L53Q & LB1L47Q;


--LB1L22 is I2C_CCD_Config:u7|I2C_Controller:u0|SCLK~147
LB1L22 = LB1L44Q & (LB1L41 $ !LB1L21);


--LB1L23 is I2C_CCD_Config:u7|I2C_Controller:u0|SCLK~148
LB1L23 = LB1L59Q & (LB1L21 & LB1_SCLK & !LB1L22 # !LB1L21 & (LB1L22)) # !LB1L59Q & LB1_SCLK;


--LB1L61 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1082
LB1L61 = LB1L44Q & LB1L50Q & LB1L53Q & LB1L47Q;


--LB1_SD[2] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[2]
LB1_SD[2] = DFFEAS(H1_mI2C_DATA[2], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1_SD[8] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[8]
LB1_SD[8] = DFFEAS(H1_mI2C_DATA[8], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1_SD[9] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[9]
LB1_SD[9] = DFFEAS(H1_mI2C_DATA[9], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1L62 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1083
LB1L62 = LB1L53Q & (LB1L44Q & (LB1_SD[9]) # !LB1L44Q & LB1_SD[8]) # !LB1L53Q & (!LB1L44Q);


--LB1_SD[1] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[1]
LB1_SD[1] = DFFEAS(H1_mI2C_DATA[1], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1L63 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1084
LB1L63 = LB1L53Q & (LB1L62) # !LB1L53Q & (LB1L62 & (LB1_SD[1]) # !LB1L62 & LB1_SD[2]);


--LB1_SD[7] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[7]
LB1_SD[7] = DFFEAS(H1_mI2C_DATA[7], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1_SD[0] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[0]
LB1_SD[0] = DFFEAS(H1_mI2C_DATA[0], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1L64 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1085
LB1L64 = LB1L44Q & (LB1_SD[0] # LB1L53Q) # !LB1L44Q & (LB1_SD[7] # !LB1L53Q);


--LB1_SD[4] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[4]
LB1_SD[4] = DFFEAS(H1_mI2C_DATA[4], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1_SD[10] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[10]
LB1_SD[10] = DFFEAS(H1_mI2C_DATA[10], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1_SD[11] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[11]
LB1_SD[11] = DFFEAS(H1_mI2C_DATA[11], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1L65 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1086
LB1L65 = LB1L53Q & (LB1L44Q & (LB1_SD[11]) # !LB1L44Q & LB1_SD[10]) # !LB1L53Q & (!LB1L44Q);


--LB1_SD[3] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[3]
LB1_SD[3] = DFFEAS(H1_mI2C_DATA[3], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1L66 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1087
LB1L66 = LB1L53Q & (LB1L65) # !LB1L53Q & (LB1L65 & (LB1_SD[3]) # !LB1L65 & LB1_SD[4]);


--LB1L67 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1088
LB1L67 = LB1L47Q & (LB1L50Q & (LB1L66) # !LB1L50Q & LB1L64) # !LB1L47Q & (!LB1L50Q);


--LB1_SD[6] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[6]
LB1_SD[6] = DFFEAS(H1_mI2C_DATA[6], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1_SD[5] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[5]
LB1_SD[5] = DFFEAS(H1_mI2C_DATA[5], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1L68 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1089
LB1L68 = LB1L44Q & LB1_SD[6] # !LB1L44Q & (LB1_SD[5]);


--LB1L69 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1090
LB1L69 = LB1L53Q & LB1L68 # !LB1L53Q & (!LB1L44Q & !LB1L25Q);


--LB1L70 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1091
LB1L70 = LB1L47Q & (LB1L67) # !LB1L47Q & (LB1L67 & (LB1L69) # !LB1L67 & LB1L63);


--LB1L71 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1092
LB1L71 = LB1L44Q & LB1L47Q;


--LB1L72 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1093
LB1L72 = LB1L44Q & (LB1L47Q # !LB1L25Q) # !LB1L44Q & !LB1L47Q;


--LB1L73 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1094
LB1L73 = LB1L50Q & (LB1L53Q & (LB1L72) # !LB1L53Q & !LB1L44Q) # !LB1L50Q & (!LB1L53Q);


--LB1_SD[15] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[15]
LB1_SD[15] = DFFEAS(H1_mI2C_DATA[15], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1_SD[13] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[13]
LB1_SD[13] = DFFEAS(H1_mI2C_DATA[13], H1_mI2C_CTRL_CLK,  ,  , LB1L40,  ,  ,  ,  );


--LB1L74 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1095
LB1L74 = LB1L44Q & (LB1L47Q & LB1_SD[15] # !LB1L47Q & (LB1_SD[13])) # !LB1L44Q & LB1_SD[15];


--LB1L75 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1096
LB1L75 = LB1L50Q & (LB1L73) # !LB1L50Q & (LB1L73 & (LB1L74) # !LB1L73 & !LB1L71);


--LB1L76 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1097
LB1L76 = LB1L59Q & (LB1L56Q & (LB1L75) # !LB1L56Q & LB1L70) # !LB1L59Q & (!LB1L56Q);


--LB1L77 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1098
LB1L77 = LB1L59Q & (!LB1L76) # !LB1L59Q & LB1L25Q & (LB1L76 # !LB1L61);


--S1_init_timer[10] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[10]
S1_init_timer[10] = DFFEAS(S1L88, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[11] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[11]
S1_init_timer[11] = DFFEAS(S1L91, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[12] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[12]
S1_init_timer[12] = DFFEAS(S1L94, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1L17 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~421
S1L17 = S1_init_timer[10] & S1_init_timer[11] & S1_init_timer[12];


--S1_init_timer[14] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[14]
S1_init_timer[14] = DFFEAS(S1L100, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[0] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[0]
S1_init_timer[0] = DFFEAS(S1L58, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[1] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[1]
S1_init_timer[1] = DFFEAS(S1L61, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[15] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[15]
S1_init_timer[15] = DFFEAS(S1L103, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1L11 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~91
S1L11 = S1_init_timer[14] & !S1_init_timer[0] & !S1_init_timer[1] & !S1_init_timer[15];


--S1_init_timer[13] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[13]
S1_init_timer[13] = DFFEAS(S1L97, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1L12 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~92
S1L12 = S1L17 & S1L11 & !S1_init_timer[13];


--S1_init_timer[9] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[9]
S1_init_timer[9] = DFFEAS(S1L85, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[3] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[3]
S1_init_timer[3] = DFFEAS(S1L67, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[6] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[6]
S1_init_timer[6] = DFFEAS(S1L76, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[2] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[2]
S1_init_timer[2] = DFFEAS(S1L64, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[4] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[4]
S1_init_timer[4] = DFFEAS(S1L70, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1L52 is Sdram_Control_4Port:u6|control_interface:control1|always3~649
S1L52 = S1_init_timer[3] & (S1_init_timer[6] & S1_init_timer[2] & !S1_init_timer[4] # !S1_init_timer[6] & !S1_init_timer[2] & S1_init_timer[4]) # !S1_init_timer[3] & (S1_init_timer[6] $ S1_init_timer[2] $ S1_init_timer[4]);


--S1_init_timer[7] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[7]
S1_init_timer[7] = DFFEAS(S1L79, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[8] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[8]
S1_init_timer[8] = DFFEAS(S1L82, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[5] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[5]
S1_init_timer[5] = DFFEAS(S1L73, KB1__clk0,  ,  , S1L23,  ,  ,  ,  );


--S1L53 is Sdram_Control_4Port:u6|control_interface:control1|always3~650
S1L53 = S1_init_timer[3] & S1_init_timer[6] & (S1_init_timer[2] # !S1_init_timer[4]) # !S1_init_timer[3] & !S1_init_timer[6] & !S1_init_timer[2] & S1_init_timer[4];


--S1L54 is Sdram_Control_4Port:u6|control_interface:control1|always3~651
S1L54 = S1_init_timer[7] & S1_init_timer[8] & S1_init_timer[5] & S1L53 # !S1_init_timer[7] & !S1_init_timer[8] & (S1_init_timer[5] $ S1L53);


--S1L55 is Sdram_Control_4Port:u6|control_interface:control1|always3~652
S1L55 = S1L54 & (S1_init_timer[9] & S1L52 & !S1_init_timer[7] # !S1_init_timer[9] & !S1L52 & S1_init_timer[7]);


--S1L25 is Sdram_Control_4Port:u6|control_interface:control1|PRECHARGE~49
S1L25 = S1_init_timer[7] & S1_init_timer[8] & S1_init_timer[6];


--S1L18 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~422
S1L18 = !S1_init_timer[9] & !S1L25 # !S1L17;


--S1L19 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~423
S1L19 = !S1_init_timer[15] & (S1L18 & !S1_init_timer[13] # !S1_init_timer[14]);


--S1L13 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~93
S1L13 = !S1_init_timer[4] & !S1_init_timer[5] & !S1_init_timer[6];


--S1L14 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~94
S1L14 = S1_init_timer[9] & S1_init_timer[7] & !S1_init_timer[2];


--S1L15 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~95
S1L15 = !S1_init_timer[8] & S1_init_timer[3] & S1L13 & S1L14;


--S1L16 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~96
S1L16 = S1L12 & !S1L55 & !S1L19 & S1L15;


--R1L56 is Sdram_Control_4Port:u6|command:command1|always3~4
R1L56 = R1_do_writea # R1_do_reada # R1_do_refresh # !R1L109;


--R1_command_delay[0] is Sdram_Control_4Port:u6|command:command1|command_delay[0]
R1_command_delay[0] = DFFEAS(R1L67, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L76 is Sdram_Control_4Port:u6|command:command1|command_done~132
R1L76 = !S1_INIT_REQ & (R1L56 # R1_command_delay[0]);


--G1_rWR1_ADDR[8] is Sdram_Control_4Port:u6|rWR1_ADDR[8]
G1_rWR1_ADDR[8] = DFFEAS(G1L371, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1L183 is Sdram_Control_4Port:u6|mADDR[16]~361
G1L183 = BB1L17 # BB6L17 & BB3L17;


--G1_rRD2_ADDR[8] is Sdram_Control_4Port:u6|rRD2_ADDR[8]
G1_rRD2_ADDR[8] = DFFEAS(G1L321, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L261 is Sdram_Control_4Port:u6|mRD~738
G1L261 = BB3L17 & !BB1L17;


--G1_rWR2_ADDR[8] is Sdram_Control_4Port:u6|rWR2_ADDR[8]
G1_rWR2_ADDR[8] = DFFEAS(G1L436, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L190 is Sdram_Control_4Port:u6|mADDR~362
G1L190 = G1L183 & (G1L261) # !G1L183 & (G1L261 & G1_rRD2_ADDR[8] # !G1L261 & (G1_rWR2_ADDR[8]));


--G1_rRD1_ADDR[8] is Sdram_Control_4Port:u6|rRD1_ADDR[8]
G1_rRD1_ADDR[8] = DFFEAS(G1L269, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L191 is Sdram_Control_4Port:u6|mADDR~363
G1L191 = G1L183 & (G1L190 & (G1_rRD1_ADDR[8]) # !G1L190 & G1_rWR1_ADDR[8]) # !G1L183 & (G1L190);


--G1_CMD[1] is Sdram_Control_4Port:u6|CMD[1]
G1_CMD[1] = DFFEAS(G1L109, KB1__clk0,  ,  , G1L8,  ,  ,  ,  );


--G1_CMD[0] is Sdram_Control_4Port:u6|CMD[0]
G1_CMD[0] = DFFEAS(G1L110, KB1__clk0,  ,  , G1L8,  ,  ,  ,  );


--S1L2 is Sdram_Control_4Port:u6|control_interface:control1|Equal~875
S1L2 = G1_CMD[1] & !G1_CMD[0];


--R1_rp_shift[0] is Sdram_Control_4Port:u6|command:command1|rp_shift[0]
R1_rp_shift[0] = DFFEAS(R1L103, KB1__clk0,  ,  , R1L99,  ,  ,  ,  );


--R1L95 is Sdram_Control_4Port:u6|command:command1|rp_done~76
R1L95 = !S1_INIT_REQ & (R1_rp_shift[0] # R1_command_done & !R1_command_delay[0]);


--R1_ex_read is Sdram_Control_4Port:u6|command:command1|ex_read
R1_ex_read = DFFEAS(R1L88, KB1__clk0,  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1_ex_write is Sdram_Control_4Port:u6|command:command1|ex_write
R1_ex_write = DFFEAS(R1L90, KB1__clk0,  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1L98 is Sdram_Control_4Port:u6|command:command1|rp_shift[0]~804
R1L98 = R1_command_delay[0] & (R1_ex_read # R1_ex_write) # !R1_command_delay[0] & !R1_command_done & (R1_ex_read # R1_ex_write);


--R1L99 is Sdram_Control_4Port:u6|command:command1|rp_shift[0]~805
R1L99 = S1_INIT_REQ # G1_PM_STOP # !R1L98;


--S1_timer[0] is Sdram_Control_4Port:u6|control_interface:control1|timer[0]
S1_timer[0] = DFFEAS(S1L107, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[1] is Sdram_Control_4Port:u6|control_interface:control1|timer[1]
S1_timer[1] = DFFEAS(S1L110, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[2] is Sdram_Control_4Port:u6|control_interface:control1|timer[2]
S1_timer[2] = DFFEAS(S1L113, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[3] is Sdram_Control_4Port:u6|control_interface:control1|timer[3]
S1_timer[3] = DFFEAS(S1L116, KB1__clk0,  ,  ,  , R1L19,  ,  , S1L33);


--S1L3 is Sdram_Control_4Port:u6|control_interface:control1|Equal~876
S1L3 = !S1_timer[0] & !S1_timer[1] & !S1_timer[2] & !S1_timer[3];


--S1_timer[4] is Sdram_Control_4Port:u6|control_interface:control1|timer[4]
S1_timer[4] = DFFEAS(S1L119, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[5] is Sdram_Control_4Port:u6|control_interface:control1|timer[5]
S1_timer[5] = DFFEAS(S1L122, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[6] is Sdram_Control_4Port:u6|control_interface:control1|timer[6]
S1_timer[6] = DFFEAS(S1L125, KB1__clk0,  ,  ,  , R1L19,  ,  , S1L33);


--S1_timer[7] is Sdram_Control_4Port:u6|control_interface:control1|timer[7]
S1_timer[7] = DFFEAS(S1L128, KB1__clk0,  ,  ,  , R1L19,  ,  , S1L33);


--S1L4 is Sdram_Control_4Port:u6|control_interface:control1|Equal~877
S1L4 = !S1_timer[4] & !S1_timer[5] & !S1_timer[6] & !S1_timer[7];


--S1_timer[8] is Sdram_Control_4Port:u6|control_interface:control1|timer[8]
S1_timer[8] = DFFEAS(S1L131, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[9] is Sdram_Control_4Port:u6|control_interface:control1|timer[9]
S1_timer[9] = DFFEAS(S1L134, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[10] is Sdram_Control_4Port:u6|control_interface:control1|timer[10]
S1_timer[10] = DFFEAS(S1L137, KB1__clk0,  ,  ,  , VCC,  ,  , S1L33);


--S1_timer[11] is Sdram_Control_4Port:u6|control_interface:control1|timer[11]
S1_timer[11] = DFFEAS(S1L140, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1L5 is Sdram_Control_4Port:u6|control_interface:control1|Equal~878
S1L5 = !S1_timer[8] & !S1_timer[9] & !S1_timer[10] & !S1_timer[11];


--S1_timer[12] is Sdram_Control_4Port:u6|control_interface:control1|timer[12]
S1_timer[12] = DFFEAS(S1L143, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[13] is Sdram_Control_4Port:u6|control_interface:control1|timer[13]
S1_timer[13] = DFFEAS(S1L146, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[14] is Sdram_Control_4Port:u6|control_interface:control1|timer[14]
S1_timer[14] = DFFEAS(S1L149, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[15] is Sdram_Control_4Port:u6|control_interface:control1|timer[15]
S1_timer[15] = DFFEAS(S1L152, KB1__clk0,  ,  ,  , ~GND,  ,  , S1L33);


--S1L6 is Sdram_Control_4Port:u6|control_interface:control1|Equal~879
S1L6 = !S1_timer[12] & !S1_timer[13] & !S1_timer[14] & !S1_timer[15];


--S1L7 is Sdram_Control_4Port:u6|control_interface:control1|Equal~880
S1L7 = S1L3 & S1L4 & S1L5 & S1L6;


--R1_REF_ACK is Sdram_Control_4Port:u6|command:command1|REF_ACK
R1_REF_ACK = DFFEAS(R1L18, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--S1L32 is Sdram_Control_4Port:u6|control_interface:control1|REF_REQ~22
S1L32 = S1L7 # S1_REF_REQ & !S1_INIT_REQ & !R1_REF_ACK;


--S1L8 is Sdram_Control_4Port:u6|control_interface:control1|Equal~881
S1L8 = G1_CMD[0] & !G1_CMD[1];


--G1L28 is Sdram_Control_4Port:u6|Equal~1128
G1L28 = G1_ST[1] & G1L20 & !G1_ST[0];


--G1L264 is Sdram_Control_4Port:u6|mWR_DONE~110
G1L264 = G1_ST[2] & G1L17 & !G1_ST[0] & !G1L28;


--G1L265 is Sdram_Control_4Port:u6|mWR_DONE~111
G1L265 = G1_Write & (G1_mWR_DONE # G1L264);


--R1L9 is Sdram_Control_4Port:u6|command:command1|CM_ACK~102
R1L9 = R1_do_refresh & (S1_REF_REQ & R1_CM_ACK # !S1_REF_REQ & (R1L56)) # !R1_do_refresh & (R1L56);


--G1_rRD2_ADDR[9] is Sdram_Control_4Port:u6|rRD2_ADDR[9]
G1_rRD2_ADDR[9] = DFFEAS(G1L328, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR1_ADDR[9] is Sdram_Control_4Port:u6|rWR1_ADDR[9]
G1_rWR1_ADDR[9] = DFFEAS(G1L378, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rWR2_ADDR[9] is Sdram_Control_4Port:u6|rWR2_ADDR[9]
G1_rWR2_ADDR[9] = DFFEAS(G1L437, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L192 is Sdram_Control_4Port:u6|mADDR~364
G1L192 = G1L261 & (G1L183) # !G1L261 & (G1L183 & G1_rWR1_ADDR[9] # !G1L183 & (G1_rWR2_ADDR[9]));


--G1_rRD1_ADDR[9] is Sdram_Control_4Port:u6|rRD1_ADDR[9]
G1_rRD1_ADDR[9] = DFFEAS(G1L272, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L193 is Sdram_Control_4Port:u6|mADDR~365
G1L193 = G1L261 & (G1L192 & (G1_rRD1_ADDR[9]) # !G1L192 & G1_rRD2_ADDR[9]) # !G1L261 & (G1L192);


--G1_rWR1_ADDR[10] is Sdram_Control_4Port:u6|rWR1_ADDR[10]
G1_rWR1_ADDR[10] = DFFEAS(G1L381, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rRD2_ADDR[10] is Sdram_Control_4Port:u6|rRD2_ADDR[10]
G1_rRD2_ADDR[10] = DFFEAS(G1L331, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR2_ADDR[10] is Sdram_Control_4Port:u6|rWR2_ADDR[10]
G1_rWR2_ADDR[10] = DFFEAS(G1L438, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L194 is Sdram_Control_4Port:u6|mADDR~366
G1L194 = G1L183 & (G1L261) # !G1L183 & (G1L261 & G1_rRD2_ADDR[10] # !G1L261 & (G1_rWR2_ADDR[10]));


--G1_rRD1_ADDR[10] is Sdram_Control_4Port:u6|rRD1_ADDR[10]
G1_rRD1_ADDR[10] = DFFEAS(G1L275, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L195 is Sdram_Control_4Port:u6|mADDR~367
G1L195 = G1L183 & (G1L194 & (G1_rRD1_ADDR[10]) # !G1L194 & G1_rWR1_ADDR[10]) # !G1L183 & (G1L194);


--G1_rRD2_ADDR[11] is Sdram_Control_4Port:u6|rRD2_ADDR[11]
G1_rRD2_ADDR[11] = DFFEAS(G1L334, KB1__clk0,  ,  , G1L327, VCC,  ,  , G1L326);


--G1_rWR1_ADDR[11] is Sdram_Control_4Port:u6|rWR1_ADDR[11]
G1_rWR1_ADDR[11] = DFFEAS(G1L384, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rWR2_ADDR[11] is Sdram_Control_4Port:u6|rWR2_ADDR[11]
G1_rWR2_ADDR[11] = DFFEAS(G1L439, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L196 is Sdram_Control_4Port:u6|mADDR~368
G1L196 = G1L261 & (G1L183) # !G1L261 & (G1L183 & G1_rWR1_ADDR[11] # !G1L183 & (G1_rWR2_ADDR[11]));


--G1_rRD1_ADDR[11] is Sdram_Control_4Port:u6|rRD1_ADDR[11]
G1_rRD1_ADDR[11] = DFFEAS(G1L278, KB1__clk0,  ,  , G1L313, VCC,  ,  , G1L312);


--G1L197 is Sdram_Control_4Port:u6|mADDR~369
G1L197 = G1L261 & (G1L196 & (G1_rRD1_ADDR[11]) # !G1L196 & G1_rRD2_ADDR[11]) # !G1L261 & (G1L196);


--G1_rWR1_ADDR[12] is Sdram_Control_4Port:u6|rWR1_ADDR[12]
G1_rWR1_ADDR[12] = DFFEAS(G1L387, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rRD2_ADDR[12] is Sdram_Control_4Port:u6|rRD2_ADDR[12]
G1_rRD2_ADDR[12] = DFFEAS(G1L337, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR2_ADDR[12] is Sdram_Control_4Port:u6|rWR2_ADDR[12]
G1_rWR2_ADDR[12] = DFFEAS(G1L440, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L198 is Sdram_Control_4Port:u6|mADDR~370
G1L198 = G1L183 & (G1L261) # !G1L183 & (G1L261 & G1_rRD2_ADDR[12] # !G1L261 & (G1_rWR2_ADDR[12]));


--G1_rRD1_ADDR[12] is Sdram_Control_4Port:u6|rRD1_ADDR[12]
G1_rRD1_ADDR[12] = DFFEAS(G1L281, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L199 is Sdram_Control_4Port:u6|mADDR~371
G1L199 = G1L183 & (G1L198 & (G1_rRD1_ADDR[12]) # !G1L198 & G1_rWR1_ADDR[12]) # !G1L183 & (G1L198);


--G1_rRD2_ADDR[13] is Sdram_Control_4Port:u6|rRD2_ADDR[13]
G1_rRD2_ADDR[13] = DFFEAS(G1L340, KB1__clk0,  ,  , G1L327, VCC,  ,  , G1L326);


--G1_rWR1_ADDR[13] is Sdram_Control_4Port:u6|rWR1_ADDR[13]
G1_rWR1_ADDR[13] = DFFEAS(G1L390, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rWR2_ADDR[13] is Sdram_Control_4Port:u6|rWR2_ADDR[13]
G1_rWR2_ADDR[13] = DFFEAS(G1L441, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L200 is Sdram_Control_4Port:u6|mADDR~372
G1L200 = G1L261 & (G1L183) # !G1L261 & (G1L183 & G1_rWR1_ADDR[13] # !G1L183 & (G1_rWR2_ADDR[13]));


--G1_rRD1_ADDR[13] is Sdram_Control_4Port:u6|rRD1_ADDR[13]
G1_rRD1_ADDR[13] = DFFEAS(G1L284, KB1__clk0,  ,  , G1L313, VCC,  ,  , G1L312);


--G1L201 is Sdram_Control_4Port:u6|mADDR~373
G1L201 = G1L261 & (G1L200 & (G1_rRD1_ADDR[13]) # !G1L200 & G1_rRD2_ADDR[13]) # !G1L261 & (G1L200);


--G1_rWR1_ADDR[14] is Sdram_Control_4Port:u6|rWR1_ADDR[14]
G1_rWR1_ADDR[14] = DFFEAS(G1L393, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rRD2_ADDR[14] is Sdram_Control_4Port:u6|rRD2_ADDR[14]
G1_rRD2_ADDR[14] = DFFEAS(G1L343, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR2_ADDR[14] is Sdram_Control_4Port:u6|rWR2_ADDR[14]
G1_rWR2_ADDR[14] = DFFEAS(G1L442, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L202 is Sdram_Control_4Port:u6|mADDR~374
G1L202 = G1L183 & (G1L261) # !G1L183 & (G1L261 & G1_rRD2_ADDR[14] # !G1L261 & (G1_rWR2_ADDR[14]));


--G1_rRD1_ADDR[14] is Sdram_Control_4Port:u6|rRD1_ADDR[14]
G1_rRD1_ADDR[14] = DFFEAS(G1L287, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L203 is Sdram_Control_4Port:u6|mADDR~375
G1L203 = G1L183 & (G1L202 & (G1_rRD1_ADDR[14]) # !G1L202 & G1_rWR1_ADDR[14]) # !G1L183 & (G1L202);


--G1_rRD2_ADDR[15] is Sdram_Control_4Port:u6|rRD2_ADDR[15]
G1_rRD2_ADDR[15] = DFFEAS(G1L346, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR1_ADDR[15] is Sdram_Control_4Port:u6|rWR1_ADDR[15]
G1_rWR1_ADDR[15] = DFFEAS(G1L396, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rWR2_ADDR[15] is Sdram_Control_4Port:u6|rWR2_ADDR[15]
G1_rWR2_ADDR[15] = DFFEAS(G1L443, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L204 is Sdram_Control_4Port:u6|mADDR~376
G1L204 = G1L261 & (G1L183) # !G1L261 & (G1L183 & G1_rWR1_ADDR[15] # !G1L183 & (G1_rWR2_ADDR[15]));


--G1_rRD1_ADDR[15] is Sdram_Control_4Port:u6|rRD1_ADDR[15]
G1_rRD1_ADDR[15] = DFFEAS(G1L290, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L205 is Sdram_Control_4Port:u6|mADDR~377
G1L205 = G1L261 & (G1L204 & (G1_rRD1_ADDR[15]) # !G1L204 & G1_rRD2_ADDR[15]) # !G1L261 & (G1L204);


--G1_rWR1_ADDR[16] is Sdram_Control_4Port:u6|rWR1_ADDR[16]
G1_rWR1_ADDR[16] = DFFEAS(G1L399, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rRD2_ADDR[16] is Sdram_Control_4Port:u6|rRD2_ADDR[16]
G1_rRD2_ADDR[16] = DFFEAS(G1L349, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR2_ADDR[16] is Sdram_Control_4Port:u6|rWR2_ADDR[16]
G1_rWR2_ADDR[16] = DFFEAS(G1L444, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L206 is Sdram_Control_4Port:u6|mADDR~378
G1L206 = G1L183 & (G1L261) # !G1L183 & (G1L261 & G1_rRD2_ADDR[16] # !G1L261 & (G1_rWR2_ADDR[16]));


--G1_rRD1_ADDR[16] is Sdram_Control_4Port:u6|rRD1_ADDR[16]
G1_rRD1_ADDR[16] = DFFEAS(G1L293, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L207 is Sdram_Control_4Port:u6|mADDR~379
G1L207 = G1L183 & (G1L206 & (G1_rRD1_ADDR[16]) # !G1L206 & G1_rWR1_ADDR[16]) # !G1L183 & (G1L206);


--G1_rRD2_ADDR[17] is Sdram_Control_4Port:u6|rRD2_ADDR[17]
G1_rRD2_ADDR[17] = DFFEAS(G1L352, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR1_ADDR[17] is Sdram_Control_4Port:u6|rWR1_ADDR[17]
G1_rWR1_ADDR[17] = DFFEAS(G1L402, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rWR2_ADDR[17] is Sdram_Control_4Port:u6|rWR2_ADDR[17]
G1_rWR2_ADDR[17] = DFFEAS(G1L445, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L208 is Sdram_Control_4Port:u6|mADDR~380
G1L208 = G1L261 & (G1L183) # !G1L261 & (G1L183 & G1_rWR1_ADDR[17] # !G1L183 & (G1_rWR2_ADDR[17]));


--G1_rRD1_ADDR[17] is Sdram_Control_4Port:u6|rRD1_ADDR[17]
G1_rRD1_ADDR[17] = DFFEAS(G1L296, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L209 is Sdram_Control_4Port:u6|mADDR~381
G1L209 = G1L261 & (G1L208 & (G1_rRD1_ADDR[17]) # !G1L208 & G1_rRD2_ADDR[17]) # !G1L261 & (G1L208);


--G1_rWR1_ADDR[18] is Sdram_Control_4Port:u6|rWR1_ADDR[18]
G1_rWR1_ADDR[18] = DFFEAS(G1L405, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rRD2_ADDR[18] is Sdram_Control_4Port:u6|rRD2_ADDR[18]
G1_rRD2_ADDR[18] = DFFEAS(G1L355, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR2_ADDR[18] is Sdram_Control_4Port:u6|rWR2_ADDR[18]
G1_rWR2_ADDR[18] = DFFEAS(G1L446, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L210 is Sdram_Control_4Port:u6|mADDR~382
G1L210 = G1L183 & (G1L261) # !G1L183 & (G1L261 & G1_rRD2_ADDR[18] # !G1L261 & (G1_rWR2_ADDR[18]));


--G1_rRD1_ADDR[18] is Sdram_Control_4Port:u6|rRD1_ADDR[18]
G1_rRD1_ADDR[18] = DFFEAS(G1L299, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L211 is Sdram_Control_4Port:u6|mADDR~383
G1L211 = G1L183 & (G1L210 & (G1_rRD1_ADDR[18]) # !G1L210 & G1_rWR1_ADDR[18]) # !G1L183 & (G1L210);


--S1L26 is Sdram_Control_4Port:u6|control_interface:control1|PRECHARGE~50
S1L26 = S1_init_timer[2] & S1_init_timer[4] & !S1_init_timer[3] & !S1_init_timer[5];


--S1L27 is Sdram_Control_4Port:u6|control_interface:control1|PRECHARGE~51
S1L27 = S1L12 & S1L25 & S1L26 & !S1_init_timer[9];


--R1_rw_shift[1] is Sdram_Control_4Port:u6|command:command1|rw_shift[1]
R1_rw_shift[1] = DFFEAS(R1L57, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L114 is Sdram_Control_4Port:u6|command:command1|rw_shift~15
R1L114 = R1_rw_shift[1] & !R1_do_writea & !R1_do_reada;


--G1_rRD2_ADDR[19] is Sdram_Control_4Port:u6|rRD2_ADDR[19]
G1_rRD2_ADDR[19] = DFFEAS(G1L358, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR1_ADDR[19] is Sdram_Control_4Port:u6|rWR1_ADDR[19]
G1_rWR1_ADDR[19] = DFFEAS(G1L408, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rWR2_ADDR[19] is Sdram_Control_4Port:u6|rWR2_ADDR[19]
G1_rWR2_ADDR[19] = DFFEAS(G1L447, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L212 is Sdram_Control_4Port:u6|mADDR~384
G1L212 = G1L261 & (G1L183) # !G1L261 & (G1L183 & G1_rWR1_ADDR[19] # !G1L183 & (G1_rWR2_ADDR[19]));


--G1_rRD1_ADDR[19] is Sdram_Control_4Port:u6|rRD1_ADDR[19]
G1_rRD1_ADDR[19] = DFFEAS(G1L302, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L213 is Sdram_Control_4Port:u6|mADDR~385
G1L213 = G1L261 & (G1L212 & (G1_rRD1_ADDR[19]) # !G1L212 & G1_rRD2_ADDR[19]) # !G1L261 & (G1L212);


--S1L30 is Sdram_Control_4Port:u6|control_interface:control1|REFRESH~81
S1L30 = S1L12 & S1L55 & !S1L19;


--G1_rWR1_ADDR[22] is Sdram_Control_4Port:u6|rWR1_ADDR[22]
G1_rWR1_ADDR[22] = DFFEAS(G1L417, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rRD2_ADDR[22] is Sdram_Control_4Port:u6|rRD2_ADDR[22]
G1_rRD2_ADDR[22] = DFFEAS(G1L367, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR2_ADDR[22] is Sdram_Control_4Port:u6|rWR2_ADDR[22]
G1_rWR2_ADDR[22] = DFFEAS(G1L448, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L214 is Sdram_Control_4Port:u6|mADDR~386
G1L214 = G1L183 & (G1L261) # !G1L183 & (G1L261 & G1_rRD2_ADDR[22] # !G1L261 & (G1_rWR2_ADDR[22]));


--G1_rRD1_ADDR[22] is Sdram_Control_4Port:u6|rRD1_ADDR[22]
G1_rRD1_ADDR[22] = DFFEAS(G1L317, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L215 is Sdram_Control_4Port:u6|mADDR~387
G1L215 = G1L183 & (G1L214 & (G1_rRD1_ADDR[22]) # !G1L214 & G1_rWR1_ADDR[22]) # !G1L183 & (G1L214);


--G1_rRD2_ADDR[20] is Sdram_Control_4Port:u6|rRD2_ADDR[20]
G1_rRD2_ADDR[20] = DFFEAS(G1L361, KB1__clk0,  ,  , G1L327, VCC,  ,  , G1L326);


--G1_rWR1_ADDR[20] is Sdram_Control_4Port:u6|rWR1_ADDR[20]
G1_rWR1_ADDR[20] = DFFEAS(G1L411, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rWR2_ADDR[20] is Sdram_Control_4Port:u6|rWR2_ADDR[20]
G1_rWR2_ADDR[20] = DFFEAS(G1L450, KB1__clk0,  ,  ,  , VCC,  ,  , !C1_oRST_0);


--G1L216 is Sdram_Control_4Port:u6|mADDR~388
G1L216 = G1L261 & (G1L183) # !G1L261 & (G1L183 & G1_rWR1_ADDR[20] # !G1L183 & (G1_rWR2_ADDR[20]));


--G1_rRD1_ADDR[20] is Sdram_Control_4Port:u6|rRD1_ADDR[20]
G1_rRD1_ADDR[20] = DFFEAS(G1L305, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L217 is Sdram_Control_4Port:u6|mADDR~389
G1L217 = G1L261 & (G1L216 & (G1_rRD1_ADDR[20]) # !G1L216 & G1_rRD2_ADDR[20]) # !G1L261 & (G1L216);


--G1_rWR1_ADDR[21] is Sdram_Control_4Port:u6|rWR1_ADDR[21]
G1_rWR1_ADDR[21] = DFFEAS(G1L414, KB1__clk0,  ,  , G1L376,  ,  , G1L375,  );


--G1_rRD2_ADDR[21] is Sdram_Control_4Port:u6|rRD2_ADDR[21]
G1_rRD2_ADDR[21] = DFFEAS(G1L364, KB1__clk0,  ,  , G1L327, ~GND,  ,  , G1L326);


--G1_rWR2_ADDR[21] is Sdram_Control_4Port:u6|rWR2_ADDR[21]
G1_rWR2_ADDR[21] = DFFEAS(G1L451, KB1__clk0,  ,  , G1L421,  ,  ,  ,  );


--G1L218 is Sdram_Control_4Port:u6|mADDR~390
G1L218 = G1L183 & (G1L261) # !G1L183 & (G1L261 & G1_rRD2_ADDR[21] # !G1L261 & (G1_rWR2_ADDR[21]));


--G1_rRD1_ADDR[21] is Sdram_Control_4Port:u6|rRD1_ADDR[21]
G1_rRD1_ADDR[21] = DFFEAS(G1L314, KB1__clk0,  ,  , G1L313, ~GND,  ,  , G1L312);


--G1L219 is Sdram_Control_4Port:u6|mADDR~391
G1L219 = G1L183 & (G1L218 & (G1_rRD1_ADDR[21]) # !G1L218 & G1_rWR1_ADDR[21]) # !G1L183 & (G1L218);


--X1_delayed_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[8]
X1_delayed_wrptr_g[8] = DFFEAS(X1_wrptr_g[8], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7]
X1_delayed_wrptr_g[7] = DFFEAS(X1_wrptr_g[7], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6]
X1_delayed_wrptr_g[6] = DFFEAS(X1_wrptr_g[6], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5]
X1_delayed_wrptr_g[5] = DFFEAS(X1_wrptr_g[5], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[4]
X1_delayed_wrptr_g[4] = DFFEAS(X1_wrptr_g[4], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3]
X1_delayed_wrptr_g[3] = DFFEAS(X1_wrptr_g[3], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[2]
X1_delayed_wrptr_g[2] = DFFEAS(X1_wrptr_g[2], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[1]
X1_delayed_wrptr_g[1] = DFFEAS(X1_wrptr_g[1], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0]
X1_delayed_wrptr_g[0] = DFFEAS(X1_wrptr_g[0], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[8]
X2_delayed_wrptr_g[8] = DFFEAS(X2_wrptr_g[8], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7]
X2_delayed_wrptr_g[7] = DFFEAS(X2_wrptr_g[7], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6]
X2_delayed_wrptr_g[6] = DFFEAS(X2_wrptr_g[6], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5]
X2_delayed_wrptr_g[5] = DFFEAS(X2_wrptr_g[5], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[4]
X2_delayed_wrptr_g[4] = DFFEAS(X2_wrptr_g[4], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3]
X2_delayed_wrptr_g[3] = DFFEAS(X2_wrptr_g[3], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[2]
X2_delayed_wrptr_g[2] = DFFEAS(X2_wrptr_g[2], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[1]
X2_delayed_wrptr_g[1] = DFFEAS(X2_wrptr_g[1], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0]
X2_delayed_wrptr_g[0] = DFFEAS(X2_wrptr_g[0], CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--G1L29 is Sdram_Control_4Port:u6|Equal~1129
G1L29 = G1L18 & G1L21 & !G1_ST[0] & !G1_ST[2];


--G1L31 is Sdram_Control_4Port:u6|IN_REQ~138
G1L31 = G1_Write & (G1L28 # G1_IN_REQ & !G1L29) # !G1_Write & (G1_IN_REQ);


--X2_rdaclr is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdaclr
X2_rdaclr = DFFEAS(VCC, !KB1__clk0, C1_oRST_0,  ,  ,  ,  ,  ,  );


--E1_mDVAL is RAW2RGB:u4|mDVAL
E1_mDVAL = DFFEAS(E1L139, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--EB1_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity_ff
EB1_parity_ff = DFFEAS(EB1_parity, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB1_parity is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity
EB1_parity = X1_valid_wrreq & !EB1_parity_ff # !X1_valid_wrreq & EB1_parity_ff & VCC;

--EB1L31 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity~COUT
EB1L31 = CARRY(X1_valid_wrreq & !EB1_parity_ff);


--EB1_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0
EB1_countera0 = X1_valid_wrreq & (EB1L31 $ (GND # !EB1_counter_ffa[0])) # !X1_valid_wrreq & (EB1_counter_ffa[0] # GND);

--EB1L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0~COUT
EB1L12 = CARRY(!EB1L31 # !X1_valid_wrreq);


--EB1_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1
EB1_countera1 = EB1L12 & (EB1_power_modified_counter_values[1] & VCC) # !EB1L12 & (EB1_counter_ffa[0] $ (!EB1_power_modified_counter_values[1] & VCC));

--EB1L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1~COUT
EB1L14 = CARRY(EB1_counter_ffa[0] & !EB1L12);


--EB1_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2
EB1_countera2 = EB1L14 & (EB1_power_modified_counter_values[1] $ (EB1_power_modified_counter_values[2] & VCC)) # !EB1L14 & (EB1_power_modified_counter_values[2] # GND);

--EB1L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2~COUT
EB1L16 = CARRY(EB1_power_modified_counter_values[1] # !EB1L14);


--EB1_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3
EB1_countera3 = EB1L16 & (EB1_power_modified_counter_values[3] & VCC) # !EB1L16 & (EB1_power_modified_counter_values[2] $ (EB1_power_modified_counter_values[3] # GND));

--EB1L18 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3~COUT
EB1L18 = CARRY(!EB1_power_modified_counter_values[2] & !EB1L16);


--EB1_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4
EB1_countera4 = EB1L18 & (EB1_power_modified_counter_values[3] $ (EB1_power_modified_counter_values[4] & VCC)) # !EB1L18 & (EB1_power_modified_counter_values[4] # GND);

--EB1L20 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4~COUT
EB1L20 = CARRY(EB1_power_modified_counter_values[3] # !EB1L18);


--EB1_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5
EB1_countera5 = EB1L20 & (EB1_power_modified_counter_values[5] & VCC) # !EB1L20 & (EB1_power_modified_counter_values[4] $ (EB1_power_modified_counter_values[5] # GND));

--EB1L22 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5~COUT
EB1L22 = CARRY(!EB1_power_modified_counter_values[4] & !EB1L20);


--EB1_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6
EB1_countera6 = EB1L22 & (EB1_power_modified_counter_values[5] $ (EB1_power_modified_counter_values[6] & VCC)) # !EB1L22 & (EB1_power_modified_counter_values[6] # GND);

--EB1L24 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6~COUT
EB1L24 = CARRY(EB1_power_modified_counter_values[5] # !EB1L22);


--EB1_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7
EB1_countera7 = EB1L24 & (EB1_power_modified_counter_values[7] & VCC) # !EB1L24 & (EB1_power_modified_counter_values[6] $ (EB1_power_modified_counter_values[7] # GND));

--EB1L26 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7~COUT
EB1L26 = CARRY(!EB1_power_modified_counter_values[6] & !EB1L24);


--EB1_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera8
EB1_countera8 = EB1_power_modified_counter_values[8] $ EB1L26;


--Z1_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity_ff
Z1_parity_ff = DFFEAS(Z1_parity, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z1_parity is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity
Z1_parity = X1_rdcnt_addr_ena & (Z1_parity_ff $ VCC) # !X1_rdcnt_addr_ena & Z1_parity_ff & VCC;

--Z1L31 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity~COUT
Z1L31 = CARRY(X1_rdcnt_addr_ena & Z1_parity_ff);


--Z1_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0
Z1_countera0 = X1_rdcnt_addr_ena & (Z1L31 $ (GND # !Z1_power_modified_counter_values[0])) # !X1_rdcnt_addr_ena & (Z1_power_modified_counter_values[0] # GND);

--Z1L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0~COUT
Z1L12 = CARRY(!Z1L31 # !X1_rdcnt_addr_ena);


--Z1_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1
Z1_countera1 = Z1L12 & (Z1_power_modified_counter_values[1] & VCC) # !Z1L12 & (Z1_power_modified_counter_values[0] $ (Z1_power_modified_counter_values[1] # GND));

--Z1L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1~COUT
Z1L14 = CARRY(!Z1_power_modified_counter_values[0] & !Z1L12);


--Z1_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2
Z1_countera2 = Z1L14 & (Z1_power_modified_counter_values[1] $ (Z1_power_modified_counter_values[2] & VCC)) # !Z1L14 & (Z1_power_modified_counter_values[2] # GND);

--Z1L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2~COUT
Z1L16 = CARRY(Z1_power_modified_counter_values[1] # !Z1L14);


--Z1_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3
Z1_countera3 = Z1L16 & (Z1_power_modified_counter_values[3] & VCC) # !Z1L16 & (Z1_power_modified_counter_values[2] $ (Z1_power_modified_counter_values[3] # GND));

--Z1L18 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3~COUT
Z1L18 = CARRY(!Z1_power_modified_counter_values[2] & !Z1L16);


--Z1_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4
Z1_countera4 = Z1L18 & (Z1_power_modified_counter_values[3] $ (Z1_power_modified_counter_values[4] & VCC)) # !Z1L18 & (Z1_power_modified_counter_values[4] # GND);

--Z1L20 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4~COUT
Z1L20 = CARRY(Z1_power_modified_counter_values[3] # !Z1L18);


--Z1_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5
Z1_countera5 = Z1L20 & (Z1_power_modified_counter_values[5] & VCC) # !Z1L20 & (Z1_power_modified_counter_values[4] $ (Z1_power_modified_counter_values[5] # GND));

--Z1L22 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5~COUT
Z1L22 = CARRY(!Z1_power_modified_counter_values[4] & !Z1L20);


--Z1_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6
Z1_countera6 = Z1L22 & (Z1_power_modified_counter_values[5] $ (Z1_power_modified_counter_values[6] & VCC)) # !Z1L22 & (Z1_power_modified_counter_values[6] # GND);

--Z1L24 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6~COUT
Z1L24 = CARRY(Z1_power_modified_counter_values[5] # !Z1L22);


--Z1_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7
Z1_countera7 = Z1L24 & (Z1_power_modified_counter_values[7] & VCC) # !Z1L24 & (Z1_power_modified_counter_values[6] $ (Z1_power_modified_counter_values[7] # GND));

--Z1L26 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7~COUT
Z1L26 = CARRY(!Z1_power_modified_counter_values[6] & !Z1L24);


--Z1_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera8
Z1_countera8 = Z1_power_modified_counter_values[8] $ Z1L26;


--E1_mCCD_B[0] is RAW2RGB:u4|mCCD_B[0]
E1_mCCD_B[0] = DFFEAS(E1L33, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--J1_Z_Cont[0] is Mirror_Col:u8|Z_Cont[0]
J1_Z_Cont[0] = DFFEAS(J1L4, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[1] is Mirror_Col:u8|Z_Cont[1]
J1_Z_Cont[1] = DFFEAS(J1L8, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[2] is Mirror_Col:u8|Z_Cont[2]
J1_Z_Cont[2] = DFFEAS(J1L12, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[3] is Mirror_Col:u8|Z_Cont[3]
J1_Z_Cont[3] = DFFEAS(J1L16, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[4] is Mirror_Col:u8|Z_Cont[4]
J1_Z_Cont[4] = DFFEAS(J1L20, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[5] is Mirror_Col:u8|Z_Cont[5]
J1_Z_Cont[5] = DFFEAS(J1L24, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[6] is Mirror_Col:u8|Z_Cont[6]
J1_Z_Cont[6] = DFFEAS(J1L28, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[7] is Mirror_Col:u8|Z_Cont[7]
J1_Z_Cont[7] = DFFEAS(J1L32, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[8] is Mirror_Col:u8|Z_Cont[8]
J1_Z_Cont[8] = DFFEAS(J1L35, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[9] is Mirror_Col:u8|Z_Cont[9]
J1_Z_Cont[9] = DFFEAS(J1L38, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  , J1L1,  );


--J1L40 is Mirror_Col:u8|add~271
J1L40 = J1_Z_Cont[7] $ J1_Z_Cont[8];


--J1L41 is Mirror_Col:u8|add~272
J1L41 = J1_Z_Cont[9] $ (!J1_Z_Cont[7] & !J1_Z_Cont[8]);


--EB2_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity_ff
EB2_parity_ff = DFFEAS(EB2_parity, CCD_PIXCLK, C1_oRST_0,  ,  ,  ,  ,  ,  );


--EB2_parity is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity
EB2_parity = X2_valid_wrreq & !EB2_parity_ff # !X2_valid_wrreq & EB2_parity_ff & VCC;

--EB2L31 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity~COUT
EB2L31 = CARRY(X2_valid_wrreq & !EB2_parity_ff);


--EB2_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0
EB2_countera0 = X2_valid_wrreq & (EB2L31 $ (GND # !EB2_counter_ffa[0])) # !X2_valid_wrreq & (EB2_counter_ffa[0] # GND);

--EB2L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0~COUT
EB2L12 = CARRY(!EB2L31 # !X2_valid_wrreq);


--EB2_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1
EB2_countera1 = EB2L12 & (EB2_power_modified_counter_values[1] & VCC) # !EB2L12 & (EB2_counter_ffa[0] $ (!EB2_power_modified_counter_values[1] & VCC));

--EB2L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1~COUT
EB2L14 = CARRY(EB2_counter_ffa[0] & !EB2L12);


--EB2_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2
EB2_countera2 = EB2L14 & (EB2_power_modified_counter_values[1] $ (EB2_power_modified_counter_values[2] & VCC)) # !EB2L14 & (EB2_power_modified_counter_values[2] # GND);

--EB2L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2~COUT
EB2L16 = CARRY(EB2_power_modified_counter_values[1] # !EB2L14);


--EB2_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3
EB2_countera3 = EB2L16 & (EB2_power_modified_counter_values[3] & VCC) # !EB2L16 & (EB2_power_modified_counter_values[2] $ (EB2_power_modified_counter_values[3] # GND));

--EB2L18 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3~COUT
EB2L18 = CARRY(!EB2_power_modified_counter_values[2] & !EB2L16);


--EB2_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4
EB2_countera4 = EB2L18 & (EB2_power_modified_counter_values[3] $ (EB2_power_modified_counter_values[4] & VCC)) # !EB2L18 & (EB2_power_modified_counter_values[4] # GND);

--EB2L20 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4~COUT
EB2L20 = CARRY(EB2_power_modified_counter_values[3] # !EB2L18);


--EB2_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5
EB2_countera5 = EB2L20 & (EB2_power_modified_counter_values[5] & VCC) # !EB2L20 & (EB2_power_modified_counter_values[4] $ (EB2_power_modified_counter_values[5] # GND));

--EB2L22 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5~COUT
EB2L22 = CARRY(!EB2_power_modified_counter_values[4] & !EB2L20);


--EB2_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6
EB2_countera6 = EB2L22 & (EB2_power_modified_counter_values[5] $ (EB2_power_modified_counter_values[6] & VCC)) # !EB2L22 & (EB2_power_modified_counter_values[6] # GND);

--EB2L24 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6~COUT
EB2L24 = CARRY(EB2_power_modified_counter_values[5] # !EB2L22);


--EB2_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7
EB2_countera7 = EB2L24 & (EB2_power_modified_counter_values[7] & VCC) # !EB2L24 & (EB2_power_modified_counter_values[6] $ (EB2_power_modified_counter_values[7] # GND));

--EB2L26 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7~COUT
EB2L26 = CARRY(!EB2_power_modified_counter_values[6] & !EB2L24);


--EB2_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera8
EB2_countera8 = EB2_power_modified_counter_values[8] $ EB2L26;


--Z2_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity_ff
Z2_parity_ff = DFFEAS(Z2_parity, KB1__clk0, X2_rdaclr,  ,  ,  ,  ,  ,  );


--Z2_parity is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity
Z2_parity = X2_rdcnt_addr_ena & (Z2_parity_ff $ VCC) # !X2_rdcnt_addr_ena & Z2_parity_ff & VCC;

--Z2L31 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity~COUT
Z2L31 = CARRY(X2_rdcnt_addr_ena & Z2_parity_ff);


--Z2_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0
Z2_countera0 = X2_rdcnt_addr_ena & (Z2L31 $ (GND # !Z2_power_modified_counter_values[0])) # !X2_rdcnt_addr_ena & (Z2_power_modified_counter_values[0] # GND);

--Z2L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0~COUT
Z2L12 = CARRY(!Z2L31 # !X2_rdcnt_addr_ena);


--Z2_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1
Z2_countera1 = Z2L12 & (Z2_power_modified_counter_values[1] & VCC) # !Z2L12 & (Z2_power_modified_counter_values[0] $ (Z2_power_modified_counter_values[1] # GND));

--Z2L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1~COUT
Z2L14 = CARRY(!Z2_power_modified_counter_values[0] & !Z2L12);


--Z2_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2
Z2_countera2 = Z2L14 & (Z2_power_modified_counter_values[1] $ (Z2_power_modified_counter_values[2] & VCC)) # !Z2L14 & (Z2_power_modified_counter_values[2] # GND);

--Z2L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2~COUT
Z2L16 = CARRY(Z2_power_modified_counter_values[1] # !Z2L14);


--Z2_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3
Z2_countera3 = Z2L16 & (Z2_power_modified_counter_values[3] & VCC) # !Z2L16 & (Z2_power_modified_counter_values[2] $ (Z2_power_modified_counter_values[3] # GND));

--Z2L18 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3~COUT
Z2L18 = CARRY(!Z2_power_modified_counter_values[2] & !Z2L16);


--Z2_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4
Z2_countera4 = Z2L18 & (Z2_power_modified_counter_values[3] $ (Z2_power_modified_counter_values[4] & VCC)) # !Z2L18 & (Z2_power_modified_counter_values[4] # GND);

--Z2L20 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4~COUT
Z2L20 = CARRY(Z2_power_modified_counter_values[3] # !Z2L18);


--Z2_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5
Z2_countera5 = Z2L20 & (Z2_power_modified_counter_values[5] & VCC) # !Z2L20 & (Z2_power_modified_counter_values[4] $ (Z2_power_modified_counter_values[5] # GND));

--Z2L22 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5~COUT
Z2L22 = CARRY(!Z2_power_modified_counter_values[4] & !Z2L20);


--Z2_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6
Z2_countera6 = Z2L22 & (Z2_power_modified_counter_values[5] $ (Z2_power_modified_counter_values[6] & VCC)) # !Z2L22 & (Z2_power_modified_counter_values[6] # GND);

--Z2L24 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6~COUT
Z2L24 = CARRY(Z2_power_modified_counter_values[5] # !Z2L22);


--Z2_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7
Z2_countera7 = Z2L24 & (Z2_power_modified_counter_values[7] & VCC) # !Z2L24 & (Z2_power_modified_counter_values[6] $ (Z2_power_modified_counter_values[7] # GND));

--Z2L26 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7~COUT
Z2L26 = CARRY(!Z2_power_modified_counter_values[6] & !Z2L24);


--Z2_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera8
Z2_countera8 = Z2_power_modified_counter_values[8] $ Z2L26;


--E1_mCCD_R[0] is RAW2RGB:u4|mCCD_R[0]
E1_mCCD_R[0] = DFFEAS(E1L97, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_B[1] is RAW2RGB:u4|mCCD_B[1]
E1_mCCD_B[1] = DFFEAS(E1L35, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_R[1] is RAW2RGB:u4|mCCD_R[1]
E1_mCCD_R[1] = DFFEAS(E1L99, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_B[2] is RAW2RGB:u4|mCCD_B[2]
E1_mCCD_B[2] = DFFEAS(E1L37, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_R[2] is RAW2RGB:u4|mCCD_R[2]
E1_mCCD_R[2] = DFFEAS(E1L101, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_B[3] is RAW2RGB:u4|mCCD_B[3]
E1_mCCD_B[3] = DFFEAS(E1L39, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_R[3] is RAW2RGB:u4|mCCD_R[3]
E1_mCCD_R[3] = DFFEAS(E1L103, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_B[4] is RAW2RGB:u4|mCCD_B[4]
E1_mCCD_B[4] = DFFEAS(E1L41, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_R[4] is RAW2RGB:u4|mCCD_R[4]
E1_mCCD_R[4] = DFFEAS(E1L105, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_B[5] is RAW2RGB:u4|mCCD_B[5]
E1_mCCD_B[5] = DFFEAS(E1L43, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_R[5] is RAW2RGB:u4|mCCD_R[5]
E1_mCCD_R[5] = DFFEAS(E1L107, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_B[6] is RAW2RGB:u4|mCCD_B[6]
E1_mCCD_B[6] = DFFEAS(E1L45, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_R[6] is RAW2RGB:u4|mCCD_R[6]
E1_mCCD_R[6] = DFFEAS(E1L109, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_B[7] is RAW2RGB:u4|mCCD_B[7]
E1_mCCD_B[7] = DFFEAS(E1L47, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_R[7] is RAW2RGB:u4|mCCD_R[7]
E1_mCCD_R[7] = DFFEAS(E1L111, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_B[8] is RAW2RGB:u4|mCCD_B[8]
E1_mCCD_B[8] = DFFEAS(E1L49, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_R[8] is RAW2RGB:u4|mCCD_R[8]
E1_mCCD_R[8] = DFFEAS(E1L113, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_B[9] is RAW2RGB:u4|mCCD_B[9]
E1_mCCD_B[9] = DFFEAS(E1L51, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_R[9] is RAW2RGB:u4|mCCD_R[9]
E1_mCCD_R[9] = DFFEAS(E1L115, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_G[6] is RAW2RGB:u4|mCCD_G[6]
E1_mCCD_G[6] = DFFEAS(E1L71, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_G[1] is RAW2RGB:u4|mCCD_G[1]
E1_mCCD_G[1] = DFFEAS(E1L56, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_G[7] is RAW2RGB:u4|mCCD_G[7]
E1_mCCD_G[7] = DFFEAS(E1L74, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_G[2] is RAW2RGB:u4|mCCD_G[2]
E1_mCCD_G[2] = DFFEAS(E1L59, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_G[8] is RAW2RGB:u4|mCCD_G[8]
E1_mCCD_G[8] = DFFEAS(E1L77, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_G[3] is RAW2RGB:u4|mCCD_G[3]
E1_mCCD_G[3] = DFFEAS(E1L62, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_G[9] is RAW2RGB:u4|mCCD_G[9]
E1_mCCD_G[9] = DFFEAS(E1L80, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_G[4] is RAW2RGB:u4|mCCD_G[4]
E1_mCCD_G[4] = DFFEAS(E1L65, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_G[10] is RAW2RGB:u4|mCCD_G[10]
E1_mCCD_G[10] = DFFEAS(E1L83, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1_mCCD_G[5] is RAW2RGB:u4|mCCD_G[5]
E1_mCCD_G[5] = DFFEAS(E1L68, CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--LB1_END is I2C_CCD_Config:u7|I2C_Controller:u0|END
LB1_END = DFFEAS(LB1L14, H1_mI2C_CTRL_CLK, KEY[1],  ,  ,  ,  ,  ,  );


--H1_mSetup_ST.0010 is I2C_CCD_Config:u7|mSetup_ST.0010
H1_mSetup_ST.0010 = DFFEAS(H1L129, H1_mI2C_CTRL_CLK, KEY[1],  , H1L38,  ,  ,  ,  );


--H1_mSetup_ST.0001 is I2C_CCD_Config:u7|mSetup_ST.0001
H1_mSetup_ST.0001 = DFFEAS(H1L40, H1_mI2C_CTRL_CLK, KEY[1],  , H1L38,  ,  ,  ,  );


--H1L39 is I2C_CCD_Config:u7|Select~135
H1L39 = H1_mI2C_GO & (LB1_END # !H1_mSetup_ST.0001) # !H1_mI2C_GO & (!H1_mSetup_ST.0010 & !H1_mSetup_ST.0001);


--H1_LUT_INDEX[2] is I2C_CCD_Config:u7|LUT_INDEX[2]
H1_LUT_INDEX[2] = DFFEAS(H1L20, H1_mI2C_CTRL_CLK, KEY[1],  , H1L29,  ,  ,  ,  );


--H1_LUT_INDEX[1] is I2C_CCD_Config:u7|LUT_INDEX[1]
H1_LUT_INDEX[1] = DFFEAS(H1L17, H1_mI2C_CTRL_CLK, KEY[1],  , H1L29,  ,  ,  ,  );


--H1_LUT_INDEX[3] is I2C_CCD_Config:u7|LUT_INDEX[3]
H1_LUT_INDEX[3] = DFFEAS(H1L23, H1_mI2C_CTRL_CLK, KEY[1],  , H1L29,  ,  ,  ,  );


--H1L37 is I2C_CCD_Config:u7|LessThan~308
H1L37 = !H1_LUT_INDEX[2] & !H1_LUT_INDEX[1] & !H1_LUT_INDEX[3];


--H1_LUT_INDEX[0] is I2C_CCD_Config:u7|LUT_INDEX[0]
H1_LUT_INDEX[0] = DFFEAS(H1L14, H1_mI2C_CTRL_CLK, KEY[1],  , H1L29,  ,  ,  ,  );


--H1_LUT_INDEX[4] is I2C_CCD_Config:u7|LUT_INDEX[4]
H1_LUT_INDEX[4] = DFFEAS(H1L26, H1_mI2C_CTRL_CLK, KEY[1],  , H1L29,  ,  ,  ,  );


--H1_LUT_INDEX[5] is I2C_CCD_Config:u7|LUT_INDEX[5]
H1_LUT_INDEX[5] = DFFEAS(H1L30, H1_mI2C_CTRL_CLK, KEY[1],  , H1L29,  ,  ,  ,  );


--H1L38 is I2C_CCD_Config:u7|LessThan~309
H1L38 = !H1_LUT_INDEX[5] & (H1L37 & !H1_LUT_INDEX[0] # !H1_LUT_INDEX[4]);


--H1_mI2C_CLK_DIV[1] is I2C_CCD_Config:u7|mI2C_CLK_DIV[1]
H1_mI2C_CLK_DIV[1] = DFFEAS(H1L47, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[0] is I2C_CCD_Config:u7|mI2C_CLK_DIV[0]
H1_mI2C_CLK_DIV[0] = DFFEAS(H1L44, CLOCK_50, KEY[1],  ,  ,  ,  , H1L36,  );


--H1L44 is I2C_CCD_Config:u7|mI2C_CLK_DIV[0]~239
H1L44 = H1_mI2C_CLK_DIV[0] $ VCC;

--H1L45 is I2C_CCD_Config:u7|mI2C_CLK_DIV[0]~240
H1L45 = CARRY(H1_mI2C_CLK_DIV[0]);


--H1L47 is I2C_CCD_Config:u7|mI2C_CLK_DIV[1]~241
H1L47 = H1_mI2C_CLK_DIV[1] & !H1L45 # !H1_mI2C_CLK_DIV[1] & (H1L45 # GND);

--H1L48 is I2C_CCD_Config:u7|mI2C_CLK_DIV[1]~242
H1L48 = CARRY(!H1L45 # !H1_mI2C_CLK_DIV[1]);


--H1L50 is I2C_CCD_Config:u7|mI2C_CLK_DIV[2]~243
H1L50 = H1_mI2C_CLK_DIV[2] & (H1L48 $ GND) # !H1_mI2C_CLK_DIV[2] & !H1L48 & VCC;

--H1L51 is I2C_CCD_Config:u7|mI2C_CLK_DIV[2]~244
H1L51 = CARRY(H1_mI2C_CLK_DIV[2] & !H1L48);


--H1L53 is I2C_CCD_Config:u7|mI2C_CLK_DIV[3]~245
H1L53 = H1_mI2C_CLK_DIV[3] & !H1L51 # !H1_mI2C_CLK_DIV[3] & (H1L51 # GND);

--H1L54 is I2C_CCD_Config:u7|mI2C_CLK_DIV[3]~246
H1L54 = CARRY(!H1L51 # !H1_mI2C_CLK_DIV[3]);


--H1L56 is I2C_CCD_Config:u7|mI2C_CLK_DIV[4]~247
H1L56 = H1_mI2C_CLK_DIV[4] & (H1L54 $ GND) # !H1_mI2C_CLK_DIV[4] & !H1L54 & VCC;

--H1L57 is I2C_CCD_Config:u7|mI2C_CLK_DIV[4]~248
H1L57 = CARRY(H1_mI2C_CLK_DIV[4] & !H1L54);


--H1L59 is I2C_CCD_Config:u7|mI2C_CLK_DIV[5]~249
H1L59 = H1_mI2C_CLK_DIV[5] & !H1L57 # !H1_mI2C_CLK_DIV[5] & (H1L57 # GND);

--H1L60 is I2C_CCD_Config:u7|mI2C_CLK_DIV[5]~250
H1L60 = CARRY(!H1L57 # !H1_mI2C_CLK_DIV[5]);


--H1L62 is I2C_CCD_Config:u7|mI2C_CLK_DIV[6]~251
H1L62 = H1_mI2C_CLK_DIV[6] & (H1L60 $ GND) # !H1_mI2C_CLK_DIV[6] & !H1L60 & VCC;

--H1L63 is I2C_CCD_Config:u7|mI2C_CLK_DIV[6]~252
H1L63 = CARRY(H1_mI2C_CLK_DIV[6] & !H1L60);


--H1L65 is I2C_CCD_Config:u7|mI2C_CLK_DIV[7]~253
H1L65 = H1_mI2C_CLK_DIV[7] & !H1L63 # !H1_mI2C_CLK_DIV[7] & (H1L63 # GND);

--H1L66 is I2C_CCD_Config:u7|mI2C_CLK_DIV[7]~254
H1L66 = CARRY(!H1L63 # !H1_mI2C_CLK_DIV[7]);


--H1L68 is I2C_CCD_Config:u7|mI2C_CLK_DIV[8]~255
H1L68 = H1_mI2C_CLK_DIV[8] & (H1L66 $ GND) # !H1_mI2C_CLK_DIV[8] & !H1L66 & VCC;

--H1L69 is I2C_CCD_Config:u7|mI2C_CLK_DIV[8]~256
H1L69 = CARRY(H1_mI2C_CLK_DIV[8] & !H1L66);


--H1L71 is I2C_CCD_Config:u7|mI2C_CLK_DIV[9]~257
H1L71 = H1_mI2C_CLK_DIV[9] & !H1L69 # !H1_mI2C_CLK_DIV[9] & (H1L69 # GND);

--H1L72 is I2C_CCD_Config:u7|mI2C_CLK_DIV[9]~258
H1L72 = CARRY(!H1L69 # !H1_mI2C_CLK_DIV[9]);


--H1L74 is I2C_CCD_Config:u7|mI2C_CLK_DIV[10]~259
H1L74 = H1_mI2C_CLK_DIV[10] & (H1L72 $ GND) # !H1_mI2C_CLK_DIV[10] & !H1L72 & VCC;

--H1L75 is I2C_CCD_Config:u7|mI2C_CLK_DIV[10]~260
H1L75 = CARRY(H1_mI2C_CLK_DIV[10] & !H1L72);


--H1L77 is I2C_CCD_Config:u7|mI2C_CLK_DIV[11]~261
H1L77 = H1_mI2C_CLK_DIV[11] & !H1L75 # !H1_mI2C_CLK_DIV[11] & (H1L75 # GND);

--H1L78 is I2C_CCD_Config:u7|mI2C_CLK_DIV[11]~262
H1L78 = CARRY(!H1L75 # !H1_mI2C_CLK_DIV[11]);


--H1L80 is I2C_CCD_Config:u7|mI2C_CLK_DIV[12]~263
H1L80 = H1_mI2C_CLK_DIV[12] & (H1L78 $ GND) # !H1_mI2C_CLK_DIV[12] & !H1L78 & VCC;

--H1L81 is I2C_CCD_Config:u7|mI2C_CLK_DIV[12]~264
H1L81 = CARRY(H1_mI2C_CLK_DIV[12] & !H1L78);


--H1L83 is I2C_CCD_Config:u7|mI2C_CLK_DIV[13]~265
H1L83 = H1_mI2C_CLK_DIV[13] & !H1L81 # !H1_mI2C_CLK_DIV[13] & (H1L81 # GND);

--H1L84 is I2C_CCD_Config:u7|mI2C_CLK_DIV[13]~266
H1L84 = CARRY(!H1L81 # !H1_mI2C_CLK_DIV[13]);


--H1L86 is I2C_CCD_Config:u7|mI2C_CLK_DIV[14]~267
H1L86 = H1_mI2C_CLK_DIV[14] & (H1L84 $ GND) # !H1_mI2C_CLK_DIV[14] & !H1L84 & VCC;

--H1L87 is I2C_CCD_Config:u7|mI2C_CLK_DIV[14]~268
H1L87 = CARRY(H1_mI2C_CLK_DIV[14] & !H1L84);


--H1L89 is I2C_CCD_Config:u7|mI2C_CLK_DIV[15]~269
H1L89 = H1_mI2C_CLK_DIV[15] $ H1L87;


--H1_mI2C_DATA[2] is I2C_CCD_Config:u7|mI2C_DATA[2]
H1_mI2C_DATA[2] = DFFEAS(H1L101, H1_mI2C_CTRL_CLK,  ,  , H1L123, SW[10],  , H1L111, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[8] is I2C_CCD_Config:u7|mI2C_DATA[8]
H1_mI2C_DATA[8] = DFFEAS(H1L131, H1_mI2C_CTRL_CLK,  ,  , H1L123,  ,  ,  ,  );


--H1_mI2C_DATA[9] is I2C_CCD_Config:u7|mI2C_DATA[9]
H1_mI2C_DATA[9] = DFFEAS(H1L132, H1_mI2C_CTRL_CLK,  ,  , H1L123,  ,  , H1_LUT_INDEX[4],  );


--H1_mI2C_DATA[1] is I2C_CCD_Config:u7|mI2C_DATA[1]
H1_mI2C_DATA[1] = DFFEAS(H1L98, H1_mI2C_CTRL_CLK,  ,  , H1L123, SW[9],  , H1L111, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[7] is I2C_CCD_Config:u7|mI2C_DATA[7]
H1_mI2C_DATA[7] = DFFEAS(H1L11, H1_mI2C_CTRL_CLK,  ,  , H1L123,  ,  ,  ,  );


--H1_mI2C_DATA[0] is I2C_CCD_Config:u7|mI2C_DATA[0]
H1_mI2C_DATA[0] = DFFEAS(H1L95, H1_mI2C_CTRL_CLK,  ,  , H1L123, SW[8],  , H1L111, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[4] is I2C_CCD_Config:u7|mI2C_DATA[4]
H1_mI2C_DATA[4] = DFFEAS(H1L107, H1_mI2C_CTRL_CLK,  ,  , H1L123, SW[12],  , H1L111, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[10] is I2C_CCD_Config:u7|mI2C_DATA[10]
H1_mI2C_DATA[10] = DFFEAS(H1L133, H1_mI2C_CTRL_CLK,  ,  , H1L123,  ,  , H1_LUT_INDEX[4],  );


--H1_mI2C_DATA[11] is I2C_CCD_Config:u7|mI2C_DATA[11]
H1_mI2C_DATA[11] = DFFEAS(H1L134, H1_mI2C_CTRL_CLK,  ,  , H1L123,  ,  , H1_LUT_INDEX[4],  );


--H1_mI2C_DATA[3] is I2C_CCD_Config:u7|mI2C_DATA[3]
H1_mI2C_DATA[3] = DFFEAS(H1L104, H1_mI2C_CTRL_CLK,  ,  , H1L123, SW[11],  , H1L111, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[6] is I2C_CCD_Config:u7|mI2C_DATA[6]
H1_mI2C_DATA[6] = DFFEAS(H1L114, H1_mI2C_CTRL_CLK,  ,  , H1L123, SW[14],  , H1L111, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[5] is I2C_CCD_Config:u7|mI2C_DATA[5]
H1_mI2C_DATA[5] = DFFEAS(H1L7, H1_mI2C_CTRL_CLK,  ,  , H1L123,  ,  ,  ,  );


--H1_mI2C_DATA[15] is I2C_CCD_Config:u7|mI2C_DATA[15]
H1_mI2C_DATA[15] = DFFEAS(H1L135, H1_mI2C_CTRL_CLK,  ,  , H1L123,  ,  , H1_LUT_INDEX[0],  );


--H1_mI2C_DATA[13] is I2C_CCD_Config:u7|mI2C_DATA[13]
H1_mI2C_DATA[13] = DFFEAS(H1L137, H1_mI2C_CTRL_CLK,  ,  , H1L123,  ,  ,  ,  );


--S1L58 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[0]~959
S1L58 = S1_init_timer[0] $ VCC;

--S1L59 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[0]~960
S1L59 = CARRY(S1_init_timer[0]);


--S1L61 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[1]~961
S1L61 = S1_init_timer[1] & !S1L59 # !S1_init_timer[1] & (S1L59 # GND);

--S1L62 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[1]~962
S1L62 = CARRY(!S1L59 # !S1_init_timer[1]);


--S1L64 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[2]~963
S1L64 = S1_init_timer[2] & (S1L62 $ GND) # !S1_init_timer[2] & !S1L62 & VCC;

--S1L65 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[2]~964
S1L65 = CARRY(S1_init_timer[2] & !S1L62);


--S1L67 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[3]~965
S1L67 = S1_init_timer[3] & !S1L65 # !S1_init_timer[3] & (S1L65 # GND);

--S1L68 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[3]~966
S1L68 = CARRY(!S1L65 # !S1_init_timer[3]);


--S1L70 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[4]~967
S1L70 = S1_init_timer[4] & (S1L68 $ GND) # !S1_init_timer[4] & !S1L68 & VCC;

--S1L71 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[4]~968
S1L71 = CARRY(S1_init_timer[4] & !S1L68);


--S1L73 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[5]~969
S1L73 = S1_init_timer[5] & !S1L71 # !S1_init_timer[5] & (S1L71 # GND);

--S1L74 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[5]~970
S1L74 = CARRY(!S1L71 # !S1_init_timer[5]);


--S1L76 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[6]~971
S1L76 = S1_init_timer[6] & (S1L74 $ GND) # !S1_init_timer[6] & !S1L74 & VCC;

--S1L77 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[6]~972
S1L77 = CARRY(S1_init_timer[6] & !S1L74);


--S1L79 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[7]~973
S1L79 = S1_init_timer[7] & !S1L77 # !S1_init_timer[7] & (S1L77 # GND);

--S1L80 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[7]~974
S1L80 = CARRY(!S1L77 # !S1_init_timer[7]);


--S1L82 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[8]~975
S1L82 = S1_init_timer[8] & (S1L80 $ GND) # !S1_init_timer[8] & !S1L80 & VCC;

--S1L83 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[8]~976
S1L83 = CARRY(S1_init_timer[8] & !S1L80);


--S1L85 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[9]~977
S1L85 = S1_init_timer[9] & !S1L83 # !S1_init_timer[9] & (S1L83 # GND);

--S1L86 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[9]~978
S1L86 = CARRY(!S1L83 # !S1_init_timer[9]);


--S1L88 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[10]~979
S1L88 = S1_init_timer[10] & (S1L86 $ GND) # !S1_init_timer[10] & !S1L86 & VCC;

--S1L89 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[10]~980
S1L89 = CARRY(S1_init_timer[10] & !S1L86);


--S1L20 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~424
S1L20 = !S1_init_timer[0] & !S1_init_timer[1] & !S1_init_timer[2];


--S1L21 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~425
S1L21 = S1L13 & (S1L20 # !S1_init_timer[3]) # !S1_init_timer[7];


--S1L22 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~426
S1L22 = S1L21 & !S1_init_timer[8] # !S1_init_timer[9] # !S1L17;


--S1L23 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~427
S1L23 = !S1_init_timer[15] & (S1L22 & !S1_init_timer[13] # !S1_init_timer[14]);


--S1L91 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[11]~981
S1L91 = S1_init_timer[11] & !S1L89 # !S1_init_timer[11] & (S1L89 # GND);

--S1L92 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[11]~982
S1L92 = CARRY(!S1L89 # !S1_init_timer[11]);


--S1L94 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[12]~983
S1L94 = S1_init_timer[12] & (S1L92 $ GND) # !S1_init_timer[12] & !S1L92 & VCC;

--S1L95 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[12]~984
S1L95 = CARRY(S1_init_timer[12] & !S1L92);


--S1L97 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[13]~985
S1L97 = S1_init_timer[13] & !S1L95 # !S1_init_timer[13] & (S1L95 # GND);

--S1L98 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[13]~986
S1L98 = CARRY(!S1L95 # !S1_init_timer[13]);


--S1L100 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[14]~987
S1L100 = S1_init_timer[14] & (S1L98 $ GND) # !S1_init_timer[14] & !S1L98 & VCC;

--S1L101 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[14]~988
S1L101 = CARRY(S1_init_timer[14] & !S1L98);


--S1L103 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[15]~989
S1L103 = S1_init_timer[15] $ S1L101;


--R1_command_delay[1] is Sdram_Control_4Port:u6|command:command1|command_delay[1]
R1_command_delay[1] = DFFEAS(R1L68, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L67 is Sdram_Control_4Port:u6|command:command1|command_delay~331
R1L67 = !S1_INIT_REQ & (R1L56 # R1_command_delay[1]);


--G1L371 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1098
G1L371 = G1_rWR1_ADDR[8] $ VCC;

--G1L372 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1099
G1L372 = CARRY(G1_rWR1_ADDR[8]);


--G1L373 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1100
G1L373 = C1_oRST_0 & !G1_rWR1_ADDR[19] & !G1_rWR1_ADDR[22] & !G1_rWR1_ADDR[20];


--G1L34 is Sdram_Control_4Port:u6|LessThan~1260
G1L34 = !G1_rWR1_ADDR[11] # !G1_rWR1_ADDR[10] # !G1_rWR1_ADDR[9] # !G1_rWR1_ADDR[8];


--G1L35 is Sdram_Control_4Port:u6|LessThan~1261
G1L35 = !G1_rWR1_ADDR[15] # !G1_rWR1_ADDR[14] # !G1_rWR1_ADDR[13] # !G1_rWR1_ADDR[12];


--G1L374 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1101
G1L374 = !G1_rWR1_ADDR[16] & !G1_rWR1_ADDR[17] & (G1L34 # G1L35);


--G1L375 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1102
G1L375 = G1_rWR1_ADDR[21] # !G1L374 & G1_rWR1_ADDR[18] # !G1L373;


--G1L376 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1103
G1L376 = G1_WR_MASK[0] & G1_mWR_DONE # !C1_oRST_0;


--G1L321 is Sdram_Control_4Port:u6|rRD2_ADDR[8]~1610
G1L321 = G1_rRD2_ADDR[8] $ VCC;

--G1L322 is Sdram_Control_4Port:u6|rRD2_ADDR[8]~1611
G1L322 = CARRY(G1_rRD2_ADDR[8]);


--G1L324 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1612
G1L324 = C1_oRST_0 & !G1_rRD2_ADDR[22] & !G1_rRD2_ADDR[21];


--G1L36 is Sdram_Control_4Port:u6|LessThan~1262
G1L36 = !G1_rRD2_ADDR[15] # !G1_rRD2_ADDR[14];


--G1L37 is Sdram_Control_4Port:u6|LessThan~1263
G1L37 = !G1_rRD2_ADDR[11] & (!G1_rRD2_ADDR[10] # !G1_rRD2_ADDR[9] # !G1_rRD2_ADDR[8]);


--G1L38 is Sdram_Control_4Port:u6|LessThan~1264
G1L38 = G1L36 # !G1_rRD2_ADDR[13] & (G1L37 # !G1_rRD2_ADDR[12]);


--G1L325 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1613
G1L325 = G1L38 & !G1_rRD2_ADDR[16] & !G1_rRD2_ADDR[17] # !G1_rRD2_ADDR[18];


--G1L326 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1614
G1L326 = G1_rRD2_ADDR[20] & (G1_rRD2_ADDR[19] # !G1L325) # !G1L324;


--G1L327 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1615
G1L327 = G1_RD_MASK[1] & G1_mRD_DONE # !C1_oRST_0;


--G1L143 is Sdram_Control_4Port:u6|add~2869
G1L143 = G1_rWR2_ADDR[8] $ VCC;

--G1L144 is Sdram_Control_4Port:u6|add~2870
G1L144 = CARRY(G1_rWR2_ADDR[8]);


--G1L39 is Sdram_Control_4Port:u6|LessThan~1265
G1L39 = !G1_rWR2_ADDR[11] # !G1_rWR2_ADDR[10] # !G1_rWR2_ADDR[9] # !G1_rWR2_ADDR[8];


--G1L40 is Sdram_Control_4Port:u6|LessThan~1266
G1L40 = !G1_rWR2_ADDR[15] # !G1_rWR2_ADDR[14] # !G1_rWR2_ADDR[13] # !G1_rWR2_ADDR[12];


--G1L41 is Sdram_Control_4Port:u6|LessThan~1267
G1L41 = !G1_rWR2_ADDR[16] & !G1_rWR2_ADDR[17] & (G1L39 # G1L40);


--G1L42 is Sdram_Control_4Port:u6|LessThan~1268
G1L42 = !G1_rWR2_ADDR[19] & (G1L41 # !G1_rWR2_ADDR[18]);


--G1L43 is Sdram_Control_4Port:u6|LessThan~1269
G1L43 = !G1_rWR2_ADDR[22] & !G1_rWR2_ADDR[21] & (G1L42 # !G1_rWR2_ADDR[20]);


--G1L436 is Sdram_Control_4Port:u6|rWR2_ADDR~1872
G1L436 = C1_oRST_0 & G1L143 & G1L43;


--G1L421 is Sdram_Control_4Port:u6|rWR2_ADDR[8]~1873
G1L421 = G1_WR_MASK[1] & G1_mWR_DONE # !C1_oRST_0;


--G1L269 is Sdram_Control_4Port:u6|rRD1_ADDR[8]~1622
G1L269 = G1_rRD1_ADDR[8] $ VCC;

--G1L270 is Sdram_Control_4Port:u6|rRD1_ADDR[8]~1623
G1L270 = CARRY(G1_rRD1_ADDR[8]);


--G1L308 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1624
G1L308 = C1_oRST_0 & !G1_rRD1_ADDR[19] & !G1_rRD1_ADDR[22] & !G1_rRD1_ADDR[20];


--G1L309 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1625
G1L309 = G1_rRD1_ADDR[11] # G1_rRD1_ADDR[8] & G1_rRD1_ADDR[9] & G1_rRD1_ADDR[10];


--G1L310 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1626
G1L310 = G1_rRD1_ADDR[15] & (G1_rRD1_ADDR[13] # G1_rRD1_ADDR[12] & G1L309);


--G1L311 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1627
G1L311 = !G1_rRD1_ADDR[16] & !G1_rRD1_ADDR[17] & (!G1L310 # !G1_rRD1_ADDR[14]);


--G1L312 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1628
G1L312 = G1_rRD1_ADDR[21] # !G1L311 & G1_rRD1_ADDR[18] # !G1L308;


--G1L313 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1629
G1L313 = G1_RD_MASK[0] & G1_mRD_DONE # !C1_oRST_0;


--G1L109 is Sdram_Control_4Port:u6|Select~184
G1L109 = !G1L25 & (G1_ST[1] # !G1L20 # !G1_ST[0]);


--G1L8 is Sdram_Control_4Port:u6|CMD[0]~690
G1L8 = G1L104 & (S1_CMD_ACK & G1L23) # !G1L104 & (G1L24 # S1_CMD_ACK & G1L23);


--G1L110 is Sdram_Control_4Port:u6|Select~185
G1L110 = G1L25 & (G1_ST[1] # !G1L20 # !G1_ST[0]);


--R1_rp_shift[1] is Sdram_Control_4Port:u6|command:command1|rp_shift[1]
R1_rp_shift[1] = DFFEAS(R1L104, KB1__clk0,  ,  , R1L99,  ,  ,  ,  );


--R1L103 is Sdram_Control_4Port:u6|command:command1|rp_shift~806
R1L103 = !S1_INIT_REQ & (R1_rp_shift[1] # R1_command_done & !R1_command_delay[0]);


--R1L48 is Sdram_Control_4Port:u6|command:command1|always0~9
R1L48 = R1L51 & S1_READA & !R1_do_reada & !S1_REF_REQ;


--R1L88 is Sdram_Control_4Port:u6|command:command1|ex_read~107
R1L88 = R1L48 & (!R1L98 # !G1_PM_STOP) # !R1L48 & R1_ex_read & (!R1L98 # !G1_PM_STOP);


--R1L90 is Sdram_Control_4Port:u6|command:command1|ex_write~107
R1L90 = R1L49 & (!R1L98 # !G1_PM_STOP) # !R1L49 & R1_ex_write & (!R1L98 # !G1_PM_STOP);


--S1L107 is Sdram_Control_4Port:u6|control_interface:control1|timer[0]~251
S1L107 = S1_timer[0] $ VCC;

--S1L108 is Sdram_Control_4Port:u6|control_interface:control1|timer[0]~252
S1L108 = CARRY(S1_timer[0]);


--S1L33 is Sdram_Control_4Port:u6|control_interface:control1|REF_REQ~23
S1L33 = S1_INIT_REQ # R1_REF_ACK;


--S1L110 is Sdram_Control_4Port:u6|control_interface:control1|timer[1]~253
S1L110 = S1_timer[1] & S1L108 & VCC # !S1_timer[1] & !S1L108;

--S1L111 is Sdram_Control_4Port:u6|control_interface:control1|timer[1]~254
S1L111 = CARRY(!S1_timer[1] & !S1L108);


--S1L113 is Sdram_Control_4Port:u6|control_interface:control1|timer[2]~255
S1L113 = S1_timer[2] & (GND # !S1L111) # !S1_timer[2] & (S1L111 $ GND);

--S1L114 is Sdram_Control_4Port:u6|control_interface:control1|timer[2]~256
S1L114 = CARRY(S1_timer[2] # !S1L111);


--S1L116 is Sdram_Control_4Port:u6|control_interface:control1|timer[3]~257
S1L116 = S1_timer[3] & S1L114 & VCC # !S1_timer[3] & !S1L114;

--S1L117 is Sdram_Control_4Port:u6|control_interface:control1|timer[3]~258
S1L117 = CARRY(!S1_timer[3] & !S1L114);


--S1L119 is Sdram_Control_4Port:u6|control_interface:control1|timer[4]~259
S1L119 = S1_timer[4] & (GND # !S1L117) # !S1_timer[4] & (S1L117 $ GND);

--S1L120 is Sdram_Control_4Port:u6|control_interface:control1|timer[4]~260
S1L120 = CARRY(S1_timer[4] # !S1L117);


--S1L122 is Sdram_Control_4Port:u6|control_interface:control1|timer[5]~261
S1L122 = S1_timer[5] & S1L120 & VCC # !S1_timer[5] & !S1L120;

--S1L123 is Sdram_Control_4Port:u6|control_interface:control1|timer[5]~262
S1L123 = CARRY(!S1_timer[5] & !S1L120);


--S1L125 is Sdram_Control_4Port:u6|control_interface:control1|timer[6]~263
S1L125 = S1_timer[6] & (GND # !S1L123) # !S1_timer[6] & (S1L123 $ GND);

--S1L126 is Sdram_Control_4Port:u6|control_interface:control1|timer[6]~264
S1L126 = CARRY(S1_timer[6] # !S1L123);


--S1L128 is Sdram_Control_4Port:u6|control_interface:control1|timer[7]~265
S1L128 = S1_timer[7] & S1L126 & VCC # !S1_timer[7] & !S1L126;

--S1L129 is Sdram_Control_4Port:u6|control_interface:control1|timer[7]~266
S1L129 = CARRY(!S1_timer[7] & !S1L126);


--S1L131 is Sdram_Control_4Port:u6|control_interface:control1|timer[8]~267
S1L131 = S1_timer[8] & (GND # !S1L129) # !S1_timer[8] & (S1L129 $ GND);

--S1L132 is Sdram_Control_4Port:u6|control_interface:control1|timer[8]~268
S1L132 = CARRY(S1_timer[8] # !S1L129);


--S1L134 is Sdram_Control_4Port:u6|control_interface:control1|timer[9]~269
S1L134 = S1_timer[9] & S1L132 & VCC # !S1_timer[9] & !S1L132;

--S1L135 is Sdram_Control_4Port:u6|control_interface:control1|timer[9]~270
S1L135 = CARRY(!S1_timer[9] & !S1L132);


--S1L137 is Sdram_Control_4Port:u6|control_interface:control1|timer[10]~271
S1L137 = S1_timer[10] & (GND # !S1L135) # !S1_timer[10] & (S1L135 $ GND);

--S1L138 is Sdram_Control_4Port:u6|control_interface:control1|timer[10]~272
S1L138 = CARRY(S1_timer[10] # !S1L135);


--S1L140 is Sdram_Control_4Port:u6|control_interface:control1|timer[11]~273
S1L140 = S1_timer[11] & S1L138 & VCC # !S1_timer[11] & !S1L138;

--S1L141 is Sdram_Control_4Port:u6|control_interface:control1|timer[11]~274
S1L141 = CARRY(!S1_timer[11] & !S1L138);


--S1L143 is Sdram_Control_4Port:u6|control_interface:control1|timer[12]~275
S1L143 = S1_timer[12] & (GND # !S1L141) # !S1_timer[12] & (S1L141 $ GND);

--S1L144 is Sdram_Control_4Port:u6|control_interface:control1|timer[12]~276
S1L144 = CARRY(S1_timer[12] # !S1L141);


--S1L146 is Sdram_Control_4Port:u6|control_interface:control1|timer[13]~277
S1L146 = S1_timer[13] & S1L144 & VCC # !S1_timer[13] & !S1L144;

--S1L147 is Sdram_Control_4Port:u6|control_interface:control1|timer[13]~278
S1L147 = CARRY(!S1_timer[13] & !S1L144);


--S1L149 is Sdram_Control_4Port:u6|control_interface:control1|timer[14]~279
S1L149 = S1_timer[14] & (GND # !S1L147) # !S1_timer[14] & (S1L147 $ GND);

--S1L150 is Sdram_Control_4Port:u6|control_interface:control1|timer[14]~280
S1L150 = CARRY(S1_timer[14] # !S1L147);


--S1L152 is Sdram_Control_4Port:u6|control_interface:control1|timer[15]~281
S1L152 = S1_timer[15] $ !S1L150;


--R1L18 is Sdram_Control_4Port:u6|command:command1|REF_ACK~55
R1L18 = R1_do_refresh & (S1_REF_REQ # R1L56 & R1_REF_ACK) # !R1_do_refresh & R1L56 & R1_REF_ACK;


--G1L328 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1616
G1L328 = G1_rRD2_ADDR[9] & !G1L322 # !G1_rRD2_ADDR[9] & (G1L322 # GND);

--G1L329 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1617
G1L329 = CARRY(!G1L322 # !G1_rRD2_ADDR[9]);


--G1L378 is Sdram_Control_4Port:u6|rWR1_ADDR[9]~1104
G1L378 = G1_rWR1_ADDR[9] & !G1L372 # !G1_rWR1_ADDR[9] & (G1L372 # GND);

--G1L379 is Sdram_Control_4Port:u6|rWR1_ADDR[9]~1105
G1L379 = CARRY(!G1L372 # !G1_rWR1_ADDR[9]);


--G1L145 is Sdram_Control_4Port:u6|add~2871
G1L145 = G1_rWR2_ADDR[9] & !G1L144 # !G1_rWR2_ADDR[9] & (G1L144 # GND);

--G1L146 is Sdram_Control_4Port:u6|add~2872
G1L146 = CARRY(!G1L144 # !G1_rWR2_ADDR[9]);


--G1L437 is Sdram_Control_4Port:u6|rWR2_ADDR~1874
G1L437 = C1_oRST_0 & G1L43 & G1L145;


--G1L272 is Sdram_Control_4Port:u6|rRD1_ADDR[9]~1630
G1L272 = G1_rRD1_ADDR[9] & !G1L270 # !G1_rRD1_ADDR[9] & (G1L270 # GND);

--G1L273 is Sdram_Control_4Port:u6|rRD1_ADDR[9]~1631
G1L273 = CARRY(!G1L270 # !G1_rRD1_ADDR[9]);


--G1L381 is Sdram_Control_4Port:u6|rWR1_ADDR[10]~1106
G1L381 = G1_rWR1_ADDR[10] & (G1L379 $ GND) # !G1_rWR1_ADDR[10] & !G1L379 & VCC;

--G1L382 is Sdram_Control_4Port:u6|rWR1_ADDR[10]~1107
G1L382 = CARRY(G1_rWR1_ADDR[10] & !G1L379);


--G1L331 is Sdram_Control_4Port:u6|rRD2_ADDR[10]~1618
G1L331 = G1_rRD2_ADDR[10] & (G1L329 $ GND) # !G1_rRD2_ADDR[10] & !G1L329 & VCC;

--G1L332 is Sdram_Control_4Port:u6|rRD2_ADDR[10]~1619
G1L332 = CARRY(G1_rRD2_ADDR[10] & !G1L329);


--G1L147 is Sdram_Control_4Port:u6|add~2873
G1L147 = G1_rWR2_ADDR[10] & (G1L146 $ GND) # !G1_rWR2_ADDR[10] & !G1L146 & VCC;

--G1L148 is Sdram_Control_4Port:u6|add~2874
G1L148 = CARRY(G1_rWR2_ADDR[10] & !G1L146);


--G1L438 is Sdram_Control_4Port:u6|rWR2_ADDR~1875
G1L438 = C1_oRST_0 & G1L43 & G1L147;


--G1L275 is Sdram_Control_4Port:u6|rRD1_ADDR[10]~1632
G1L275 = G1_rRD1_ADDR[10] & (G1L273 $ GND) # !G1_rRD1_ADDR[10] & !G1L273 & VCC;

--G1L276 is Sdram_Control_4Port:u6|rRD1_ADDR[10]~1633
G1L276 = CARRY(G1_rRD1_ADDR[10] & !G1L273);


--G1L334 is Sdram_Control_4Port:u6|rRD2_ADDR[11]~1620
G1L334 = G1_rRD2_ADDR[11] & !G1L332 # !G1_rRD2_ADDR[11] & (G1L332 # GND);

--G1L335 is Sdram_Control_4Port:u6|rRD2_ADDR[11]~1621
G1L335 = CARRY(!G1L332 # !G1_rRD2_ADDR[11]);


--G1L384 is Sdram_Control_4Port:u6|rWR1_ADDR[11]~1108
G1L384 = G1_rWR1_ADDR[11] & !G1L382 # !G1_rWR1_ADDR[11] & (G1L382 # GND);

--G1L385 is Sdram_Control_4Port:u6|rWR1_ADDR[11]~1109
G1L385 = CARRY(!G1L382 # !G1_rWR1_ADDR[11]);


--G1L149 is Sdram_Control_4Port:u6|add~2875
G1L149 = G1_rWR2_ADDR[11] & !G1L148 # !G1_rWR2_ADDR[11] & (G1L148 # GND);

--G1L150 is Sdram_Control_4Port:u6|add~2876
G1L150 = CARRY(!G1L148 # !G1_rWR2_ADDR[11]);


--G1L439 is Sdram_Control_4Port:u6|rWR2_ADDR~1876
G1L439 = C1_oRST_0 & G1L43 & G1L149;


--G1L278 is Sdram_Control_4Port:u6|rRD1_ADDR[11]~1634
G1L278 = G1_rRD1_ADDR[11] & !G1L276 # !G1_rRD1_ADDR[11] & (G1L276 # GND);

--G1L279 is Sdram_Control_4Port:u6|rRD1_ADDR[11]~1635
G1L279 = CARRY(!G1L276 # !G1_rRD1_ADDR[11]);


--G1L387 is Sdram_Control_4Port:u6|rWR1_ADDR[12]~1110
G1L387 = G1_rWR1_ADDR[12] & (G1L385 $ GND) # !G1_rWR1_ADDR[12] & !G1L385 & VCC;

--G1L388 is Sdram_Control_4Port:u6|rWR1_ADDR[12]~1111
G1L388 = CARRY(G1_rWR1_ADDR[12] & !G1L385);


--G1L337 is Sdram_Control_4Port:u6|rRD2_ADDR[12]~1622
G1L337 = G1_rRD2_ADDR[12] & (G1L335 $ GND) # !G1_rRD2_ADDR[12] & !G1L335 & VCC;

--G1L338 is Sdram_Control_4Port:u6|rRD2_ADDR[12]~1623
G1L338 = CARRY(G1_rRD2_ADDR[12] & !G1L335);


--G1L151 is Sdram_Control_4Port:u6|add~2877
G1L151 = G1_rWR2_ADDR[12] & (G1L150 $ GND) # !G1_rWR2_ADDR[12] & !G1L150 & VCC;

--G1L152 is Sdram_Control_4Port:u6|add~2878
G1L152 = CARRY(G1_rWR2_ADDR[12] & !G1L150);


--G1L440 is Sdram_Control_4Port:u6|rWR2_ADDR~1877
G1L440 = C1_oRST_0 & G1L43 & G1L151;


--G1L281 is Sdram_Control_4Port:u6|rRD1_ADDR[12]~1636
G1L281 = G1_rRD1_ADDR[12] & (G1L279 $ GND) # !G1_rRD1_ADDR[12] & !G1L279 & VCC;

--G1L282 is Sdram_Control_4Port:u6|rRD1_ADDR[12]~1637
G1L282 = CARRY(G1_rRD1_ADDR[12] & !G1L279);


--G1L340 is Sdram_Control_4Port:u6|rRD2_ADDR[13]~1624
G1L340 = G1_rRD2_ADDR[13] & !G1L338 # !G1_rRD2_ADDR[13] & (G1L338 # GND);

--G1L341 is Sdram_Control_4Port:u6|rRD2_ADDR[13]~1625
G1L341 = CARRY(!G1L338 # !G1_rRD2_ADDR[13]);


--G1L390 is Sdram_Control_4Port:u6|rWR1_ADDR[13]~1112
G1L390 = G1_rWR1_ADDR[13] & !G1L388 # !G1_rWR1_ADDR[13] & (G1L388 # GND);

--G1L391 is Sdram_Control_4Port:u6|rWR1_ADDR[13]~1113
G1L391 = CARRY(!G1L388 # !G1_rWR1_ADDR[13]);


--G1L153 is Sdram_Control_4Port:u6|add~2879
G1L153 = G1_rWR2_ADDR[13] & !G1L152 # !G1_rWR2_ADDR[13] & (G1L152 # GND);

--G1L154 is Sdram_Control_4Port:u6|add~2880
G1L154 = CARRY(!G1L152 # !G1_rWR2_ADDR[13]);


--G1L441 is Sdram_Control_4Port:u6|rWR2_ADDR~1878
G1L441 = C1_oRST_0 & G1L43 & G1L153;


--G1L284 is Sdram_Control_4Port:u6|rRD1_ADDR[13]~1638
G1L284 = G1_rRD1_ADDR[13] & !G1L282 # !G1_rRD1_ADDR[13] & (G1L282 # GND);

--G1L285 is Sdram_Control_4Port:u6|rRD1_ADDR[13]~1639
G1L285 = CARRY(!G1L282 # !G1_rRD1_ADDR[13]);


--G1L393 is Sdram_Control_4Port:u6|rWR1_ADDR[14]~1114
G1L393 = G1_rWR1_ADDR[14] & (G1L391 $ GND) # !G1_rWR1_ADDR[14] & !G1L391 & VCC;

--G1L394 is Sdram_Control_4Port:u6|rWR1_ADDR[14]~1115
G1L394 = CARRY(G1_rWR1_ADDR[14] & !G1L391);


--G1L343 is Sdram_Control_4Port:u6|rRD2_ADDR[14]~1626
G1L343 = G1_rRD2_ADDR[14] & (G1L341 $ GND) # !G1_rRD2_ADDR[14] & !G1L341 & VCC;

--G1L344 is Sdram_Control_4Port:u6|rRD2_ADDR[14]~1627
G1L344 = CARRY(G1_rRD2_ADDR[14] & !G1L341);


--G1L155 is Sdram_Control_4Port:u6|add~2881
G1L155 = G1_rWR2_ADDR[14] & (G1L154 $ GND) # !G1_rWR2_ADDR[14] & !G1L154 & VCC;

--G1L156 is Sdram_Control_4Port:u6|add~2882
G1L156 = CARRY(G1_rWR2_ADDR[14] & !G1L154);


--G1L442 is Sdram_Control_4Port:u6|rWR2_ADDR~1879
G1L442 = C1_oRST_0 & G1L43 & G1L155;


--G1L287 is Sdram_Control_4Port:u6|rRD1_ADDR[14]~1640
G1L287 = G1_rRD1_ADDR[14] & (G1L285 $ GND) # !G1_rRD1_ADDR[14] & !G1L285 & VCC;

--G1L288 is Sdram_Control_4Port:u6|rRD1_ADDR[14]~1641
G1L288 = CARRY(G1_rRD1_ADDR[14] & !G1L285);


--G1L346 is Sdram_Control_4Port:u6|rRD2_ADDR[15]~1628
G1L346 = G1_rRD2_ADDR[15] & !G1L344 # !G1_rRD2_ADDR[15] & (G1L344 # GND);

--G1L347 is Sdram_Control_4Port:u6|rRD2_ADDR[15]~1629
G1L347 = CARRY(!G1L344 # !G1_rRD2_ADDR[15]);


--G1L396 is Sdram_Control_4Port:u6|rWR1_ADDR[15]~1116
G1L396 = G1_rWR1_ADDR[15] & !G1L394 # !G1_rWR1_ADDR[15] & (G1L394 # GND);

--G1L397 is Sdram_Control_4Port:u6|rWR1_ADDR[15]~1117
G1L397 = CARRY(!G1L394 # !G1_rWR1_ADDR[15]);


--G1L157 is Sdram_Control_4Port:u6|add~2883
G1L157 = G1_rWR2_ADDR[15] & !G1L156 # !G1_rWR2_ADDR[15] & (G1L156 # GND);

--G1L158 is Sdram_Control_4Port:u6|add~2884
G1L158 = CARRY(!G1L156 # !G1_rWR2_ADDR[15]);


--G1L443 is Sdram_Control_4Port:u6|rWR2_ADDR~1880
G1L443 = C1_oRST_0 & G1L43 & G1L157;


--G1L290 is Sdram_Control_4Port:u6|rRD1_ADDR[15]~1642
G1L290 = G1_rRD1_ADDR[15] & !G1L288 # !G1_rRD1_ADDR[15] & (G1L288 # GND);

--G1L291 is Sdram_Control_4Port:u6|rRD1_ADDR[15]~1643
G1L291 = CARRY(!G1L288 # !G1_rRD1_ADDR[15]);


--G1L399 is Sdram_Control_4Port:u6|rWR1_ADDR[16]~1118
G1L399 = G1_rWR1_ADDR[16] & (G1L397 $ GND) # !G1_rWR1_ADDR[16] & !G1L397 & VCC;

--G1L400 is Sdram_Control_4Port:u6|rWR1_ADDR[16]~1119
G1L400 = CARRY(G1_rWR1_ADDR[16] & !G1L397);


--G1L349 is Sdram_Control_4Port:u6|rRD2_ADDR[16]~1630
G1L349 = G1_rRD2_ADDR[16] & (G1L347 $ GND) # !G1_rRD2_ADDR[16] & !G1L347 & VCC;

--G1L350 is Sdram_Control_4Port:u6|rRD2_ADDR[16]~1631
G1L350 = CARRY(G1_rRD2_ADDR[16] & !G1L347);


--G1L159 is Sdram_Control_4Port:u6|add~2885
G1L159 = G1_rWR2_ADDR[16] & (G1L158 $ GND) # !G1_rWR2_ADDR[16] & !G1L158 & VCC;

--G1L160 is Sdram_Control_4Port:u6|add~2886
G1L160 = CARRY(G1_rWR2_ADDR[16] & !G1L158);


--G1L444 is Sdram_Control_4Port:u6|rWR2_ADDR~1881
G1L444 = C1_oRST_0 & G1L43 & G1L159;


--G1L293 is Sdram_Control_4Port:u6|rRD1_ADDR[16]~1644
G1L293 = G1_rRD1_ADDR[16] & (G1L291 $ GND) # !G1_rRD1_ADDR[16] & !G1L291 & VCC;

--G1L294 is Sdram_Control_4Port:u6|rRD1_ADDR[16]~1645
G1L294 = CARRY(G1_rRD1_ADDR[16] & !G1L291);


--G1L352 is Sdram_Control_4Port:u6|rRD2_ADDR[17]~1632
G1L352 = G1_rRD2_ADDR[17] & !G1L350 # !G1_rRD2_ADDR[17] & (G1L350 # GND);

--G1L353 is Sdram_Control_4Port:u6|rRD2_ADDR[17]~1633
G1L353 = CARRY(!G1L350 # !G1_rRD2_ADDR[17]);


--G1L402 is Sdram_Control_4Port:u6|rWR1_ADDR[17]~1120
G1L402 = G1_rWR1_ADDR[17] & !G1L400 # !G1_rWR1_ADDR[17] & (G1L400 # GND);

--G1L403 is Sdram_Control_4Port:u6|rWR1_ADDR[17]~1121
G1L403 = CARRY(!G1L400 # !G1_rWR1_ADDR[17]);


--G1L161 is Sdram_Control_4Port:u6|add~2887
G1L161 = G1_rWR2_ADDR[17] & !G1L160 # !G1_rWR2_ADDR[17] & (G1L160 # GND);

--G1L162 is Sdram_Control_4Port:u6|add~2888
G1L162 = CARRY(!G1L160 # !G1_rWR2_ADDR[17]);


--G1L445 is Sdram_Control_4Port:u6|rWR2_ADDR~1882
G1L445 = C1_oRST_0 & G1L43 & G1L161;


--G1L296 is Sdram_Control_4Port:u6|rRD1_ADDR[17]~1646
G1L296 = G1_rRD1_ADDR[17] & !G1L294 # !G1_rRD1_ADDR[17] & (G1L294 # GND);

--G1L297 is Sdram_Control_4Port:u6|rRD1_ADDR[17]~1647
G1L297 = CARRY(!G1L294 # !G1_rRD1_ADDR[17]);


--G1L405 is Sdram_Control_4Port:u6|rWR1_ADDR[18]~1122
G1L405 = G1_rWR1_ADDR[18] & (G1L403 $ GND) # !G1_rWR1_ADDR[18] & !G1L403 & VCC;

--G1L406 is Sdram_Control_4Port:u6|rWR1_ADDR[18]~1123
G1L406 = CARRY(G1_rWR1_ADDR[18] & !G1L403);


--G1L355 is Sdram_Control_4Port:u6|rRD2_ADDR[18]~1634
G1L355 = G1_rRD2_ADDR[18] & (G1L353 $ GND) # !G1_rRD2_ADDR[18] & !G1L353 & VCC;

--G1L356 is Sdram_Control_4Port:u6|rRD2_ADDR[18]~1635
G1L356 = CARRY(G1_rRD2_ADDR[18] & !G1L353);


--G1L163 is Sdram_Control_4Port:u6|add~2889
G1L163 = G1_rWR2_ADDR[18] & (G1L162 $ GND) # !G1_rWR2_ADDR[18] & !G1L162 & VCC;

--G1L164 is Sdram_Control_4Port:u6|add~2890
G1L164 = CARRY(G1_rWR2_ADDR[18] & !G1L162);


--G1L446 is Sdram_Control_4Port:u6|rWR2_ADDR~1883
G1L446 = C1_oRST_0 & G1L43 & G1L163;


--G1L299 is Sdram_Control_4Port:u6|rRD1_ADDR[18]~1648
G1L299 = G1_rRD1_ADDR[18] & (G1L297 $ GND) # !G1_rRD1_ADDR[18] & !G1L297 & VCC;

--G1L300 is Sdram_Control_4Port:u6|rRD1_ADDR[18]~1649
G1L300 = CARRY(G1_rRD1_ADDR[18] & !G1L297);


--G1L358 is Sdram_Control_4Port:u6|rRD2_ADDR[19]~1636
G1L358 = G1_rRD2_ADDR[19] & !G1L356 # !G1_rRD2_ADDR[19] & (G1L356 # GND);

--G1L359 is Sdram_Control_4Port:u6|rRD2_ADDR[19]~1637
G1L359 = CARRY(!G1L356 # !G1_rRD2_ADDR[19]);


--G1L408 is Sdram_Control_4Port:u6|rWR1_ADDR[19]~1124
G1L408 = G1_rWR1_ADDR[19] & !G1L406 # !G1_rWR1_ADDR[19] & (G1L406 # GND);

--G1L409 is Sdram_Control_4Port:u6|rWR1_ADDR[19]~1125
G1L409 = CARRY(!G1L406 # !G1_rWR1_ADDR[19]);


--G1L165 is Sdram_Control_4Port:u6|add~2891
G1L165 = G1_rWR2_ADDR[19] & !G1L164 # !G1_rWR2_ADDR[19] & (G1L164 # GND);

--G1L166 is Sdram_Control_4Port:u6|add~2892
G1L166 = CARRY(!G1L164 # !G1_rWR2_ADDR[19]);


--G1L447 is Sdram_Control_4Port:u6|rWR2_ADDR~1884
G1L447 = C1_oRST_0 & G1L43 & G1L165;


--G1L302 is Sdram_Control_4Port:u6|rRD1_ADDR[19]~1650
G1L302 = G1_rRD1_ADDR[19] & !G1L300 # !G1_rRD1_ADDR[19] & (G1L300 # GND);

--G1L303 is Sdram_Control_4Port:u6|rRD1_ADDR[19]~1651
G1L303 = CARRY(!G1L300 # !G1_rRD1_ADDR[19]);


--G1L411 is Sdram_Control_4Port:u6|rWR1_ADDR[20]~1126
G1L411 = G1_rWR1_ADDR[20] & (G1L409 $ GND) # !G1_rWR1_ADDR[20] & !G1L409 & VCC;

--G1L412 is Sdram_Control_4Port:u6|rWR1_ADDR[20]~1127
G1L412 = CARRY(G1_rWR1_ADDR[20] & !G1L409);


--G1L414 is Sdram_Control_4Port:u6|rWR1_ADDR[21]~1128
G1L414 = G1_rWR1_ADDR[21] & !G1L412 # !G1_rWR1_ADDR[21] & (G1L412 # GND);

--G1L415 is Sdram_Control_4Port:u6|rWR1_ADDR[21]~1129
G1L415 = CARRY(!G1L412 # !G1_rWR1_ADDR[21]);


--G1L417 is Sdram_Control_4Port:u6|rWR1_ADDR[22]~1130
G1L417 = G1_rWR1_ADDR[22] $ !G1L415;


--G1L361 is Sdram_Control_4Port:u6|rRD2_ADDR[20]~1638
G1L361 = G1_rRD2_ADDR[20] & (G1L359 $ GND) # !G1_rRD2_ADDR[20] & !G1L359 & VCC;

--G1L362 is Sdram_Control_4Port:u6|rRD2_ADDR[20]~1639
G1L362 = CARRY(G1_rRD2_ADDR[20] & !G1L359);


--G1L364 is Sdram_Control_4Port:u6|rRD2_ADDR[21]~1640
G1L364 = G1_rRD2_ADDR[21] & !G1L362 # !G1_rRD2_ADDR[21] & (G1L362 # GND);

--G1L365 is Sdram_Control_4Port:u6|rRD2_ADDR[21]~1641
G1L365 = CARRY(!G1L362 # !G1_rRD2_ADDR[21]);


--G1L367 is Sdram_Control_4Port:u6|rRD2_ADDR[22]~1642
G1L367 = G1_rRD2_ADDR[22] $ !G1L365;


--G1L167 is Sdram_Control_4Port:u6|add~2893
G1L167 = G1_rWR2_ADDR[20] & (G1L166 $ GND) # !G1_rWR2_ADDR[20] & !G1L166 & VCC;

--G1L168 is Sdram_Control_4Port:u6|add~2894
G1L168 = CARRY(G1_rWR2_ADDR[20] & !G1L166);


--G1L169 is Sdram_Control_4Port:u6|add~2895
G1L169 = G1_rWR2_ADDR[21] & !G1L168 # !G1_rWR2_ADDR[21] & (G1L168 # GND);

--G1L170 is Sdram_Control_4Port:u6|add~2896
G1L170 = CARRY(!G1L168 # !G1_rWR2_ADDR[21]);


--G1L171 is Sdram_Control_4Port:u6|add~2897
G1L171 = G1_rWR2_ADDR[22] $ !G1L170;


--G1L448 is Sdram_Control_4Port:u6|rWR2_ADDR~1885
G1L448 = G1L171 & C1_oRST_0 & G1L43;


--G1L305 is Sdram_Control_4Port:u6|rRD1_ADDR[20]~1652
G1L305 = G1_rRD1_ADDR[20] & (G1L303 $ GND) # !G1_rRD1_ADDR[20] & !G1L303 & VCC;

--G1L306 is Sdram_Control_4Port:u6|rRD1_ADDR[20]~1653
G1L306 = CARRY(G1_rRD1_ADDR[20] & !G1L303);


--G1L314 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1654
G1L314 = G1_rRD1_ADDR[21] & !G1L306 # !G1_rRD1_ADDR[21] & (G1L306 # GND);

--G1L315 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1655
G1L315 = CARRY(!G1L306 # !G1_rRD1_ADDR[21]);


--G1L317 is Sdram_Control_4Port:u6|rRD1_ADDR[22]~1656
G1L317 = G1_rRD1_ADDR[22] $ !G1L315;


--G1L449 is Sdram_Control_4Port:u6|rWR2_ADDR~1886
G1L449 = G1_WR_MASK[1] & G1_mWR_DONE;


--G1L450 is Sdram_Control_4Port:u6|rWR2_ADDR~1887
G1L450 = G1L449 & (G1L167 # !G1L43) # !G1L449 & (G1_rWR2_ADDR[20]);


--G1L451 is Sdram_Control_4Port:u6|rWR2_ADDR~1888
G1L451 = C1_oRST_0 & G1L43 & G1L169;


--E1L139 is RAW2RGB:u4|mDVAL~25
E1L139 = D1_mCCD_FVAL & D1_mCCD_LVAL & !D1_Y_Cont[0] & !D1_X_Cont[0];


--N1_q_b[10] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[10]_PORT_A_data_in = N1_q_b[0];
N1_q_b[10]_PORT_A_data_in_reg = DFFE(N1_q_b[10]_PORT_A_data_in, N1_q_b[10]_clock_0, , , N1_q_b[10]_clock_enable_0);
N1_q_b[10]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[10]_PORT_A_address_reg = DFFE(N1_q_b[10]_PORT_A_address, N1_q_b[10]_clock_0, , , N1_q_b[10]_clock_enable_0);
N1_q_b[10]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[10]_PORT_B_address_reg = DFFE(N1_q_b[10]_PORT_B_address, N1_q_b[10]_clock_0, , , N1_q_b[10]_clock_enable_0);
N1_q_b[10]_PORT_A_write_enable = VCC;
N1_q_b[10]_PORT_A_write_enable_reg = DFFE(N1_q_b[10]_PORT_A_write_enable, N1_q_b[10]_clock_0, , , N1_q_b[10]_clock_enable_0);
N1_q_b[10]_PORT_B_read_enable = VCC;
N1_q_b[10]_PORT_B_read_enable_reg = DFFE(N1_q_b[10]_PORT_B_read_enable, N1_q_b[10]_clock_0, , , N1_q_b[10]_clock_enable_0);
N1_q_b[10]_clock_0 = CCD_PIXCLK;
N1_q_b[10]_clock_enable_0 = D1_oDVAL;
N1_q_b[10]_PORT_B_data_out = MEMORY(N1_q_b[10]_PORT_A_data_in_reg, , N1_q_b[10]_PORT_A_address_reg, N1_q_b[10]_PORT_B_address_reg, N1_q_b[10]_PORT_A_write_enable_reg, N1_q_b[10]_PORT_B_read_enable_reg, , , N1_q_b[10]_clock_0, , N1_q_b[10]_clock_enable_0, , , );
N1_q_b[10]_PORT_B_data_out_reg = DFFE(N1_q_b[10]_PORT_B_data_out, N1_q_b[10]_clock_0, , , N1_q_b[10]_clock_enable_0);
N1_q_b[10] = N1_q_b[10]_PORT_B_data_out_reg[0];


--E1_mDATAd_1[0] is RAW2RGB:u4|mDATAd_1[0]
E1_mDATAd_1[0] = DFFEAS(N1_q_b[0], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--N1_q_b[0] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[0]_PORT_A_data_in = D1_mCCD_DATA[0];
N1_q_b[0]_PORT_A_data_in_reg = DFFE(N1_q_b[0]_PORT_A_data_in, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[0]_PORT_A_address_reg = DFFE(N1_q_b[0]_PORT_A_address, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[0]_PORT_B_address_reg = DFFE(N1_q_b[0]_PORT_B_address, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_A_write_enable = VCC;
N1_q_b[0]_PORT_A_write_enable_reg = DFFE(N1_q_b[0]_PORT_A_write_enable, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_B_read_enable = VCC;
N1_q_b[0]_PORT_B_read_enable_reg = DFFE(N1_q_b[0]_PORT_B_read_enable, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_clock_0 = CCD_PIXCLK;
N1_q_b[0]_clock_enable_0 = D1_oDVAL;
N1_q_b[0]_PORT_B_data_out = MEMORY(N1_q_b[0]_PORT_A_data_in_reg, , N1_q_b[0]_PORT_A_address_reg, N1_q_b[0]_PORT_B_address_reg, N1_q_b[0]_PORT_A_write_enable_reg, N1_q_b[0]_PORT_B_read_enable_reg, , , N1_q_b[0]_clock_0, , N1_q_b[0]_clock_enable_0, , , );
N1_q_b[0]_PORT_B_data_out_reg = DFFE(N1_q_b[0]_PORT_B_data_out, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0] = N1_q_b[0]_PORT_B_data_out_reg[0];


--E1L32 is RAW2RGB:u4|mCCD_B~150
E1L32 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[0] # !D1_X_Cont[0] & (N1_q_b[0]));


--E1_mDATAd_0[0] is RAW2RGB:u4|mDATAd_0[0]
E1_mDATAd_0[0] = DFFEAS(N1_q_b[10], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1L33 is RAW2RGB:u4|mCCD_B~151
E1L33 = D1_Y_Cont[0] & (E1L32 & (E1_mDATAd_0[0]) # !E1L32 & N1_q_b[10]) # !D1_Y_Cont[0] & (E1L32);


--J1L4 is Mirror_Col:u8|Z_Cont[0]~163
J1L4 = J1_Z_Cont[0] & (E1_mDVAL $ VCC) # !J1_Z_Cont[0] & E1_mDVAL & VCC;

--J1L5 is Mirror_Col:u8|Z_Cont[0]~164
J1L5 = CARRY(J1_Z_Cont[0] & E1_mDVAL);


--J1L1 is Mirror_Col:u8|LessThan~84
J1L1 = J1_Z_Cont[9] & (J1_Z_Cont[7] # J1_Z_Cont[8]);


--J1L8 is Mirror_Col:u8|Z_Cont[1]~165
J1L8 = J1_Z_Cont[1] & !J1L5 # !J1_Z_Cont[1] & (J1L5 # GND);

--J1L9 is Mirror_Col:u8|Z_Cont[1]~166
J1L9 = CARRY(!J1L5 # !J1_Z_Cont[1]);


--J1L12 is Mirror_Col:u8|Z_Cont[2]~167
J1L12 = J1_Z_Cont[2] & (J1L9 $ GND) # !J1_Z_Cont[2] & !J1L9 & VCC;

--J1L13 is Mirror_Col:u8|Z_Cont[2]~168
J1L13 = CARRY(J1_Z_Cont[2] & !J1L9);


--J1L16 is Mirror_Col:u8|Z_Cont[3]~169
J1L16 = J1_Z_Cont[3] & !J1L13 # !J1_Z_Cont[3] & (J1L13 # GND);

--J1L17 is Mirror_Col:u8|Z_Cont[3]~170
J1L17 = CARRY(!J1L13 # !J1_Z_Cont[3]);


--J1L20 is Mirror_Col:u8|Z_Cont[4]~171
J1L20 = J1_Z_Cont[4] & (J1L17 $ GND) # !J1_Z_Cont[4] & !J1L17 & VCC;

--J1L21 is Mirror_Col:u8|Z_Cont[4]~172
J1L21 = CARRY(J1_Z_Cont[4] & !J1L17);


--J1L24 is Mirror_Col:u8|Z_Cont[5]~173
J1L24 = J1_Z_Cont[5] & !J1L21 # !J1_Z_Cont[5] & (J1L21 # GND);

--J1L25 is Mirror_Col:u8|Z_Cont[5]~174
J1L25 = CARRY(!J1L21 # !J1_Z_Cont[5]);


--J1L28 is Mirror_Col:u8|Z_Cont[6]~175
J1L28 = J1_Z_Cont[6] & (J1L25 $ GND) # !J1_Z_Cont[6] & !J1L25 & VCC;

--J1L29 is Mirror_Col:u8|Z_Cont[6]~176
J1L29 = CARRY(J1_Z_Cont[6] & !J1L25);


--J1L32 is Mirror_Col:u8|Z_Cont[7]~177
J1L32 = J1_Z_Cont[7] & !J1L29 # !J1_Z_Cont[7] & (J1L29 # GND);

--J1L33 is Mirror_Col:u8|Z_Cont[7]~178
J1L33 = CARRY(!J1L29 # !J1_Z_Cont[7]);


--J1L35 is Mirror_Col:u8|Z_Cont[8]~179
J1L35 = J1_Z_Cont[8] & (J1L33 $ GND) # !J1_Z_Cont[8] & !J1L33 & VCC;

--J1L36 is Mirror_Col:u8|Z_Cont[8]~180
J1L36 = CARRY(J1_Z_Cont[8] & !J1L33);


--J1L38 is Mirror_Col:u8|Z_Cont[9]~181
J1L38 = J1_Z_Cont[9] $ J1L36;


--E1L96 is RAW2RGB:u4|mCCD_R~941
E1L96 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[0] # !D1_Y_Cont[0] & (E1_mDATAd_0[0]));


--E1L97 is RAW2RGB:u4|mCCD_R~942
E1L97 = D1_X_Cont[0] & (E1L96 & (N1_q_b[0]) # !E1L96 & N1_q_b[10]) # !D1_X_Cont[0] & (E1L96);


--N1_q_b[11] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[11]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[11]_PORT_A_data_in = N1_q_b[1];
N1_q_b[11]_PORT_A_data_in_reg = DFFE(N1_q_b[11]_PORT_A_data_in, N1_q_b[11]_clock_0, , , N1_q_b[11]_clock_enable_0);
N1_q_b[11]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[11]_PORT_A_address_reg = DFFE(N1_q_b[11]_PORT_A_address, N1_q_b[11]_clock_0, , , N1_q_b[11]_clock_enable_0);
N1_q_b[11]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[11]_PORT_B_address_reg = DFFE(N1_q_b[11]_PORT_B_address, N1_q_b[11]_clock_0, , , N1_q_b[11]_clock_enable_0);
N1_q_b[11]_PORT_A_write_enable = VCC;
N1_q_b[11]_PORT_A_write_enable_reg = DFFE(N1_q_b[11]_PORT_A_write_enable, N1_q_b[11]_clock_0, , , N1_q_b[11]_clock_enable_0);
N1_q_b[11]_PORT_B_read_enable = VCC;
N1_q_b[11]_PORT_B_read_enable_reg = DFFE(N1_q_b[11]_PORT_B_read_enable, N1_q_b[11]_clock_0, , , N1_q_b[11]_clock_enable_0);
N1_q_b[11]_clock_0 = CCD_PIXCLK;
N1_q_b[11]_clock_enable_0 = D1_oDVAL;
N1_q_b[11]_PORT_B_data_out = MEMORY(N1_q_b[11]_PORT_A_data_in_reg, , N1_q_b[11]_PORT_A_address_reg, N1_q_b[11]_PORT_B_address_reg, N1_q_b[11]_PORT_A_write_enable_reg, N1_q_b[11]_PORT_B_read_enable_reg, , , N1_q_b[11]_clock_0, , N1_q_b[11]_clock_enable_0, , , );
N1_q_b[11]_PORT_B_data_out_reg = DFFE(N1_q_b[11]_PORT_B_data_out, N1_q_b[11]_clock_0, , , N1_q_b[11]_clock_enable_0);
N1_q_b[11] = N1_q_b[11]_PORT_B_data_out_reg[0];


--E1_mDATAd_1[1] is RAW2RGB:u4|mDATAd_1[1]
E1_mDATAd_1[1] = DFFEAS(N1_q_b[1], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--N1_q_b[1] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[1]_PORT_A_data_in = D1_mCCD_DATA[1];
N1_q_b[1]_PORT_A_data_in_reg = DFFE(N1_q_b[1]_PORT_A_data_in, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[1]_PORT_A_address_reg = DFFE(N1_q_b[1]_PORT_A_address, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[1]_PORT_B_address_reg = DFFE(N1_q_b[1]_PORT_B_address, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_A_write_enable = VCC;
N1_q_b[1]_PORT_A_write_enable_reg = DFFE(N1_q_b[1]_PORT_A_write_enable, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_B_read_enable = VCC;
N1_q_b[1]_PORT_B_read_enable_reg = DFFE(N1_q_b[1]_PORT_B_read_enable, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_clock_0 = CCD_PIXCLK;
N1_q_b[1]_clock_enable_0 = D1_oDVAL;
N1_q_b[1]_PORT_B_data_out = MEMORY(N1_q_b[1]_PORT_A_data_in_reg, , N1_q_b[1]_PORT_A_address_reg, N1_q_b[1]_PORT_B_address_reg, N1_q_b[1]_PORT_A_write_enable_reg, N1_q_b[1]_PORT_B_read_enable_reg, , , N1_q_b[1]_clock_0, , N1_q_b[1]_clock_enable_0, , , );
N1_q_b[1]_PORT_B_data_out_reg = DFFE(N1_q_b[1]_PORT_B_data_out, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1] = N1_q_b[1]_PORT_B_data_out_reg[0];


--E1L34 is RAW2RGB:u4|mCCD_B~152
E1L34 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[1] # !D1_X_Cont[0] & (N1_q_b[1]));


--E1_mDATAd_0[1] is RAW2RGB:u4|mDATAd_0[1]
E1_mDATAd_0[1] = DFFEAS(N1_q_b[11], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1L35 is RAW2RGB:u4|mCCD_B~153
E1L35 = D1_Y_Cont[0] & (E1L34 & (E1_mDATAd_0[1]) # !E1L34 & N1_q_b[11]) # !D1_Y_Cont[0] & (E1L34);


--E1L98 is RAW2RGB:u4|mCCD_R~943
E1L98 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[1] # !D1_Y_Cont[0] & (E1_mDATAd_0[1]));


--E1L99 is RAW2RGB:u4|mCCD_R~944
E1L99 = D1_X_Cont[0] & (E1L98 & (N1_q_b[1]) # !E1L98 & N1_q_b[11]) # !D1_X_Cont[0] & (E1L98);


--N1_q_b[12] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[12]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[12]_PORT_A_data_in = N1_q_b[2];
N1_q_b[12]_PORT_A_data_in_reg = DFFE(N1_q_b[12]_PORT_A_data_in, N1_q_b[12]_clock_0, , , N1_q_b[12]_clock_enable_0);
N1_q_b[12]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[12]_PORT_A_address_reg = DFFE(N1_q_b[12]_PORT_A_address, N1_q_b[12]_clock_0, , , N1_q_b[12]_clock_enable_0);
N1_q_b[12]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[12]_PORT_B_address_reg = DFFE(N1_q_b[12]_PORT_B_address, N1_q_b[12]_clock_0, , , N1_q_b[12]_clock_enable_0);
N1_q_b[12]_PORT_A_write_enable = VCC;
N1_q_b[12]_PORT_A_write_enable_reg = DFFE(N1_q_b[12]_PORT_A_write_enable, N1_q_b[12]_clock_0, , , N1_q_b[12]_clock_enable_0);
N1_q_b[12]_PORT_B_read_enable = VCC;
N1_q_b[12]_PORT_B_read_enable_reg = DFFE(N1_q_b[12]_PORT_B_read_enable, N1_q_b[12]_clock_0, , , N1_q_b[12]_clock_enable_0);
N1_q_b[12]_clock_0 = CCD_PIXCLK;
N1_q_b[12]_clock_enable_0 = D1_oDVAL;
N1_q_b[12]_PORT_B_data_out = MEMORY(N1_q_b[12]_PORT_A_data_in_reg, , N1_q_b[12]_PORT_A_address_reg, N1_q_b[12]_PORT_B_address_reg, N1_q_b[12]_PORT_A_write_enable_reg, N1_q_b[12]_PORT_B_read_enable_reg, , , N1_q_b[12]_clock_0, , N1_q_b[12]_clock_enable_0, , , );
N1_q_b[12]_PORT_B_data_out_reg = DFFE(N1_q_b[12]_PORT_B_data_out, N1_q_b[12]_clock_0, , , N1_q_b[12]_clock_enable_0);
N1_q_b[12] = N1_q_b[12]_PORT_B_data_out_reg[0];


--E1_mDATAd_1[2] is RAW2RGB:u4|mDATAd_1[2]
E1_mDATAd_1[2] = DFFEAS(N1_q_b[2], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--N1_q_b[2] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[2]_PORT_A_data_in = D1_mCCD_DATA[2];
N1_q_b[2]_PORT_A_data_in_reg = DFFE(N1_q_b[2]_PORT_A_data_in, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[2]_PORT_A_address_reg = DFFE(N1_q_b[2]_PORT_A_address, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[2]_PORT_B_address_reg = DFFE(N1_q_b[2]_PORT_B_address, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_A_write_enable = VCC;
N1_q_b[2]_PORT_A_write_enable_reg = DFFE(N1_q_b[2]_PORT_A_write_enable, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_B_read_enable = VCC;
N1_q_b[2]_PORT_B_read_enable_reg = DFFE(N1_q_b[2]_PORT_B_read_enable, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_clock_0 = CCD_PIXCLK;
N1_q_b[2]_clock_enable_0 = D1_oDVAL;
N1_q_b[2]_PORT_B_data_out = MEMORY(N1_q_b[2]_PORT_A_data_in_reg, , N1_q_b[2]_PORT_A_address_reg, N1_q_b[2]_PORT_B_address_reg, N1_q_b[2]_PORT_A_write_enable_reg, N1_q_b[2]_PORT_B_read_enable_reg, , , N1_q_b[2]_clock_0, , N1_q_b[2]_clock_enable_0, , , );
N1_q_b[2]_PORT_B_data_out_reg = DFFE(N1_q_b[2]_PORT_B_data_out, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2] = N1_q_b[2]_PORT_B_data_out_reg[0];


--E1L36 is RAW2RGB:u4|mCCD_B~154
E1L36 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[2] # !D1_X_Cont[0] & (N1_q_b[2]));


--E1_mDATAd_0[2] is RAW2RGB:u4|mDATAd_0[2]
E1_mDATAd_0[2] = DFFEAS(N1_q_b[12], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1L37 is RAW2RGB:u4|mCCD_B~155
E1L37 = D1_Y_Cont[0] & (E1L36 & (E1_mDATAd_0[2]) # !E1L36 & N1_q_b[12]) # !D1_Y_Cont[0] & (E1L36);


--E1L100 is RAW2RGB:u4|mCCD_R~945
E1L100 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[2] # !D1_Y_Cont[0] & (E1_mDATAd_0[2]));


--E1L101 is RAW2RGB:u4|mCCD_R~946
E1L101 = D1_X_Cont[0] & (E1L100 & (N1_q_b[2]) # !E1L100 & N1_q_b[12]) # !D1_X_Cont[0] & (E1L100);


--N1_q_b[13] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[13]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[13]_PORT_A_data_in = N1_q_b[3];
N1_q_b[13]_PORT_A_data_in_reg = DFFE(N1_q_b[13]_PORT_A_data_in, N1_q_b[13]_clock_0, , , N1_q_b[13]_clock_enable_0);
N1_q_b[13]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[13]_PORT_A_address_reg = DFFE(N1_q_b[13]_PORT_A_address, N1_q_b[13]_clock_0, , , N1_q_b[13]_clock_enable_0);
N1_q_b[13]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[13]_PORT_B_address_reg = DFFE(N1_q_b[13]_PORT_B_address, N1_q_b[13]_clock_0, , , N1_q_b[13]_clock_enable_0);
N1_q_b[13]_PORT_A_write_enable = VCC;
N1_q_b[13]_PORT_A_write_enable_reg = DFFE(N1_q_b[13]_PORT_A_write_enable, N1_q_b[13]_clock_0, , , N1_q_b[13]_clock_enable_0);
N1_q_b[13]_PORT_B_read_enable = VCC;
N1_q_b[13]_PORT_B_read_enable_reg = DFFE(N1_q_b[13]_PORT_B_read_enable, N1_q_b[13]_clock_0, , , N1_q_b[13]_clock_enable_0);
N1_q_b[13]_clock_0 = CCD_PIXCLK;
N1_q_b[13]_clock_enable_0 = D1_oDVAL;
N1_q_b[13]_PORT_B_data_out = MEMORY(N1_q_b[13]_PORT_A_data_in_reg, , N1_q_b[13]_PORT_A_address_reg, N1_q_b[13]_PORT_B_address_reg, N1_q_b[13]_PORT_A_write_enable_reg, N1_q_b[13]_PORT_B_read_enable_reg, , , N1_q_b[13]_clock_0, , N1_q_b[13]_clock_enable_0, , , );
N1_q_b[13]_PORT_B_data_out_reg = DFFE(N1_q_b[13]_PORT_B_data_out, N1_q_b[13]_clock_0, , , N1_q_b[13]_clock_enable_0);
N1_q_b[13] = N1_q_b[13]_PORT_B_data_out_reg[0];


--E1_mDATAd_1[3] is RAW2RGB:u4|mDATAd_1[3]
E1_mDATAd_1[3] = DFFEAS(N1_q_b[3], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--N1_q_b[3] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[3]_PORT_A_data_in = D1_mCCD_DATA[3];
N1_q_b[3]_PORT_A_data_in_reg = DFFE(N1_q_b[3]_PORT_A_data_in, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[3]_PORT_A_address_reg = DFFE(N1_q_b[3]_PORT_A_address, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[3]_PORT_B_address_reg = DFFE(N1_q_b[3]_PORT_B_address, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_A_write_enable = VCC;
N1_q_b[3]_PORT_A_write_enable_reg = DFFE(N1_q_b[3]_PORT_A_write_enable, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_B_read_enable = VCC;
N1_q_b[3]_PORT_B_read_enable_reg = DFFE(N1_q_b[3]_PORT_B_read_enable, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_clock_0 = CCD_PIXCLK;
N1_q_b[3]_clock_enable_0 = D1_oDVAL;
N1_q_b[3]_PORT_B_data_out = MEMORY(N1_q_b[3]_PORT_A_data_in_reg, , N1_q_b[3]_PORT_A_address_reg, N1_q_b[3]_PORT_B_address_reg, N1_q_b[3]_PORT_A_write_enable_reg, N1_q_b[3]_PORT_B_read_enable_reg, , , N1_q_b[3]_clock_0, , N1_q_b[3]_clock_enable_0, , , );
N1_q_b[3]_PORT_B_data_out_reg = DFFE(N1_q_b[3]_PORT_B_data_out, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3] = N1_q_b[3]_PORT_B_data_out_reg[0];


--E1L38 is RAW2RGB:u4|mCCD_B~156
E1L38 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[3] # !D1_X_Cont[0] & (N1_q_b[3]));


--E1_mDATAd_0[3] is RAW2RGB:u4|mDATAd_0[3]
E1_mDATAd_0[3] = DFFEAS(N1_q_b[13], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1L39 is RAW2RGB:u4|mCCD_B~157
E1L39 = D1_Y_Cont[0] & (E1L38 & (E1_mDATAd_0[3]) # !E1L38 & N1_q_b[13]) # !D1_Y_Cont[0] & (E1L38);


--E1L102 is RAW2RGB:u4|mCCD_R~947
E1L102 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[3] # !D1_Y_Cont[0] & (E1_mDATAd_0[3]));


--E1L103 is RAW2RGB:u4|mCCD_R~948
E1L103 = D1_X_Cont[0] & (E1L102 & (N1_q_b[3]) # !E1L102 & N1_q_b[13]) # !D1_X_Cont[0] & (E1L102);


--N1_q_b[14] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[14]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[14]_PORT_A_data_in = N1_q_b[4];
N1_q_b[14]_PORT_A_data_in_reg = DFFE(N1_q_b[14]_PORT_A_data_in, N1_q_b[14]_clock_0, , , N1_q_b[14]_clock_enable_0);
N1_q_b[14]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[14]_PORT_A_address_reg = DFFE(N1_q_b[14]_PORT_A_address, N1_q_b[14]_clock_0, , , N1_q_b[14]_clock_enable_0);
N1_q_b[14]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[14]_PORT_B_address_reg = DFFE(N1_q_b[14]_PORT_B_address, N1_q_b[14]_clock_0, , , N1_q_b[14]_clock_enable_0);
N1_q_b[14]_PORT_A_write_enable = VCC;
N1_q_b[14]_PORT_A_write_enable_reg = DFFE(N1_q_b[14]_PORT_A_write_enable, N1_q_b[14]_clock_0, , , N1_q_b[14]_clock_enable_0);
N1_q_b[14]_PORT_B_read_enable = VCC;
N1_q_b[14]_PORT_B_read_enable_reg = DFFE(N1_q_b[14]_PORT_B_read_enable, N1_q_b[14]_clock_0, , , N1_q_b[14]_clock_enable_0);
N1_q_b[14]_clock_0 = CCD_PIXCLK;
N1_q_b[14]_clock_enable_0 = D1_oDVAL;
N1_q_b[14]_PORT_B_data_out = MEMORY(N1_q_b[14]_PORT_A_data_in_reg, , N1_q_b[14]_PORT_A_address_reg, N1_q_b[14]_PORT_B_address_reg, N1_q_b[14]_PORT_A_write_enable_reg, N1_q_b[14]_PORT_B_read_enable_reg, , , N1_q_b[14]_clock_0, , N1_q_b[14]_clock_enable_0, , , );
N1_q_b[14]_PORT_B_data_out_reg = DFFE(N1_q_b[14]_PORT_B_data_out, N1_q_b[14]_clock_0, , , N1_q_b[14]_clock_enable_0);
N1_q_b[14] = N1_q_b[14]_PORT_B_data_out_reg[0];


--E1_mDATAd_1[4] is RAW2RGB:u4|mDATAd_1[4]
E1_mDATAd_1[4] = DFFEAS(N1_q_b[4], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--N1_q_b[4] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[4]_PORT_A_data_in = D1_mCCD_DATA[4];
N1_q_b[4]_PORT_A_data_in_reg = DFFE(N1_q_b[4]_PORT_A_data_in, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[4]_PORT_A_address_reg = DFFE(N1_q_b[4]_PORT_A_address, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[4]_PORT_B_address_reg = DFFE(N1_q_b[4]_PORT_B_address, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_A_write_enable = VCC;
N1_q_b[4]_PORT_A_write_enable_reg = DFFE(N1_q_b[4]_PORT_A_write_enable, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_B_read_enable = VCC;
N1_q_b[4]_PORT_B_read_enable_reg = DFFE(N1_q_b[4]_PORT_B_read_enable, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_clock_0 = CCD_PIXCLK;
N1_q_b[4]_clock_enable_0 = D1_oDVAL;
N1_q_b[4]_PORT_B_data_out = MEMORY(N1_q_b[4]_PORT_A_data_in_reg, , N1_q_b[4]_PORT_A_address_reg, N1_q_b[4]_PORT_B_address_reg, N1_q_b[4]_PORT_A_write_enable_reg, N1_q_b[4]_PORT_B_read_enable_reg, , , N1_q_b[4]_clock_0, , N1_q_b[4]_clock_enable_0, , , );
N1_q_b[4]_PORT_B_data_out_reg = DFFE(N1_q_b[4]_PORT_B_data_out, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4] = N1_q_b[4]_PORT_B_data_out_reg[0];


--E1L40 is RAW2RGB:u4|mCCD_B~158
E1L40 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[4] # !D1_X_Cont[0] & (N1_q_b[4]));


--E1_mDATAd_0[4] is RAW2RGB:u4|mDATAd_0[4]
E1_mDATAd_0[4] = DFFEAS(N1_q_b[14], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1L41 is RAW2RGB:u4|mCCD_B~159
E1L41 = D1_Y_Cont[0] & (E1L40 & (E1_mDATAd_0[4]) # !E1L40 & N1_q_b[14]) # !D1_Y_Cont[0] & (E1L40);


--E1L104 is RAW2RGB:u4|mCCD_R~949
E1L104 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[4] # !D1_Y_Cont[0] & (E1_mDATAd_0[4]));


--E1L105 is RAW2RGB:u4|mCCD_R~950
E1L105 = D1_X_Cont[0] & (E1L104 & (N1_q_b[4]) # !E1L104 & N1_q_b[14]) # !D1_X_Cont[0] & (E1L104);


--N1_q_b[15] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[15]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[15]_PORT_A_data_in = N1_q_b[5];
N1_q_b[15]_PORT_A_data_in_reg = DFFE(N1_q_b[15]_PORT_A_data_in, N1_q_b[15]_clock_0, , , N1_q_b[15]_clock_enable_0);
N1_q_b[15]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[15]_PORT_A_address_reg = DFFE(N1_q_b[15]_PORT_A_address, N1_q_b[15]_clock_0, , , N1_q_b[15]_clock_enable_0);
N1_q_b[15]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[15]_PORT_B_address_reg = DFFE(N1_q_b[15]_PORT_B_address, N1_q_b[15]_clock_0, , , N1_q_b[15]_clock_enable_0);
N1_q_b[15]_PORT_A_write_enable = VCC;
N1_q_b[15]_PORT_A_write_enable_reg = DFFE(N1_q_b[15]_PORT_A_write_enable, N1_q_b[15]_clock_0, , , N1_q_b[15]_clock_enable_0);
N1_q_b[15]_PORT_B_read_enable = VCC;
N1_q_b[15]_PORT_B_read_enable_reg = DFFE(N1_q_b[15]_PORT_B_read_enable, N1_q_b[15]_clock_0, , , N1_q_b[15]_clock_enable_0);
N1_q_b[15]_clock_0 = CCD_PIXCLK;
N1_q_b[15]_clock_enable_0 = D1_oDVAL;
N1_q_b[15]_PORT_B_data_out = MEMORY(N1_q_b[15]_PORT_A_data_in_reg, , N1_q_b[15]_PORT_A_address_reg, N1_q_b[15]_PORT_B_address_reg, N1_q_b[15]_PORT_A_write_enable_reg, N1_q_b[15]_PORT_B_read_enable_reg, , , N1_q_b[15]_clock_0, , N1_q_b[15]_clock_enable_0, , , );
N1_q_b[15]_PORT_B_data_out_reg = DFFE(N1_q_b[15]_PORT_B_data_out, N1_q_b[15]_clock_0, , , N1_q_b[15]_clock_enable_0);
N1_q_b[15] = N1_q_b[15]_PORT_B_data_out_reg[0];


--E1_mDATAd_1[5] is RAW2RGB:u4|mDATAd_1[5]
E1_mDATAd_1[5] = DFFEAS(N1_q_b[5], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--N1_q_b[5] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[5]_PORT_A_data_in = D1_mCCD_DATA[5];
N1_q_b[5]_PORT_A_data_in_reg = DFFE(N1_q_b[5]_PORT_A_data_in, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[5]_PORT_A_address_reg = DFFE(N1_q_b[5]_PORT_A_address, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[5]_PORT_B_address_reg = DFFE(N1_q_b[5]_PORT_B_address, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_A_write_enable = VCC;
N1_q_b[5]_PORT_A_write_enable_reg = DFFE(N1_q_b[5]_PORT_A_write_enable, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_B_read_enable = VCC;
N1_q_b[5]_PORT_B_read_enable_reg = DFFE(N1_q_b[5]_PORT_B_read_enable, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_clock_0 = CCD_PIXCLK;
N1_q_b[5]_clock_enable_0 = D1_oDVAL;
N1_q_b[5]_PORT_B_data_out = MEMORY(N1_q_b[5]_PORT_A_data_in_reg, , N1_q_b[5]_PORT_A_address_reg, N1_q_b[5]_PORT_B_address_reg, N1_q_b[5]_PORT_A_write_enable_reg, N1_q_b[5]_PORT_B_read_enable_reg, , , N1_q_b[5]_clock_0, , N1_q_b[5]_clock_enable_0, , , );
N1_q_b[5]_PORT_B_data_out_reg = DFFE(N1_q_b[5]_PORT_B_data_out, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5] = N1_q_b[5]_PORT_B_data_out_reg[0];


--E1L42 is RAW2RGB:u4|mCCD_B~160
E1L42 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[5] # !D1_X_Cont[0] & (N1_q_b[5]));


--E1_mDATAd_0[5] is RAW2RGB:u4|mDATAd_0[5]
E1_mDATAd_0[5] = DFFEAS(N1_q_b[15], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1L43 is RAW2RGB:u4|mCCD_B~161
E1L43 = D1_Y_Cont[0] & (E1L42 & (E1_mDATAd_0[5]) # !E1L42 & N1_q_b[15]) # !D1_Y_Cont[0] & (E1L42);


--E1L106 is RAW2RGB:u4|mCCD_R~951
E1L106 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[5] # !D1_Y_Cont[0] & (E1_mDATAd_0[5]));


--E1L107 is RAW2RGB:u4|mCCD_R~952
E1L107 = D1_X_Cont[0] & (E1L106 & (N1_q_b[5]) # !E1L106 & N1_q_b[15]) # !D1_X_Cont[0] & (E1L106);


--N1_q_b[16] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[16]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[16]_PORT_A_data_in = N1_q_b[6];
N1_q_b[16]_PORT_A_data_in_reg = DFFE(N1_q_b[16]_PORT_A_data_in, N1_q_b[16]_clock_0, , , N1_q_b[16]_clock_enable_0);
N1_q_b[16]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[16]_PORT_A_address_reg = DFFE(N1_q_b[16]_PORT_A_address, N1_q_b[16]_clock_0, , , N1_q_b[16]_clock_enable_0);
N1_q_b[16]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[16]_PORT_B_address_reg = DFFE(N1_q_b[16]_PORT_B_address, N1_q_b[16]_clock_0, , , N1_q_b[16]_clock_enable_0);
N1_q_b[16]_PORT_A_write_enable = VCC;
N1_q_b[16]_PORT_A_write_enable_reg = DFFE(N1_q_b[16]_PORT_A_write_enable, N1_q_b[16]_clock_0, , , N1_q_b[16]_clock_enable_0);
N1_q_b[16]_PORT_B_read_enable = VCC;
N1_q_b[16]_PORT_B_read_enable_reg = DFFE(N1_q_b[16]_PORT_B_read_enable, N1_q_b[16]_clock_0, , , N1_q_b[16]_clock_enable_0);
N1_q_b[16]_clock_0 = CCD_PIXCLK;
N1_q_b[16]_clock_enable_0 = D1_oDVAL;
N1_q_b[16]_PORT_B_data_out = MEMORY(N1_q_b[16]_PORT_A_data_in_reg, , N1_q_b[16]_PORT_A_address_reg, N1_q_b[16]_PORT_B_address_reg, N1_q_b[16]_PORT_A_write_enable_reg, N1_q_b[16]_PORT_B_read_enable_reg, , , N1_q_b[16]_clock_0, , N1_q_b[16]_clock_enable_0, , , );
N1_q_b[16]_PORT_B_data_out_reg = DFFE(N1_q_b[16]_PORT_B_data_out, N1_q_b[16]_clock_0, , , N1_q_b[16]_clock_enable_0);
N1_q_b[16] = N1_q_b[16]_PORT_B_data_out_reg[0];


--E1_mDATAd_1[6] is RAW2RGB:u4|mDATAd_1[6]
E1_mDATAd_1[6] = DFFEAS(N1_q_b[6], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--N1_q_b[6] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[6]_PORT_A_data_in = D1_mCCD_DATA[6];
N1_q_b[6]_PORT_A_data_in_reg = DFFE(N1_q_b[6]_PORT_A_data_in, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[6]_PORT_A_address_reg = DFFE(N1_q_b[6]_PORT_A_address, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[6]_PORT_B_address_reg = DFFE(N1_q_b[6]_PORT_B_address, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_A_write_enable = VCC;
N1_q_b[6]_PORT_A_write_enable_reg = DFFE(N1_q_b[6]_PORT_A_write_enable, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_B_read_enable = VCC;
N1_q_b[6]_PORT_B_read_enable_reg = DFFE(N1_q_b[6]_PORT_B_read_enable, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_clock_0 = CCD_PIXCLK;
N1_q_b[6]_clock_enable_0 = D1_oDVAL;
N1_q_b[6]_PORT_B_data_out = MEMORY(N1_q_b[6]_PORT_A_data_in_reg, , N1_q_b[6]_PORT_A_address_reg, N1_q_b[6]_PORT_B_address_reg, N1_q_b[6]_PORT_A_write_enable_reg, N1_q_b[6]_PORT_B_read_enable_reg, , , N1_q_b[6]_clock_0, , N1_q_b[6]_clock_enable_0, , , );
N1_q_b[6]_PORT_B_data_out_reg = DFFE(N1_q_b[6]_PORT_B_data_out, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6] = N1_q_b[6]_PORT_B_data_out_reg[0];


--E1L44 is RAW2RGB:u4|mCCD_B~162
E1L44 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[6] # !D1_X_Cont[0] & (N1_q_b[6]));


--E1_mDATAd_0[6] is RAW2RGB:u4|mDATAd_0[6]
E1_mDATAd_0[6] = DFFEAS(N1_q_b[16], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1L45 is RAW2RGB:u4|mCCD_B~163
E1L45 = D1_Y_Cont[0] & (E1L44 & (E1_mDATAd_0[6]) # !E1L44 & N1_q_b[16]) # !D1_Y_Cont[0] & (E1L44);


--E1L108 is RAW2RGB:u4|mCCD_R~953
E1L108 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[6] # !D1_Y_Cont[0] & (E1_mDATAd_0[6]));


--E1L109 is RAW2RGB:u4|mCCD_R~954
E1L109 = D1_X_Cont[0] & (E1L108 & (N1_q_b[6]) # !E1L108 & N1_q_b[16]) # !D1_X_Cont[0] & (E1L108);


--N1_q_b[17] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[17]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[17]_PORT_A_data_in = N1_q_b[7];
N1_q_b[17]_PORT_A_data_in_reg = DFFE(N1_q_b[17]_PORT_A_data_in, N1_q_b[17]_clock_0, , , N1_q_b[17]_clock_enable_0);
N1_q_b[17]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[17]_PORT_A_address_reg = DFFE(N1_q_b[17]_PORT_A_address, N1_q_b[17]_clock_0, , , N1_q_b[17]_clock_enable_0);
N1_q_b[17]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[17]_PORT_B_address_reg = DFFE(N1_q_b[17]_PORT_B_address, N1_q_b[17]_clock_0, , , N1_q_b[17]_clock_enable_0);
N1_q_b[17]_PORT_A_write_enable = VCC;
N1_q_b[17]_PORT_A_write_enable_reg = DFFE(N1_q_b[17]_PORT_A_write_enable, N1_q_b[17]_clock_0, , , N1_q_b[17]_clock_enable_0);
N1_q_b[17]_PORT_B_read_enable = VCC;
N1_q_b[17]_PORT_B_read_enable_reg = DFFE(N1_q_b[17]_PORT_B_read_enable, N1_q_b[17]_clock_0, , , N1_q_b[17]_clock_enable_0);
N1_q_b[17]_clock_0 = CCD_PIXCLK;
N1_q_b[17]_clock_enable_0 = D1_oDVAL;
N1_q_b[17]_PORT_B_data_out = MEMORY(N1_q_b[17]_PORT_A_data_in_reg, , N1_q_b[17]_PORT_A_address_reg, N1_q_b[17]_PORT_B_address_reg, N1_q_b[17]_PORT_A_write_enable_reg, N1_q_b[17]_PORT_B_read_enable_reg, , , N1_q_b[17]_clock_0, , N1_q_b[17]_clock_enable_0, , , );
N1_q_b[17]_PORT_B_data_out_reg = DFFE(N1_q_b[17]_PORT_B_data_out, N1_q_b[17]_clock_0, , , N1_q_b[17]_clock_enable_0);
N1_q_b[17] = N1_q_b[17]_PORT_B_data_out_reg[0];


--E1_mDATAd_1[7] is RAW2RGB:u4|mDATAd_1[7]
E1_mDATAd_1[7] = DFFEAS(N1_q_b[7], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--N1_q_b[7] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[7]_PORT_A_data_in = D1_mCCD_DATA[7];
N1_q_b[7]_PORT_A_data_in_reg = DFFE(N1_q_b[7]_PORT_A_data_in, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[7]_PORT_A_address_reg = DFFE(N1_q_b[7]_PORT_A_address, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[7]_PORT_B_address_reg = DFFE(N1_q_b[7]_PORT_B_address, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_A_write_enable = VCC;
N1_q_b[7]_PORT_A_write_enable_reg = DFFE(N1_q_b[7]_PORT_A_write_enable, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_B_read_enable = VCC;
N1_q_b[7]_PORT_B_read_enable_reg = DFFE(N1_q_b[7]_PORT_B_read_enable, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_clock_0 = CCD_PIXCLK;
N1_q_b[7]_clock_enable_0 = D1_oDVAL;
N1_q_b[7]_PORT_B_data_out = MEMORY(N1_q_b[7]_PORT_A_data_in_reg, , N1_q_b[7]_PORT_A_address_reg, N1_q_b[7]_PORT_B_address_reg, N1_q_b[7]_PORT_A_write_enable_reg, N1_q_b[7]_PORT_B_read_enable_reg, , , N1_q_b[7]_clock_0, , N1_q_b[7]_clock_enable_0, , , );
N1_q_b[7]_PORT_B_data_out_reg = DFFE(N1_q_b[7]_PORT_B_data_out, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7] = N1_q_b[7]_PORT_B_data_out_reg[0];


--E1L46 is RAW2RGB:u4|mCCD_B~164
E1L46 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[7] # !D1_X_Cont[0] & (N1_q_b[7]));


--E1_mDATAd_0[7] is RAW2RGB:u4|mDATAd_0[7]
E1_mDATAd_0[7] = DFFEAS(N1_q_b[17], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1L47 is RAW2RGB:u4|mCCD_B~165
E1L47 = D1_Y_Cont[0] & (E1L46 & (E1_mDATAd_0[7]) # !E1L46 & N1_q_b[17]) # !D1_Y_Cont[0] & (E1L46);


--E1L110 is RAW2RGB:u4|mCCD_R~955
E1L110 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[7] # !D1_Y_Cont[0] & (E1_mDATAd_0[7]));


--E1L111 is RAW2RGB:u4|mCCD_R~956
E1L111 = D1_X_Cont[0] & (E1L110 & (N1_q_b[7]) # !E1L110 & N1_q_b[17]) # !D1_X_Cont[0] & (E1L110);


--N1_q_b[18] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[18]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[18]_PORT_A_data_in = N1_q_b[8];
N1_q_b[18]_PORT_A_data_in_reg = DFFE(N1_q_b[18]_PORT_A_data_in, N1_q_b[18]_clock_0, , , N1_q_b[18]_clock_enable_0);
N1_q_b[18]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[18]_PORT_A_address_reg = DFFE(N1_q_b[18]_PORT_A_address, N1_q_b[18]_clock_0, , , N1_q_b[18]_clock_enable_0);
N1_q_b[18]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[18]_PORT_B_address_reg = DFFE(N1_q_b[18]_PORT_B_address, N1_q_b[18]_clock_0, , , N1_q_b[18]_clock_enable_0);
N1_q_b[18]_PORT_A_write_enable = VCC;
N1_q_b[18]_PORT_A_write_enable_reg = DFFE(N1_q_b[18]_PORT_A_write_enable, N1_q_b[18]_clock_0, , , N1_q_b[18]_clock_enable_0);
N1_q_b[18]_PORT_B_read_enable = VCC;
N1_q_b[18]_PORT_B_read_enable_reg = DFFE(N1_q_b[18]_PORT_B_read_enable, N1_q_b[18]_clock_0, , , N1_q_b[18]_clock_enable_0);
N1_q_b[18]_clock_0 = CCD_PIXCLK;
N1_q_b[18]_clock_enable_0 = D1_oDVAL;
N1_q_b[18]_PORT_B_data_out = MEMORY(N1_q_b[18]_PORT_A_data_in_reg, , N1_q_b[18]_PORT_A_address_reg, N1_q_b[18]_PORT_B_address_reg, N1_q_b[18]_PORT_A_write_enable_reg, N1_q_b[18]_PORT_B_read_enable_reg, , , N1_q_b[18]_clock_0, , N1_q_b[18]_clock_enable_0, , , );
N1_q_b[18]_PORT_B_data_out_reg = DFFE(N1_q_b[18]_PORT_B_data_out, N1_q_b[18]_clock_0, , , N1_q_b[18]_clock_enable_0);
N1_q_b[18] = N1_q_b[18]_PORT_B_data_out_reg[0];


--E1_mDATAd_1[8] is RAW2RGB:u4|mDATAd_1[8]
E1_mDATAd_1[8] = DFFEAS(N1_q_b[8], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--N1_q_b[8] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[8]_PORT_A_data_in = D1_mCCD_DATA[8];
N1_q_b[8]_PORT_A_data_in_reg = DFFE(N1_q_b[8]_PORT_A_data_in, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[8]_PORT_A_address_reg = DFFE(N1_q_b[8]_PORT_A_address, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[8]_PORT_B_address_reg = DFFE(N1_q_b[8]_PORT_B_address, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_A_write_enable = VCC;
N1_q_b[8]_PORT_A_write_enable_reg = DFFE(N1_q_b[8]_PORT_A_write_enable, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_B_read_enable = VCC;
N1_q_b[8]_PORT_B_read_enable_reg = DFFE(N1_q_b[8]_PORT_B_read_enable, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_clock_0 = CCD_PIXCLK;
N1_q_b[8]_clock_enable_0 = D1_oDVAL;
N1_q_b[8]_PORT_B_data_out = MEMORY(N1_q_b[8]_PORT_A_data_in_reg, , N1_q_b[8]_PORT_A_address_reg, N1_q_b[8]_PORT_B_address_reg, N1_q_b[8]_PORT_A_write_enable_reg, N1_q_b[8]_PORT_B_read_enable_reg, , , N1_q_b[8]_clock_0, , N1_q_b[8]_clock_enable_0, , , );
N1_q_b[8]_PORT_B_data_out_reg = DFFE(N1_q_b[8]_PORT_B_data_out, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8] = N1_q_b[8]_PORT_B_data_out_reg[0];


--E1L48 is RAW2RGB:u4|mCCD_B~166
E1L48 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[8] # !D1_X_Cont[0] & (N1_q_b[8]));


--E1_mDATAd_0[8] is RAW2RGB:u4|mDATAd_0[8]
E1_mDATAd_0[8] = DFFEAS(N1_q_b[18], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1L49 is RAW2RGB:u4|mCCD_B~167
E1L49 = D1_Y_Cont[0] & (E1L48 & (E1_mDATAd_0[8]) # !E1L48 & N1_q_b[18]) # !D1_Y_Cont[0] & (E1L48);


--E1L112 is RAW2RGB:u4|mCCD_R~957
E1L112 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[8] # !D1_Y_Cont[0] & (E1_mDATAd_0[8]));


--E1L113 is RAW2RGB:u4|mCCD_R~958
E1L113 = D1_X_Cont[0] & (E1L112 & (N1_q_b[8]) # !E1L112 & N1_q_b[18]) # !D1_X_Cont[0] & (E1L112);


--N1_q_b[19] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[19]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[19]_PORT_A_data_in = N1_q_b[9];
N1_q_b[19]_PORT_A_data_in_reg = DFFE(N1_q_b[19]_PORT_A_data_in, N1_q_b[19]_clock_0, , , N1_q_b[19]_clock_enable_0);
N1_q_b[19]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[19]_PORT_A_address_reg = DFFE(N1_q_b[19]_PORT_A_address, N1_q_b[19]_clock_0, , , N1_q_b[19]_clock_enable_0);
N1_q_b[19]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[19]_PORT_B_address_reg = DFFE(N1_q_b[19]_PORT_B_address, N1_q_b[19]_clock_0, , , N1_q_b[19]_clock_enable_0);
N1_q_b[19]_PORT_A_write_enable = VCC;
N1_q_b[19]_PORT_A_write_enable_reg = DFFE(N1_q_b[19]_PORT_A_write_enable, N1_q_b[19]_clock_0, , , N1_q_b[19]_clock_enable_0);
N1_q_b[19]_PORT_B_read_enable = VCC;
N1_q_b[19]_PORT_B_read_enable_reg = DFFE(N1_q_b[19]_PORT_B_read_enable, N1_q_b[19]_clock_0, , , N1_q_b[19]_clock_enable_0);
N1_q_b[19]_clock_0 = CCD_PIXCLK;
N1_q_b[19]_clock_enable_0 = D1_oDVAL;
N1_q_b[19]_PORT_B_data_out = MEMORY(N1_q_b[19]_PORT_A_data_in_reg, , N1_q_b[19]_PORT_A_address_reg, N1_q_b[19]_PORT_B_address_reg, N1_q_b[19]_PORT_A_write_enable_reg, N1_q_b[19]_PORT_B_read_enable_reg, , , N1_q_b[19]_clock_0, , N1_q_b[19]_clock_enable_0, , , );
N1_q_b[19]_PORT_B_data_out_reg = DFFE(N1_q_b[19]_PORT_B_data_out, N1_q_b[19]_clock_0, , , N1_q_b[19]_clock_enable_0);
N1_q_b[19] = N1_q_b[19]_PORT_B_data_out_reg[0];


--E1_mDATAd_1[9] is RAW2RGB:u4|mDATAd_1[9]
E1_mDATAd_1[9] = DFFEAS(N1_q_b[9], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--N1_q_b[9] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1278, Port A Width: 1, Port B Depth: 1278, Port B Width: 1
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[9]_PORT_A_data_in = D1_mCCD_DATA[9];
N1_q_b[9]_PORT_A_data_in_reg = DFFE(N1_q_b[9]_PORT_A_data_in, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[9]_PORT_A_address_reg = DFFE(N1_q_b[9]_PORT_A_address, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[9]_PORT_B_address_reg = DFFE(N1_q_b[9]_PORT_B_address, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_A_write_enable = VCC;
N1_q_b[9]_PORT_A_write_enable_reg = DFFE(N1_q_b[9]_PORT_A_write_enable, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_B_read_enable = VCC;
N1_q_b[9]_PORT_B_read_enable_reg = DFFE(N1_q_b[9]_PORT_B_read_enable, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_clock_0 = CCD_PIXCLK;
N1_q_b[9]_clock_enable_0 = D1_oDVAL;
N1_q_b[9]_PORT_B_data_out = MEMORY(N1_q_b[9]_PORT_A_data_in_reg, , N1_q_b[9]_PORT_A_address_reg, N1_q_b[9]_PORT_B_address_reg, N1_q_b[9]_PORT_A_write_enable_reg, N1_q_b[9]_PORT_B_read_enable_reg, , , N1_q_b[9]_clock_0, , N1_q_b[9]_clock_enable_0, , , );
N1_q_b[9]_PORT_B_data_out_reg = DFFE(N1_q_b[9]_PORT_B_data_out, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9] = N1_q_b[9]_PORT_B_data_out_reg[0];


--E1L50 is RAW2RGB:u4|mCCD_B~168
E1L50 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[9] # !D1_X_Cont[0] & (N1_q_b[9]));


--E1_mDATAd_0[9] is RAW2RGB:u4|mDATAd_0[9]
E1_mDATAd_0[9] = DFFEAS(N1_q_b[19], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--E1L51 is RAW2RGB:u4|mCCD_B~169
E1L51 = D1_Y_Cont[0] & (E1L50 & (E1_mDATAd_0[9]) # !E1L50 & N1_q_b[19]) # !D1_Y_Cont[0] & (E1L50);


--E1L114 is RAW2RGB:u4|mCCD_R~959
E1L114 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[9] # !D1_Y_Cont[0] & (E1_mDATAd_0[9]));


--E1L115 is RAW2RGB:u4|mCCD_R~960
E1L115 = D1_X_Cont[0] & (E1L114 & (N1_q_b[9]) # !E1L114 & N1_q_b[19]) # !D1_X_Cont[0] & (E1L114);


--E1L1 is RAW2RGB:u4|add~1591
E1L1 = N1_q_b[16] & (N1_q_b[6] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !N1_q_b[16] & N1_q_b[6] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L2 is RAW2RGB:u4|add~1592
E1L2 = E1_mDATAd_1[6] & (E1_mDATAd_0[6] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !E1_mDATAd_1[6] & E1_mDATAd_0[6] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L3 is RAW2RGB:u4|add~1593
E1L3 = N1_q_b[15] & (N1_q_b[5] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !N1_q_b[15] & N1_q_b[5] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L4 is RAW2RGB:u4|add~1594
E1L4 = E1_mDATAd_1[5] & (E1_mDATAd_0[5] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !E1_mDATAd_1[5] & E1_mDATAd_0[5] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L5 is RAW2RGB:u4|add~1595
E1L5 = N1_q_b[14] & (N1_q_b[4] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !N1_q_b[14] & N1_q_b[4] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L6 is RAW2RGB:u4|add~1596
E1L6 = E1_mDATAd_1[4] & (E1_mDATAd_0[4] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !E1_mDATAd_1[4] & E1_mDATAd_0[4] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L7 is RAW2RGB:u4|add~1597
E1L7 = N1_q_b[13] & (N1_q_b[3] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !N1_q_b[13] & N1_q_b[3] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L8 is RAW2RGB:u4|add~1598
E1L8 = E1_mDATAd_1[3] & (E1_mDATAd_0[3] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !E1_mDATAd_1[3] & E1_mDATAd_0[3] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L9 is RAW2RGB:u4|add~1599
E1L9 = N1_q_b[12] & (N1_q_b[2] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !N1_q_b[12] & N1_q_b[2] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L10 is RAW2RGB:u4|add~1600
E1L10 = E1_mDATAd_1[2] & (E1_mDATAd_0[2] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !E1_mDATAd_1[2] & E1_mDATAd_0[2] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L11 is RAW2RGB:u4|add~1601
E1L11 = N1_q_b[11] & (N1_q_b[1] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !N1_q_b[11] & N1_q_b[1] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L12 is RAW2RGB:u4|add~1602
E1L12 = E1_mDATAd_1[1] & (E1_mDATAd_0[1] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !E1_mDATAd_1[1] & E1_mDATAd_0[1] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L13 is RAW2RGB:u4|add~1603
E1L13 = N1_q_b[10] & (N1_q_b[0] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !N1_q_b[10] & N1_q_b[0] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L14 is RAW2RGB:u4|add~1604
E1L14 = E1_mDATAd_1[0] & (E1_mDATAd_0[0] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !E1_mDATAd_1[0] & E1_mDATAd_0[0] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L55 is RAW2RGB:u4|mCCD_G[1]~868
E1L55 = CARRY(E1L13 & E1L14);


--E1L56 is RAW2RGB:u4|mCCD_G[1]~869
E1L56 = E1L11 & (E1L12 & E1L55 & VCC # !E1L12 & !E1L55) # !E1L11 & (E1L12 & !E1L55 # !E1L12 & (E1L55 # GND));

--E1L57 is RAW2RGB:u4|mCCD_G[1]~870
E1L57 = CARRY(E1L11 & !E1L12 & !E1L55 # !E1L11 & (!E1L55 # !E1L12));


--E1L59 is RAW2RGB:u4|mCCD_G[2]~871
E1L59 = (E1L9 $ E1L10 $ !E1L57) # GND;

--E1L60 is RAW2RGB:u4|mCCD_G[2]~872
E1L60 = CARRY(E1L9 & (E1L10 # !E1L57) # !E1L9 & E1L10 & !E1L57);


--E1L62 is RAW2RGB:u4|mCCD_G[3]~873
E1L62 = E1L7 & (E1L8 & E1L60 & VCC # !E1L8 & !E1L60) # !E1L7 & (E1L8 & !E1L60 # !E1L8 & (E1L60 # GND));

--E1L63 is RAW2RGB:u4|mCCD_G[3]~874
E1L63 = CARRY(E1L7 & !E1L8 & !E1L60 # !E1L7 & (!E1L60 # !E1L8));


--E1L65 is RAW2RGB:u4|mCCD_G[4]~875
E1L65 = (E1L5 $ E1L6 $ !E1L63) # GND;

--E1L66 is RAW2RGB:u4|mCCD_G[4]~876
E1L66 = CARRY(E1L5 & (E1L6 # !E1L63) # !E1L5 & E1L6 & !E1L63);


--E1L68 is RAW2RGB:u4|mCCD_G[5]~877
E1L68 = E1L3 & (E1L4 & E1L66 & VCC # !E1L4 & !E1L66) # !E1L3 & (E1L4 & !E1L66 # !E1L4 & (E1L66 # GND));

--E1L69 is RAW2RGB:u4|mCCD_G[5]~878
E1L69 = CARRY(E1L3 & !E1L4 & !E1L66 # !E1L3 & (!E1L66 # !E1L4));


--E1L71 is RAW2RGB:u4|mCCD_G[6]~879
E1L71 = (E1L1 $ E1L2 $ !E1L69) # GND;

--E1L72 is RAW2RGB:u4|mCCD_G[6]~880
E1L72 = CARRY(E1L1 & (E1L2 # !E1L69) # !E1L1 & E1L2 & !E1L69);


--E1L15 is RAW2RGB:u4|add~1605
E1L15 = N1_q_b[17] & (N1_q_b[7] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !N1_q_b[17] & N1_q_b[7] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L16 is RAW2RGB:u4|add~1606
E1L16 = E1_mDATAd_1[7] & (E1_mDATAd_0[7] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !E1_mDATAd_1[7] & E1_mDATAd_0[7] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L74 is RAW2RGB:u4|mCCD_G[7]~881
E1L74 = E1L15 & (E1L16 & E1L72 & VCC # !E1L16 & !E1L72) # !E1L15 & (E1L16 & !E1L72 # !E1L16 & (E1L72 # GND));

--E1L75 is RAW2RGB:u4|mCCD_G[7]~882
E1L75 = CARRY(E1L15 & !E1L16 & !E1L72 # !E1L15 & (!E1L72 # !E1L16));


--E1L17 is RAW2RGB:u4|add~1607
E1L17 = N1_q_b[18] & (N1_q_b[8] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !N1_q_b[18] & N1_q_b[8] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L18 is RAW2RGB:u4|add~1608
E1L18 = E1_mDATAd_1[8] & (E1_mDATAd_0[8] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !E1_mDATAd_1[8] & E1_mDATAd_0[8] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L77 is RAW2RGB:u4|mCCD_G[8]~883
E1L77 = (E1L17 $ E1L18 $ !E1L75) # GND;

--E1L78 is RAW2RGB:u4|mCCD_G[8]~884
E1L78 = CARRY(E1L17 & (E1L18 # !E1L75) # !E1L17 & E1L18 & !E1L75);


--E1L19 is RAW2RGB:u4|add~1609
E1L19 = N1_q_b[19] & (N1_q_b[9] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !N1_q_b[19] & N1_q_b[9] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L20 is RAW2RGB:u4|add~1610
E1L20 = E1_mDATAd_1[9] & (E1_mDATAd_0[9] # D1_Y_Cont[0] $ !D1_X_Cont[0]) # !E1_mDATAd_1[9] & E1_mDATAd_0[9] & (D1_Y_Cont[0] $ D1_X_Cont[0]);


--E1L80 is RAW2RGB:u4|mCCD_G[9]~885
E1L80 = E1L19 & (E1L20 & E1L78 & VCC # !E1L20 & !E1L78) # !E1L19 & (E1L20 & !E1L78 # !E1L20 & (E1L78 # GND));

--E1L81 is RAW2RGB:u4|mCCD_G[9]~886
E1L81 = CARRY(E1L19 & !E1L20 & !E1L78 # !E1L19 & (!E1L78 # !E1L20));


--E1L83 is RAW2RGB:u4|mCCD_G[10]~887
E1L83 = !E1L81;


--LB1L13 is I2C_CCD_Config:u7|I2C_Controller:u0|END~124
LB1L13 = LB1L56Q & LB1L44Q & LB1L50Q & LB1L53Q;


--LB1L14 is I2C_CCD_Config:u7|I2C_Controller:u0|END~125
LB1L14 = LB1L47Q & (LB1L13 & (LB1L59Q) # !LB1L13 & LB1_END) # !LB1L47Q & (LB1_END);


--LB1_ACK3 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK3
LB1_ACK3 = DFFEAS(LB1L11, H1_mI2C_CTRL_CLK, KEY[1],  ,  ,  ,  ,  ,  );


--LB1_ACK1 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK1
LB1_ACK1 = DFFEAS(LB1L3, H1_mI2C_CTRL_CLK, KEY[1],  ,  ,  ,  ,  ,  );


--LB1_ACK2 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK2
LB1_ACK2 = DFFEAS(LB1L8, H1_mI2C_CTRL_CLK, KEY[1],  ,  ,  ,  ,  ,  );


--H1L128 is I2C_CCD_Config:u7|mSetup_ST~124
H1L128 = !LB1_ACK3 & !LB1_ACK1 & !LB1_ACK2;


--H1L129 is I2C_CCD_Config:u7|mSetup_ST~125
H1L129 = H1_mSetup_ST.0001 & H1L128 & !LB1_END;


--H1_mSetup_ST.0000 is I2C_CCD_Config:u7|mSetup_ST.0000
H1_mSetup_ST.0000 = DFFEAS(H1L41, H1_mI2C_CTRL_CLK, KEY[1],  , H1L38,  ,  ,  ,  );


--H1L40 is I2C_CCD_Config:u7|Select~136
H1L40 = H1_mSetup_ST.0001 & LB1_END # !H1_mSetup_ST.0000;


--H1L14 is I2C_CCD_Config:u7|LUT_INDEX[0]~821
H1L14 = H1_LUT_INDEX[0] $ VCC;

--H1L15 is I2C_CCD_Config:u7|LUT_INDEX[0]~822
H1L15 = CARRY(H1_LUT_INDEX[0]);


--H1L17 is I2C_CCD_Config:u7|LUT_INDEX[1]~823
H1L17 = H1_LUT_INDEX[1] & !H1L15 # !H1_LUT_INDEX[1] & (H1L15 # GND);

--H1L18 is I2C_CCD_Config:u7|LUT_INDEX[1]~824
H1L18 = CARRY(!H1L15 # !H1_LUT_INDEX[1]);


--H1L20 is I2C_CCD_Config:u7|LUT_INDEX[2]~825
H1L20 = H1_LUT_INDEX[2] & (H1L18 $ GND) # !H1_LUT_INDEX[2] & !H1L18 & VCC;

--H1L21 is I2C_CCD_Config:u7|LUT_INDEX[2]~826
H1L21 = CARRY(H1_LUT_INDEX[2] & !H1L18);


--H1L29 is I2C_CCD_Config:u7|LUT_INDEX[5]~0
H1L29 = H1_mSetup_ST.0010 & H1L38;


--H1L23 is I2C_CCD_Config:u7|LUT_INDEX[3]~827
H1L23 = H1_LUT_INDEX[3] & !H1L21 # !H1_LUT_INDEX[3] & (H1L21 # GND);

--H1L24 is I2C_CCD_Config:u7|LUT_INDEX[3]~828
H1L24 = CARRY(!H1L21 # !H1_LUT_INDEX[3]);


--H1L26 is I2C_CCD_Config:u7|LUT_INDEX[4]~829
H1L26 = H1_LUT_INDEX[4] & (H1L24 $ GND) # !H1_LUT_INDEX[4] & !H1L24 & VCC;

--H1L27 is I2C_CCD_Config:u7|LUT_INDEX[4]~830
H1L27 = CARRY(H1_LUT_INDEX[4] & !H1L24);


--H1L30 is I2C_CCD_Config:u7|LUT_INDEX[5]~831
H1L30 = H1_LUT_INDEX[5] $ H1L27;


--H1L8 is I2C_CCD_Config:u7|LUT_DATA[6]~1513
H1L8 = H1_LUT_INDEX[3] & !H1_LUT_INDEX[4] & !H1_LUT_INDEX[2];


--H1L109 is I2C_CCD_Config:u7|mI2C_DATA[4]~969
H1L109 = H1_LUT_INDEX[4] # H1_LUT_INDEX[1] # H1_LUT_INDEX[3] # !H1_LUT_INDEX[2];


--H1L101 is I2C_CCD_Config:u7|mI2C_DATA[2]~906
H1L101 = H1L109 & (H1L8) # !H1L109 & SW[2];


--H1L110 is I2C_CCD_Config:u7|mI2C_DATA[4]~970
H1L110 = H1_LUT_INDEX[4] # H1_LUT_INDEX[2] # H1_LUT_INDEX[3] # !H1_LUT_INDEX[1];


--H1L111 is I2C_CCD_Config:u7|mI2C_DATA[4]~971
H1L111 = H1_LUT_INDEX[5] # H1_LUT_INDEX[0] & H1L110;


--H1L123 is I2C_CCD_Config:u7|mI2C_DATA[15]~972
H1L123 = KEY[1] & H1L38 & !H1_mSetup_ST.0000;


--H1L130 is I2C_CCD_Config:u7|reduce_or~162
H1L130 = H1_LUT_INDEX[1] & (!H1_LUT_INDEX[2] & !H1_LUT_INDEX[3] # !H1_LUT_INDEX[0]) # !H1_LUT_INDEX[1] & (H1_LUT_INDEX[2] # H1_LUT_INDEX[3]);


--H1L131 is I2C_CCD_Config:u7|reduce_or~163
H1L131 = H1_LUT_INDEX[4] & (H1L37 & !H1_LUT_INDEX[0]) # !H1_LUT_INDEX[4] & H1L130;


--H1L132 is I2C_CCD_Config:u7|reduce_or~164
H1L132 = H1_LUT_INDEX[0] & (H1_LUT_INDEX[1] & (H1_LUT_INDEX[3]) # !H1_LUT_INDEX[1] & H1_LUT_INDEX[2] & !H1_LUT_INDEX[3]);


--H1L98 is I2C_CCD_Config:u7|mI2C_DATA[1]~907
H1L98 = H1L109 & (H1L8) # !H1L109 & SW[1];


--H1L9 is I2C_CCD_Config:u7|LUT_DATA[7]~1514
H1L9 = H1_LUT_INDEX[3] # H1_LUT_INDEX[2] & (SW[7] # H1_LUT_INDEX[1]);


--H1L10 is I2C_CCD_Config:u7|LUT_DATA[7]~1515
H1L10 = H1_LUT_INDEX[0] & SW[15] # !H1_LUT_INDEX[0] & (H1L9 & !H1_LUT_INDEX[4]);


--H1L1 is I2C_CCD_Config:u7|LUT_DATA[0]~1516
H1L1 = !H1_LUT_INDEX[2] & (H1_LUT_INDEX[4] $ (H1_LUT_INDEX[1] # H1_LUT_INDEX[3]));


--H1L95 is I2C_CCD_Config:u7|mI2C_DATA[0]~908
H1L95 = H1L109 & (H1L1) # !H1L109 & SW[0];


--H1L4 is I2C_CCD_Config:u7|LUT_DATA[4]~1517
H1L4 = H1_LUT_INDEX[2] & !H1_LUT_INDEX[4] & (!H1_LUT_INDEX[3] # !H1_LUT_INDEX[1]) # !H1_LUT_INDEX[2] & !H1_LUT_INDEX[1] & !H1_LUT_INDEX[3] & H1_LUT_INDEX[4];


--H1L107 is I2C_CCD_Config:u7|mI2C_DATA[4]~909
H1L107 = H1L109 & (H1L4) # !H1L109 & SW[4];


--H1L133 is I2C_CCD_Config:u7|reduce_or~165
H1L133 = H1_LUT_INDEX[0] & (H1_LUT_INDEX[3] # H1_LUT_INDEX[1] & H1_LUT_INDEX[2]);


--H1L134 is I2C_CCD_Config:u7|reduce_or~166
H1L134 = H1_LUT_INDEX[0] & (H1_LUT_INDEX[2] & (!H1_LUT_INDEX[3]) # !H1_LUT_INDEX[2] & (H1_LUT_INDEX[1] # H1_LUT_INDEX[3]));


--H1L2 is I2C_CCD_Config:u7|LUT_DATA[3]~1518
H1L2 = !H1_LUT_INDEX[1] & (H1_LUT_INDEX[4] & (!H1_LUT_INDEX[2]) # !H1_LUT_INDEX[4] & SW[3] & H1_LUT_INDEX[2]);


--H1L3 is I2C_CCD_Config:u7|LUT_DATA[3]~1519
H1L3 = !H1_LUT_INDEX[4] & (H1_LUT_INDEX[1] # !H1_LUT_INDEX[2]);


--H1L104 is I2C_CCD_Config:u7|mI2C_DATA[3]~910
H1L104 = H1_LUT_INDEX[3] & (H1L3) # !H1_LUT_INDEX[3] & H1L2;


--H1L114 is I2C_CCD_Config:u7|mI2C_DATA[6]~911
H1L114 = H1L109 & (H1L8) # !H1L109 & SW[6];


--H1L5 is I2C_CCD_Config:u7|LUT_DATA[5]~1520
H1L5 = H1_LUT_INDEX[1] & (!H1_LUT_INDEX[3]) # !H1_LUT_INDEX[1] & (SW[5] # H1_LUT_INDEX[3]);


--H1L6 is I2C_CCD_Config:u7|LUT_DATA[5]~1521
H1L6 = H1_LUT_INDEX[2] & H1L5 & !H1_LUT_INDEX[4] & !H1_LUT_INDEX[0];


--H1L7 is I2C_CCD_Config:u7|LUT_DATA[5]~1522
H1L7 = !H1L111 & (H1L6 # SW[13] & H1_LUT_INDEX[0]);


--H1L135 is I2C_CCD_Config:u7|reduce_or~167
H1L135 = H1_LUT_INDEX[4] $ (H1_LUT_INDEX[1] # H1_LUT_INDEX[2] # H1_LUT_INDEX[3]);


--H1L136 is I2C_CCD_Config:u7|reduce_or~168
H1L136 = H1_LUT_INDEX[2] & (!H1_LUT_INDEX[3] # !H1_LUT_INDEX[0]) # !H1_LUT_INDEX[2] & (H1_LUT_INDEX[3] # H1_LUT_INDEX[0] $ H1_LUT_INDEX[1]);


--H1L137 is I2C_CCD_Config:u7|reduce_or~169
H1L137 = H1_LUT_INDEX[4] & (H1L37 & !H1_LUT_INDEX[0]) # !H1_LUT_INDEX[4] & H1L136;


--R1_command_delay[2] is Sdram_Control_4Port:u6|command:command1|command_delay[2]
R1_command_delay[2] = DFFEAS(R1L69, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L68 is Sdram_Control_4Port:u6|command:command1|command_delay~332
R1L68 = !S1_INIT_REQ & (R1L56 # R1_command_delay[2]);


--R1_rp_shift[2] is Sdram_Control_4Port:u6|command:command1|rp_shift[2]
R1_rp_shift[2] = DFFEAS(R1L105, KB1__clk0,  ,  , R1L99,  ,  ,  ,  );


--R1L104 is Sdram_Control_4Port:u6|command:command1|rp_shift~807
R1L104 = !S1_INIT_REQ & (R1_rp_shift[2] # R1_command_done & !R1_command_delay[0]);


--D1_oDVAL is CCD_Capture:u3|oDVAL
D1_oDVAL = D1_mCCD_FVAL & D1_mCCD_LVAL;


--P1_safe_q[0] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[0]
P1_safe_q[0] = DFFEAS(P1_counter_comb_bita0, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[1] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[1]
P1_safe_q[1] = DFFEAS(P1_counter_comb_bita1, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[2] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[2]
P1_safe_q[2] = DFFEAS(P1_counter_comb_bita2, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[3] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[3]
P1_safe_q[3] = DFFEAS(P1_counter_comb_bita3, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[4] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[4]
P1_safe_q[4] = DFFEAS(P1_counter_comb_bita4, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[5] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[5]
P1_safe_q[5] = DFFEAS(P1_counter_comb_bita5, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[6] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[6]
P1_safe_q[6] = DFFEAS(P1_counter_comb_bita6, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[7] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[7]
P1_safe_q[7] = DFFEAS(P1_counter_comb_bita7, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[8] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[8]
P1_safe_q[8] = DFFEAS(P1_counter_comb_bita8, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[9] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[9]
P1_safe_q[9] = DFFEAS(P1_counter_comb_bita9, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[10] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[10]
P1_safe_q[10] = DFFEAS(P1_counter_comb_bita10, CCD_PIXCLK,  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--D1_mCCD_DATA[0] is CCD_Capture:u3|mCCD_DATA[0]
D1_mCCD_DATA[0] = DFFEAS(rCCD_DATA[0], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[1] is CCD_Capture:u3|mCCD_DATA[1]
D1_mCCD_DATA[1] = DFFEAS(rCCD_DATA[1], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[2] is CCD_Capture:u3|mCCD_DATA[2]
D1_mCCD_DATA[2] = DFFEAS(rCCD_DATA[2], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[3] is CCD_Capture:u3|mCCD_DATA[3]
D1_mCCD_DATA[3] = DFFEAS(rCCD_DATA[3], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[4] is CCD_Capture:u3|mCCD_DATA[4]
D1_mCCD_DATA[4] = DFFEAS(rCCD_DATA[4], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[5] is CCD_Capture:u3|mCCD_DATA[5]
D1_mCCD_DATA[5] = DFFEAS(rCCD_DATA[5], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[6] is CCD_Capture:u3|mCCD_DATA[6]
D1_mCCD_DATA[6] = DFFEAS(rCCD_DATA[6], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[7] is CCD_Capture:u3|mCCD_DATA[7]
D1_mCCD_DATA[7] = DFFEAS(rCCD_DATA[7], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[8] is CCD_Capture:u3|mCCD_DATA[8]
D1_mCCD_DATA[8] = DFFEAS(rCCD_DATA[8], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[9] is CCD_Capture:u3|mCCD_DATA[9]
D1_mCCD_DATA[9] = DFFEAS(rCCD_DATA[9], CCD_PIXCLK, C1_oRST_1,  ,  ,  ,  ,  ,  );


--LB1L10 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK3~215
LB1L10 = LB1L44Q & LB1L59Q & (LB1L41 # LB1L60);


--LB1L78 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1099
LB1L78 = LB1L44Q & (CCD_SDAT & !LB1L50Q) # !LB1L44Q & LB1_ACK1;


--LB1L2 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK1~170
LB1L2 = LB1L56Q & LB1L59Q & (LB1L50Q $ !LB1L53Q);


--LB1L3 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK1~171
LB1L3 = LB1L47Q & (LB1L2 & LB1L78 # !LB1L2 & (LB1_ACK1)) # !LB1L47Q & (LB1_ACK1);


--LB1L6 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK2~251
LB1L6 = LB1L56Q & (!LB1L50Q # !LB1L44Q) # !LB1L56Q & (LB1L44Q # LB1L50Q) # !LB1L59Q;


--H1L41 is I2C_CCD_Config:u7|Select~137
H1L41 = !H1_mSetup_ST.0010 & (LB1_END # H1L128 # !H1_mSetup_ST.0001);


--R1_command_delay[3] is Sdram_Control_4Port:u6|command:command1|command_delay[3]
R1_command_delay[3] = DFFEAS(R1L70, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L69 is Sdram_Control_4Port:u6|command:command1|command_delay~333
R1L69 = !S1_INIT_REQ & (R1L56 # R1_command_delay[3]);


--R1_rp_shift[3] is Sdram_Control_4Port:u6|command:command1|rp_shift[3]
R1_rp_shift[3] = DFFEAS(R1L107, KB1__clk0,  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1L105 is Sdram_Control_4Port:u6|command:command1|rp_shift~808
R1L105 = !S1_INIT_REQ & (R1_rp_shift[3] # R1_command_done & !R1_command_delay[0]);


--P1_counter_comb_bita0 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita0
P1_counter_comb_bita0 = P1_safe_q[0] $ VCC;

--P1L5 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita0~COUT
P1L5 = CARRY(P1_safe_q[0]);


--P1_counter_comb_bita1 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita1
P1_counter_comb_bita1 = P1_safe_q[1] & !P1L5 # !P1_safe_q[1] & (P1L5 # GND);

--P1L7 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita1~COUT
P1L7 = CARRY(!P1L5 # !P1_safe_q[1]);


--P1_counter_comb_bita2 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita2
P1_counter_comb_bita2 = P1_safe_q[2] & (P1L7 $ GND) # !P1_safe_q[2] & !P1L7 & VCC;

--P1L9 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita2~COUT
P1L9 = CARRY(P1_safe_q[2] & !P1L7);


--P1_counter_comb_bita3 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita3
P1_counter_comb_bita3 = P1_safe_q[3] & !P1L9 # !P1_safe_q[3] & (P1L9 # GND);

--P1L11 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita3~COUT
P1L11 = CARRY(!P1L9 # !P1_safe_q[3]);


--P1_counter_comb_bita4 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita4
P1_counter_comb_bita4 = P1_safe_q[4] & (P1L11 $ GND) # !P1_safe_q[4] & !P1L11 & VCC;

--P1L13 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita4~COUT
P1L13 = CARRY(P1_safe_q[4] & !P1L11);


--P1_counter_comb_bita5 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita5
P1_counter_comb_bita5 = P1_safe_q[5] & !P1L13 # !P1_safe_q[5] & (P1L13 # GND);

--P1L15 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita5~COUT
P1L15 = CARRY(!P1L13 # !P1_safe_q[5]);


--P1_counter_comb_bita6 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita6
P1_counter_comb_bita6 = P1_safe_q[6] & (P1L15 $ GND) # !P1_safe_q[6] & !P1L15 & VCC;

--P1L17 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita6~COUT
P1L17 = CARRY(P1_safe_q[6] & !P1L15);


--P1_counter_comb_bita7 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita7
P1_counter_comb_bita7 = P1_safe_q[7] & !P1L17 # !P1_safe_q[7] & (P1L17 # GND);

--P1L19 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita7~COUT
P1L19 = CARRY(!P1L17 # !P1_safe_q[7]);


--P1_counter_comb_bita8 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita8
P1_counter_comb_bita8 = P1_safe_q[8] & (P1L19 $ GND) # !P1_safe_q[8] & !P1L19 & VCC;

--P1L21 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita8~COUT
P1L21 = CARRY(P1_safe_q[8] & !P1L19);


--P1_counter_comb_bita9 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita9
P1_counter_comb_bita9 = P1_safe_q[9] & !P1L21 # !P1_safe_q[9] & (P1L21 # GND);

--P1L23 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita9~COUT
P1L23 = CARRY(!P1L21 # !P1_safe_q[9]);


--P1_counter_comb_bita10 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita10
P1_counter_comb_bita10 = P1_safe_q[10] & (P1L23 $ GND) # !P1_safe_q[10] & !P1L23 & VCC;

--P1L27 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita10~COUT
P1L27 = CARRY(P1_safe_q[10] & !P1L23);


--P1L25 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita10~9
P1L25 = P1L27;


--P1L1 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|cmpr5_aeb_int~68
P1L1 = P1_safe_q[0] & P1_safe_q[2] & P1_safe_q[3] & !P1_safe_q[1];


--P1L2 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|cmpr5_aeb_int~69
P1L2 = P1_safe_q[4] & P1_safe_q[5] & P1_safe_q[6] & P1_safe_q[7];


--P1L3 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|cmpr5_aeb_int~70
P1L3 = P1_safe_q[10] & !P1_safe_q[8] & !P1_safe_q[9];


--P1_cout_actual is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|cout_actual
P1_cout_actual = P1L25 # P1L1 & P1L2 & P1L3;


--rCCD_DATA[0] is rCCD_DATA[0]
rCCD_DATA[0] = DFFEAS(A1L168, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--rCCD_DATA[1] is rCCD_DATA[1]
rCCD_DATA[1] = DFFEAS(A1L170, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--rCCD_DATA[2] is rCCD_DATA[2]
rCCD_DATA[2] = DFFEAS(A1L178, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--rCCD_DATA[3] is rCCD_DATA[3]
rCCD_DATA[3] = DFFEAS(A1L174, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--rCCD_DATA[4] is rCCD_DATA[4]
rCCD_DATA[4] = DFFEAS(A1L172, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--rCCD_DATA[5] is rCCD_DATA[5]
rCCD_DATA[5] = DFFEAS(A1L176, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--rCCD_DATA[6] is rCCD_DATA[6]
rCCD_DATA[6] = DFFEAS(A1L180, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--rCCD_DATA[7] is rCCD_DATA[7]
rCCD_DATA[7] = DFFEAS(A1L182, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--rCCD_DATA[8] is rCCD_DATA[8]
rCCD_DATA[8] = DFFEAS(A1L184, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--rCCD_DATA[9] is rCCD_DATA[9]
rCCD_DATA[9] = DFFEAS(A1L186, CCD_PIXCLK,  ,  ,  ,  ,  ,  ,  );


--R1_command_delay[4] is Sdram_Control_4Port:u6|command:command1|command_delay[4]
R1_command_delay[4] = DFFEAS(R1L71, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L70 is Sdram_Control_4Port:u6|command:command1|command_delay~334
R1L70 = !S1_INIT_REQ & (R1L56 # R1_command_delay[4]);


--R1L106 is Sdram_Control_4Port:u6|command:command1|rp_shift~809
R1L106 = R1_rp_shift[3] & (R1_ex_read # R1_ex_write);


--R1L107 is Sdram_Control_4Port:u6|command:command1|rp_shift~810
R1L107 = R1_command_done & (!G1_PM_STOP & R1L106 # !R1_command_delay[0]) # !R1_command_done & (!G1_PM_STOP & R1L106);


--R1_command_delay[5] is Sdram_Control_4Port:u6|command:command1|command_delay[5]
R1_command_delay[5] = DFFEAS(R1L72, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L71 is Sdram_Control_4Port:u6|command:command1|command_delay~335
R1L71 = !S1_INIT_REQ & (R1L56 # R1_command_delay[5]);


--R1_command_delay[6] is Sdram_Control_4Port:u6|command:command1|command_delay[6]
R1_command_delay[6] = DFFEAS(R1L73, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L72 is Sdram_Control_4Port:u6|command:command1|command_delay~336
R1L72 = !S1_INIT_REQ & (R1L56 # R1_command_delay[6]);


--R1_command_delay[7] is Sdram_Control_4Port:u6|command:command1|command_delay[7]
R1_command_delay[7] = DFFEAS(R1L74, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--R1L73 is Sdram_Control_4Port:u6|command:command1|command_delay~337
R1L73 = !S1_INIT_REQ & (R1L56 # R1_command_delay[7]);


--R1L74 is Sdram_Control_4Port:u6|command:command1|command_delay~338
R1L74 = !S1_INIT_REQ & (R1_do_reada # !R1L54 # !R1L109);


--LB1L40 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[15]~8
LB1L40 = LB1L59Q & !LB1L44Q & LB1L41 & KEY[1];


--H1L11 is I2C_CCD_Config:u7|LUT_DATA[7]~1523
H1L11 = !H1_LUT_INDEX[5] & H1L10 & (!H1L110 # !H1_LUT_INDEX[0]);


--LB1L11 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK3~216
LB1L11 = LB1L10 & CCD_SDAT & !LB1L56Q # !LB1L10 & (LB1_ACK3);


--LB1L5 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK2~237
LB1L5 = !LB1L50Q & !LB1L56Q & CCD_SDAT & !LB1L44Q;


--LB1L7 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK2~252
LB1L7 = LB1_ACK2 & (LB1L6 # LB1L59Q & LB1L5) # !LB1_ACK2 & LB1L59Q & LB1L5;


--LB1L8 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK2~253
LB1L8 = LB1L53Q & (LB1L47Q & (LB1L7) # !LB1L47Q & LB1_ACK2) # !LB1L53Q & LB1_ACK2;


--A1L8 is CCD_MCLK~2
A1L8 = !CCD_MCLK;


--X4L39 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]~19
X4L39 = !EB4_counter_ffa[0];


--X3L37 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]~19
X3L37 = !EB3_counter_ffa[0];


--X1L37 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]~19
X1L37 = !EB1_counter_ffa[0];


--X2L39 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]~19
X2L39 = !EB2_counter_ffa[0];


--~GND is ~GND
~GND = GND;


--CLOCK_27 is CLOCK_27
--operation mode is input

CLOCK_27 = INPUT();


--EXT_CLOCK is EXT_CLOCK
--operation mode is input

EXT_CLOCK = INPUT();


--UART_RXD is UART_RXD
--operation mode is input

UART_RXD = INPUT();


--IRDA_RXD is IRDA_RXD
--operation mode is input

IRDA_RXD = INPUT();


--OTG_INT0 is OTG_INT0
--operation mode is input

OTG_INT0 = INPUT();


--OTG_INT1 is OTG_INT1
--operation mode is input

OTG_INT1 = INPUT();


--OTG_DREQ0 is OTG_DREQ0
--operation mode is input

OTG_DREQ0 = INPUT();


--OTG_DREQ1 is OTG_DREQ1
--operation mode is input

OTG_DREQ1 = INPUT();


--TDI is TDI
--operation mode is input

TDI = INPUT();


--TCK is TCK
--operation mode is input

TCK = INPUT();


--TCS is TCS
--operation mode is input

TCS = INPUT();


--PS2_DAT is PS2_DAT
--operation mode is input

PS2_DAT = INPUT();


--PS2_CLK is PS2_CLK
--operation mode is input

PS2_CLK = INPUT();


--ENET_INT is ENET_INT
--operation mode is input

ENET_INT = INPUT();


--AUD_ADCDAT is AUD_ADCDAT
--operation mode is input

AUD_ADCDAT = INPUT();


--TD_DATA[0] is TD_DATA[0]
--operation mode is input

TD_DATA[0] = INPUT();


--TD_DATA[1] is TD_DATA[1]
--operation mode is input

TD_DATA[1] = INPUT();


--TD_DATA[2] is TD_DATA[2]
--operation mode is input

TD_DATA[2] = INPUT();


--TD_DATA[3] is TD_DATA[3]
--operation mode is input

TD_DATA[3] = INPUT();


--TD_DATA[4] is TD_DATA[4]
--operation mode is input

TD_DATA[4] = INPUT();


--TD_DATA[5] is TD_DATA[5]
--operation mode is input

TD_DATA[5] = INPUT();


--TD_DATA[6] is TD_DATA[6]
--operation mode is input

TD_DATA[6] = INPUT();


--TD_DATA[7] is TD_DATA[7]
--operation mode is input

TD_DATA[7] = INPUT();


--TD_HS is TD_HS
--operation mode is input

TD_HS = INPUT();


--TD_VS is TD_VS
--operation mode is input

TD_VS = INPUT();


--SW[0] is SW[0]
--operation mode is input

SW[0] = INPUT();


--SW[1] is SW[1]
--operation mode is input

SW[1] = INPUT();


--SW[2] is SW[2]
--operation mode is input

SW[2] = INPUT();


--SW[3] is SW[3]
--operation mode is input

SW[3] = INPUT();


--SW[4] is SW[4]
--operation mode is input

SW[4] = INPUT();


--SW[5] is SW[5]
--operation mode is input

SW[5] = INPUT();


--SW[6] is SW[6]
--operation mode is input

SW[6] = INPUT();


--SW[7] is SW[7]
--operation mode is input

SW[7] = INPUT();


--SW[8] is SW[8]
--operation mode is input

SW[8] = INPUT();


--SW[9] is SW[9]
--operation mode is input

SW[9] = INPUT();


--SW[10] is SW[10]
--operation mode is input

SW[10] = INPUT();


--SW[11] is SW[11]
--operation mode is input

SW[11] = INPUT();


--SW[12] is SW[12]
--operation mode is input

SW[12] = INPUT();


--SW[13] is SW[13]
--operation mode is input

SW[13] = INPUT();


--SW[14] is SW[14]
--operation mode is input

SW[14] = INPUT();


--SW[15] is SW[15]
--operation mode is input

SW[15] = INPUT();


--SW[16] is SW[16]
--operation mode is input

SW[16] = INPUT();


--SW[17] is SW[17]
--operation mode is input

SW[17] = INPUT();


--CLOCK_50 is CLOCK_50
--operation mode is input

CLOCK_50 = INPUT();


--KEY[0] is KEY[0]
--operation mode is input

KEY[0] = INPUT();


--KEY[2] is KEY[2]
--operation mode is input

KEY[2] = INPUT();


--KEY[3] is KEY[3]
--operation mode is input

KEY[3] = INPUT();


--KEY[1] is KEY[1]
--operation mode is input

KEY[1] = INPUT();


--HEX0[0] is HEX0[0]
--operation mode is output

HEX0[0] = OUTPUT(Q1L1);


--HEX0[1] is HEX0[1]
--operation mode is output

HEX0[1] = OUTPUT(Q1L2);


--HEX0[2] is HEX0[2]
--operation mode is output

HEX0[2] = OUTPUT(Q1L3);


--HEX0[3] is HEX0[3]
--operation mode is output

HEX0[3] = OUTPUT(Q1L4);


--HEX0[4] is HEX0[4]
--operation mode is output

HEX0[4] = OUTPUT(Q1L5);


--HEX0[5] is HEX0[5]
--operation mode is output

HEX0[5] = OUTPUT(Q1L6);


--HEX0[6] is HEX0[6]
--operation mode is output

HEX0[6] = OUTPUT(!Q1L7);


--HEX1[0] is HEX1[0]
--operation mode is output

HEX1[0] = OUTPUT(Q2L1);


--HEX1[1] is HEX1[1]
--operation mode is output

HEX1[1] = OUTPUT(Q2L2);


--HEX1[2] is HEX1[2]
--operation mode is output

HEX1[2] = OUTPUT(Q2L3);


--HEX1[3] is HEX1[3]
--operation mode is output

HEX1[3] = OUTPUT(Q2L4);


--HEX1[4] is HEX1[4]
--operation mode is output

HEX1[4] = OUTPUT(Q2L5);


--HEX1[5] is HEX1[5]
--operation mode is output

HEX1[5] = OUTPUT(Q2L6);


--HEX1[6] is HEX1[6]
--operation mode is output

HEX1[6] = OUTPUT(!Q2L7);


--HEX2[0] is HEX2[0]
--operation mode is output

HEX2[0] = OUTPUT(Q3L1);


--HEX2[1] is HEX2[1]
--operation mode is output

HEX2[1] = OUTPUT(Q3L2);


--HEX2[2] is HEX2[2]
--operation mode is output

HEX2[2] = OUTPUT(Q3L3);


--HEX2[3] is HEX2[3]
--operation mode is output

HEX2[3] = OUTPUT(Q3L4);


--HEX2[4] is HEX2[4]
--operation mode is output

HEX2[4] = OUTPUT(Q3L5);


--HEX2[5] is HEX2[5]
--operation mode is output

HEX2[5] = OUTPUT(Q3L6);


--HEX2[6] is HEX2[6]
--operation mode is output

HEX2[6] = OUTPUT(!Q3L7);


--HEX3[0] is HEX3[0]
--operation mode is output

HEX3[0] = OUTPUT(Q4L1);


--HEX3[1] is HEX3[1]
--operation mode is output

HEX3[1] = OUTPUT(Q4L2);


--HEX3[2] is HEX3[2]
--operation mode is output

HEX3[2] = OUTPUT(Q4L3);


--HEX3[3] is HEX3[3]
--operation mode is output

HEX3[3] = OUTPUT(Q4L4);


--HEX3[4] is HEX3[4]
--operation mode is output

HEX3[4] = OUTPUT(Q4L5);


--HEX3[5] is HEX3[5]
--operation mode is output

HEX3[5] = OUTPUT(Q4L6);


--HEX3[6] is HEX3[6]
--operation mode is output

HEX3[6] = OUTPUT(!Q4L7);


--HEX4[0] is HEX4[0]
--operation mode is output

HEX4[0] = OUTPUT(Q5L1);


--HEX4[1] is HEX4[1]
--operation mode is output

HEX4[1] = OUTPUT(Q5L2);


--HEX4[2] is HEX4[2]
--operation mode is output

HEX4[2] = OUTPUT(Q5L3);


--HEX4[3] is HEX4[3]
--operation mode is output

HEX4[3] = OUTPUT(Q5L4);


--HEX4[4] is HEX4[4]
--operation mode is output

HEX4[4] = OUTPUT(Q5L5);


--HEX4[5] is HEX4[5]
--operation mode is output

HEX4[5] = OUTPUT(Q5L6);


--HEX4[6] is HEX4[6]
--operation mode is output

HEX4[6] = OUTPUT(!Q5L7);


--HEX5[0] is HEX5[0]
--operation mode is output

HEX5[0] = OUTPUT(Q6L1);


--HEX5[1] is HEX5[1]
--operation mode is output

HEX5[1] = OUTPUT(Q6L2);


--HEX5[2] is HEX5[2]
--operation mode is output

HEX5[2] = OUTPUT(Q6L3);


--HEX5[3] is HEX5[3]
--operation mode is output

HEX5[3] = OUTPUT(Q6L4);


--HEX5[4] is HEX5[4]
--operation mode is output

HEX5[4] = OUTPUT(Q6L5);


--HEX5[5] is HEX5[5]
--operation mode is output

HEX5[5] = OUTPUT(Q6L6);


--HEX5[6] is HEX5[6]
--operation mode is output

HEX5[6] = OUTPUT(!Q6L7);


--HEX6[0] is HEX6[0]
--operation mode is output

HEX6[0] = OUTPUT(Q7L1);


--HEX6[1] is HEX6[1]
--operation mode is output

HEX6[1] = OUTPUT(Q7L2);


--HEX6[2] is HEX6[2]
--operation mode is output

HEX6[2] = OUTPUT(Q7L3);


--HEX6[3] is HEX6[3]
--operation mode is output

HEX6[3] = OUTPUT(Q7L4);


--HEX6[4] is HEX6[4]
--operation mode is output

HEX6[4] = OUTPUT(Q7L5);


--HEX6[5] is HEX6[5]
--operation mode is output

HEX6[5] = OUTPUT(Q7L6);


--HEX6[6] is HEX6[6]
--operation mode is output

HEX6[6] = OUTPUT(!Q7L7);


--HEX7[0] is HEX7[0]
--operation mode is output

HEX7[0] = OUTPUT(Q8L1);


--HEX7[1] is HEX7[1]
--operation mode is output

HEX7[1] = OUTPUT(Q8L2);


--HEX7[2] is HEX7[2]
--operation mode is output

HEX7[2] = OUTPUT(Q8L3);


--HEX7[3] is HEX7[3]
--operation mode is output

HEX7[3] = OUTPUT(Q8L4);


--HEX7[4] is HEX7[4]
--operation mode is output

HEX7[4] = OUTPUT(Q8L5);


--HEX7[5] is HEX7[5]
--operation mode is output

HEX7[5] = OUTPUT(Q8L6);


--HEX7[6] is HEX7[6]
--operation mode is output

HEX7[6] = OUTPUT(!Q8L7);


--LEDG[0] is LEDG[0]
--operation mode is output

LEDG[0] = OUTPUT(D1_Y_Cont[0]);


--LEDG[1] is LEDG[1]
--operation mode is output

LEDG[1] = OUTPUT(D1_Y_Cont[1]);


--LEDG[2] is LEDG[2]
--operation mode is output

LEDG[2] = OUTPUT(D1_Y_Cont[2]);


--LEDG[3] is LEDG[3]
--operation mode is output

LEDG[3] = OUTPUT(D1_Y_Cont[3]);


--LEDG[4] is LEDG[4]
--operation mode is output

LEDG[4] = OUTPUT(D1_Y_Cont[4]);


--LEDG[5] is LEDG[5]
--operation mode is output

LEDG[5] = OUTPUT(D1_Y_Cont[5]);


--LEDG[6] is LEDG[6]
--operation mode is output

LEDG[6] = OUTPUT(D1_Y_Cont[6]);


--LEDG[7] is LEDG[7]
--operation mode is output

LEDG[7] = OUTPUT(D1_Y_Cont[7]);


--LEDG[8] is LEDG[8]
--operation mode is output

LEDG[8] = OUTPUT(D1_Y_Cont[8]);


--LEDR[0] is LEDR[0]
--operation mode is output

LEDR[0] = OUTPUT(SW[0]);


--LEDR[1] is LEDR[1]
--operation mode is output

LEDR[1] = OUTPUT(SW[1]);


--LEDR[2] is LEDR[2]
--operation mode is output

LEDR[2] = OUTPUT(SW[2]);


--LEDR[3] is LEDR[3]
--operation mode is output

LEDR[3] = OUTPUT(SW[3]);


--LEDR[4] is LEDR[4]
--operation mode is output

LEDR[4] = OUTPUT(SW[4]);


--LEDR[5] is LEDR[5]
--operation mode is output

LEDR[5] = OUTPUT(SW[5]);


--LEDR[6] is LEDR[6]
--operation mode is output

LEDR[6] = OUTPUT(SW[6]);


--LEDR[7] is LEDR[7]
--operation mode is output

LEDR[7] = OUTPUT(SW[7]);


--LEDR[8] is LEDR[8]
--operation mode is output

LEDR[8] = OUTPUT(SW[8]);


--LEDR[9] is LEDR[9]
--operation mode is output

LEDR[9] = OUTPUT(SW[9]);


--LEDR[10] is LEDR[10]
--operation mode is output

LEDR[10] = OUTPUT(SW[10]);


--LEDR[11] is LEDR[11]
--operation mode is output

LEDR[11] = OUTPUT(SW[11]);


--LEDR[12] is LEDR[12]
--operation mode is output

LEDR[12] = OUTPUT(SW[12]);


--LEDR[13] is LEDR[13]
--operation mode is output

LEDR[13] = OUTPUT(SW[13]);


--LEDR[14] is LEDR[14]
--operation mode is output

LEDR[14] = OUTPUT(SW[14]);


--LEDR[15] is LEDR[15]
--operation mode is output

LEDR[15] = OUTPUT(SW[15]);


--LEDR[16] is LEDR[16]
--operation mode is output

LEDR[16] = OUTPUT(SW[16]);


--LEDR[17] is LEDR[17]
--operation mode is output

LEDR[17] = OUTPUT(SW[17]);


--UART_TXD is UART_TXD
--operation mode is output

UART_TXD = OUTPUT(GND);


--IRDA_TXD is IRDA_TXD
--operation mode is output

IRDA_TXD = OUTPUT(GND);


--DRAM_ADDR[0] is DRAM_ADDR[0]
--operation mode is output

DRAM_ADDR[0] = OUTPUT(G1_SA[0]);


--DRAM_ADDR[1] is DRAM_ADDR[1]
--operation mode is output

DRAM_ADDR[1] = OUTPUT(G1_SA[1]);


--DRAM_ADDR[2] is DRAM_ADDR[2]
--operation mode is output

DRAM_ADDR[2] = OUTPUT(G1_SA[2]);


--DRAM_ADDR[3] is DRAM_ADDR[3]
--operation mode is output

DRAM_ADDR[3] = OUTPUT(G1_SA[3]);


--DRAM_ADDR[4] is DRAM_ADDR[4]
--operation mode is output

DRAM_ADDR[4] = OUTPUT(G1_SA[4]);


--DRAM_ADDR[5] is DRAM_ADDR[5]
--operation mode is output

DRAM_ADDR[5] = OUTPUT(G1_SA[5]);


--DRAM_ADDR[6] is DRAM_ADDR[6]
--operation mode is output

DRAM_ADDR[6] = OUTPUT(G1_SA[6]);


--DRAM_ADDR[7] is DRAM_ADDR[7]
--operation mode is output

DRAM_ADDR[7] = OUTPUT(G1_SA[7]);


--DRAM_ADDR[8] is DRAM_ADDR[8]
--operation mode is output

DRAM_ADDR[8] = OUTPUT(G1_SA[8]);


--DRAM_ADDR[9] is DRAM_ADDR[9]
--operation mode is output

DRAM_ADDR[9] = OUTPUT(G1_SA[9]);


--DRAM_ADDR[10] is DRAM_ADDR[10]
--operation mode is output

DRAM_ADDR[10] = OUTPUT(G1_SA[10]);


--DRAM_ADDR[11] is DRAM_ADDR[11]
--operation mode is output

DRAM_ADDR[11] = OUTPUT(G1_SA[11]);


--DRAM_LDQM is DRAM_LDQM
--operation mode is output

DRAM_LDQM = OUTPUT(G1_DQM[1]);


--DRAM_UDQM is DRAM_UDQM
--operation mode is output

DRAM_UDQM = OUTPUT(G1_DQM[1]);


--DRAM_WE_N is DRAM_WE_N
--operation mode is output

DRAM_WE_N = OUTPUT(G1_WE_N);


--DRAM_CAS_N is DRAM_CAS_N
--operation mode is output

DRAM_CAS_N = OUTPUT(G1_CAS_N);


--DRAM_RAS_N is DRAM_RAS_N
--operation mode is output

DRAM_RAS_N = OUTPUT(G1_RAS_N);


--DRAM_CS_N is DRAM_CS_N
--operation mode is output

DRAM_CS_N = OUTPUT(G1_CS_N[0]);


--DRAM_BA_0 is DRAM_BA_0
--operation mode is output

DRAM_BA_0 = OUTPUT(G1_BA[0]);


--DRAM_BA_1 is DRAM_BA_1
--operation mode is output

DRAM_BA_1 = OUTPUT(G1_BA[1]);


--DRAM_CLK is DRAM_CLK
--operation mode is output

DRAM_CLK = OUTPUT(KB1__clk1);


--DRAM_CKE is DRAM_CKE
--operation mode is output

DRAM_CKE = OUTPUT(VCC);


--FL_ADDR[0] is FL_ADDR[0]
--operation mode is output

FL_ADDR[0] = OUTPUT(GND);


--FL_ADDR[1] is FL_ADDR[1]
--operation mode is output

FL_ADDR[1] = OUTPUT(GND);


--FL_ADDR[2] is FL_ADDR[2]
--operation mode is output

FL_ADDR[2] = OUTPUT(GND);


--FL_ADDR[3] is FL_ADDR[3]
--operation mode is output

FL_ADDR[3] = OUTPUT(GND);


--FL_ADDR[4] is FL_ADDR[4]
--operation mode is output

FL_ADDR[4] = OUTPUT(GND);


--FL_ADDR[5] is FL_ADDR[5]
--operation mode is output

FL_ADDR[5] = OUTPUT(GND);


--FL_ADDR[6] is FL_ADDR[6]
--operation mode is output

FL_ADDR[6] = OUTPUT(GND);


--FL_ADDR[7] is FL_ADDR[7]
--operation mode is output

FL_ADDR[7] = OUTPUT(GND);


--FL_ADDR[8] is FL_ADDR[8]
--operation mode is output

FL_ADDR[8] = OUTPUT(GND);


--FL_ADDR[9] is FL_ADDR[9]
--operation mode is output

FL_ADDR[9] = OUTPUT(GND);


--FL_ADDR[10] is FL_ADDR[10]
--operation mode is output

FL_ADDR[10] = OUTPUT(GND);


--FL_ADDR[11] is FL_ADDR[11]
--operation mode is output

FL_ADDR[11] = OUTPUT(GND);


--FL_ADDR[12] is FL_ADDR[12]
--operation mode is output

FL_ADDR[12] = OUTPUT(GND);


--FL_ADDR[13] is FL_ADDR[13]
--operation mode is output

FL_ADDR[13] = OUTPUT(GND);


--FL_ADDR[14] is FL_ADDR[14]
--operation mode is output

FL_ADDR[14] = OUTPUT(GND);


--FL_ADDR[15] is FL_ADDR[15]
--operation mode is output

FL_ADDR[15] = OUTPUT(GND);


--FL_ADDR[16] is FL_ADDR[16]
--operation mode is output

FL_ADDR[16] = OUTPUT(GND);


--FL_ADDR[17] is FL_ADDR[17]
--operation mode is output

FL_ADDR[17] = OUTPUT(GND);


--FL_ADDR[18] is FL_ADDR[18]
--operation mode is output

FL_ADDR[18] = OUTPUT(GND);


--FL_ADDR[19] is FL_ADDR[19]
--operation mode is output

FL_ADDR[19] = OUTPUT(GND);


--FL_ADDR[20] is FL_ADDR[20]
--operation mode is output

FL_ADDR[20] = OUTPUT(GND);


--FL_ADDR[21] is FL_ADDR[21]
--operation mode is output

FL_ADDR[21] = OUTPUT(GND);


--FL_WE_N is FL_WE_N
--operation mode is output

FL_WE_N = OUTPUT(GND);


--FL_RST_N is FL_RST_N
--operation mode is output

FL_RST_N = OUTPUT(GND);


--FL_OE_N is FL_OE_N
--operation mode is output

FL_OE_N = OUTPUT(GND);


--FL_CE_N is FL_CE_N
--operation mode is output

FL_CE_N = OUTPUT(GND);


--SRAM_ADDR[0] is SRAM_ADDR[0]
--operation mode is output

SRAM_ADDR[0] = OUTPUT(GND);


--SRAM_ADDR[1] is SRAM_ADDR[1]
--operation mode is output

SRAM_ADDR[1] = OUTPUT(GND);


--SRAM_ADDR[2] is SRAM_ADDR[2]
--operation mode is output

SRAM_ADDR[2] = OUTPUT(GND);


--SRAM_ADDR[3] is SRAM_ADDR[3]
--operation mode is output

SRAM_ADDR[3] = OUTPUT(GND);


--SRAM_ADDR[4] is SRAM_ADDR[4]
--operation mode is output

SRAM_ADDR[4] = OUTPUT(GND);


--SRAM_ADDR[5] is SRAM_ADDR[5]
--operation mode is output

SRAM_ADDR[5] = OUTPUT(GND);


--SRAM_ADDR[6] is SRAM_ADDR[6]
--operation mode is output

SRAM_ADDR[6] = OUTPUT(GND);


--SRAM_ADDR[7] is SRAM_ADDR[7]
--operation mode is output

SRAM_ADDR[7] = OUTPUT(GND);


--SRAM_ADDR[8] is SRAM_ADDR[8]
--operation mode is output

SRAM_ADDR[8] = OUTPUT(GND);


--SRAM_ADDR[9] is SRAM_ADDR[9]
--operation mode is output

SRAM_ADDR[9] = OUTPUT(GND);


--SRAM_ADDR[10] is SRAM_ADDR[10]
--operation mode is output

SRAM_ADDR[10] = OUTPUT(GND);


--SRAM_ADDR[11] is SRAM_ADDR[11]
--operation mode is output

SRAM_ADDR[11] = OUTPUT(GND);


--SRAM_ADDR[12] is SRAM_ADDR[12]
--operation mode is output

SRAM_ADDR[12] = OUTPUT(GND);


--SRAM_ADDR[13] is SRAM_ADDR[13]
--operation mode is output

SRAM_ADDR[13] = OUTPUT(GND);


--SRAM_ADDR[14] is SRAM_ADDR[14]
--operation mode is output

SRAM_ADDR[14] = OUTPUT(GND);


--SRAM_ADDR[15] is SRAM_ADDR[15]
--operation mode is output

SRAM_ADDR[15] = OUTPUT(GND);


--SRAM_ADDR[16] is SRAM_ADDR[16]
--operation mode is output

SRAM_ADDR[16] = OUTPUT(GND);


--SRAM_ADDR[17] is SRAM_ADDR[17]
--operation mode is output

SRAM_ADDR[17] = OUTPUT(GND);


--SRAM_UB_N is SRAM_UB_N
--operation mode is output

SRAM_UB_N = OUTPUT(GND);


--SRAM_LB_N is SRAM_LB_N
--operation mode is output

SRAM_LB_N = OUTPUT(GND);


--SRAM_WE_N is SRAM_WE_N
--operation mode is output

SRAM_WE_N = OUTPUT(GND);


--SRAM_CE_N is SRAM_CE_N
--operation mode is output

SRAM_CE_N = OUTPUT(GND);


--SRAM_OE_N is SRAM_OE_N
--operation mode is output

SRAM_OE_N = OUTPUT(GND);


--OTG_ADDR[0] is OTG_ADDR[0]
--operation mode is output

OTG_ADDR[0] = OUTPUT(GND);


--OTG_ADDR[1] is OTG_ADDR[1]
--operation mode is output

OTG_ADDR[1] = OUTPUT(GND);


--OTG_CS_N is OTG_CS_N
--operation mode is output

OTG_CS_N = OUTPUT(GND);


--OTG_RD_N is OTG_RD_N
--operation mode is output

OTG_RD_N = OUTPUT(GND);


--OTG_WR_N is OTG_WR_N
--operation mode is output

OTG_WR_N = OUTPUT(GND);


--OTG_RST_N is OTG_RST_N
--operation mode is output

OTG_RST_N = OUTPUT(GND);


--OTG_FSPEED is OTG_FSPEED
--operation mode is output

OTG_FSPEED = OUTPUT(GND);


--OTG_LSPEED is OTG_LSPEED
--operation mode is output

OTG_LSPEED = OUTPUT(GND);


--OTG_DACK0_N is OTG_DACK0_N
--operation mode is output

OTG_DACK0_N = OUTPUT(GND);


--OTG_DACK1_N is OTG_DACK1_N
--operation mode is output

OTG_DACK1_N = OUTPUT(GND);


--LCD_ON is LCD_ON
--operation mode is output

LCD_ON = OUTPUT(VCC);


--LCD_BLON is LCD_BLON
--operation mode is output

LCD_BLON = OUTPUT(VCC);


--LCD_RW is LCD_RW
--operation mode is output

LCD_RW = OUTPUT(GND);


--LCD_EN is LCD_EN
--operation mode is output

LCD_EN = OUTPUT(GND);


--LCD_RS is LCD_RS
--operation mode is output

LCD_RS = OUTPUT(GND);


--SD_CLK is SD_CLK
--operation mode is output

SD_CLK = OUTPUT(GND);


--TDO is TDO
--operation mode is output

TDO = OUTPUT(GND);


--I2C_SCLK is I2C_SCLK
--operation mode is output

I2C_SCLK = OUTPUT(GND);


--VGA_CLK is VGA_CLK
--operation mode is output

VGA_CLK = OUTPUT(!CCD_MCLK);


--VGA_HS is VGA_HS
--operation mode is output

VGA_HS = OUTPUT(B1_oVGA_H_SYNC);


--VGA_VS is VGA_VS
--operation mode is output

VGA_VS = OUTPUT(B1_oVGA_V_SYNC);


--VGA_BLANK is VGA_BLANK
--operation mode is output

VGA_BLANK = OUTPUT(B1_oVGA_BLANK);


--VGA_SYNC is VGA_SYNC
--operation mode is output

VGA_SYNC = OUTPUT(GND);


--VGA_R[0] is VGA_R[0]
--operation mode is output

VGA_R[0] = OUTPUT(B1L104);


--VGA_R[1] is VGA_R[1]
--operation mode is output

VGA_R[1] = OUTPUT(B1L105);


--VGA_R[2] is VGA_R[2]
--operation mode is output

VGA_R[2] = OUTPUT(B1L106);


--VGA_R[3] is VGA_R[3]
--operation mode is output

VGA_R[3] = OUTPUT(B1L107);


--VGA_R[4] is VGA_R[4]
--operation mode is output

VGA_R[4] = OUTPUT(B1L108);


--VGA_R[5] is VGA_R[5]
--operation mode is output

VGA_R[5] = OUTPUT(B1L109);


--VGA_R[6] is VGA_R[6]
--operation mode is output

VGA_R[6] = OUTPUT(B1L110);


--VGA_R[7] is VGA_R[7]
--operation mode is output

VGA_R[7] = OUTPUT(B1L111);


--VGA_R[8] is VGA_R[8]
--operation mode is output

VGA_R[8] = OUTPUT(B1L112);


--VGA_R[9] is VGA_R[9]
--operation mode is output

VGA_R[9] = OUTPUT(B1L113);


--VGA_G[0] is VGA_G[0]
--operation mode is output

VGA_G[0] = OUTPUT(B1L93);


--VGA_G[1] is VGA_G[1]
--operation mode is output

VGA_G[1] = OUTPUT(B1L94);


--VGA_G[2] is VGA_G[2]
--operation mode is output

VGA_G[2] = OUTPUT(B1L95);


--VGA_G[3] is VGA_G[3]
--operation mode is output

VGA_G[3] = OUTPUT(B1L96);


--VGA_G[4] is VGA_G[4]
--operation mode is output

VGA_G[4] = OUTPUT(B1L97);


--VGA_G[5] is VGA_G[5]
--operation mode is output

VGA_G[5] = OUTPUT(B1L98);


--VGA_G[6] is VGA_G[6]
--operation mode is output

VGA_G[6] = OUTPUT(B1L99);


--VGA_G[7] is VGA_G[7]
--operation mode is output

VGA_G[7] = OUTPUT(B1L100);


--VGA_G[8] is VGA_G[8]
--operation mode is output

VGA_G[8] = OUTPUT(B1L101);


--VGA_G[9] is VGA_G[9]
--operation mode is output

VGA_G[9] = OUTPUT(B1L102);


--VGA_B[0] is VGA_B[0]
--operation mode is output

VGA_B[0] = OUTPUT(B1L83);


--VGA_B[1] is VGA_B[1]
--operation mode is output

VGA_B[1] = OUTPUT(B1L84);


--VGA_B[2] is VGA_B[2]
--operation mode is output

VGA_B[2] = OUTPUT(B1L85);


--VGA_B[3] is VGA_B[3]
--operation mode is output

VGA_B[3] = OUTPUT(B1L86);


--VGA_B[4] is VGA_B[4]
--operation mode is output

VGA_B[4] = OUTPUT(B1L87);


--VGA_B[5] is VGA_B[5]
--operation mode is output

VGA_B[5] = OUTPUT(B1L88);


--VGA_B[6] is VGA_B[6]
--operation mode is output

VGA_B[6] = OUTPUT(B1L89);


--VGA_B[7] is VGA_B[7]
--operation mode is output

VGA_B[7] = OUTPUT(B1L90);


--VGA_B[8] is VGA_B[8]
--operation mode is output

VGA_B[8] = OUTPUT(B1L91);


--VGA_B[9] is VGA_B[9]
--operation mode is output

VGA_B[9] = OUTPUT(B1L92);


--ENET_CMD is ENET_CMD
--operation mode is output

ENET_CMD = OUTPUT(GND);


--ENET_CS_N is ENET_CS_N
--operation mode is output

ENET_CS_N = OUTPUT(GND);


--ENET_WR_N is ENET_WR_N
--operation mode is output

ENET_WR_N = OUTPUT(GND);


--ENET_RD_N is ENET_RD_N
--operation mode is output

ENET_RD_N = OUTPUT(GND);


--ENET_RST_N is ENET_RST_N
--operation mode is output

ENET_RST_N = OUTPUT(GND);


--ENET_CLK is ENET_CLK
--operation mode is output

ENET_CLK = OUTPUT(GND);


--AUD_DACDAT is AUD_DACDAT
--operation mode is output

AUD_DACDAT = OUTPUT(GND);


--AUD_XCK is AUD_XCK
--operation mode is output

AUD_XCK = OUTPUT(GND);


--TD_RESET is TD_RESET
--operation mode is output

TD_RESET = OUTPUT(VCC);


--SD_DAT3 is SD_DAT3
--operation mode is bidir

SD_DAT3 = BIDIR(OPNDRN(VCC));


--SD_CMD is SD_CMD
--operation mode is bidir

SD_CMD = BIDIR(OPNDRN(VCC));


--GPIO_0[0] is GPIO_0[0]
--operation mode is bidir

GPIO_0[0] = BIDIR(OPNDRN(VCC));


--GPIO_0[1] is GPIO_0[1]
--operation mode is bidir

GPIO_0[1] = BIDIR(OPNDRN(VCC));


--GPIO_0[2] is GPIO_0[2]
--operation mode is bidir

GPIO_0[2] = BIDIR(OPNDRN(VCC));


--GPIO_0[3] is GPIO_0[3]
--operation mode is bidir

GPIO_0[3] = BIDIR(OPNDRN(VCC));


--GPIO_0[4] is GPIO_0[4]
--operation mode is bidir

GPIO_0[4] = BIDIR(OPNDRN(VCC));


--GPIO_0[5] is GPIO_0[5]
--operation mode is bidir

GPIO_0[5] = BIDIR(OPNDRN(VCC));


--GPIO_0[6] is GPIO_0[6]
--operation mode is bidir

GPIO_0[6] = BIDIR(OPNDRN(VCC));


--GPIO_0[7] is GPIO_0[7]
--operation mode is bidir

GPIO_0[7] = BIDIR(OPNDRN(VCC));


--GPIO_0[8] is GPIO_0[8]
--operation mode is bidir

GPIO_0[8] = BIDIR(OPNDRN(VCC));


--GPIO_0[9] is GPIO_0[9]
--operation mode is bidir

GPIO_0[9] = BIDIR(OPNDRN(VCC));


--GPIO_0[10] is GPIO_0[10]
--operation mode is bidir

GPIO_0[10] = BIDIR(OPNDRN(VCC));


--GPIO_0[11] is GPIO_0[11]
--operation mode is bidir

GPIO_0[11] = BIDIR(OPNDRN(VCC));


--GPIO_0[12] is GPIO_0[12]
--operation mode is bidir

GPIO_0[12] = BIDIR(OPNDRN(VCC));


--GPIO_0[13] is GPIO_0[13]
--operation mode is bidir

GPIO_0[13] = BIDIR(OPNDRN(VCC));


--GPIO_0[14] is GPIO_0[14]
--operation mode is bidir

GPIO_0[14] = BIDIR(OPNDRN(VCC));


--GPIO_0[15] is GPIO_0[15]
--operation mode is bidir

GPIO_0[15] = BIDIR(OPNDRN(VCC));


--GPIO_0[16] is GPIO_0[16]
--operation mode is bidir

GPIO_0[16] = BIDIR(OPNDRN(VCC));


--GPIO_0[17] is GPIO_0[17]
--operation mode is bidir

GPIO_0[17] = BIDIR(OPNDRN(VCC));


--GPIO_0[18] is GPIO_0[18]
--operation mode is bidir

GPIO_0[18] = BIDIR(OPNDRN(VCC));


--GPIO_0[19] is GPIO_0[19]
--operation mode is bidir

GPIO_0[19] = BIDIR(OPNDRN(VCC));


--GPIO_0[20] is GPIO_0[20]
--operation mode is bidir

GPIO_0[20] = BIDIR(OPNDRN(VCC));


--GPIO_0[21] is GPIO_0[21]
--operation mode is bidir

GPIO_0[21] = BIDIR(OPNDRN(VCC));


--GPIO_0[22] is GPIO_0[22]
--operation mode is bidir

GPIO_0[22] = BIDIR(OPNDRN(VCC));


--GPIO_0[23] is GPIO_0[23]
--operation mode is bidir

GPIO_0[23] = BIDIR(OPNDRN(VCC));


--GPIO_0[24] is GPIO_0[24]
--operation mode is bidir

GPIO_0[24] = BIDIR(OPNDRN(VCC));


--GPIO_0[25] is GPIO_0[25]
--operation mode is bidir

GPIO_0[25] = BIDIR(OPNDRN(VCC));


--GPIO_0[26] is GPIO_0[26]
--operation mode is bidir

GPIO_0[26] = BIDIR(OPNDRN(VCC));


--GPIO_0[27] is GPIO_0[27]
--operation mode is bidir

GPIO_0[27] = BIDIR(OPNDRN(VCC));


--GPIO_0[28] is GPIO_0[28]
--operation mode is bidir

GPIO_0[28] = BIDIR(OPNDRN(VCC));


--GPIO_0[29] is GPIO_0[29]
--operation mode is bidir

GPIO_0[29] = BIDIR(OPNDRN(VCC));


--GPIO_0[30] is GPIO_0[30]
--operation mode is bidir

GPIO_0[30] = BIDIR(OPNDRN(VCC));


--GPIO_0[31] is GPIO_0[31]
--operation mode is bidir

GPIO_0[31] = BIDIR(OPNDRN(VCC));


--GPIO_0[32] is GPIO_0[32]
--operation mode is bidir

GPIO_0[32] = BIDIR(OPNDRN(VCC));


--GPIO_0[33] is GPIO_0[33]
--operation mode is bidir

GPIO_0[33] = BIDIR(OPNDRN(VCC));


--GPIO_0[34] is GPIO_0[34]
--operation mode is bidir

GPIO_0[34] = BIDIR(OPNDRN(VCC));


--GPIO_0[35] is GPIO_0[35]
--operation mode is bidir

GPIO_0[35] = BIDIR(OPNDRN(VCC));


--GPIO_1[16] is GPIO_1[16]
--operation mode is bidir

GPIO_1[16] = BIDIR(OPNDRN(VCC));


--GPIO_1[17] is GPIO_1[17]
--operation mode is bidir

GPIO_1[17] = BIDIR(OPNDRN(VCC));


--GPIO_1[18] is GPIO_1[18]
--operation mode is bidir

GPIO_1[18] = BIDIR(OPNDRN(VCC));


--GPIO_1[19] is GPIO_1[19]
--operation mode is bidir

GPIO_1[19] = BIDIR(OPNDRN(VCC));


--GPIO_1[20] is GPIO_1[20]
--operation mode is bidir

GPIO_1[20] = BIDIR(OPNDRN(VCC));


--GPIO_1[21] is GPIO_1[21]
--operation mode is bidir

GPIO_1[21] = BIDIR(OPNDRN(VCC));


--GPIO_1[22] is GPIO_1[22]
--operation mode is bidir

GPIO_1[22] = BIDIR(OPNDRN(VCC));


--GPIO_1[23] is GPIO_1[23]
--operation mode is bidir

GPIO_1[23] = BIDIR(OPNDRN(VCC));


--GPIO_1[24] is GPIO_1[24]
--operation mode is bidir

GPIO_1[24] = BIDIR(OPNDRN(VCC));


--GPIO_1[25] is GPIO_1[25]
--operation mode is bidir

GPIO_1[25] = BIDIR(OPNDRN(VCC));


--GPIO_1[26] is GPIO_1[26]
--operation mode is bidir

GPIO_1[26] = BIDIR(OPNDRN(VCC));


--GPIO_1[27] is GPIO_1[27]
--operation mode is bidir

GPIO_1[27] = BIDIR(OPNDRN(VCC));


--GPIO_1[28] is GPIO_1[28]
--operation mode is bidir

GPIO_1[28] = BIDIR(OPNDRN(VCC));


--GPIO_1[29] is GPIO_1[29]
--operation mode is bidir

GPIO_1[29] = BIDIR(OPNDRN(VCC));


--GPIO_1[30] is GPIO_1[30]
--operation mode is bidir

GPIO_1[30] = BIDIR(OPNDRN(VCC));


--GPIO_1[31] is GPIO_1[31]
--operation mode is bidir

GPIO_1[31] = BIDIR(OPNDRN(VCC));


--GPIO_1[32] is GPIO_1[32]
--operation mode is bidir

GPIO_1[32] = BIDIR(OPNDRN(VCC));


--GPIO_1[33] is GPIO_1[33]
--operation mode is bidir

GPIO_1[33] = BIDIR(OPNDRN(VCC));


--GPIO_1[34] is GPIO_1[34]
--operation mode is bidir

GPIO_1[34] = BIDIR(OPNDRN(VCC));


--GPIO_1[35] is GPIO_1[35]
--operation mode is bidir

GPIO_1[35] = BIDIR(OPNDRN(VCC));


--A1L34 is DRAM_DQ[0]~15
--operation mode is bidir

A1L34 = DRAM_DQ[0];

--DRAM_DQ[0] is DRAM_DQ[0]
--operation mode is bidir

DRAM_DQ[0]_tri_out = TRI(G1L220, R1_OE);
DRAM_DQ[0] = BIDIR(DRAM_DQ[0]_tri_out);


--A1L36 is DRAM_DQ[1]~14
--operation mode is bidir

A1L36 = DRAM_DQ[1];

--DRAM_DQ[1] is DRAM_DQ[1]
--operation mode is bidir

DRAM_DQ[1]_tri_out = TRI(G1L221, R1_OE);
DRAM_DQ[1] = BIDIR(DRAM_DQ[1]_tri_out);


--A1L38 is DRAM_DQ[2]~13
--operation mode is bidir

A1L38 = DRAM_DQ[2];

--DRAM_DQ[2] is DRAM_DQ[2]
--operation mode is bidir

DRAM_DQ[2]_tri_out = TRI(G1L222, R1_OE);
DRAM_DQ[2] = BIDIR(DRAM_DQ[2]_tri_out);


--A1L40 is DRAM_DQ[3]~12
--operation mode is bidir

A1L40 = DRAM_DQ[3];

--DRAM_DQ[3] is DRAM_DQ[3]
--operation mode is bidir

DRAM_DQ[3]_tri_out = TRI(G1L223, R1_OE);
DRAM_DQ[3] = BIDIR(DRAM_DQ[3]_tri_out);


--A1L42 is DRAM_DQ[4]~11
--operation mode is bidir

A1L42 = DRAM_DQ[4];

--DRAM_DQ[4] is DRAM_DQ[4]
--operation mode is bidir

DRAM_DQ[4]_tri_out = TRI(G1L224, R1_OE);
DRAM_DQ[4] = BIDIR(DRAM_DQ[4]_tri_out);


--A1L44 is DRAM_DQ[5]~10
--operation mode is bidir

A1L44 = DRAM_DQ[5];

--DRAM_DQ[5] is DRAM_DQ[5]
--operation mode is bidir

DRAM_DQ[5]_tri_out = TRI(G1L225, R1_OE);
DRAM_DQ[5] = BIDIR(DRAM_DQ[5]_tri_out);


--A1L46 is DRAM_DQ[6]~9
--operation mode is bidir

A1L46 = DRAM_DQ[6];

--DRAM_DQ[6] is DRAM_DQ[6]
--operation mode is bidir

DRAM_DQ[6]_tri_out = TRI(G1L226, R1_OE);
DRAM_DQ[6] = BIDIR(DRAM_DQ[6]_tri_out);


--A1L48 is DRAM_DQ[7]~8
--operation mode is bidir

A1L48 = DRAM_DQ[7];

--DRAM_DQ[7] is DRAM_DQ[7]
--operation mode is bidir

DRAM_DQ[7]_tri_out = TRI(G1L227, R1_OE);
DRAM_DQ[7] = BIDIR(DRAM_DQ[7]_tri_out);


--A1L50 is DRAM_DQ[8]~7
--operation mode is bidir

A1L50 = DRAM_DQ[8];

--DRAM_DQ[8] is DRAM_DQ[8]
--operation mode is bidir

DRAM_DQ[8]_tri_out = TRI(G1L228, R1_OE);
DRAM_DQ[8] = BIDIR(DRAM_DQ[8]_tri_out);


--A1L52 is DRAM_DQ[9]~6
--operation mode is bidir

A1L52 = DRAM_DQ[9];

--DRAM_DQ[9] is DRAM_DQ[9]
--operation mode is bidir

DRAM_DQ[9]_tri_out = TRI(G1L229, R1_OE);
DRAM_DQ[9] = BIDIR(DRAM_DQ[9]_tri_out);


--A1L54 is DRAM_DQ[10]~5
--operation mode is bidir

A1L54 = DRAM_DQ[10];

--DRAM_DQ[10] is DRAM_DQ[10]
--operation mode is bidir

DRAM_DQ[10]_tri_out = TRI(G1L230, R1_OE);
DRAM_DQ[10] = BIDIR(DRAM_DQ[10]_tri_out);


--A1L56 is DRAM_DQ[11]~4
--operation mode is bidir

A1L56 = DRAM_DQ[11];

--DRAM_DQ[11] is DRAM_DQ[11]
--operation mode is bidir

DRAM_DQ[11]_tri_out = TRI(G1L231, R1_OE);
DRAM_DQ[11] = BIDIR(DRAM_DQ[11]_tri_out);


--A1L58 is DRAM_DQ[12]~3
--operation mode is bidir

A1L58 = DRAM_DQ[12];

--DRAM_DQ[12] is DRAM_DQ[12]
--operation mode is bidir

DRAM_DQ[12]_tri_out = TRI(G1L232, R1_OE);
DRAM_DQ[12] = BIDIR(DRAM_DQ[12]_tri_out);


--A1L60 is DRAM_DQ[13]~2
--operation mode is bidir

A1L60 = DRAM_DQ[13];

--DRAM_DQ[13] is DRAM_DQ[13]
--operation mode is bidir

DRAM_DQ[13]_tri_out = TRI(G1L233, R1_OE);
DRAM_DQ[13] = BIDIR(DRAM_DQ[13]_tri_out);


--A1L62 is DRAM_DQ[14]~1
--operation mode is bidir

A1L62 = DRAM_DQ[14];

--DRAM_DQ[14] is DRAM_DQ[14]
--operation mode is bidir

DRAM_DQ[14]_tri_out = TRI(G1L234, R1_OE);
DRAM_DQ[14] = BIDIR(DRAM_DQ[14]_tri_out);


--DRAM_DQ[15] is DRAM_DQ[15]
--operation mode is bidir

DRAM_DQ[15]_tri_out = TRI(G1L235, R1_OE);
DRAM_DQ[15] = BIDIR(DRAM_DQ[15]_tri_out);


--FL_DQ[0] is FL_DQ[0]
--operation mode is bidir

FL_DQ[0] = BIDIR(OPNDRN(VCC));


--FL_DQ[1] is FL_DQ[1]
--operation mode is bidir

FL_DQ[1] = BIDIR(OPNDRN(VCC));


--FL_DQ[2] is FL_DQ[2]
--operation mode is bidir

FL_DQ[2] = BIDIR(OPNDRN(VCC));


--FL_DQ[3] is FL_DQ[3]
--operation mode is bidir

FL_DQ[3] = BIDIR(OPNDRN(VCC));


--FL_DQ[4] is FL_DQ[4]
--operation mode is bidir

FL_DQ[4] = BIDIR(OPNDRN(VCC));


--FL_DQ[5] is FL_DQ[5]
--operation mode is bidir

FL_DQ[5] = BIDIR(OPNDRN(VCC));


--FL_DQ[6] is FL_DQ[6]
--operation mode is bidir

FL_DQ[6] = BIDIR(OPNDRN(VCC));


--FL_DQ[7] is FL_DQ[7]
--operation mode is bidir

FL_DQ[7] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[0] is SRAM_DQ[0]
--operation mode is bidir

SRAM_DQ[0] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[1] is SRAM_DQ[1]
--operation mode is bidir

SRAM_DQ[1] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[2] is SRAM_DQ[2]
--operation mode is bidir

SRAM_DQ[2] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[3] is SRAM_DQ[3]
--operation mode is bidir

SRAM_DQ[3] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[4] is SRAM_DQ[4]
--operation mode is bidir

SRAM_DQ[4] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[5] is SRAM_DQ[5]
--operation mode is bidir

SRAM_DQ[5] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[6] is SRAM_DQ[6]
--operation mode is bidir

SRAM_DQ[6] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[7] is SRAM_DQ[7]
--operation mode is bidir

SRAM_DQ[7] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[8] is SRAM_DQ[8]
--operation mode is bidir

SRAM_DQ[8] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[9] is SRAM_DQ[9]
--operation mode is bidir

SRAM_DQ[9] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[10] is SRAM_DQ[10]
--operation mode is bidir

SRAM_DQ[10] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[11] is SRAM_DQ[11]
--operation mode is bidir

SRAM_DQ[11] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[12] is SRAM_DQ[12]
--operation mode is bidir

SRAM_DQ[12] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[13] is SRAM_DQ[13]
--operation mode is bidir

SRAM_DQ[13] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[14] is SRAM_DQ[14]
--operation mode is bidir

SRAM_DQ[14] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[15] is SRAM_DQ[15]
--operation mode is bidir

SRAM_DQ[15] = BIDIR(OPNDRN(VCC));


--OTG_DATA[0] is OTG_DATA[0]
--operation mode is bidir

OTG_DATA[0] = BIDIR(OPNDRN(VCC));


--OTG_DATA[1] is OTG_DATA[1]
--operation mode is bidir

OTG_DATA[1] = BIDIR(OPNDRN(VCC));


--OTG_DATA[2] is OTG_DATA[2]
--operation mode is bidir

OTG_DATA[2] = BIDIR(OPNDRN(VCC));


--OTG_DATA[3] is OTG_DATA[3]
--operation mode is bidir

OTG_DATA[3] = BIDIR(OPNDRN(VCC));


--OTG_DATA[4] is OTG_DATA[4]
--operation mode is bidir

OTG_DATA[4] = BIDIR(OPNDRN(VCC));


--OTG_DATA[5] is OTG_DATA[5]
--operation mode is bidir

OTG_DATA[5] = BIDIR(OPNDRN(VCC));


--OTG_DATA[6] is OTG_DATA[6]
--operation mode is bidir

OTG_DATA[6] = BIDIR(OPNDRN(VCC));


--OTG_DATA[7] is OTG_DATA[7]
--operation mode is bidir

OTG_DATA[7] = BIDIR(OPNDRN(VCC));


--OTG_DATA[8] is OTG_DATA[8]
--operation mode is bidir

OTG_DATA[8] = BIDIR(OPNDRN(VCC));


--OTG_DATA[9] is OTG_DATA[9]
--operation mode is bidir

OTG_DATA[9] = BIDIR(OPNDRN(VCC));


--OTG_DATA[10] is OTG_DATA[10]
--operation mode is bidir

OTG_DATA[10] = BIDIR(OPNDRN(VCC));


--OTG_DATA[11] is OTG_DATA[11]
--operation mode is bidir

OTG_DATA[11] = BIDIR(OPNDRN(VCC));


--OTG_DATA[12] is OTG_DATA[12]
--operation mode is bidir

OTG_DATA[12] = BIDIR(OPNDRN(VCC));


--OTG_DATA[13] is OTG_DATA[13]
--operation mode is bidir

OTG_DATA[13] = BIDIR(OPNDRN(VCC));


--OTG_DATA[14] is OTG_DATA[14]
--operation mode is bidir

OTG_DATA[14] = BIDIR(OPNDRN(VCC));


--OTG_DATA[15] is OTG_DATA[15]
--operation mode is bidir

OTG_DATA[15] = BIDIR(OPNDRN(VCC));


--LCD_DATA[0] is LCD_DATA[0]
--operation mode is bidir

LCD_DATA[0] = BIDIR(OPNDRN(VCC));


--LCD_DATA[1] is LCD_DATA[1]
--operation mode is bidir

LCD_DATA[1] = BIDIR(OPNDRN(VCC));


--LCD_DATA[2] is LCD_DATA[2]
--operation mode is bidir

LCD_DATA[2] = BIDIR(OPNDRN(VCC));


--LCD_DATA[3] is LCD_DATA[3]
--operation mode is bidir

LCD_DATA[3] = BIDIR(OPNDRN(VCC));


--LCD_DATA[4] is LCD_DATA[4]
--operation mode is bidir

LCD_DATA[4] = BIDIR(OPNDRN(VCC));


--LCD_DATA[5] is LCD_DATA[5]
--operation mode is bidir

LCD_DATA[5] = BIDIR(OPNDRN(VCC));


--LCD_DATA[6] is LCD_DATA[6]
--operation mode is bidir

LCD_DATA[6] = BIDIR(OPNDRN(VCC));


--LCD_DATA[7] is LCD_DATA[7]
--operation mode is bidir

LCD_DATA[7] = BIDIR(OPNDRN(VCC));


--SD_DAT is SD_DAT
--operation mode is bidir

SD_DAT = BIDIR(OPNDRN(VCC));


--I2C_SDAT is I2C_SDAT
--operation mode is bidir

I2C_SDAT = BIDIR(OPNDRN(VCC));


--ENET_DATA[0] is ENET_DATA[0]
--operation mode is bidir

ENET_DATA[0] = BIDIR(OPNDRN(VCC));


--ENET_DATA[1] is ENET_DATA[1]
--operation mode is bidir

ENET_DATA[1] = BIDIR(OPNDRN(VCC));


--ENET_DATA[2] is ENET_DATA[2]
--operation mode is bidir

ENET_DATA[2] = BIDIR(OPNDRN(VCC));


--ENET_DATA[3] is ENET_DATA[3]
--operation mode is bidir

ENET_DATA[3] = BIDIR(OPNDRN(VCC));


--ENET_DATA[4] is ENET_DATA[4]
--operation mode is bidir

ENET_DATA[4] = BIDIR(OPNDRN(VCC));


--ENET_DATA[5] is ENET_DATA[5]
--operation mode is bidir

ENET_DATA[5] = BIDIR(OPNDRN(VCC));


--ENET_DATA[6] is ENET_DATA[6]
--operation mode is bidir

ENET_DATA[6] = BIDIR(OPNDRN(VCC));


--ENET_DATA[7] is ENET_DATA[7]
--operation mode is bidir

ENET_DATA[7] = BIDIR(OPNDRN(VCC));


--ENET_DATA[8] is ENET_DATA[8]
--operation mode is bidir

ENET_DATA[8] = BIDIR(OPNDRN(VCC));


--ENET_DATA[9] is ENET_DATA[9]
--operation mode is bidir

ENET_DATA[9] = BIDIR(OPNDRN(VCC));


--ENET_DATA[10] is ENET_DATA[10]
--operation mode is bidir

ENET_DATA[10] = BIDIR(OPNDRN(VCC));


--ENET_DATA[11] is ENET_DATA[11]
--operation mode is bidir

ENET_DATA[11] = BIDIR(OPNDRN(VCC));


--ENET_DATA[12] is ENET_DATA[12]
--operation mode is bidir

ENET_DATA[12] = BIDIR(OPNDRN(VCC));


--ENET_DATA[13] is ENET_DATA[13]
--operation mode is bidir

ENET_DATA[13] = BIDIR(OPNDRN(VCC));


--ENET_DATA[14] is ENET_DATA[14]
--operation mode is bidir

ENET_DATA[14] = BIDIR(OPNDRN(VCC));


--ENET_DATA[15] is ENET_DATA[15]
--operation mode is bidir

ENET_DATA[15] = BIDIR(OPNDRN(VCC));


--AUD_ADCLRCK is AUD_ADCLRCK
--operation mode is bidir

AUD_ADCLRCK = BIDIR(OPNDRN(VCC));


--AUD_DACLRCK is AUD_DACLRCK
--operation mode is bidir

AUD_DACLRCK = BIDIR(OPNDRN(VCC));


--AUD_BCLK is AUD_BCLK
--operation mode is bidir

AUD_BCLK = BIDIR(OPNDRN(VCC));


--A1L168 is GPIO_1[0]~9
--operation mode is bidir

A1L168 = GPIO_1[0];

--GPIO_1[0] is GPIO_1[0]
--operation mode is bidir

GPIO_1[0] = BIDIR(OPNDRN(VCC));


--A1L170 is GPIO_1[1]~8
--operation mode is bidir

A1L170 = GPIO_1[1];

--GPIO_1[1] is GPIO_1[1]
--operation mode is bidir

GPIO_1[1] = BIDIR(OPNDRN(VCC));


--A1L172 is GPIO_1[2]~5
--operation mode is bidir

A1L172 = GPIO_1[2];

--GPIO_1[2] is GPIO_1[2]
--operation mode is bidir

GPIO_1[2] = BIDIR(OPNDRN(VCC));


--A1L174 is GPIO_1[3]~6
--operation mode is bidir

A1L174 = GPIO_1[3];

--GPIO_1[3] is GPIO_1[3]
--operation mode is bidir

GPIO_1[3] = BIDIR(OPNDRN(VCC));


--A1L176 is GPIO_1[4]~4
--operation mode is bidir

A1L176 = GPIO_1[4];

--GPIO_1[4] is GPIO_1[4]
--operation mode is bidir

GPIO_1[4] = BIDIR(OPNDRN(VCC));


--A1L178 is GPIO_1[5]~7
--operation mode is bidir

A1L178 = GPIO_1[5];

--GPIO_1[5] is GPIO_1[5]
--operation mode is bidir

GPIO_1[5] = BIDIR(OPNDRN(VCC));


--A1L180 is GPIO_1[6]~3
--operation mode is bidir

A1L180 = GPIO_1[6];

--GPIO_1[6] is GPIO_1[6]
--operation mode is bidir

GPIO_1[6] = BIDIR(OPNDRN(VCC));


--A1L182 is GPIO_1[7]~2
--operation mode is bidir

A1L182 = GPIO_1[7];

--GPIO_1[7] is GPIO_1[7]
--operation mode is bidir

GPIO_1[7] = BIDIR(OPNDRN(VCC));


--A1L184 is GPIO_1[8]~1
--operation mode is bidir

A1L184 = GPIO_1[8];

--GPIO_1[8] is GPIO_1[8]
--operation mode is bidir

GPIO_1[8] = BIDIR(OPNDRN(VCC));


--A1L186 is GPIO_1[9]~0
--operation mode is bidir

A1L186 = GPIO_1[9];

--GPIO_1[9] is GPIO_1[9]
--operation mode is bidir

GPIO_1[9] = BIDIR(OPNDRN(VCC));


--CCD_PIXCLK is CCD_PIXCLK
--operation mode is bidir

CCD_PIXCLK = GPIO_1[10];

--GPIO_1[10] is GPIO_1[10]
--operation mode is bidir

GPIO_1[10] = BIDIR(OPNDRN(VCC));


--GPIO_1[11] is GPIO_1[11]
--operation mode is bidir

GPIO_1[11]_tri_out = TRI(CCD_MCLK, VCC);
GPIO_1[11] = BIDIR(GPIO_1[11]_tri_out);


--A1L190 is GPIO_1[12]~11
--operation mode is bidir

A1L190 = GPIO_1[12];

--GPIO_1[12] is GPIO_1[12]
--operation mode is bidir

GPIO_1[12] = BIDIR(OPNDRN(VCC));


--A1L192 is GPIO_1[13]~10
--operation mode is bidir

A1L192 = GPIO_1[13];

--GPIO_1[13] is GPIO_1[13]
--operation mode is bidir

GPIO_1[13] = BIDIR(OPNDRN(VCC));


--GPIO_1[14] is GPIO_1[14]
--operation mode is bidir

GPIO_1[14]_tri_out = TRI(LB1L17, VCC);
GPIO_1[14] = BIDIR(GPIO_1[14]_tri_out);


--CCD_SDAT is CCD_SDAT
--operation mode is bidir

CCD_SDAT = GPIO_1[15];

--GPIO_1[15] is GPIO_1[15]
--operation mode is bidir

GPIO_1[15] = BIDIR(OPNDRN(!LB1L25Q));


--J1L6 is Mirror_Col:u8|Z_Cont[0]~183
J1L6 = !J1_Z_Cont[0];


--J1L10 is Mirror_Col:u8|Z_Cont[1]~184
J1L10 = !J1_Z_Cont[1];


--J1L14 is Mirror_Col:u8|Z_Cont[2]~185
J1L14 = !J1_Z_Cont[2];


--J1L18 is Mirror_Col:u8|Z_Cont[3]~186
J1L18 = !J1_Z_Cont[3];


--J1L22 is Mirror_Col:u8|Z_Cont[4]~187
J1L22 = !J1_Z_Cont[4];


--J1L26 is Mirror_Col:u8|Z_Cont[5]~188
J1L26 = !J1_Z_Cont[5];


--J1L30 is Mirror_Col:u8|Z_Cont[6]~189
J1L30 = !J1_Z_Cont[6];


--R1L19 is Sdram_Control_4Port:u6|command:command1|REF_ACK~56
R1L19 = !R1_REF_ACK;


