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--D1_Frame_Cont[0] is CCD_Capture:u3|Frame_Cont[0] at LCFF_X12_Y11_N1
D1_Frame_Cont[0] = DFFEAS(D1L3, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[1] is CCD_Capture:u3|Frame_Cont[1] at LCFF_X12_Y11_N3
D1_Frame_Cont[1] = DFFEAS(D1L6, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[2] is CCD_Capture:u3|Frame_Cont[2] at LCFF_X12_Y11_N5
D1_Frame_Cont[2] = DFFEAS(D1L9, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[3] is CCD_Capture:u3|Frame_Cont[3] at LCFF_X12_Y11_N7
D1_Frame_Cont[3] = DFFEAS(D1L12, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--Q1L1 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[0]~70 at LCCOMB_X25_Y1_N0
Q1L1 = D1_Frame_Cont[2] & !D1_Frame_Cont[1] & (D1_Frame_Cont[0] $ !D1_Frame_Cont[3]) # !D1_Frame_Cont[2] & D1_Frame_Cont[0] & (D1_Frame_Cont[3] $ !D1_Frame_Cont[1]);


--Q1L2 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[1]~71 at LCCOMB_X25_Y1_N16
Q1L2 = D1_Frame_Cont[3] & (D1_Frame_Cont[0] & (D1_Frame_Cont[1]) # !D1_Frame_Cont[0] & D1_Frame_Cont[2]) # !D1_Frame_Cont[3] & D1_Frame_Cont[2] & (D1_Frame_Cont[0] $ D1_Frame_Cont[1]);


--Q1L3 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[2]~72 at LCCOMB_X25_Y1_N4
Q1L3 = D1_Frame_Cont[2] & D1_Frame_Cont[3] & (D1_Frame_Cont[1] # !D1_Frame_Cont[0]) # !D1_Frame_Cont[2] & !D1_Frame_Cont[0] & !D1_Frame_Cont[3] & D1_Frame_Cont[1];


--Q1L4 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[3]~73 at LCCOMB_X25_Y1_N8
Q1L4 = D1_Frame_Cont[0] & (D1_Frame_Cont[2] $ (!D1_Frame_Cont[1])) # !D1_Frame_Cont[0] & (D1_Frame_Cont[2] & !D1_Frame_Cont[3] & !D1_Frame_Cont[1] # !D1_Frame_Cont[2] & D1_Frame_Cont[3] & D1_Frame_Cont[1]);


--Q1L5 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[4]~74 at LCCOMB_X25_Y1_N10
Q1L5 = D1_Frame_Cont[1] & (D1_Frame_Cont[0] & !D1_Frame_Cont[3]) # !D1_Frame_Cont[1] & (D1_Frame_Cont[2] & (!D1_Frame_Cont[3]) # !D1_Frame_Cont[2] & D1_Frame_Cont[0]);


--Q1L6 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[5]~75 at LCCOMB_X25_Y1_N18
Q1L6 = D1_Frame_Cont[2] & D1_Frame_Cont[0] & (D1_Frame_Cont[3] $ D1_Frame_Cont[1]) # !D1_Frame_Cont[2] & !D1_Frame_Cont[3] & (D1_Frame_Cont[0] # D1_Frame_Cont[1]);


--Q1L7 is SEG7_LUT_8:u5|SEG7_LUT:u0|oSEG[6]~76 at LCCOMB_X25_Y1_N12
Q1L7 = D1_Frame_Cont[0] & (D1_Frame_Cont[3] # D1_Frame_Cont[2] $ D1_Frame_Cont[1]) # !D1_Frame_Cont[0] & (D1_Frame_Cont[1] # D1_Frame_Cont[2] $ D1_Frame_Cont[3]);


--D1_Frame_Cont[4] is CCD_Capture:u3|Frame_Cont[4] at LCFF_X12_Y11_N9
D1_Frame_Cont[4] = DFFEAS(D1L15, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[5] is CCD_Capture:u3|Frame_Cont[5] at LCFF_X12_Y11_N11
D1_Frame_Cont[5] = DFFEAS(D1L18, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[6] is CCD_Capture:u3|Frame_Cont[6] at LCFF_X12_Y11_N13
D1_Frame_Cont[6] = DFFEAS(D1L21, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[7] is CCD_Capture:u3|Frame_Cont[7] at LCFF_X12_Y11_N15
D1_Frame_Cont[7] = DFFEAS(D1L24, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--Q2L1 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[0]~70 at LCCOMB_X64_Y5_N16
Q2L1 = D1_Frame_Cont[6] & !D1_Frame_Cont[5] & (D1_Frame_Cont[7] $ !D1_Frame_Cont[4]) # !D1_Frame_Cont[6] & D1_Frame_Cont[4] & (D1_Frame_Cont[5] $ !D1_Frame_Cont[7]);


--Q2L2 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[1]~71 at LCCOMB_X64_Y5_N22
Q2L2 = D1_Frame_Cont[5] & (D1_Frame_Cont[4] & (D1_Frame_Cont[7]) # !D1_Frame_Cont[4] & D1_Frame_Cont[6]) # !D1_Frame_Cont[5] & D1_Frame_Cont[6] & (D1_Frame_Cont[7] $ D1_Frame_Cont[4]);


--Q2L3 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[2]~72 at LCCOMB_X64_Y5_N12
Q2L3 = D1_Frame_Cont[6] & D1_Frame_Cont[7] & (D1_Frame_Cont[5] # !D1_Frame_Cont[4]) # !D1_Frame_Cont[6] & D1_Frame_Cont[5] & !D1_Frame_Cont[7] & !D1_Frame_Cont[4];


--Q2L4 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[3]~73 at LCCOMB_X64_Y5_N4
Q2L4 = D1_Frame_Cont[4] & (D1_Frame_Cont[5] $ !D1_Frame_Cont[6]) # !D1_Frame_Cont[4] & (D1_Frame_Cont[5] & !D1_Frame_Cont[6] & D1_Frame_Cont[7] # !D1_Frame_Cont[5] & D1_Frame_Cont[6] & !D1_Frame_Cont[7]);


--Q2L5 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[4]~74 at LCCOMB_X64_Y5_N8
Q2L5 = D1_Frame_Cont[5] & (!D1_Frame_Cont[7] & D1_Frame_Cont[4]) # !D1_Frame_Cont[5] & (D1_Frame_Cont[6] & !D1_Frame_Cont[7] # !D1_Frame_Cont[6] & (D1_Frame_Cont[4]));


--Q2L6 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[5]~75 at LCCOMB_X64_Y5_N6
Q2L6 = D1_Frame_Cont[5] & !D1_Frame_Cont[7] & (D1_Frame_Cont[4] # !D1_Frame_Cont[6]) # !D1_Frame_Cont[5] & D1_Frame_Cont[4] & (D1_Frame_Cont[6] $ !D1_Frame_Cont[7]);


--Q2L7 is SEG7_LUT_8:u5|SEG7_LUT:u1|oSEG[6]~76 at LCCOMB_X64_Y5_N18
Q2L7 = D1_Frame_Cont[4] & (D1_Frame_Cont[7] # D1_Frame_Cont[5] $ D1_Frame_Cont[6]) # !D1_Frame_Cont[4] & (D1_Frame_Cont[5] # D1_Frame_Cont[6] $ D1_Frame_Cont[7]);


--D1_Frame_Cont[8] is CCD_Capture:u3|Frame_Cont[8] at LCFF_X12_Y11_N17
D1_Frame_Cont[8] = DFFEAS(D1L27, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[9] is CCD_Capture:u3|Frame_Cont[9] at LCFF_X12_Y11_N19
D1_Frame_Cont[9] = DFFEAS(D1L30, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[10] is CCD_Capture:u3|Frame_Cont[10] at LCFF_X12_Y11_N21
D1_Frame_Cont[10] = DFFEAS(D1L33, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[11] is CCD_Capture:u3|Frame_Cont[11] at LCFF_X12_Y11_N23
D1_Frame_Cont[11] = DFFEAS(D1L36, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--Q3L1 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[0]~70 at LCCOMB_X64_Y7_N18
Q3L1 = D1_Frame_Cont[10] & !D1_Frame_Cont[9] & (D1_Frame_Cont[8] $ !D1_Frame_Cont[11]) # !D1_Frame_Cont[10] & D1_Frame_Cont[8] & (D1_Frame_Cont[9] $ !D1_Frame_Cont[11]);


--Q3L2 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[1]~71 at LCCOMB_X64_Y7_N16
Q3L2 = D1_Frame_Cont[9] & (D1_Frame_Cont[8] & (D1_Frame_Cont[11]) # !D1_Frame_Cont[8] & D1_Frame_Cont[10]) # !D1_Frame_Cont[9] & D1_Frame_Cont[10] & (D1_Frame_Cont[8] $ D1_Frame_Cont[11]);


--Q3L3 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[2]~72 at LCCOMB_X64_Y7_N12
Q3L3 = D1_Frame_Cont[10] & D1_Frame_Cont[11] & (D1_Frame_Cont[9] # !D1_Frame_Cont[8]) # !D1_Frame_Cont[10] & !D1_Frame_Cont[8] & D1_Frame_Cont[9] & !D1_Frame_Cont[11];


--Q3L4 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[3]~73 at LCCOMB_X64_Y7_N10
Q3L4 = D1_Frame_Cont[8] & (D1_Frame_Cont[10] $ !D1_Frame_Cont[9]) # !D1_Frame_Cont[8] & (D1_Frame_Cont[10] & !D1_Frame_Cont[9] & !D1_Frame_Cont[11] # !D1_Frame_Cont[10] & D1_Frame_Cont[9] & D1_Frame_Cont[11]);


--Q3L5 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[4]~74 at LCCOMB_X64_Y7_N6
Q3L5 = D1_Frame_Cont[9] & (D1_Frame_Cont[8] & !D1_Frame_Cont[11]) # !D1_Frame_Cont[9] & (D1_Frame_Cont[10] & (!D1_Frame_Cont[11]) # !D1_Frame_Cont[10] & D1_Frame_Cont[8]);


--Q3L6 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[5]~75 at LCCOMB_X64_Y7_N8
Q3L6 = D1_Frame_Cont[10] & D1_Frame_Cont[8] & (D1_Frame_Cont[9] $ D1_Frame_Cont[11]) # !D1_Frame_Cont[10] & !D1_Frame_Cont[11] & (D1_Frame_Cont[8] # D1_Frame_Cont[9]);


--Q3L7 is SEG7_LUT_8:u5|SEG7_LUT:u2|oSEG[6]~76 at LCCOMB_X64_Y7_N4
Q3L7 = D1_Frame_Cont[8] & (D1_Frame_Cont[11] # D1_Frame_Cont[10] $ D1_Frame_Cont[9]) # !D1_Frame_Cont[8] & (D1_Frame_Cont[9] # D1_Frame_Cont[10] $ D1_Frame_Cont[11]);


--D1_Frame_Cont[12] is CCD_Capture:u3|Frame_Cont[12] at LCFF_X12_Y11_N25
D1_Frame_Cont[12] = DFFEAS(D1L39, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[13] is CCD_Capture:u3|Frame_Cont[13] at LCFF_X12_Y11_N27
D1_Frame_Cont[13] = DFFEAS(D1L42, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[14] is CCD_Capture:u3|Frame_Cont[14] at LCFF_X12_Y11_N29
D1_Frame_Cont[14] = DFFEAS(D1L45, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[15] is CCD_Capture:u3|Frame_Cont[15] at LCFF_X12_Y11_N31
D1_Frame_Cont[15] = DFFEAS(D1L48, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--Q4L1 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[0]~70 at LCCOMB_X64_Y9_N16
Q4L1 = D1_Frame_Cont[14] & !D1_Frame_Cont[13] & (D1_Frame_Cont[15] $ !D1_Frame_Cont[12]) # !D1_Frame_Cont[14] & D1_Frame_Cont[12] & (D1_Frame_Cont[13] $ !D1_Frame_Cont[15]);


--Q4L2 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[1]~71 at LCCOMB_X64_Y9_N22
Q4L2 = D1_Frame_Cont[13] & (D1_Frame_Cont[12] & (D1_Frame_Cont[15]) # !D1_Frame_Cont[12] & D1_Frame_Cont[14]) # !D1_Frame_Cont[13] & D1_Frame_Cont[14] & (D1_Frame_Cont[15] $ D1_Frame_Cont[12]);


--Q4L3 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[2]~72 at LCCOMB_X64_Y9_N12
Q4L3 = D1_Frame_Cont[14] & D1_Frame_Cont[15] & (D1_Frame_Cont[13] # !D1_Frame_Cont[12]) # !D1_Frame_Cont[14] & D1_Frame_Cont[13] & !D1_Frame_Cont[15] & !D1_Frame_Cont[12];


--Q4L4 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[3]~73 at LCCOMB_X64_Y9_N4
Q4L4 = D1_Frame_Cont[12] & (D1_Frame_Cont[14] $ !D1_Frame_Cont[13]) # !D1_Frame_Cont[12] & (D1_Frame_Cont[14] & !D1_Frame_Cont[13] & !D1_Frame_Cont[15] # !D1_Frame_Cont[14] & D1_Frame_Cont[13] & D1_Frame_Cont[15]);


--Q4L5 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[4]~74 at LCCOMB_X64_Y9_N8
Q4L5 = D1_Frame_Cont[13] & (!D1_Frame_Cont[15] & D1_Frame_Cont[12]) # !D1_Frame_Cont[13] & (D1_Frame_Cont[14] & !D1_Frame_Cont[15] # !D1_Frame_Cont[14] & (D1_Frame_Cont[12]));


--Q4L6 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[5]~75 at LCCOMB_X64_Y9_N6
Q4L6 = D1_Frame_Cont[14] & D1_Frame_Cont[12] & (D1_Frame_Cont[13] $ D1_Frame_Cont[15]) # !D1_Frame_Cont[14] & !D1_Frame_Cont[15] & (D1_Frame_Cont[13] # D1_Frame_Cont[12]);


--Q4L7 is SEG7_LUT_8:u5|SEG7_LUT:u3|oSEG[6]~76 at LCCOMB_X64_Y9_N18
Q4L7 = D1_Frame_Cont[12] & (D1_Frame_Cont[15] # D1_Frame_Cont[14] $ D1_Frame_Cont[13]) # !D1_Frame_Cont[12] & (D1_Frame_Cont[13] # D1_Frame_Cont[14] $ D1_Frame_Cont[15]);


--D1_Frame_Cont[16] is CCD_Capture:u3|Frame_Cont[16] at LCFF_X12_Y10_N1
D1_Frame_Cont[16] = DFFEAS(D1L51, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[17] is CCD_Capture:u3|Frame_Cont[17] at LCFF_X12_Y10_N3
D1_Frame_Cont[17] = DFFEAS(D1L54, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[18] is CCD_Capture:u3|Frame_Cont[18] at LCFF_X12_Y10_N5
D1_Frame_Cont[18] = DFFEAS(D1L57, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[19] is CCD_Capture:u3|Frame_Cont[19] at LCFF_X12_Y10_N7
D1_Frame_Cont[19] = DFFEAS(D1L60, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--Q5L1 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[0]~70 at LCCOMB_X1_Y13_N28
Q5L1 = D1_Frame_Cont[19] & D1_Frame_Cont[16] & (D1_Frame_Cont[17] $ D1_Frame_Cont[18]) # !D1_Frame_Cont[19] & !D1_Frame_Cont[17] & (D1_Frame_Cont[18] $ D1_Frame_Cont[16]);


--Q5L2 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[1]~71 at LCCOMB_X1_Y13_N20
Q5L2 = D1_Frame_Cont[17] & (D1_Frame_Cont[16] & D1_Frame_Cont[19] # !D1_Frame_Cont[16] & (D1_Frame_Cont[18])) # !D1_Frame_Cont[17] & D1_Frame_Cont[18] & (D1_Frame_Cont[19] $ D1_Frame_Cont[16]);


--Q5L3 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[2]~72 at LCCOMB_X1_Y13_N10
Q5L3 = D1_Frame_Cont[19] & D1_Frame_Cont[18] & (D1_Frame_Cont[17] # !D1_Frame_Cont[16]) # !D1_Frame_Cont[19] & D1_Frame_Cont[17] & !D1_Frame_Cont[18] & !D1_Frame_Cont[16];


--Q5L4 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[3]~73 at LCCOMB_X1_Y13_N0
Q5L4 = D1_Frame_Cont[16] & (D1_Frame_Cont[17] $ (!D1_Frame_Cont[18])) # !D1_Frame_Cont[16] & (D1_Frame_Cont[17] & D1_Frame_Cont[19] & !D1_Frame_Cont[18] # !D1_Frame_Cont[17] & !D1_Frame_Cont[19] & D1_Frame_Cont[18]);


--Q5L5 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[4]~74 at LCCOMB_X1_Y13_N26
Q5L5 = D1_Frame_Cont[17] & !D1_Frame_Cont[19] & (D1_Frame_Cont[16]) # !D1_Frame_Cont[17] & (D1_Frame_Cont[18] & !D1_Frame_Cont[19] # !D1_Frame_Cont[18] & (D1_Frame_Cont[16]));


--Q5L6 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[5]~75 at LCCOMB_X1_Y13_N4
Q5L6 = D1_Frame_Cont[17] & !D1_Frame_Cont[19] & (D1_Frame_Cont[16] # !D1_Frame_Cont[18]) # !D1_Frame_Cont[17] & D1_Frame_Cont[16] & (D1_Frame_Cont[19] $ !D1_Frame_Cont[18]);


--Q5L7 is SEG7_LUT_8:u5|SEG7_LUT:u4|oSEG[6]~76 at LCCOMB_X1_Y13_N12
Q5L7 = D1_Frame_Cont[16] & (D1_Frame_Cont[19] # D1_Frame_Cont[17] $ D1_Frame_Cont[18]) # !D1_Frame_Cont[16] & (D1_Frame_Cont[17] # D1_Frame_Cont[19] $ D1_Frame_Cont[18]);


--D1_Frame_Cont[20] is CCD_Capture:u3|Frame_Cont[20] at LCFF_X12_Y10_N9
D1_Frame_Cont[20] = DFFEAS(D1L63, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[21] is CCD_Capture:u3|Frame_Cont[21] at LCFF_X12_Y10_N11
D1_Frame_Cont[21] = DFFEAS(D1L66, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[22] is CCD_Capture:u3|Frame_Cont[22] at LCFF_X12_Y10_N13
D1_Frame_Cont[22] = DFFEAS(D1L69, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[23] is CCD_Capture:u3|Frame_Cont[23] at LCFF_X12_Y10_N15
D1_Frame_Cont[23] = DFFEAS(D1L72, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--Q6L1 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[0]~70 at LCCOMB_X1_Y15_N12
Q6L1 = D1_Frame_Cont[22] & !D1_Frame_Cont[21] & (D1_Frame_Cont[23] $ !D1_Frame_Cont[20]) # !D1_Frame_Cont[22] & D1_Frame_Cont[20] & (D1_Frame_Cont[23] $ !D1_Frame_Cont[21]);


--Q6L2 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[1]~71 at LCCOMB_X1_Y15_N28
Q6L2 = D1_Frame_Cont[23] & (D1_Frame_Cont[20] & (D1_Frame_Cont[21]) # !D1_Frame_Cont[20] & D1_Frame_Cont[22]) # !D1_Frame_Cont[23] & D1_Frame_Cont[22] & (D1_Frame_Cont[21] $ D1_Frame_Cont[20]);


--Q6L3 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[2]~72 at LCCOMB_X1_Y15_N20
Q6L3 = D1_Frame_Cont[22] & D1_Frame_Cont[23] & (D1_Frame_Cont[21] # !D1_Frame_Cont[20]) # !D1_Frame_Cont[22] & !D1_Frame_Cont[23] & D1_Frame_Cont[21] & !D1_Frame_Cont[20];


--Q6L4 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[3]~73 at LCCOMB_X1_Y15_N0
Q6L4 = D1_Frame_Cont[20] & (D1_Frame_Cont[22] $ (!D1_Frame_Cont[21])) # !D1_Frame_Cont[20] & (D1_Frame_Cont[22] & !D1_Frame_Cont[23] & !D1_Frame_Cont[21] # !D1_Frame_Cont[22] & D1_Frame_Cont[23] & D1_Frame_Cont[21]);


--Q6L5 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[4]~74 at LCCOMB_X1_Y15_N26
Q6L5 = D1_Frame_Cont[21] & (!D1_Frame_Cont[23] & D1_Frame_Cont[20]) # !D1_Frame_Cont[21] & (D1_Frame_Cont[22] & !D1_Frame_Cont[23] # !D1_Frame_Cont[22] & (D1_Frame_Cont[20]));


--Q6L6 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[5]~75 at LCCOMB_X1_Y15_N4
Q6L6 = D1_Frame_Cont[22] & D1_Frame_Cont[20] & (D1_Frame_Cont[23] $ D1_Frame_Cont[21]) # !D1_Frame_Cont[22] & !D1_Frame_Cont[23] & (D1_Frame_Cont[21] # D1_Frame_Cont[20]);


--Q6L7 is SEG7_LUT_8:u5|SEG7_LUT:u5|oSEG[6]~76 at LCCOMB_X1_Y15_N10
Q6L7 = D1_Frame_Cont[20] & (D1_Frame_Cont[23] # D1_Frame_Cont[22] $ D1_Frame_Cont[21]) # !D1_Frame_Cont[20] & (D1_Frame_Cont[21] # D1_Frame_Cont[22] $ D1_Frame_Cont[23]);


--D1_Frame_Cont[24] is CCD_Capture:u3|Frame_Cont[24] at LCFF_X12_Y10_N17
D1_Frame_Cont[24] = DFFEAS(D1L75, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[25] is CCD_Capture:u3|Frame_Cont[25] at LCFF_X12_Y10_N19
D1_Frame_Cont[25] = DFFEAS(D1L78, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[26] is CCD_Capture:u3|Frame_Cont[26] at LCFF_X12_Y10_N21
D1_Frame_Cont[26] = DFFEAS(D1L81, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[27] is CCD_Capture:u3|Frame_Cont[27] at LCFF_X12_Y10_N23
D1_Frame_Cont[27] = DFFEAS(D1L84, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--Q7L1 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[0]~70 at LCCOMB_X1_Y17_N28
Q7L1 = D1_Frame_Cont[26] & !D1_Frame_Cont[25] & (D1_Frame_Cont[27] $ !D1_Frame_Cont[24]) # !D1_Frame_Cont[26] & D1_Frame_Cont[24] & (D1_Frame_Cont[25] $ !D1_Frame_Cont[27]);


--Q7L2 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[1]~71 at LCCOMB_X1_Y17_N18
Q7L2 = D1_Frame_Cont[25] & (D1_Frame_Cont[24] & (D1_Frame_Cont[27]) # !D1_Frame_Cont[24] & D1_Frame_Cont[26]) # !D1_Frame_Cont[25] & D1_Frame_Cont[26] & (D1_Frame_Cont[27] $ D1_Frame_Cont[24]);


--Q7L3 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[2]~72 at LCCOMB_X1_Y17_N20
Q7L3 = D1_Frame_Cont[26] & D1_Frame_Cont[27] & (D1_Frame_Cont[25] # !D1_Frame_Cont[24]) # !D1_Frame_Cont[26] & D1_Frame_Cont[25] & !D1_Frame_Cont[27] & !D1_Frame_Cont[24];


--Q7L4 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[3]~73 at LCCOMB_X1_Y17_N12
Q7L4 = D1_Frame_Cont[24] & (D1_Frame_Cont[25] $ !D1_Frame_Cont[26]) # !D1_Frame_Cont[24] & (D1_Frame_Cont[25] & !D1_Frame_Cont[26] & D1_Frame_Cont[27] # !D1_Frame_Cont[25] & D1_Frame_Cont[26] & !D1_Frame_Cont[27]);


--Q7L5 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[4]~74 at LCCOMB_X1_Y17_N26
Q7L5 = D1_Frame_Cont[25] & (!D1_Frame_Cont[27] & D1_Frame_Cont[24]) # !D1_Frame_Cont[25] & (D1_Frame_Cont[26] & !D1_Frame_Cont[27] # !D1_Frame_Cont[26] & (D1_Frame_Cont[24]));


--Q7L6 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[5]~75 at LCCOMB_X1_Y17_N10
Q7L6 = D1_Frame_Cont[25] & !D1_Frame_Cont[27] & (D1_Frame_Cont[24] # !D1_Frame_Cont[26]) # !D1_Frame_Cont[25] & D1_Frame_Cont[24] & (D1_Frame_Cont[26] $ !D1_Frame_Cont[27]);


--Q7L7 is SEG7_LUT_8:u5|SEG7_LUT:u6|oSEG[6]~76 at LCCOMB_X1_Y17_N4
Q7L7 = D1_Frame_Cont[24] & (D1_Frame_Cont[27] # D1_Frame_Cont[25] $ D1_Frame_Cont[26]) # !D1_Frame_Cont[24] & (D1_Frame_Cont[25] # D1_Frame_Cont[26] $ D1_Frame_Cont[27]);


--D1_Frame_Cont[28] is CCD_Capture:u3|Frame_Cont[28] at LCFF_X12_Y10_N25
D1_Frame_Cont[28] = DFFEAS(D1L87, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[29] is CCD_Capture:u3|Frame_Cont[29] at LCFF_X12_Y10_N27
D1_Frame_Cont[29] = DFFEAS(D1L90, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[30] is CCD_Capture:u3|Frame_Cont[30] at LCFF_X12_Y10_N29
D1_Frame_Cont[30] = DFFEAS(D1L93, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--D1_Frame_Cont[31] is CCD_Capture:u3|Frame_Cont[31] at LCFF_X12_Y10_N31
D1_Frame_Cont[31] = DFFEAS(D1L96, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L167,  ,  ,  ,  );


--Q8L1 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[0]~70 at LCCOMB_X1_Y24_N28
Q8L1 = D1_Frame_Cont[30] & !D1_Frame_Cont[29] & (D1_Frame_Cont[31] $ !D1_Frame_Cont[28]) # !D1_Frame_Cont[30] & D1_Frame_Cont[28] & (D1_Frame_Cont[31] $ !D1_Frame_Cont[29]);


--Q8L2 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[1]~71 at LCCOMB_X1_Y24_N12
Q8L2 = D1_Frame_Cont[31] & (D1_Frame_Cont[28] & (D1_Frame_Cont[29]) # !D1_Frame_Cont[28] & D1_Frame_Cont[30]) # !D1_Frame_Cont[31] & D1_Frame_Cont[30] & (D1_Frame_Cont[29] $ D1_Frame_Cont[28]);


--Q8L3 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[2]~72 at LCCOMB_X1_Y24_N26
Q8L3 = D1_Frame_Cont[30] & D1_Frame_Cont[31] & (D1_Frame_Cont[29] # !D1_Frame_Cont[28]) # !D1_Frame_Cont[30] & !D1_Frame_Cont[31] & D1_Frame_Cont[29] & !D1_Frame_Cont[28];


--Q8L4 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[3]~73 at LCCOMB_X1_Y24_N20
Q8L4 = D1_Frame_Cont[28] & (D1_Frame_Cont[30] $ (!D1_Frame_Cont[29])) # !D1_Frame_Cont[28] & (D1_Frame_Cont[30] & !D1_Frame_Cont[31] & !D1_Frame_Cont[29] # !D1_Frame_Cont[30] & D1_Frame_Cont[31] & D1_Frame_Cont[29]);


--Q8L5 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[4]~74 at LCCOMB_X1_Y24_N4
Q8L5 = D1_Frame_Cont[29] & (!D1_Frame_Cont[31] & D1_Frame_Cont[28]) # !D1_Frame_Cont[29] & (D1_Frame_Cont[30] & !D1_Frame_Cont[31] # !D1_Frame_Cont[30] & (D1_Frame_Cont[28]));


--Q8L6 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[5]~75 at LCCOMB_X1_Y24_N0
Q8L6 = D1_Frame_Cont[30] & D1_Frame_Cont[28] & (D1_Frame_Cont[31] $ D1_Frame_Cont[29]) # !D1_Frame_Cont[30] & !D1_Frame_Cont[31] & (D1_Frame_Cont[29] # D1_Frame_Cont[28]);


--Q8L7 is SEG7_LUT_8:u5|SEG7_LUT:u7|oSEG[6]~76 at LCCOMB_X1_Y24_N10
Q8L7 = D1_Frame_Cont[28] & (D1_Frame_Cont[31] # D1_Frame_Cont[30] $ D1_Frame_Cont[29]) # !D1_Frame_Cont[28] & (D1_Frame_Cont[29] # D1_Frame_Cont[30] $ D1_Frame_Cont[31]);


--D1_Y_Cont[0] is CCD_Capture:u3|Y_Cont[0] at LCFF_X57_Y1_N11
D1_Y_Cont[0] = DFFEAS(D1L140, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[1] is CCD_Capture:u3|Y_Cont[1] at LCFF_X57_Y1_N13
D1_Y_Cont[1] = DFFEAS(D1L143, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[2] is CCD_Capture:u3|Y_Cont[2] at LCFF_X57_Y1_N15
D1_Y_Cont[2] = DFFEAS(D1L146, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[3] is CCD_Capture:u3|Y_Cont[3] at LCFF_X57_Y1_N17
D1_Y_Cont[3] = DFFEAS(D1L149, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[4] is CCD_Capture:u3|Y_Cont[4] at LCFF_X57_Y1_N19
D1_Y_Cont[4] = DFFEAS(D1L152, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[5] is CCD_Capture:u3|Y_Cont[5] at LCFF_X57_Y1_N21
D1_Y_Cont[5] = DFFEAS(D1L155, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[6] is CCD_Capture:u3|Y_Cont[6] at LCFF_X57_Y1_N23
D1_Y_Cont[6] = DFFEAS(D1L158, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[7] is CCD_Capture:u3|Y_Cont[7] at LCFF_X57_Y1_N25
D1_Y_Cont[7] = DFFEAS(D1L161, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[8] is CCD_Capture:u3|Y_Cont[8] at LCFF_X57_Y1_N27
D1_Y_Cont[8] = DFFEAS(D1L164, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--G1_SA[0] is Sdram_Control_4Port:u6|SA[0] at LCFF_X18_Y11_N27
G1_SA[0] = DFFEAS(G1L75, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[1] is Sdram_Control_4Port:u6|SA[1] at LCFF_X18_Y11_N3
G1_SA[1] = DFFEAS(G1L76, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[2] is Sdram_Control_4Port:u6|SA[2] at LCFF_X18_Y11_N5
G1_SA[2] = DFFEAS(G1L77, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[3] is Sdram_Control_4Port:u6|SA[3] at LCFF_X18_Y11_N31
G1_SA[3] = DFFEAS(G1L78, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[4] is Sdram_Control_4Port:u6|SA[4] at LCFF_X18_Y11_N1
G1_SA[4] = DFFEAS(G1L79, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[5] is Sdram_Control_4Port:u6|SA[5] at LCFF_X18_Y11_N9
G1_SA[5] = DFFEAS(G1L80, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[6] is Sdram_Control_4Port:u6|SA[6] at LCFF_X18_Y11_N17
G1_SA[6] = DFFEAS(G1L81, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[7] is Sdram_Control_4Port:u6|SA[7] at LCFF_X18_Y11_N7
G1_SA[7] = DFFEAS(G1L82, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[8] is Sdram_Control_4Port:u6|SA[8] at LCFF_X18_Y11_N21
G1_SA[8] = DFFEAS(G1L83, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[9] is Sdram_Control_4Port:u6|SA[9] at LCFF_X18_Y11_N25
G1_SA[9] = DFFEAS(G1L84, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[10] is Sdram_Control_4Port:u6|SA[10] at LCFF_X19_Y12_N21
G1_SA[10] = DFFEAS(G1L85, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[11] is Sdram_Control_4Port:u6|SA[11] at LCFF_X19_Y10_N23
G1_SA[11] = DFFEAS(G1L86, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_DQM[1] is Sdram_Control_4Port:u6|DQM[1] at LCFF_X19_Y11_N9
G1_DQM[1] = DFFEAS(G1L17, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_WE_N is Sdram_Control_4Port:u6|WE_N at LCFF_X19_Y10_N17
G1_WE_N = DFFEAS(G1L115, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_CAS_N is Sdram_Control_4Port:u6|CAS_N at LCFF_X19_Y10_N27
G1_CAS_N = DFFEAS(G1L7, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_RAS_N is Sdram_Control_4Port:u6|RAS_N at LCFF_X19_Y10_N15
G1_RAS_N = DFFEAS(G1L53, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_CS_N[0] is Sdram_Control_4Port:u6|CS_N[0] at LCFF_X19_Y10_N5
G1_CS_N[0] = DFFEAS(G1L14, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_BA[0] is Sdram_Control_4Port:u6|BA[0] at LCFF_X20_Y12_N7
G1_BA[0] = DFFEAS(G1L3, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_BA[1] is Sdram_Control_4Port:u6|BA[1] at LCFF_X19_Y12_N23
G1_BA[1] = DFFEAS(G1L5, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--KB1__clk0 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 at PLL_1
KB1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());

--KB1__clk1 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1 at PLL_1
KB1__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());


--CCD_MCLK is CCD_MCLK at LCFF_X58_Y32_N15
CCD_MCLK = DFFEAS(A1L8, GLOBAL(A1L15),  ,  ,  ,  ,  ,  ,  );


--B1_oVGA_H_SYNC is VGA_Controller:u1|oVGA_H_SYNC at LCFF_X19_Y35_N1
B1_oVGA_H_SYNC = DFFEAS(B1L42, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  ,  ,  );


--B1_oVGA_V_SYNC is VGA_Controller:u1|oVGA_V_SYNC at LCFF_X19_Y35_N27
B1_oVGA_V_SYNC = DFFEAS(B1L117, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  ,  ,  );


--B1_oVGA_BLANK is VGA_Controller:u1|oVGA_BLANK at LCCOMB_X19_Y35_N18
B1_oVGA_BLANK = B1_oVGA_V_SYNC & B1_oVGA_H_SYNC;


--GB4_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0] at M4K_X26_Y16
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 6, Port B Depth: 512, Port B Width: 6
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0] = GB4_q_a[0]_PORT_A_data_out_reg[0];

--GB4_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14] at M4K_X26_Y16
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[14] = GB4_q_a[0]_PORT_A_data_out_reg[5];

--GB4_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13] at M4K_X26_Y16
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[13] = GB4_q_a[0]_PORT_A_data_out_reg[4];

--GB4_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10] at M4K_X26_Y16
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[10] = GB4_q_a[0]_PORT_A_data_out_reg[3];

--GB4_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8] at M4K_X26_Y16
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[8] = GB4_q_a[0]_PORT_A_data_out_reg[2];

--GB4_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3] at M4K_X26_Y16
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[3] = GB4_q_a[0]_PORT_A_data_out_reg[1];


--B1_V_Cont[6] is VGA_Controller:u1|V_Cont[6] at LCFF_X20_Y35_N13
B1_V_Cont[6] = DFFEAS(B1L68, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[7] is VGA_Controller:u1|V_Cont[7] at LCFF_X20_Y35_N15
B1_V_Cont[7] = DFFEAS(B1L71, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[8] is VGA_Controller:u1|V_Cont[8] at LCFF_X20_Y35_N17
B1_V_Cont[8] = DFFEAS(B1L74, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1L38 is VGA_Controller:u1|LessThan~1087 at LCCOMB_X20_Y35_N30
B1L38 = !B1_V_Cont[8] & !B1_V_Cont[7] & !B1_V_Cont[6];


--B1_V_Cont[1] is VGA_Controller:u1|V_Cont[1] at LCFF_X20_Y35_N3
B1_V_Cont[1] = DFFEAS(B1L53, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[2] is VGA_Controller:u1|V_Cont[2] at LCFF_X20_Y35_N5
B1_V_Cont[2] = DFFEAS(B1L56, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[3] is VGA_Controller:u1|V_Cont[3] at LCFF_X20_Y35_N7
B1_V_Cont[3] = DFFEAS(B1L59, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1L39 is VGA_Controller:u1|LessThan~1088 at LCCOMB_X20_Y35_N24
B1L39 = !B1_V_Cont[3] & !B1_V_Cont[2] & !B1_V_Cont[1];


--B1_V_Cont[4] is VGA_Controller:u1|V_Cont[4] at LCFF_X20_Y35_N9
B1_V_Cont[4] = DFFEAS(B1L62, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[5] is VGA_Controller:u1|V_Cont[5] at LCFF_X20_Y35_N11
B1_V_Cont[5] = DFFEAS(B1L65, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1L40 is VGA_Controller:u1|LessThan~1089 at LCCOMB_X19_Y35_N2
B1L40 = !B1_V_Cont[4] & B1L39 # !B1_V_Cont[5];


--B1_V_Cont[9] is VGA_Controller:u1|V_Cont[9] at LCFF_X20_Y35_N19
B1_V_Cont[9] = DFFEAS(B1L77, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1L41 is VGA_Controller:u1|LessThan~1090 at LCCOMB_X19_Y35_N10
B1L41 = B1_V_Cont[5] # B1_V_Cont[4] # !B1L39 # !B1L38;


--B1L114 is VGA_Controller:u1|oVGA_R~266 at LCCOMB_X19_Y35_N28
B1L114 = B1_V_Cont[9] & (!B1L41) # !B1_V_Cont[9] & (!B1L40 # !B1L38);


--B1_H_Cont[4] is VGA_Controller:u1|H_Cont[4] at LCFF_X18_Y35_N13
B1_H_Cont[4] = DFFEAS(B1L20, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1_H_Cont[5] is VGA_Controller:u1|H_Cont[5] at LCFF_X18_Y35_N15
B1_H_Cont[5] = DFFEAS(B1L23, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1_H_Cont[6] is VGA_Controller:u1|H_Cont[6] at LCFF_X18_Y35_N17
B1_H_Cont[6] = DFFEAS(B1L27, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1L1 is VGA_Controller:u1|Equal~115 at LCCOMB_X18_Y35_N30
B1L1 = !B1_H_Cont[6] & !B1_H_Cont[5] & !B1_H_Cont[4];


--B1_H_Cont[7] is VGA_Controller:u1|H_Cont[7] at LCFF_X18_Y35_N19
B1_H_Cont[7] = DFFEAS(B1L30, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1_H_Cont[8] is VGA_Controller:u1|H_Cont[8] at LCFF_X18_Y35_N21
B1_H_Cont[8] = DFFEAS(B1L33, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1_H_Cont[9] is VGA_Controller:u1|H_Cont[9] at LCFF_X18_Y35_N23
B1_H_Cont[9] = DFFEAS(B1L36, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1L115 is VGA_Controller:u1|oVGA_R~267 at LCCOMB_X19_Y35_N16
B1L115 = B1_H_Cont[8] & (!B1_H_Cont[7] & B1L1 # !B1_H_Cont[9]) # !B1_H_Cont[8] & (B1_H_Cont[9] # B1_H_Cont[7] & !B1L1);


--B1L104 is VGA_Controller:u1|oVGA_R[0]~268 at LCCOMB_X25_Y25_N22
B1L104 = B1L114 & B1L115 & GB4_q_a[0];


--GB4_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1] at M4K_X26_Y17
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 9, Port B Depth: 512, Port B Width: 9
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1] = GB4_q_a[1]_PORT_A_data_out_reg[0];

--GB4_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[12] = GB4_q_a[1]_PORT_A_data_out_reg[8];

--GB4_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[11] = GB4_q_a[1]_PORT_A_data_out_reg[7];

--GB4_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[9] = GB4_q_a[1]_PORT_A_data_out_reg[6];

--GB4_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[7] = GB4_q_a[1]_PORT_A_data_out_reg[5];

--GB4_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[6] = GB4_q_a[1]_PORT_A_data_out_reg[4];

--GB4_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[5] = GB4_q_a[1]_PORT_A_data_out_reg[3];

--GB4_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[4] = GB4_q_a[1]_PORT_A_data_out_reg[2];

--GB4_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[2] = GB4_q_a[1]_PORT_A_data_out_reg[1];


--B1L105 is VGA_Controller:u1|oVGA_R[1]~269 at LCCOMB_X25_Y26_N22
B1L105 = GB4_q_a[1] & B1L114 & B1L115;


--B1L106 is VGA_Controller:u1|oVGA_R[2]~270 at LCCOMB_X25_Y25_N24
B1L106 = B1L114 & GB4_q_a[2] & B1L115;


--B1L107 is VGA_Controller:u1|oVGA_R[3]~271 at LCCOMB_X25_Y26_N4
B1L107 = GB4_q_a[3] & B1L114 & B1L115;


--B1L108 is VGA_Controller:u1|oVGA_R[4]~272 at LCCOMB_X25_Y25_N16
B1L108 = B1L114 & GB4_q_a[4] & B1L115;


--B1L109 is VGA_Controller:u1|oVGA_R[5]~273 at LCCOMB_X25_Y25_N20
B1L109 = B1L114 & GB4_q_a[5] & B1L115;


--B1L110 is VGA_Controller:u1|oVGA_R[6]~274 at LCCOMB_X25_Y26_N18
B1L110 = GB4_q_a[6] & B1L114 & B1L115;


--B1L111 is VGA_Controller:u1|oVGA_R[7]~275 at LCCOMB_X25_Y25_N26
B1L111 = B1L114 & GB4_q_a[7] & B1L115;


--B1L112 is VGA_Controller:u1|oVGA_R[8]~276 at LCCOMB_X25_Y25_N14
B1L112 = B1L114 & GB4_q_a[8] & B1L115;


--B1L113 is VGA_Controller:u1|oVGA_R[9]~277 at LCCOMB_X25_Y26_N12
B1L113 = B1L114 & GB4_q_a[9] & B1L115;


--B1L93 is VGA_Controller:u1|oVGA_G[0]~110 at LCCOMB_X25_Y25_N18
B1L93 = B1L114 & GB4_q_a[10] & B1L115;


--B1L94 is VGA_Controller:u1|oVGA_G[1]~111 at LCCOMB_X25_Y26_N20
B1L94 = B1L114 & GB4_q_a[11] & B1L115;


--B1L95 is VGA_Controller:u1|oVGA_G[2]~112 at LCCOMB_X25_Y26_N6
B1L95 = GB4_q_a[12] & B1L114 & B1L115;


--B1L96 is VGA_Controller:u1|oVGA_G[3]~113 at LCCOMB_X25_Y25_N28
B1L96 = B1L114 & GB4_q_a[13] & B1L115;


--B1L97 is VGA_Controller:u1|oVGA_G[4]~114 at LCCOMB_X25_Y26_N14
B1L97 = GB4_q_a[14] & B1L114 & B1L115;


--B1L98 is VGA_Controller:u1|oVGA_G[5]~115 at LCCOMB_X25_Y26_N24
B1L98 = B1L114 & GB3_q_a[10] & B1L115;


--B1L99 is VGA_Controller:u1|oVGA_G[6]~116 at LCCOMB_X25_Y25_N0
B1L99 = B1L114 & GB3_q_a[11] & B1L115;


--B1L100 is VGA_Controller:u1|oVGA_G[7]~117 at LCCOMB_X25_Y26_N10
B1L100 = B1L114 & GB3_q_a[12] & B1L115;


--B1L101 is VGA_Controller:u1|oVGA_G[8]~118 at LCCOMB_X25_Y25_N12
B1L101 = B1L114 & GB3_q_a[13] & B1L115;


--B1L102 is VGA_Controller:u1|oVGA_G[9]~119 at LCCOMB_X25_Y25_N2
B1L102 = B1L114 & GB3_q_a[14] & B1L115;


--GB3_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0] at M4K_X26_Y20
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 6, Port B Depth: 512, Port B Width: 6
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[0]_PORT_A_data_in_reg = DFFE(GB3_q_a[0]_PORT_A_data_in, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[2], G1_mDATAOUT[5], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[14]);
GB3_q_a[0]_PORT_B_data_in_reg = DFFE(GB3_q_a[0]_PORT_B_data_in, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[0]_PORT_A_address_reg = DFFE(GB3_q_a[0]_PORT_A_address, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[0]_PORT_B_address_reg = DFFE(GB3_q_a[0]_PORT_B_address, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_write_enable = GND;
GB3_q_a[0]_PORT_A_write_enable_reg = DFFE(GB3_q_a[0]_PORT_A_write_enable, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[0]_PORT_B_write_enable_reg = DFFE(GB3_q_a[0]_PORT_B_write_enable, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_clock_0 = GLOBAL(A1L9);
GB3_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[0]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[0]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[0]_PORT_A_data_out = MEMORY(GB3_q_a[0]_PORT_A_data_in_reg, GB3_q_a[0]_PORT_B_data_in_reg, GB3_q_a[0]_PORT_A_address_reg, GB3_q_a[0]_PORT_B_address_reg, GB3_q_a[0]_PORT_A_write_enable_reg, GB3_q_a[0]_PORT_B_write_enable_reg, , , GB3_q_a[0]_clock_0, GB3_q_a[0]_clock_1, GB3_q_a[0]_clock_enable_0, GB3_q_a[0]_clock_enable_1, , GB3_q_a[0]_clear_1);
GB3_q_a[0]_PORT_A_data_out_reg = DFFE(GB3_q_a[0]_PORT_A_data_out, GB3_q_a[0]_clock_0, GB3_q_a[0]_clear_1, , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0] = GB3_q_a[0]_PORT_A_data_out_reg[0];

--GB3_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14] at M4K_X26_Y20
GB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[0]_PORT_A_data_in_reg = DFFE(GB3_q_a[0]_PORT_A_data_in, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[2], G1_mDATAOUT[5], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[14]);
GB3_q_a[0]_PORT_B_data_in_reg = DFFE(GB3_q_a[0]_PORT_B_data_in, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[0]_PORT_A_address_reg = DFFE(GB3_q_a[0]_PORT_A_address, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[0]_PORT_B_address_reg = DFFE(GB3_q_a[0]_PORT_B_address, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_write_enable = GND;
GB3_q_a[0]_PORT_A_write_enable_reg = DFFE(GB3_q_a[0]_PORT_A_write_enable, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[0]_PORT_B_write_enable_reg = DFFE(GB3_q_a[0]_PORT_B_write_enable, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_clock_0 = GLOBAL(A1L9);
GB3_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[0]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[0]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[0]_PORT_A_data_out = MEMORY(GB3_q_a[0]_PORT_A_data_in_reg, GB3_q_a[0]_PORT_B_data_in_reg, GB3_q_a[0]_PORT_A_address_reg, GB3_q_a[0]_PORT_B_address_reg, GB3_q_a[0]_PORT_A_write_enable_reg, GB3_q_a[0]_PORT_B_write_enable_reg, , , GB3_q_a[0]_clock_0, GB3_q_a[0]_clock_1, GB3_q_a[0]_clock_enable_0, GB3_q_a[0]_clock_enable_1, , GB3_q_a[0]_clear_1);
GB3_q_a[0]_PORT_A_data_out_reg = DFFE(GB3_q_a[0]_PORT_A_data_out, GB3_q_a[0]_clock_0, GB3_q_a[0]_clear_1, , GB3_q_a[0]_clock_enable_0);
GB3_q_a[14] = GB3_q_a[0]_PORT_A_data_out_reg[5];

--GB3_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11] at M4K_X26_Y20
GB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[0]_PORT_A_data_in_reg = DFFE(GB3_q_a[0]_PORT_A_data_in, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[2], G1_mDATAOUT[5], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[14]);
GB3_q_a[0]_PORT_B_data_in_reg = DFFE(GB3_q_a[0]_PORT_B_data_in, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[0]_PORT_A_address_reg = DFFE(GB3_q_a[0]_PORT_A_address, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[0]_PORT_B_address_reg = DFFE(GB3_q_a[0]_PORT_B_address, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_write_enable = GND;
GB3_q_a[0]_PORT_A_write_enable_reg = DFFE(GB3_q_a[0]_PORT_A_write_enable, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[0]_PORT_B_write_enable_reg = DFFE(GB3_q_a[0]_PORT_B_write_enable, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_clock_0 = GLOBAL(A1L9);
GB3_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[0]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[0]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[0]_PORT_A_data_out = MEMORY(GB3_q_a[0]_PORT_A_data_in_reg, GB3_q_a[0]_PORT_B_data_in_reg, GB3_q_a[0]_PORT_A_address_reg, GB3_q_a[0]_PORT_B_address_reg, GB3_q_a[0]_PORT_A_write_enable_reg, GB3_q_a[0]_PORT_B_write_enable_reg, , , GB3_q_a[0]_clock_0, GB3_q_a[0]_clock_1, GB3_q_a[0]_clock_enable_0, GB3_q_a[0]_clock_enable_1, , GB3_q_a[0]_clear_1);
GB3_q_a[0]_PORT_A_data_out_reg = DFFE(GB3_q_a[0]_PORT_A_data_out, GB3_q_a[0]_clock_0, GB3_q_a[0]_clear_1, , GB3_q_a[0]_clock_enable_0);
GB3_q_a[11] = GB3_q_a[0]_PORT_A_data_out_reg[4];

--GB3_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9] at M4K_X26_Y20
GB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[0]_PORT_A_data_in_reg = DFFE(GB3_q_a[0]_PORT_A_data_in, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[2], G1_mDATAOUT[5], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[14]);
GB3_q_a[0]_PORT_B_data_in_reg = DFFE(GB3_q_a[0]_PORT_B_data_in, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[0]_PORT_A_address_reg = DFFE(GB3_q_a[0]_PORT_A_address, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[0]_PORT_B_address_reg = DFFE(GB3_q_a[0]_PORT_B_address, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_write_enable = GND;
GB3_q_a[0]_PORT_A_write_enable_reg = DFFE(GB3_q_a[0]_PORT_A_write_enable, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[0]_PORT_B_write_enable_reg = DFFE(GB3_q_a[0]_PORT_B_write_enable, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_clock_0 = GLOBAL(A1L9);
GB3_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[0]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[0]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[0]_PORT_A_data_out = MEMORY(GB3_q_a[0]_PORT_A_data_in_reg, GB3_q_a[0]_PORT_B_data_in_reg, GB3_q_a[0]_PORT_A_address_reg, GB3_q_a[0]_PORT_B_address_reg, GB3_q_a[0]_PORT_A_write_enable_reg, GB3_q_a[0]_PORT_B_write_enable_reg, , , GB3_q_a[0]_clock_0, GB3_q_a[0]_clock_1, GB3_q_a[0]_clock_enable_0, GB3_q_a[0]_clock_enable_1, , GB3_q_a[0]_clear_1);
GB3_q_a[0]_PORT_A_data_out_reg = DFFE(GB3_q_a[0]_PORT_A_data_out, GB3_q_a[0]_clock_0, GB3_q_a[0]_clear_1, , GB3_q_a[0]_clock_enable_0);
GB3_q_a[9] = GB3_q_a[0]_PORT_A_data_out_reg[3];

--GB3_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5] at M4K_X26_Y20
GB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[0]_PORT_A_data_in_reg = DFFE(GB3_q_a[0]_PORT_A_data_in, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[2], G1_mDATAOUT[5], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[14]);
GB3_q_a[0]_PORT_B_data_in_reg = DFFE(GB3_q_a[0]_PORT_B_data_in, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[0]_PORT_A_address_reg = DFFE(GB3_q_a[0]_PORT_A_address, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[0]_PORT_B_address_reg = DFFE(GB3_q_a[0]_PORT_B_address, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_write_enable = GND;
GB3_q_a[0]_PORT_A_write_enable_reg = DFFE(GB3_q_a[0]_PORT_A_write_enable, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[0]_PORT_B_write_enable_reg = DFFE(GB3_q_a[0]_PORT_B_write_enable, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_clock_0 = GLOBAL(A1L9);
GB3_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[0]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[0]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[0]_PORT_A_data_out = MEMORY(GB3_q_a[0]_PORT_A_data_in_reg, GB3_q_a[0]_PORT_B_data_in_reg, GB3_q_a[0]_PORT_A_address_reg, GB3_q_a[0]_PORT_B_address_reg, GB3_q_a[0]_PORT_A_write_enable_reg, GB3_q_a[0]_PORT_B_write_enable_reg, , , GB3_q_a[0]_clock_0, GB3_q_a[0]_clock_1, GB3_q_a[0]_clock_enable_0, GB3_q_a[0]_clock_enable_1, , GB3_q_a[0]_clear_1);
GB3_q_a[0]_PORT_A_data_out_reg = DFFE(GB3_q_a[0]_PORT_A_data_out, GB3_q_a[0]_clock_0, GB3_q_a[0]_clear_1, , GB3_q_a[0]_clock_enable_0);
GB3_q_a[5] = GB3_q_a[0]_PORT_A_data_out_reg[2];

--GB3_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2] at M4K_X26_Y20
GB3_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[0]_PORT_A_data_in_reg = DFFE(GB3_q_a[0]_PORT_A_data_in, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[2], G1_mDATAOUT[5], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[14]);
GB3_q_a[0]_PORT_B_data_in_reg = DFFE(GB3_q_a[0]_PORT_B_data_in, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[0]_PORT_A_address_reg = DFFE(GB3_q_a[0]_PORT_A_address, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[0]_PORT_B_address_reg = DFFE(GB3_q_a[0]_PORT_B_address, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_PORT_A_write_enable = GND;
GB3_q_a[0]_PORT_A_write_enable_reg = DFFE(GB3_q_a[0]_PORT_A_write_enable, GB3_q_a[0]_clock_0, , , GB3_q_a[0]_clock_enable_0);
GB3_q_a[0]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[0]_PORT_B_write_enable_reg = DFFE(GB3_q_a[0]_PORT_B_write_enable, GB3_q_a[0]_clock_1, , , GB3_q_a[0]_clock_enable_1);
GB3_q_a[0]_clock_0 = GLOBAL(A1L9);
GB3_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[0]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[0]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[0]_PORT_A_data_out = MEMORY(GB3_q_a[0]_PORT_A_data_in_reg, GB3_q_a[0]_PORT_B_data_in_reg, GB3_q_a[0]_PORT_A_address_reg, GB3_q_a[0]_PORT_B_address_reg, GB3_q_a[0]_PORT_A_write_enable_reg, GB3_q_a[0]_PORT_B_write_enable_reg, , , GB3_q_a[0]_clock_0, GB3_q_a[0]_clock_1, GB3_q_a[0]_clock_enable_0, GB3_q_a[0]_clock_enable_1, , GB3_q_a[0]_clear_1);
GB3_q_a[0]_PORT_A_data_out_reg = DFFE(GB3_q_a[0]_PORT_A_data_out, GB3_q_a[0]_clock_0, GB3_q_a[0]_clear_1, , GB3_q_a[0]_clock_enable_0);
GB3_q_a[2] = GB3_q_a[0]_PORT_A_data_out_reg[1];


--B1L83 is VGA_Controller:u1|oVGA_B[0]~110 at LCCOMB_X25_Y25_N8
B1L83 = B1L114 & GB3_q_a[0] & B1L115;


--GB3_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1] at M4K_X26_Y19
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 9, Port B Depth: 512, Port B Width: 9
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[1]_PORT_A_data_in_reg = DFFE(GB3_q_a[1]_PORT_A_data_in, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[3], G1_mDATAOUT[4], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[12], G1_mDATAOUT[13]);
GB3_q_a[1]_PORT_B_data_in_reg = DFFE(GB3_q_a[1]_PORT_B_data_in, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[1]_PORT_A_address_reg = DFFE(GB3_q_a[1]_PORT_A_address, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[1]_PORT_B_address_reg = DFFE(GB3_q_a[1]_PORT_B_address, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_write_enable = GND;
GB3_q_a[1]_PORT_A_write_enable_reg = DFFE(GB3_q_a[1]_PORT_A_write_enable, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[1]_PORT_B_write_enable_reg = DFFE(GB3_q_a[1]_PORT_B_write_enable, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_clock_0 = GLOBAL(A1L9);
GB3_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[1]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[1]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[1]_PORT_A_data_out = MEMORY(GB3_q_a[1]_PORT_A_data_in_reg, GB3_q_a[1]_PORT_B_data_in_reg, GB3_q_a[1]_PORT_A_address_reg, GB3_q_a[1]_PORT_B_address_reg, GB3_q_a[1]_PORT_A_write_enable_reg, GB3_q_a[1]_PORT_B_write_enable_reg, , , GB3_q_a[1]_clock_0, GB3_q_a[1]_clock_1, GB3_q_a[1]_clock_enable_0, GB3_q_a[1]_clock_enable_1, , GB3_q_a[1]_clear_1);
GB3_q_a[1]_PORT_A_data_out_reg = DFFE(GB3_q_a[1]_PORT_A_data_out, GB3_q_a[1]_clock_0, GB3_q_a[1]_clear_1, , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1] = GB3_q_a[1]_PORT_A_data_out_reg[0];

--GB3_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13] at M4K_X26_Y19
GB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[1]_PORT_A_data_in_reg = DFFE(GB3_q_a[1]_PORT_A_data_in, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[3], G1_mDATAOUT[4], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[12], G1_mDATAOUT[13]);
GB3_q_a[1]_PORT_B_data_in_reg = DFFE(GB3_q_a[1]_PORT_B_data_in, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[1]_PORT_A_address_reg = DFFE(GB3_q_a[1]_PORT_A_address, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[1]_PORT_B_address_reg = DFFE(GB3_q_a[1]_PORT_B_address, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_write_enable = GND;
GB3_q_a[1]_PORT_A_write_enable_reg = DFFE(GB3_q_a[1]_PORT_A_write_enable, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[1]_PORT_B_write_enable_reg = DFFE(GB3_q_a[1]_PORT_B_write_enable, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_clock_0 = GLOBAL(A1L9);
GB3_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[1]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[1]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[1]_PORT_A_data_out = MEMORY(GB3_q_a[1]_PORT_A_data_in_reg, GB3_q_a[1]_PORT_B_data_in_reg, GB3_q_a[1]_PORT_A_address_reg, GB3_q_a[1]_PORT_B_address_reg, GB3_q_a[1]_PORT_A_write_enable_reg, GB3_q_a[1]_PORT_B_write_enable_reg, , , GB3_q_a[1]_clock_0, GB3_q_a[1]_clock_1, GB3_q_a[1]_clock_enable_0, GB3_q_a[1]_clock_enable_1, , GB3_q_a[1]_clear_1);
GB3_q_a[1]_PORT_A_data_out_reg = DFFE(GB3_q_a[1]_PORT_A_data_out, GB3_q_a[1]_clock_0, GB3_q_a[1]_clear_1, , GB3_q_a[1]_clock_enable_0);
GB3_q_a[13] = GB3_q_a[1]_PORT_A_data_out_reg[8];

--GB3_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12] at M4K_X26_Y19
GB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[1]_PORT_A_data_in_reg = DFFE(GB3_q_a[1]_PORT_A_data_in, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[3], G1_mDATAOUT[4], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[12], G1_mDATAOUT[13]);
GB3_q_a[1]_PORT_B_data_in_reg = DFFE(GB3_q_a[1]_PORT_B_data_in, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[1]_PORT_A_address_reg = DFFE(GB3_q_a[1]_PORT_A_address, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[1]_PORT_B_address_reg = DFFE(GB3_q_a[1]_PORT_B_address, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_write_enable = GND;
GB3_q_a[1]_PORT_A_write_enable_reg = DFFE(GB3_q_a[1]_PORT_A_write_enable, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[1]_PORT_B_write_enable_reg = DFFE(GB3_q_a[1]_PORT_B_write_enable, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_clock_0 = GLOBAL(A1L9);
GB3_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[1]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[1]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[1]_PORT_A_data_out = MEMORY(GB3_q_a[1]_PORT_A_data_in_reg, GB3_q_a[1]_PORT_B_data_in_reg, GB3_q_a[1]_PORT_A_address_reg, GB3_q_a[1]_PORT_B_address_reg, GB3_q_a[1]_PORT_A_write_enable_reg, GB3_q_a[1]_PORT_B_write_enable_reg, , , GB3_q_a[1]_clock_0, GB3_q_a[1]_clock_1, GB3_q_a[1]_clock_enable_0, GB3_q_a[1]_clock_enable_1, , GB3_q_a[1]_clear_1);
GB3_q_a[1]_PORT_A_data_out_reg = DFFE(GB3_q_a[1]_PORT_A_data_out, GB3_q_a[1]_clock_0, GB3_q_a[1]_clear_1, , GB3_q_a[1]_clock_enable_0);
GB3_q_a[12] = GB3_q_a[1]_PORT_A_data_out_reg[7];

--GB3_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10] at M4K_X26_Y19
GB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[1]_PORT_A_data_in_reg = DFFE(GB3_q_a[1]_PORT_A_data_in, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[3], G1_mDATAOUT[4], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[12], G1_mDATAOUT[13]);
GB3_q_a[1]_PORT_B_data_in_reg = DFFE(GB3_q_a[1]_PORT_B_data_in, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[1]_PORT_A_address_reg = DFFE(GB3_q_a[1]_PORT_A_address, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[1]_PORT_B_address_reg = DFFE(GB3_q_a[1]_PORT_B_address, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_write_enable = GND;
GB3_q_a[1]_PORT_A_write_enable_reg = DFFE(GB3_q_a[1]_PORT_A_write_enable, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[1]_PORT_B_write_enable_reg = DFFE(GB3_q_a[1]_PORT_B_write_enable, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_clock_0 = GLOBAL(A1L9);
GB3_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[1]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[1]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[1]_PORT_A_data_out = MEMORY(GB3_q_a[1]_PORT_A_data_in_reg, GB3_q_a[1]_PORT_B_data_in_reg, GB3_q_a[1]_PORT_A_address_reg, GB3_q_a[1]_PORT_B_address_reg, GB3_q_a[1]_PORT_A_write_enable_reg, GB3_q_a[1]_PORT_B_write_enable_reg, , , GB3_q_a[1]_clock_0, GB3_q_a[1]_clock_1, GB3_q_a[1]_clock_enable_0, GB3_q_a[1]_clock_enable_1, , GB3_q_a[1]_clear_1);
GB3_q_a[1]_PORT_A_data_out_reg = DFFE(GB3_q_a[1]_PORT_A_data_out, GB3_q_a[1]_clock_0, GB3_q_a[1]_clear_1, , GB3_q_a[1]_clock_enable_0);
GB3_q_a[10] = GB3_q_a[1]_PORT_A_data_out_reg[6];

--GB3_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8] at M4K_X26_Y19
GB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[1]_PORT_A_data_in_reg = DFFE(GB3_q_a[1]_PORT_A_data_in, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[3], G1_mDATAOUT[4], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[12], G1_mDATAOUT[13]);
GB3_q_a[1]_PORT_B_data_in_reg = DFFE(GB3_q_a[1]_PORT_B_data_in, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[1]_PORT_A_address_reg = DFFE(GB3_q_a[1]_PORT_A_address, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[1]_PORT_B_address_reg = DFFE(GB3_q_a[1]_PORT_B_address, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_write_enable = GND;
GB3_q_a[1]_PORT_A_write_enable_reg = DFFE(GB3_q_a[1]_PORT_A_write_enable, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[1]_PORT_B_write_enable_reg = DFFE(GB3_q_a[1]_PORT_B_write_enable, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_clock_0 = GLOBAL(A1L9);
GB3_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[1]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[1]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[1]_PORT_A_data_out = MEMORY(GB3_q_a[1]_PORT_A_data_in_reg, GB3_q_a[1]_PORT_B_data_in_reg, GB3_q_a[1]_PORT_A_address_reg, GB3_q_a[1]_PORT_B_address_reg, GB3_q_a[1]_PORT_A_write_enable_reg, GB3_q_a[1]_PORT_B_write_enable_reg, , , GB3_q_a[1]_clock_0, GB3_q_a[1]_clock_1, GB3_q_a[1]_clock_enable_0, GB3_q_a[1]_clock_enable_1, , GB3_q_a[1]_clear_1);
GB3_q_a[1]_PORT_A_data_out_reg = DFFE(GB3_q_a[1]_PORT_A_data_out, GB3_q_a[1]_clock_0, GB3_q_a[1]_clear_1, , GB3_q_a[1]_clock_enable_0);
GB3_q_a[8] = GB3_q_a[1]_PORT_A_data_out_reg[5];

--GB3_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7] at M4K_X26_Y19
GB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[1]_PORT_A_data_in_reg = DFFE(GB3_q_a[1]_PORT_A_data_in, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[3], G1_mDATAOUT[4], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[12], G1_mDATAOUT[13]);
GB3_q_a[1]_PORT_B_data_in_reg = DFFE(GB3_q_a[1]_PORT_B_data_in, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[1]_PORT_A_address_reg = DFFE(GB3_q_a[1]_PORT_A_address, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[1]_PORT_B_address_reg = DFFE(GB3_q_a[1]_PORT_B_address, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_write_enable = GND;
GB3_q_a[1]_PORT_A_write_enable_reg = DFFE(GB3_q_a[1]_PORT_A_write_enable, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[1]_PORT_B_write_enable_reg = DFFE(GB3_q_a[1]_PORT_B_write_enable, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_clock_0 = GLOBAL(A1L9);
GB3_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[1]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[1]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[1]_PORT_A_data_out = MEMORY(GB3_q_a[1]_PORT_A_data_in_reg, GB3_q_a[1]_PORT_B_data_in_reg, GB3_q_a[1]_PORT_A_address_reg, GB3_q_a[1]_PORT_B_address_reg, GB3_q_a[1]_PORT_A_write_enable_reg, GB3_q_a[1]_PORT_B_write_enable_reg, , , GB3_q_a[1]_clock_0, GB3_q_a[1]_clock_1, GB3_q_a[1]_clock_enable_0, GB3_q_a[1]_clock_enable_1, , GB3_q_a[1]_clear_1);
GB3_q_a[1]_PORT_A_data_out_reg = DFFE(GB3_q_a[1]_PORT_A_data_out, GB3_q_a[1]_clock_0, GB3_q_a[1]_clear_1, , GB3_q_a[1]_clock_enable_0);
GB3_q_a[7] = GB3_q_a[1]_PORT_A_data_out_reg[4];

--GB3_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6] at M4K_X26_Y19
GB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[1]_PORT_A_data_in_reg = DFFE(GB3_q_a[1]_PORT_A_data_in, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[3], G1_mDATAOUT[4], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[12], G1_mDATAOUT[13]);
GB3_q_a[1]_PORT_B_data_in_reg = DFFE(GB3_q_a[1]_PORT_B_data_in, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[1]_PORT_A_address_reg = DFFE(GB3_q_a[1]_PORT_A_address, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[1]_PORT_B_address_reg = DFFE(GB3_q_a[1]_PORT_B_address, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_write_enable = GND;
GB3_q_a[1]_PORT_A_write_enable_reg = DFFE(GB3_q_a[1]_PORT_A_write_enable, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[1]_PORT_B_write_enable_reg = DFFE(GB3_q_a[1]_PORT_B_write_enable, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_clock_0 = GLOBAL(A1L9);
GB3_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[1]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[1]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[1]_PORT_A_data_out = MEMORY(GB3_q_a[1]_PORT_A_data_in_reg, GB3_q_a[1]_PORT_B_data_in_reg, GB3_q_a[1]_PORT_A_address_reg, GB3_q_a[1]_PORT_B_address_reg, GB3_q_a[1]_PORT_A_write_enable_reg, GB3_q_a[1]_PORT_B_write_enable_reg, , , GB3_q_a[1]_clock_0, GB3_q_a[1]_clock_1, GB3_q_a[1]_clock_enable_0, GB3_q_a[1]_clock_enable_1, , GB3_q_a[1]_clear_1);
GB3_q_a[1]_PORT_A_data_out_reg = DFFE(GB3_q_a[1]_PORT_A_data_out, GB3_q_a[1]_clock_0, GB3_q_a[1]_clear_1, , GB3_q_a[1]_clock_enable_0);
GB3_q_a[6] = GB3_q_a[1]_PORT_A_data_out_reg[3];

--GB3_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4] at M4K_X26_Y19
GB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[1]_PORT_A_data_in_reg = DFFE(GB3_q_a[1]_PORT_A_data_in, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[3], G1_mDATAOUT[4], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[12], G1_mDATAOUT[13]);
GB3_q_a[1]_PORT_B_data_in_reg = DFFE(GB3_q_a[1]_PORT_B_data_in, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[1]_PORT_A_address_reg = DFFE(GB3_q_a[1]_PORT_A_address, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[1]_PORT_B_address_reg = DFFE(GB3_q_a[1]_PORT_B_address, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_write_enable = GND;
GB3_q_a[1]_PORT_A_write_enable_reg = DFFE(GB3_q_a[1]_PORT_A_write_enable, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[1]_PORT_B_write_enable_reg = DFFE(GB3_q_a[1]_PORT_B_write_enable, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_clock_0 = GLOBAL(A1L9);
GB3_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[1]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[1]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[1]_PORT_A_data_out = MEMORY(GB3_q_a[1]_PORT_A_data_in_reg, GB3_q_a[1]_PORT_B_data_in_reg, GB3_q_a[1]_PORT_A_address_reg, GB3_q_a[1]_PORT_B_address_reg, GB3_q_a[1]_PORT_A_write_enable_reg, GB3_q_a[1]_PORT_B_write_enable_reg, , , GB3_q_a[1]_clock_0, GB3_q_a[1]_clock_1, GB3_q_a[1]_clock_enable_0, GB3_q_a[1]_clock_enable_1, , GB3_q_a[1]_clear_1);
GB3_q_a[1]_PORT_A_data_out_reg = DFFE(GB3_q_a[1]_PORT_A_data_out, GB3_q_a[1]_clock_0, GB3_q_a[1]_clear_1, , GB3_q_a[1]_clock_enable_0);
GB3_q_a[4] = GB3_q_a[1]_PORT_A_data_out_reg[2];

--GB3_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3] at M4K_X26_Y19
GB3_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB3_q_a[1]_PORT_A_data_in_reg = DFFE(GB3_q_a[1]_PORT_A_data_in, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[3], G1_mDATAOUT[4], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[12], G1_mDATAOUT[13]);
GB3_q_a[1]_PORT_B_data_in_reg = DFFE(GB3_q_a[1]_PORT_B_data_in, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_address = BUS(Z3_power_modified_counter_values[0], Z3_power_modified_counter_values[1], Z3_power_modified_counter_values[2], Z3_power_modified_counter_values[3], Z3_power_modified_counter_values[4], Z3_power_modified_counter_values[5], Z3_power_modified_counter_values[6], Z3_power_modified_counter_values[7], Z3_power_modified_counter_values[8]);
GB3_q_a[1]_PORT_A_address_reg = DFFE(GB3_q_a[1]_PORT_A_address, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_address = BUS(X3_wrptr_g[0], X3_wrptr_g[1], X3_wrptr_g[2], X3_wrptr_g[3], X3_wrptr_g[4], X3_wrptr_g[5], X3_wrptr_g[6], X3_wrptr_g[7], X3_wrptr_g[8]);
GB3_q_a[1]_PORT_B_address_reg = DFFE(GB3_q_a[1]_PORT_B_address, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_PORT_A_write_enable = GND;
GB3_q_a[1]_PORT_A_write_enable_reg = DFFE(GB3_q_a[1]_PORT_A_write_enable, GB3_q_a[1]_clock_0, , , GB3_q_a[1]_clock_enable_0);
GB3_q_a[1]_PORT_B_write_enable = X3_valid_wrreq;
GB3_q_a[1]_PORT_B_write_enable_reg = DFFE(GB3_q_a[1]_PORT_B_write_enable, GB3_q_a[1]_clock_1, , , GB3_q_a[1]_clock_enable_1);
GB3_q_a[1]_clock_0 = GLOBAL(A1L9);
GB3_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB3_q_a[1]_clock_enable_0 = X3_valid_rdreq;
GB3_q_a[1]_clock_enable_1 = X3_valid_wrreq;
GB3_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB3_q_a[1]_PORT_A_data_out = MEMORY(GB3_q_a[1]_PORT_A_data_in_reg, GB3_q_a[1]_PORT_B_data_in_reg, GB3_q_a[1]_PORT_A_address_reg, GB3_q_a[1]_PORT_B_address_reg, GB3_q_a[1]_PORT_A_write_enable_reg, GB3_q_a[1]_PORT_B_write_enable_reg, , , GB3_q_a[1]_clock_0, GB3_q_a[1]_clock_1, GB3_q_a[1]_clock_enable_0, GB3_q_a[1]_clock_enable_1, , GB3_q_a[1]_clear_1);
GB3_q_a[1]_PORT_A_data_out_reg = DFFE(GB3_q_a[1]_PORT_A_data_out, GB3_q_a[1]_clock_0, GB3_q_a[1]_clear_1, , GB3_q_a[1]_clock_enable_0);
GB3_q_a[3] = GB3_q_a[1]_PORT_A_data_out_reg[1];


--B1L84 is VGA_Controller:u1|oVGA_B[1]~111 at LCCOMB_X25_Y26_N8
B1L84 = GB3_q_a[1] & B1L114 & B1L115;


--B1L85 is VGA_Controller:u1|oVGA_B[2]~112 at LCCOMB_X25_Y25_N10
B1L85 = B1L114 & GB3_q_a[2] & B1L115;


--B1L86 is VGA_Controller:u1|oVGA_B[3]~113 at LCCOMB_X25_Y25_N6
B1L86 = B1L114 & GB3_q_a[3] & B1L115;


--B1L87 is VGA_Controller:u1|oVGA_B[4]~114 at LCCOMB_X25_Y26_N28
B1L87 = B1L114 & GB3_q_a[4] & B1L115;


--B1L88 is VGA_Controller:u1|oVGA_B[5]~115 at LCCOMB_X25_Y25_N4
B1L88 = B1L114 & GB3_q_a[5] & B1L115;


--B1L89 is VGA_Controller:u1|oVGA_B[6]~116 at LCCOMB_X25_Y26_N30
B1L89 = GB3_q_a[6] & B1L114 & B1L115;


--B1L90 is VGA_Controller:u1|oVGA_B[7]~117 at LCCOMB_X25_Y26_N26
B1L90 = GB3_q_a[7] & B1L114 & B1L115;


--B1L91 is VGA_Controller:u1|oVGA_B[8]~118 at LCCOMB_X25_Y26_N16
B1L91 = GB3_q_a[8] & B1L114 & B1L115;


--B1L92 is VGA_Controller:u1|oVGA_B[9]~119 at LCCOMB_X25_Y25_N30
B1L92 = B1L114 & B1L115 & GB3_q_a[9];


--D1L3 is CCD_Capture:u3|Frame_Cont[0]~1192 at LCCOMB_X12_Y11_N0
D1L3 = D1_Frame_Cont[0] $ VCC;

--D1L4 is CCD_Capture:u3|Frame_Cont[0]~1193 at LCCOMB_X12_Y11_N0
D1L4 = CARRY(D1_Frame_Cont[0]);


--C1_oRST_1 is Reset_Delay:u2|oRST_1 at LCFF_X21_Y16_N5
C1_oRST_1 = DFFEAS(C1L80, GLOBAL(A1L15), KEY[0],  ,  ,  ,  ,  ,  );


--D1_mSTART is CCD_Capture:u3|mSTART at LCFF_X57_Y10_N13
D1_mSTART = DFFEAS(D1L191, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--D1_Pre_FVAL is CCD_Capture:u3|Pre_FVAL at LCFF_X57_Y10_N1
D1_Pre_FVAL = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , rCCD_FVAL,  ,  , VCC);


--D1L167 is CCD_Capture:u3|always2~28 at LCCOMB_X57_Y10_N0
D1L167 = rCCD_FVAL & !D1_Pre_FVAL & D1_mSTART;


--D1L6 is CCD_Capture:u3|Frame_Cont[1]~1194 at LCCOMB_X12_Y11_N2
D1L6 = D1_Frame_Cont[1] & !D1L4 # !D1_Frame_Cont[1] & (D1L4 # GND);

--D1L7 is CCD_Capture:u3|Frame_Cont[1]~1195 at LCCOMB_X12_Y11_N2
D1L7 = CARRY(!D1L4 # !D1_Frame_Cont[1]);


--D1L9 is CCD_Capture:u3|Frame_Cont[2]~1196 at LCCOMB_X12_Y11_N4
D1L9 = D1_Frame_Cont[2] & (D1L7 $ GND) # !D1_Frame_Cont[2] & !D1L7 & VCC;

--D1L10 is CCD_Capture:u3|Frame_Cont[2]~1197 at LCCOMB_X12_Y11_N4
D1L10 = CARRY(D1_Frame_Cont[2] & !D1L7);


--D1L12 is CCD_Capture:u3|Frame_Cont[3]~1198 at LCCOMB_X12_Y11_N6
D1L12 = D1_Frame_Cont[3] & !D1L10 # !D1_Frame_Cont[3] & (D1L10 # GND);

--D1L13 is CCD_Capture:u3|Frame_Cont[3]~1199 at LCCOMB_X12_Y11_N6
D1L13 = CARRY(!D1L10 # !D1_Frame_Cont[3]);


--D1L15 is CCD_Capture:u3|Frame_Cont[4]~1200 at LCCOMB_X12_Y11_N8
D1L15 = D1_Frame_Cont[4] & (D1L13 $ GND) # !D1_Frame_Cont[4] & !D1L13 & VCC;

--D1L16 is CCD_Capture:u3|Frame_Cont[4]~1201 at LCCOMB_X12_Y11_N8
D1L16 = CARRY(D1_Frame_Cont[4] & !D1L13);


--D1L18 is CCD_Capture:u3|Frame_Cont[5]~1202 at LCCOMB_X12_Y11_N10
D1L18 = D1_Frame_Cont[5] & !D1L16 # !D1_Frame_Cont[5] & (D1L16 # GND);

--D1L19 is CCD_Capture:u3|Frame_Cont[5]~1203 at LCCOMB_X12_Y11_N10
D1L19 = CARRY(!D1L16 # !D1_Frame_Cont[5]);


--D1L21 is CCD_Capture:u3|Frame_Cont[6]~1204 at LCCOMB_X12_Y11_N12
D1L21 = D1_Frame_Cont[6] & (D1L19 $ GND) # !D1_Frame_Cont[6] & !D1L19 & VCC;

--D1L22 is CCD_Capture:u3|Frame_Cont[6]~1205 at LCCOMB_X12_Y11_N12
D1L22 = CARRY(D1_Frame_Cont[6] & !D1L19);


--D1L24 is CCD_Capture:u3|Frame_Cont[7]~1206 at LCCOMB_X12_Y11_N14
D1L24 = D1_Frame_Cont[7] & !D1L22 # !D1_Frame_Cont[7] & (D1L22 # GND);

--D1L25 is CCD_Capture:u3|Frame_Cont[7]~1207 at LCCOMB_X12_Y11_N14
D1L25 = CARRY(!D1L22 # !D1_Frame_Cont[7]);


--D1L27 is CCD_Capture:u3|Frame_Cont[8]~1208 at LCCOMB_X12_Y11_N16
D1L27 = D1_Frame_Cont[8] & (D1L25 $ GND) # !D1_Frame_Cont[8] & !D1L25 & VCC;

--D1L28 is CCD_Capture:u3|Frame_Cont[8]~1209 at LCCOMB_X12_Y11_N16
D1L28 = CARRY(D1_Frame_Cont[8] & !D1L25);


--D1L30 is CCD_Capture:u3|Frame_Cont[9]~1210 at LCCOMB_X12_Y11_N18
D1L30 = D1_Frame_Cont[9] & !D1L28 # !D1_Frame_Cont[9] & (D1L28 # GND);

--D1L31 is CCD_Capture:u3|Frame_Cont[9]~1211 at LCCOMB_X12_Y11_N18
D1L31 = CARRY(!D1L28 # !D1_Frame_Cont[9]);


--D1L33 is CCD_Capture:u3|Frame_Cont[10]~1212 at LCCOMB_X12_Y11_N20
D1L33 = D1_Frame_Cont[10] & (D1L31 $ GND) # !D1_Frame_Cont[10] & !D1L31 & VCC;

--D1L34 is CCD_Capture:u3|Frame_Cont[10]~1213 at LCCOMB_X12_Y11_N20
D1L34 = CARRY(D1_Frame_Cont[10] & !D1L31);


--D1L36 is CCD_Capture:u3|Frame_Cont[11]~1214 at LCCOMB_X12_Y11_N22
D1L36 = D1_Frame_Cont[11] & !D1L34 # !D1_Frame_Cont[11] & (D1L34 # GND);

--D1L37 is CCD_Capture:u3|Frame_Cont[11]~1215 at LCCOMB_X12_Y11_N22
D1L37 = CARRY(!D1L34 # !D1_Frame_Cont[11]);


--D1L39 is CCD_Capture:u3|Frame_Cont[12]~1216 at LCCOMB_X12_Y11_N24
D1L39 = D1_Frame_Cont[12] & (D1L37 $ GND) # !D1_Frame_Cont[12] & !D1L37 & VCC;

--D1L40 is CCD_Capture:u3|Frame_Cont[12]~1217 at LCCOMB_X12_Y11_N24
D1L40 = CARRY(D1_Frame_Cont[12] & !D1L37);


--D1L42 is CCD_Capture:u3|Frame_Cont[13]~1218 at LCCOMB_X12_Y11_N26
D1L42 = D1_Frame_Cont[13] & !D1L40 # !D1_Frame_Cont[13] & (D1L40 # GND);

--D1L43 is CCD_Capture:u3|Frame_Cont[13]~1219 at LCCOMB_X12_Y11_N26
D1L43 = CARRY(!D1L40 # !D1_Frame_Cont[13]);


--D1L45 is CCD_Capture:u3|Frame_Cont[14]~1220 at LCCOMB_X12_Y11_N28
D1L45 = D1_Frame_Cont[14] & (D1L43 $ GND) # !D1_Frame_Cont[14] & !D1L43 & VCC;

--D1L46 is CCD_Capture:u3|Frame_Cont[14]~1221 at LCCOMB_X12_Y11_N28
D1L46 = CARRY(D1_Frame_Cont[14] & !D1L43);


--D1L48 is CCD_Capture:u3|Frame_Cont[15]~1222 at LCCOMB_X12_Y11_N30
D1L48 = D1_Frame_Cont[15] & !D1L46 # !D1_Frame_Cont[15] & (D1L46 # GND);

--D1L49 is CCD_Capture:u3|Frame_Cont[15]~1223 at LCCOMB_X12_Y11_N30
D1L49 = CARRY(!D1L46 # !D1_Frame_Cont[15]);


--D1L51 is CCD_Capture:u3|Frame_Cont[16]~1224 at LCCOMB_X12_Y10_N0
D1L51 = D1_Frame_Cont[16] & (D1L49 $ GND) # !D1_Frame_Cont[16] & !D1L49 & VCC;

--D1L52 is CCD_Capture:u3|Frame_Cont[16]~1225 at LCCOMB_X12_Y10_N0
D1L52 = CARRY(D1_Frame_Cont[16] & !D1L49);


--D1L54 is CCD_Capture:u3|Frame_Cont[17]~1226 at LCCOMB_X12_Y10_N2
D1L54 = D1_Frame_Cont[17] & !D1L52 # !D1_Frame_Cont[17] & (D1L52 # GND);

--D1L55 is CCD_Capture:u3|Frame_Cont[17]~1227 at LCCOMB_X12_Y10_N2
D1L55 = CARRY(!D1L52 # !D1_Frame_Cont[17]);


--D1L57 is CCD_Capture:u3|Frame_Cont[18]~1228 at LCCOMB_X12_Y10_N4
D1L57 = D1_Frame_Cont[18] & (D1L55 $ GND) # !D1_Frame_Cont[18] & !D1L55 & VCC;

--D1L58 is CCD_Capture:u3|Frame_Cont[18]~1229 at LCCOMB_X12_Y10_N4
D1L58 = CARRY(D1_Frame_Cont[18] & !D1L55);


--D1L60 is CCD_Capture:u3|Frame_Cont[19]~1230 at LCCOMB_X12_Y10_N6
D1L60 = D1_Frame_Cont[19] & !D1L58 # !D1_Frame_Cont[19] & (D1L58 # GND);

--D1L61 is CCD_Capture:u3|Frame_Cont[19]~1231 at LCCOMB_X12_Y10_N6
D1L61 = CARRY(!D1L58 # !D1_Frame_Cont[19]);


--D1L63 is CCD_Capture:u3|Frame_Cont[20]~1232 at LCCOMB_X12_Y10_N8
D1L63 = D1_Frame_Cont[20] & (D1L61 $ GND) # !D1_Frame_Cont[20] & !D1L61 & VCC;

--D1L64 is CCD_Capture:u3|Frame_Cont[20]~1233 at LCCOMB_X12_Y10_N8
D1L64 = CARRY(D1_Frame_Cont[20] & !D1L61);


--D1L66 is CCD_Capture:u3|Frame_Cont[21]~1234 at LCCOMB_X12_Y10_N10
D1L66 = D1_Frame_Cont[21] & !D1L64 # !D1_Frame_Cont[21] & (D1L64 # GND);

--D1L67 is CCD_Capture:u3|Frame_Cont[21]~1235 at LCCOMB_X12_Y10_N10
D1L67 = CARRY(!D1L64 # !D1_Frame_Cont[21]);


--D1L69 is CCD_Capture:u3|Frame_Cont[22]~1236 at LCCOMB_X12_Y10_N12
D1L69 = D1_Frame_Cont[22] & (D1L67 $ GND) # !D1_Frame_Cont[22] & !D1L67 & VCC;

--D1L70 is CCD_Capture:u3|Frame_Cont[22]~1237 at LCCOMB_X12_Y10_N12
D1L70 = CARRY(D1_Frame_Cont[22] & !D1L67);


--D1L72 is CCD_Capture:u3|Frame_Cont[23]~1238 at LCCOMB_X12_Y10_N14
D1L72 = D1_Frame_Cont[23] & !D1L70 # !D1_Frame_Cont[23] & (D1L70 # GND);

--D1L73 is CCD_Capture:u3|Frame_Cont[23]~1239 at LCCOMB_X12_Y10_N14
D1L73 = CARRY(!D1L70 # !D1_Frame_Cont[23]);


--D1L75 is CCD_Capture:u3|Frame_Cont[24]~1240 at LCCOMB_X12_Y10_N16
D1L75 = D1_Frame_Cont[24] & (D1L73 $ GND) # !D1_Frame_Cont[24] & !D1L73 & VCC;

--D1L76 is CCD_Capture:u3|Frame_Cont[24]~1241 at LCCOMB_X12_Y10_N16
D1L76 = CARRY(D1_Frame_Cont[24] & !D1L73);


--D1L78 is CCD_Capture:u3|Frame_Cont[25]~1242 at LCCOMB_X12_Y10_N18
D1L78 = D1_Frame_Cont[25] & !D1L76 # !D1_Frame_Cont[25] & (D1L76 # GND);

--D1L79 is CCD_Capture:u3|Frame_Cont[25]~1243 at LCCOMB_X12_Y10_N18
D1L79 = CARRY(!D1L76 # !D1_Frame_Cont[25]);


--D1L81 is CCD_Capture:u3|Frame_Cont[26]~1244 at LCCOMB_X12_Y10_N20
D1L81 = D1_Frame_Cont[26] & (D1L79 $ GND) # !D1_Frame_Cont[26] & !D1L79 & VCC;

--D1L82 is CCD_Capture:u3|Frame_Cont[26]~1245 at LCCOMB_X12_Y10_N20
D1L82 = CARRY(D1_Frame_Cont[26] & !D1L79);


--D1L84 is CCD_Capture:u3|Frame_Cont[27]~1246 at LCCOMB_X12_Y10_N22
D1L84 = D1_Frame_Cont[27] & !D1L82 # !D1_Frame_Cont[27] & (D1L82 # GND);

--D1L85 is CCD_Capture:u3|Frame_Cont[27]~1247 at LCCOMB_X12_Y10_N22
D1L85 = CARRY(!D1L82 # !D1_Frame_Cont[27]);


--D1L87 is CCD_Capture:u3|Frame_Cont[28]~1248 at LCCOMB_X12_Y10_N24
D1L87 = D1_Frame_Cont[28] & (D1L85 $ GND) # !D1_Frame_Cont[28] & !D1L85 & VCC;

--D1L88 is CCD_Capture:u3|Frame_Cont[28]~1249 at LCCOMB_X12_Y10_N24
D1L88 = CARRY(D1_Frame_Cont[28] & !D1L85);


--D1L90 is CCD_Capture:u3|Frame_Cont[29]~1250 at LCCOMB_X12_Y10_N26
D1L90 = D1_Frame_Cont[29] & !D1L88 # !D1_Frame_Cont[29] & (D1L88 # GND);

--D1L91 is CCD_Capture:u3|Frame_Cont[29]~1251 at LCCOMB_X12_Y10_N26
D1L91 = CARRY(!D1L88 # !D1_Frame_Cont[29]);


--D1L93 is CCD_Capture:u3|Frame_Cont[30]~1252 at LCCOMB_X12_Y10_N28
D1L93 = D1_Frame_Cont[30] & (D1L91 $ GND) # !D1_Frame_Cont[30] & !D1L91 & VCC;

--D1L94 is CCD_Capture:u3|Frame_Cont[30]~1253 at LCCOMB_X12_Y10_N28
D1L94 = CARRY(D1_Frame_Cont[30] & !D1L91);


--D1L96 is CCD_Capture:u3|Frame_Cont[31]~1254 at LCCOMB_X12_Y10_N30
D1L96 = D1L94 $ D1_Frame_Cont[31];


--D1_X_Cont[8] is CCD_Capture:u3|X_Cont[8] at LCFF_X57_Y2_N17
D1_X_Cont[8] = DFFEAS(D1L130, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[9] is CCD_Capture:u3|X_Cont[9] at LCFF_X57_Y2_N19
D1_X_Cont[9] = DFFEAS(D1L133, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1L98 is CCD_Capture:u3|LessThan~137 at LCCOMB_X57_Y2_N26
D1L98 = !D1_X_Cont[8] & !D1_X_Cont[9];


--D1_X_Cont[0] is CCD_Capture:u3|X_Cont[0] at LCFF_X57_Y2_N1
D1_X_Cont[0] = DFFEAS(D1L105, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[1] is CCD_Capture:u3|X_Cont[1] at LCFF_X57_Y2_N3
D1_X_Cont[1] = DFFEAS(D1L109, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[2] is CCD_Capture:u3|X_Cont[2] at LCFF_X57_Y2_N5
D1_X_Cont[2] = DFFEAS(D1L112, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[3] is CCD_Capture:u3|X_Cont[3] at LCFF_X57_Y2_N7
D1_X_Cont[3] = DFFEAS(D1L115, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1L99 is CCD_Capture:u3|LessThan~138 at LCCOMB_X57_Y2_N22
D1L99 = !D1_X_Cont[1] # !D1_X_Cont[2] # !D1_X_Cont[0] # !D1_X_Cont[3];


--D1_X_Cont[4] is CCD_Capture:u3|X_Cont[4] at LCFF_X57_Y2_N9
D1_X_Cont[4] = DFFEAS(D1L118, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[5] is CCD_Capture:u3|X_Cont[5] at LCFF_X57_Y2_N11
D1_X_Cont[5] = DFFEAS(D1L121, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[6] is CCD_Capture:u3|X_Cont[6] at LCFF_X57_Y2_N13
D1_X_Cont[6] = DFFEAS(D1L124, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1_X_Cont[7] is CCD_Capture:u3|X_Cont[7] at LCFF_X57_Y2_N15
D1_X_Cont[7] = DFFEAS(D1L127, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1L100 is CCD_Capture:u3|LessThan~139 at LCCOMB_X57_Y2_N24
D1L100 = !D1_X_Cont[5] # !D1_X_Cont[4] # !D1_X_Cont[7] # !D1_X_Cont[6];


--D1_X_Cont[10] is CCD_Capture:u3|X_Cont[10] at LCFF_X57_Y2_N21
D1_X_Cont[10] = DFFEAS(D1L136, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , D1L107,  );


--D1L101 is CCD_Capture:u3|LessThan~140 at LCCOMB_X57_Y2_N28
D1L101 = D1L98 & (D1L100 # D1L99) # !D1_X_Cont[10];


--D1L140 is CCD_Capture:u3|Y_Cont[0]~822 at LCCOMB_X57_Y1_N10
D1L140 = D1_Y_Cont[0] & (D1L101 $ GND) # !D1_Y_Cont[0] & !D1L101 & VCC;

--D1L141 is CCD_Capture:u3|Y_Cont[0]~823 at LCCOMB_X57_Y1_N10
D1L141 = CARRY(D1_Y_Cont[0] & !D1L101);


--D1_mCCD_FVAL is CCD_Capture:u3|mCCD_FVAL at LCFF_X57_Y10_N23
D1_mCCD_FVAL = DFFEAS(D1L188, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--D1_mCCD_LVAL is CCD_Capture:u3|mCCD_LVAL at LCFF_X57_Y10_N9
D1_mCCD_LVAL = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , rCCD_LVAL,  ,  , VCC);


--D1L166 is CCD_Capture:u3|Y_Cont[10]~824 at LCCOMB_X57_Y1_N0
D1L166 = D1_mCCD_LVAL # !D1_mCCD_FVAL;


--D1L143 is CCD_Capture:u3|Y_Cont[1]~825 at LCCOMB_X57_Y1_N12
D1L143 = D1_Y_Cont[1] & !D1L141 # !D1_Y_Cont[1] & (D1L141 # GND);

--D1L144 is CCD_Capture:u3|Y_Cont[1]~826 at LCCOMB_X57_Y1_N12
D1L144 = CARRY(!D1L141 # !D1_Y_Cont[1]);


--D1L146 is CCD_Capture:u3|Y_Cont[2]~827 at LCCOMB_X57_Y1_N14
D1L146 = D1_Y_Cont[2] & (D1L144 $ GND) # !D1_Y_Cont[2] & !D1L144 & VCC;

--D1L147 is CCD_Capture:u3|Y_Cont[2]~828 at LCCOMB_X57_Y1_N14
D1L147 = CARRY(D1_Y_Cont[2] & !D1L144);


--D1L149 is CCD_Capture:u3|Y_Cont[3]~829 at LCCOMB_X57_Y1_N16
D1L149 = D1_Y_Cont[3] & !D1L147 # !D1_Y_Cont[3] & (D1L147 # GND);

--D1L150 is CCD_Capture:u3|Y_Cont[3]~830 at LCCOMB_X57_Y1_N16
D1L150 = CARRY(!D1L147 # !D1_Y_Cont[3]);


--D1L152 is CCD_Capture:u3|Y_Cont[4]~831 at LCCOMB_X57_Y1_N18
D1L152 = D1_Y_Cont[4] & (D1L150 $ GND) # !D1_Y_Cont[4] & !D1L150 & VCC;

--D1L153 is CCD_Capture:u3|Y_Cont[4]~832 at LCCOMB_X57_Y1_N18
D1L153 = CARRY(D1_Y_Cont[4] & !D1L150);


--D1L155 is CCD_Capture:u3|Y_Cont[5]~833 at LCCOMB_X57_Y1_N20
D1L155 = D1_Y_Cont[5] & !D1L153 # !D1_Y_Cont[5] & (D1L153 # GND);

--D1L156 is CCD_Capture:u3|Y_Cont[5]~834 at LCCOMB_X57_Y1_N20
D1L156 = CARRY(!D1L153 # !D1_Y_Cont[5]);


--D1L158 is CCD_Capture:u3|Y_Cont[6]~835 at LCCOMB_X57_Y1_N22
D1L158 = D1_Y_Cont[6] & (D1L156 $ GND) # !D1_Y_Cont[6] & !D1L156 & VCC;

--D1L159 is CCD_Capture:u3|Y_Cont[6]~836 at LCCOMB_X57_Y1_N22
D1L159 = CARRY(D1_Y_Cont[6] & !D1L156);


--D1L161 is CCD_Capture:u3|Y_Cont[7]~837 at LCCOMB_X57_Y1_N24
D1L161 = D1_Y_Cont[7] & !D1L159 # !D1_Y_Cont[7] & (D1L159 # GND);

--D1L162 is CCD_Capture:u3|Y_Cont[7]~838 at LCCOMB_X57_Y1_N24
D1L162 = CARRY(!D1L159 # !D1_Y_Cont[7]);


--D1L164 is CCD_Capture:u3|Y_Cont[8]~839 at LCCOMB_X57_Y1_N26
D1L164 = D1L162 $ !D1_Y_Cont[8];


--R1_SA[0] is Sdram_Control_4Port:u6|command:command1|SA[0] at LCFF_X20_Y12_N9
R1_SA[0] = DFFEAS(R1L34, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_ST[2] is Sdram_Control_4Port:u6|ST[2] at LCFF_X18_Y10_N29
G1_ST[2] = DFFEAS(G1L95, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_ST[0] is Sdram_Control_4Port:u6|ST[0] at LCFF_X18_Y10_N11
G1_ST[0] = DFFEAS(G1L90, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_ST[9] is Sdram_Control_4Port:u6|ST[9] at LCFF_X17_Y10_N3
G1_ST[9] = DFFEAS(G1L111, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_ST[7] is Sdram_Control_4Port:u6|ST[7] at LCFF_X17_Y10_N27
G1_ST[7] = DFFEAS(G1L105, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_ST[6] is Sdram_Control_4Port:u6|ST[6] at LCFF_X17_Y10_N5
G1_ST[6] = DFFEAS(G1L103, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_ST[5] is Sdram_Control_4Port:u6|ST[5] at LCFF_X17_Y10_N29
G1_ST[5] = DFFEAS(G1L101, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L18 is Sdram_Control_4Port:u6|Equal~1115 at LCCOMB_X17_Y10_N30
G1L18 = !G1_ST[9] & !G1_ST[5] & !G1_ST[6] & !G1_ST[7];


--G1_ST[4] is Sdram_Control_4Port:u6|ST[4] at LCFF_X18_Y10_N3
G1_ST[4] = DFFEAS(G1L99, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_ST[3] is Sdram_Control_4Port:u6|ST[3] at LCFF_X18_Y10_N9
G1_ST[3] = DFFEAS(G1L97, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L19 is Sdram_Control_4Port:u6|Equal~1116 at LCCOMB_X18_Y10_N18
G1L19 = !G1_ST[3] & !G1_ST[4];


--G1_ST[8] is Sdram_Control_4Port:u6|ST[8] at LCFF_X17_Y10_N1
G1_ST[8] = DFFEAS(G1L109, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_ST[1] is Sdram_Control_4Port:u6|ST[1] at LCFF_X18_Y10_N21
G1_ST[1] = DFFEAS(G1L93, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L20 is Sdram_Control_4Port:u6|Equal~1117 at LCCOMB_X18_Y10_N0
G1L20 = G1_ST[8] & G1L19 & G1_ST[1] & G1L18;


--G1L75 is Sdram_Control_4Port:u6|SA~482 at LCCOMB_X18_Y11_N26
G1L75 = R1_SA[0] & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_SA[1] is Sdram_Control_4Port:u6|command:command1|SA[1] at LCFF_X20_Y12_N21
R1_SA[1] = DFFEAS(R1L35, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L76 is Sdram_Control_4Port:u6|SA~483 at LCCOMB_X18_Y11_N2
G1L76 = R1_SA[1] & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_SA[2] is Sdram_Control_4Port:u6|command:command1|SA[2] at LCFF_X19_Y12_N5
R1_SA[2] = DFFEAS(R1L36, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L77 is Sdram_Control_4Port:u6|SA~484 at LCCOMB_X18_Y11_N4
G1L77 = R1_SA[2] & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_SA[3] is Sdram_Control_4Port:u6|command:command1|SA[3] at LCFF_X19_Y12_N31
R1_SA[3] = DFFEAS(R1L37, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L78 is Sdram_Control_4Port:u6|SA~485 at LCCOMB_X18_Y11_N30
G1L78 = R1_SA[3] & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_SA[4] is Sdram_Control_4Port:u6|command:command1|SA[4] at LCFF_X19_Y12_N9
R1_SA[4] = DFFEAS(R1L38, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L79 is Sdram_Control_4Port:u6|SA~486 at LCCOMB_X18_Y11_N0
G1L79 = R1_SA[4] & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_SA[5] is Sdram_Control_4Port:u6|command:command1|SA[5] at LCFF_X19_Y12_N15
R1_SA[5] = DFFEAS(R1L39, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L80 is Sdram_Control_4Port:u6|SA~487 at LCCOMB_X18_Y11_N8
G1L80 = R1_SA[5] & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_SA[6] is Sdram_Control_4Port:u6|command:command1|SA[6] at LCFF_X20_Y12_N25
R1_SA[6] = DFFEAS(R1L40, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L81 is Sdram_Control_4Port:u6|SA~488 at LCCOMB_X18_Y11_N16
G1L81 = R1_SA[6] & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_SA[7] is Sdram_Control_4Port:u6|command:command1|SA[7] at LCFF_X19_Y12_N27
R1_SA[7] = DFFEAS(R1L41, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L82 is Sdram_Control_4Port:u6|SA~489 at LCCOMB_X18_Y11_N6
G1L82 = R1_SA[7] & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_SA[8] is Sdram_Control_4Port:u6|command:command1|SA[8] at LCFF_X20_Y12_N17
R1_SA[8] = DFFEAS(R1L42, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L83 is Sdram_Control_4Port:u6|SA~490 at LCCOMB_X18_Y11_N20
G1L83 = R1_SA[8] & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_SA[9] is Sdram_Control_4Port:u6|command:command1|SA[9] at LCFF_X19_Y12_N25
R1_SA[9] = DFFEAS(R1L43, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L84 is Sdram_Control_4Port:u6|SA~491 at LCCOMB_X18_Y11_N24
G1L84 = R1_SA[9] # G1_ST[0] & G1L20 & !G1_ST[2];


--R1_SA[10] is Sdram_Control_4Port:u6|command:command1|SA[10] at LCFF_X19_Y12_N13
R1_SA[10] = DFFEAS(R1L44, GLOBAL(KB1L2),  ,  ,  ,  ,  , R1_do_load_mode,  );


--G1L85 is Sdram_Control_4Port:u6|SA~492 at LCCOMB_X19_Y12_N20
G1L85 = R1_SA[10] & (G1_ST[2] # !G1_ST[0] # !G1L20);


--R1_SA[11] is Sdram_Control_4Port:u6|command:command1|SA[11] at LCFF_X19_Y12_N11
R1_SA[11] = DFFEAS(R1L45, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L86 is Sdram_Control_4Port:u6|SA~493 at LCCOMB_X19_Y10_N22
G1L86 = R1_SA[11] & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--G1L21 is Sdram_Control_4Port:u6|Equal~1118 at LCCOMB_X18_Y10_N6
G1L21 = !G1_ST[3] & G1L18 & !G1_ST[4];


--G1L35 is Sdram_Control_4Port:u6|LessThan~1258 at LCCOMB_X19_Y11_N10
G1L35 = G1_ST[1] & G1_ST[0];


--G1L36 is Sdram_Control_4Port:u6|LessThan~1259 at LCCOMB_X19_Y11_N24
G1L36 = !G1_ST[2] & G1L21 & !G1_ST[8] & !G1L35;


--G1L22 is Sdram_Control_4Port:u6|Equal~1119 at LCCOMB_X19_Y11_N16
G1L22 = !G1_ST[2] & G1_ST[0] & G1L20;


--G1_Write is Sdram_Control_4Port:u6|Write at LCFF_X19_Y11_N7
G1_Write = DFFEAS(G1L125, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_Read is Sdram_Control_4Port:u6|Read at LCFF_X19_Y11_N23
G1_Read = DFFEAS(G1L61, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L17 is Sdram_Control_4Port:u6|DQM~82 at LCCOMB_X19_Y11_N8
G1L17 = G1L36 # G1_Write & G1L22 # !G1_Write & (!G1_Read);


--R1_WE_N is Sdram_Control_4Port:u6|command:command1|WE_N at LCFF_X19_Y10_N11
R1_WE_N = DFFEAS(R1L48, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L115 is Sdram_Control_4Port:u6|WE_N~43 at LCCOMB_X19_Y10_N16
G1L115 = R1_WE_N & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_CAS_N is Sdram_Control_4Port:u6|command:command1|CAS_N at LCFF_X19_Y10_N7
R1_CAS_N = DFFEAS(R1L7, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L7 is Sdram_Control_4Port:u6|CAS_N~9 at LCCOMB_X19_Y10_N26
G1L7 = R1_CAS_N # G1_ST[0] & !G1_ST[2] & G1L20;


--R1_RAS_N is Sdram_Control_4Port:u6|command:command1|RAS_N at LCFF_X19_Y10_N19
R1_RAS_N = DFFEAS(R1L17, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L53 is Sdram_Control_4Port:u6|RAS_N~45 at LCCOMB_X19_Y10_N14
G1L53 = R1_RAS_N & (G1_ST[2] # !G1L20 # !G1_ST[0]);


--R1_CS_N[0] is Sdram_Control_4Port:u6|command:command1|CS_N[0] at LCFF_X19_Y10_N31
R1_CS_N[0] = DFFEAS(R1L12, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1_BA[0] is Sdram_Control_4Port:u6|command:command1|BA[0] at LCFF_X20_Y12_N13
R1_BA[0] = DFFEAS(R1L4, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1_BA[1] is Sdram_Control_4Port:u6|command:command1|BA[1] at LCFF_X19_Y12_N3
R1_BA[1] = DFFEAS(R1L5, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--B1L2 is VGA_Controller:u1|Equal~116 at LCCOMB_X19_Y35_N12
B1L2 = !B1_H_Cont[8] & !B1_H_Cont[9];


--B1L42 is VGA_Controller:u1|LessThan~1091 at LCCOMB_X19_Y35_N0
B1L42 = B1_H_Cont[7] # B1_H_Cont[5] & B1_H_Cont[6] # !B1L2;


--C1_oRST_2 is Reset_Delay:u2|oRST_2 at LCFF_X21_Y15_N29
C1_oRST_2 = DFFEAS(C1L83, GLOBAL(A1L15), KEY[0],  ,  ,  ,  ,  ,  );


--B1_H_Cont[0] is VGA_Controller:u1|H_Cont[0] at LCFF_X18_Y35_N5
B1_H_Cont[0] = DFFEAS(B1L8, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1_H_Cont[1] is VGA_Controller:u1|H_Cont[1] at LCFF_X18_Y35_N7
B1_H_Cont[1] = DFFEAS(B1L11, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1L3 is VGA_Controller:u1|Equal~117 at LCCOMB_X18_Y35_N2
B1L3 = !B1_H_Cont[1] & !B1_H_Cont[8] & !B1_H_Cont[0] & !B1_H_Cont[9];


--B1_H_Cont[2] is VGA_Controller:u1|H_Cont[2] at LCFF_X18_Y35_N9
B1_H_Cont[2] = DFFEAS(B1L14, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1_H_Cont[3] is VGA_Controller:u1|H_Cont[3] at LCFF_X18_Y35_N11
B1_H_Cont[3] = DFFEAS(B1L17, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1L4 is VGA_Controller:u1|Equal~118 at LCCOMB_X18_Y35_N0
B1L4 = !B1_H_Cont[2] & !B1_H_Cont[3];


--B1L5 is VGA_Controller:u1|Equal~119 at LCCOMB_X18_Y35_N26
B1L5 = B1L1 & B1L4 & !B1_H_Cont[7] & B1L3;


--B1L117 is VGA_Controller:u1|oVGA_V_SYNC~174 at LCCOMB_X19_Y35_N26
B1L117 = B1L5 & (B1L41 # B1_V_Cont[9]) # !B1L5 & (B1_oVGA_V_SYNC);


--B1_oRequest is VGA_Controller:u1|oRequest at LCFF_X24_Y16_N23
B1_oRequest = DFFEAS(B1L80, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  ,  ,  );


--X4_rdptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[7] at LCFF_X25_Y16_N5
X4_rdptr_g[7] = DFFEAS(X4L40, GLOBAL(A1L9), GLOBAL(C1L78),  , X4_valid_rdreq,  ,  ,  ,  );


--HB4_dffe7a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[7] at LCFF_X24_Y16_N1
HB4_dffe7a[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X4_delayed_wrptr_g[7],  ,  , VCC);


--X4_rdptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0] at LCFF_X25_Y16_N3
X4_rdptr_g[0] = DFFEAS(X4L29, GLOBAL(A1L9), GLOBAL(C1L78),  , X4_valid_rdreq,  ,  ,  ,  );


--X4_rdptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2] at LCFF_X23_Y16_N23
X4_rdptr_g[2] = DFFEAS(X4L32, GLOBAL(A1L9), GLOBAL(C1L78),  , X4_valid_rdreq,  ,  ,  ,  );


--HB4_dffe7a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[2] at LCFF_X24_Y16_N7
HB4_dffe7a[2] = DFFEAS(HB4L6, GLOBAL(A1L9), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--HB4_dffe7a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0] at LCFF_X24_Y16_N29
HB4_dffe7a[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X4_delayed_wrptr_g[0],  ,  , VCC);


--X4L22 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~54 at LCCOMB_X24_Y16_N28
X4L22 = X4_rdptr_g[0] & HB4_dffe7a[0] & (X4_rdptr_g[2] $ !HB4_dffe7a[2]) # !X4_rdptr_g[0] & !HB4_dffe7a[0] & (X4_rdptr_g[2] $ !HB4_dffe7a[2]);


--X4_rdptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[6] at LCFF_X23_Y16_N15
X4_rdptr_g[6] = DFFEAS(X4L38, GLOBAL(A1L9), GLOBAL(C1L78),  , X4_valid_rdreq,  ,  ,  ,  );


--X4_rdptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[1] at LCFF_X25_Y16_N9
X4_rdptr_g[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  , X4_valid_rdreq, Z4_power_modified_counter_values[1],  ,  , VCC);


--HB4_dffe7a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1] at LCFF_X24_Y16_N31
HB4_dffe7a[1] = DFFEAS(HB4L4, GLOBAL(A1L9), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--HB4_dffe7a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[6] at LCFF_X24_Y16_N13
HB4_dffe7a[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X4_delayed_wrptr_g[6],  ,  , VCC);


--X4L23 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~55 at LCCOMB_X24_Y16_N12
X4L23 = X4_rdptr_g[6] & HB4_dffe7a[6] & (X4_rdptr_g[1] $ !HB4_dffe7a[1]) # !X4_rdptr_g[6] & !HB4_dffe7a[6] & (X4_rdptr_g[1] $ !HB4_dffe7a[1]);


--X4_rdptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[3] at LCFF_X23_Y16_N13
X4_rdptr_g[3] = DFFEAS(X4L34, GLOBAL(A1L9), GLOBAL(C1L78),  , X4_valid_rdreq,  ,  ,  ,  );


--X4_rdptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8] at LCFF_X25_Y16_N7
X4_rdptr_g[8] = DFFEAS(X4L42, GLOBAL(A1L9), GLOBAL(C1L78),  , X4_valid_rdreq,  ,  ,  ,  );


--HB4_dffe7a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[8] at LCFF_X24_Y16_N19
HB4_dffe7a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X4_delayed_wrptr_g[8],  ,  , VCC);


--HB4_dffe7a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[3] at LCFF_X24_Y16_N27
HB4_dffe7a[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X4_delayed_wrptr_g[3],  ,  , VCC);


--X4L24 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~56 at LCCOMB_X24_Y16_N26
X4L24 = X4_rdptr_g[8] & HB4_dffe7a[8] & (HB4_dffe7a[3] $ !X4_rdptr_g[3]) # !X4_rdptr_g[8] & !HB4_dffe7a[8] & (HB4_dffe7a[3] $ !X4_rdptr_g[3]);


--X4_rdptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[5] at LCFF_X23_Y16_N29
X4_rdptr_g[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  , X4_valid_rdreq, Z4_power_modified_counter_values[5],  ,  , VCC);


--X4_rdptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4] at LCFF_X23_Y16_N7
X4_rdptr_g[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  , X4_valid_rdreq, Z4_power_modified_counter_values[4],  ,  , VCC);


--HB4_dffe7a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4] at LCFF_X24_Y16_N25
HB4_dffe7a[4] = DFFEAS(HB4L9, GLOBAL(A1L9), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--HB4_dffe7a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[5] at LCFF_X24_Y16_N17
HB4_dffe7a[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X4_delayed_wrptr_g[5],  ,  , VCC);


--X4L25 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~57 at LCCOMB_X24_Y16_N16
X4L25 = HB4_dffe7a[4] & X4_rdptr_g[4] & (X4_rdptr_g[5] $ !HB4_dffe7a[5]) # !HB4_dffe7a[4] & !X4_rdptr_g[4] & (X4_rdptr_g[5] $ !HB4_dffe7a[5]);


--X4L26 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~58 at LCCOMB_X24_Y16_N2
X4L26 = X4L23 & X4L24 & X4L25 & X4L22;


--X4_valid_rdreq is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq at LCCOMB_X24_Y16_N0
X4_valid_rdreq = B1_oRequest & (X4_rdptr_g[7] $ HB4_dffe7a[7] # !X4L26);


--X4_p0addr is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|p0addr at LCFF_X28_Y20_N11
X4_p0addr = DFFEAS(X4L17, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--X4_rdcnt_addr_ena is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdcnt_addr_ena at LCCOMB_X24_Y16_N14
X4_rdcnt_addr_ena = X4_valid_rdreq # !X4_p0addr;


--G1_OUT_VALID is Sdram_Control_4Port:u6|OUT_VALID at LCFF_X19_Y11_N29
G1_OUT_VALID = DFFEAS(G1L48, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_RD_MASK[1] is Sdram_Control_4Port:u6|RD_MASK[1] at LCFF_X21_Y13_N9
G1_RD_MASK[1] = DFFEAS(G1L57, GLOBAL(KB1L2),  ,  , G1L273,  ,  ,  ,  );


--JB4_dffe9a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[7] at LCFF_X24_Y15_N1
JB4_dffe9a[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_rdptr_g[7],  ,  , VCC);


--EB4_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[7] at LCFF_X24_Y15_N25
EB4_power_modified_counter_values[7] = DFFEAS(EB4_countera7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X4L1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|_~16 at LCCOMB_X24_Y15_N0
X4L1 = EB4_power_modified_counter_values[7] $ JB4_dffe9a[7];


--JB4_dffe9a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[2] at LCFF_X23_Y16_N5
JB4_dffe9a[2] = DFFEAS(JB4L5, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[2] at LCFF_X24_Y15_N15
EB4_power_modified_counter_values[2] = DFFEAS(EB4_countera2, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB4_dffe9a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[0] at LCFF_X24_Y15_N7
JB4_dffe9a[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_rdptr_g[0],  ,  , VCC);


--EB4_counter_ffa[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|counter_ffa[0] at LCFF_X24_Y15_N11
EB4_counter_ffa[0] = DFFEAS(EB4_countera0, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X4L45 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~55 at LCCOMB_X24_Y15_N6
X4L45 = EB4_counter_ffa[0] & !JB4_dffe9a[0] & (EB4_power_modified_counter_values[2] $ !JB4_dffe9a[2]) # !EB4_counter_ffa[0] & JB4_dffe9a[0] & (EB4_power_modified_counter_values[2] $ !JB4_dffe9a[2]);


--JB4_dffe9a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[6] at LCFF_X23_Y16_N19
JB4_dffe9a[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_rdptr_g[6],  ,  , VCC);


--JB4_dffe9a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[1] at LCFF_X24_Y15_N29
JB4_dffe9a[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_rdptr_g[1],  ,  , VCC);


--EB4_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[1] at LCFF_X24_Y15_N13
EB4_power_modified_counter_values[1] = DFFEAS(EB4_countera1, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[6] at LCFF_X24_Y15_N23
EB4_power_modified_counter_values[6] = DFFEAS(EB4_countera6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X4L46 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~56 at LCCOMB_X24_Y15_N28
X4L46 = EB4_power_modified_counter_values[1] & JB4_dffe9a[1] & (JB4_dffe9a[6] $ !EB4_power_modified_counter_values[6]) # !EB4_power_modified_counter_values[1] & !JB4_dffe9a[1] & (JB4_dffe9a[6] $ !EB4_power_modified_counter_values[6]);


--JB4_dffe9a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[3] at LCFF_X23_Y16_N25
JB4_dffe9a[3] = DFFEAS(JB4L7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB4_dffe9a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[8] at LCFF_X24_Y15_N3
JB4_dffe9a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_rdptr_g[8],  ,  , VCC);


--EB4_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[8] at LCFF_X24_Y15_N27
EB4_power_modified_counter_values[8] = DFFEAS(EB4_countera8, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[3] at LCFF_X24_Y15_N17
EB4_power_modified_counter_values[3] = DFFEAS(EB4_countera3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X4L47 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~57 at LCCOMB_X24_Y15_N2
X4L47 = EB4_power_modified_counter_values[3] & JB4_dffe9a[3] & (JB4_dffe9a[8] $ !EB4_power_modified_counter_values[8]) # !EB4_power_modified_counter_values[3] & !JB4_dffe9a[3] & (JB4_dffe9a[8] $ !EB4_power_modified_counter_values[8]);


--JB4_dffe9a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5] at LCFF_X23_Y16_N11
JB4_dffe9a[5] = DFFEAS(JB4L10, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB4_dffe9a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[4] at LCFF_X23_Y16_N17
JB4_dffe9a[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_rdptr_g[4],  ,  , VCC);


--EB4_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[4] at LCFF_X24_Y15_N19
EB4_power_modified_counter_values[4] = DFFEAS(EB4_countera4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB4_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[5] at LCFF_X24_Y15_N21
EB4_power_modified_counter_values[5] = DFFEAS(EB4_countera5, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X4L48 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~58 at LCCOMB_X23_Y16_N16
X4L48 = EB4_power_modified_counter_values[4] & JB4_dffe9a[4] & (EB4_power_modified_counter_values[5] $ !JB4_dffe9a[5]) # !EB4_power_modified_counter_values[4] & !JB4_dffe9a[4] & (EB4_power_modified_counter_values[5] $ !JB4_dffe9a[5]);


--X4L49 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~59 at LCCOMB_X24_Y15_N4
X4L49 = X4L45 & X4L47 & X4L48 & X4L46;


--X4_valid_wrreq is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_wrreq at LCCOMB_X24_Y15_N30
X4_valid_wrreq = G1_RD_MASK[1] & G1_OUT_VALID & (X4L1 # !X4L49);


--C1_oRST_0 is Reset_Delay:u2|oRST_0 at LCFF_X21_Y13_N23
C1_oRST_0 = DFFEAS(C1L77, GLOBAL(A1L15), KEY[0],  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[0] at LCFF_X25_Y16_N13
Z4_power_modified_counter_values[0] = DFFEAS(Z4_countera0, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[1] at LCFF_X25_Y16_N15
Z4_power_modified_counter_values[1] = DFFEAS(Z4_countera1, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[2] at LCFF_X25_Y16_N17
Z4_power_modified_counter_values[2] = DFFEAS(Z4_countera2, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[3] at LCFF_X25_Y16_N19
Z4_power_modified_counter_values[3] = DFFEAS(Z4_countera3, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[4] at LCFF_X25_Y16_N21
Z4_power_modified_counter_values[4] = DFFEAS(Z4_countera4, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[5] at LCFF_X25_Y16_N23
Z4_power_modified_counter_values[5] = DFFEAS(Z4_countera5, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[6] at LCFF_X25_Y16_N25
Z4_power_modified_counter_values[6] = DFFEAS(Z4_countera6, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[7] at LCFF_X25_Y16_N27
Z4_power_modified_counter_values[7] = DFFEAS(Z4_countera7, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z4_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8] at LCFF_X25_Y16_N29
Z4_power_modified_counter_values[8] = DFFEAS(Z4_countera8, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[0] is Sdram_Control_4Port:u6|mDATAOUT[0] at LCFF_X22_Y16_N11
G1_mDATAOUT[0] = DFFEAS(G1L241, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--X4_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0] at LCFF_X24_Y17_N17
X4_wrptr_g[0] = DFFEAS(X4L52, GLOBAL(KB1L2), GLOBAL(C1L78),  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[1] at LCFF_X23_Y15_N15
X4_wrptr_g[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X4_valid_wrreq, EB4_power_modified_counter_values[1],  ,  , VCC);


--X4_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2] at LCFF_X23_Y15_N21
X4_wrptr_g[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X4_valid_wrreq, EB4_power_modified_counter_values[2],  ,  , VCC);


--X4_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[3] at LCFF_X23_Y15_N7
X4_wrptr_g[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X4_valid_wrreq, EB4_power_modified_counter_values[3],  ,  , VCC);


--X4_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[4] at LCFF_X23_Y15_N31
X4_wrptr_g[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X4_valid_wrreq, EB4_power_modified_counter_values[4],  ,  , VCC);


--X4_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5] at LCFF_X23_Y15_N23
X4_wrptr_g[5] = DFFEAS(X4L58, GLOBAL(KB1L2), GLOBAL(C1L78),  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6] at LCFF_X23_Y15_N3
X4_wrptr_g[6] = DFFEAS(X4L60, GLOBAL(KB1L2), GLOBAL(C1L78),  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[7] at LCFF_X23_Y15_N11
X4_wrptr_g[7] = DFFEAS(X4L62, GLOBAL(KB1L2), GLOBAL(C1L78),  , X4_valid_wrreq,  ,  ,  ,  );


--X4_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8] at LCFF_X23_Y15_N5
X4_wrptr_g[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X4_valid_wrreq, EB4_power_modified_counter_values[8],  ,  , VCC);


--B1_V_Cont[0] is VGA_Controller:u1|V_Cont[0] at LCFF_X20_Y35_N1
B1_V_Cont[0] = DFFEAS(B1L50, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1L50 is VGA_Controller:u1|V_Cont[0]~900 at LCCOMB_X20_Y35_N0
B1L50 = B1_V_Cont[0] $ VCC;

--B1L51 is VGA_Controller:u1|V_Cont[0]~901 at LCCOMB_X20_Y35_N0
B1L51 = CARRY(B1_V_Cont[0]);


--B1L53 is VGA_Controller:u1|V_Cont[1]~902 at LCCOMB_X20_Y35_N2
B1L53 = B1_V_Cont[1] & !B1L51 # !B1_V_Cont[1] & (B1L51 # GND);

--B1L54 is VGA_Controller:u1|V_Cont[1]~903 at LCCOMB_X20_Y35_N2
B1L54 = CARRY(!B1L51 # !B1_V_Cont[1]);


--B1L56 is VGA_Controller:u1|V_Cont[2]~904 at LCCOMB_X20_Y35_N4
B1L56 = B1_V_Cont[2] & (B1L54 $ GND) # !B1_V_Cont[2] & !B1L54 & VCC;

--B1L57 is VGA_Controller:u1|V_Cont[2]~905 at LCCOMB_X20_Y35_N4
B1L57 = CARRY(B1_V_Cont[2] & !B1L54);


--B1L59 is VGA_Controller:u1|V_Cont[3]~906 at LCCOMB_X20_Y35_N6
B1L59 = B1_V_Cont[3] & !B1L57 # !B1_V_Cont[3] & (B1L57 # GND);

--B1L60 is VGA_Controller:u1|V_Cont[3]~907 at LCCOMB_X20_Y35_N6
B1L60 = CARRY(!B1L57 # !B1_V_Cont[3]);


--B1L62 is VGA_Controller:u1|V_Cont[4]~908 at LCCOMB_X20_Y35_N8
B1L62 = B1_V_Cont[4] & (B1L60 $ GND) # !B1_V_Cont[4] & !B1L60 & VCC;

--B1L63 is VGA_Controller:u1|V_Cont[4]~909 at LCCOMB_X20_Y35_N8
B1L63 = CARRY(B1_V_Cont[4] & !B1L60);


--B1L65 is VGA_Controller:u1|V_Cont[5]~910 at LCCOMB_X20_Y35_N10
B1L65 = B1_V_Cont[5] & !B1L63 # !B1_V_Cont[5] & (B1L63 # GND);

--B1L66 is VGA_Controller:u1|V_Cont[5]~911 at LCCOMB_X20_Y35_N10
B1L66 = CARRY(!B1L63 # !B1_V_Cont[5]);


--B1L68 is VGA_Controller:u1|V_Cont[6]~912 at LCCOMB_X20_Y35_N12
B1L68 = B1_V_Cont[6] & (B1L66 $ GND) # !B1_V_Cont[6] & !B1L66 & VCC;

--B1L69 is VGA_Controller:u1|V_Cont[6]~913 at LCCOMB_X20_Y35_N12
B1L69 = CARRY(B1_V_Cont[6] & !B1L66);


--B1L43 is VGA_Controller:u1|LessThan~1092 at LCCOMB_X20_Y35_N28
B1L43 = !B1_V_Cont[8] & !B1_V_Cont[5] & !B1_V_Cont[7] & !B1_V_Cont[6];


--B1L44 is VGA_Controller:u1|LessThan~1093 at LCCOMB_X20_Y35_N26
B1L44 = !B1_V_Cont[1] & !B1_V_Cont[0] # !B1_V_Cont[2] # !B1_V_Cont[3];


--B1L45 is VGA_Controller:u1|LessThan~1094 at LCCOMB_X20_Y35_N22
B1L45 = B1_V_Cont[9] & (B1_V_Cont[4] # !B1L44 # !B1L43);


--B1L71 is VGA_Controller:u1|V_Cont[7]~914 at LCCOMB_X20_Y35_N14
B1L71 = B1_V_Cont[7] & !B1L69 # !B1_V_Cont[7] & (B1L69 # GND);

--B1L72 is VGA_Controller:u1|V_Cont[7]~915 at LCCOMB_X20_Y35_N14
B1L72 = CARRY(!B1L69 # !B1_V_Cont[7]);


--B1L74 is VGA_Controller:u1|V_Cont[8]~916 at LCCOMB_X20_Y35_N16
B1L74 = B1_V_Cont[8] & (B1L72 $ GND) # !B1_V_Cont[8] & !B1L72 & VCC;

--B1L75 is VGA_Controller:u1|V_Cont[8]~917 at LCCOMB_X20_Y35_N16
B1L75 = CARRY(B1_V_Cont[8] & !B1L72);


--B1L77 is VGA_Controller:u1|V_Cont[9]~918 at LCCOMB_X20_Y35_N18
B1L77 = B1L75 $ B1_V_Cont[9];


--B1L8 is VGA_Controller:u1|H_Cont[0]~246 at LCCOMB_X18_Y35_N4
B1L8 = B1_H_Cont[0] $ VCC;

--B1L9 is VGA_Controller:u1|H_Cont[0]~247 at LCCOMB_X18_Y35_N4
B1L9 = CARRY(B1_H_Cont[0]);


--B1L11 is VGA_Controller:u1|H_Cont[1]~248 at LCCOMB_X18_Y35_N6
B1L11 = B1_H_Cont[1] & !B1L9 # !B1_H_Cont[1] & (B1L9 # GND);

--B1L12 is VGA_Controller:u1|H_Cont[1]~249 at LCCOMB_X18_Y35_N6
B1L12 = CARRY(!B1L9 # !B1_H_Cont[1]);


--B1L14 is VGA_Controller:u1|H_Cont[2]~250 at LCCOMB_X18_Y35_N8
B1L14 = B1_H_Cont[2] & (B1L12 $ GND) # !B1_H_Cont[2] & !B1L12 & VCC;

--B1L15 is VGA_Controller:u1|H_Cont[2]~251 at LCCOMB_X18_Y35_N8
B1L15 = CARRY(B1_H_Cont[2] & !B1L12);


--B1L17 is VGA_Controller:u1|H_Cont[3]~252 at LCCOMB_X18_Y35_N10
B1L17 = B1_H_Cont[3] & !B1L15 # !B1_H_Cont[3] & (B1L15 # GND);

--B1L18 is VGA_Controller:u1|H_Cont[3]~253 at LCCOMB_X18_Y35_N10
B1L18 = CARRY(!B1L15 # !B1_H_Cont[3]);


--B1L20 is VGA_Controller:u1|H_Cont[4]~254 at LCCOMB_X18_Y35_N12
B1L20 = B1_H_Cont[4] & (B1L18 $ GND) # !B1_H_Cont[4] & !B1L18 & VCC;

--B1L21 is VGA_Controller:u1|H_Cont[4]~255 at LCCOMB_X18_Y35_N12
B1L21 = CARRY(B1_H_Cont[4] & !B1L18);


--B1L26 is VGA_Controller:u1|H_Cont[6]~256 at LCCOMB_X19_Y35_N30
B1L26 = !B1_H_Cont[6] & !B1_H_Cont[5];


--B1L46 is VGA_Controller:u1|LessThan~1095 at LCCOMB_X18_Y35_N28
B1L46 = B1_H_Cont[9] & B1_H_Cont[8] & (B1_H_Cont[7] # !B1L26);


--B1L23 is VGA_Controller:u1|H_Cont[5]~257 at LCCOMB_X18_Y35_N14
B1L23 = B1_H_Cont[5] & !B1L21 # !B1_H_Cont[5] & (B1L21 # GND);

--B1L24 is VGA_Controller:u1|H_Cont[5]~258 at LCCOMB_X18_Y35_N14
B1L24 = CARRY(!B1L21 # !B1_H_Cont[5]);


--B1L27 is VGA_Controller:u1|H_Cont[6]~259 at LCCOMB_X18_Y35_N16
B1L27 = B1_H_Cont[6] & (B1L24 $ GND) # !B1_H_Cont[6] & !B1L24 & VCC;

--B1L28 is VGA_Controller:u1|H_Cont[6]~260 at LCCOMB_X18_Y35_N16
B1L28 = CARRY(B1_H_Cont[6] & !B1L24);


--B1L30 is VGA_Controller:u1|H_Cont[7]~261 at LCCOMB_X18_Y35_N18
B1L30 = B1_H_Cont[7] & !B1L28 # !B1_H_Cont[7] & (B1L28 # GND);

--B1L31 is VGA_Controller:u1|H_Cont[7]~262 at LCCOMB_X18_Y35_N18
B1L31 = CARRY(!B1L28 # !B1_H_Cont[7]);


--B1L33 is VGA_Controller:u1|H_Cont[8]~263 at LCCOMB_X18_Y35_N20
B1L33 = B1_H_Cont[8] & (B1L31 $ GND) # !B1_H_Cont[8] & !B1L31 & VCC;

--B1L34 is VGA_Controller:u1|H_Cont[8]~264 at LCCOMB_X18_Y35_N20
B1L34 = CARRY(B1_H_Cont[8] & !B1L31);


--B1L36 is VGA_Controller:u1|H_Cont[9]~265 at LCCOMB_X18_Y35_N22
B1L36 = B1L34 $ B1_H_Cont[9];


--G1_mDATAOUT[1] is Sdram_Control_4Port:u6|mDATAOUT[1] at LCFF_X22_Y17_N3
G1_mDATAOUT[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2),  ,  ,  , A1L40,  ,  , VCC);


--G1_mDATAOUT[2] is Sdram_Control_4Port:u6|mDATAOUT[2] at LCFF_X6_Y17_N5
G1_mDATAOUT[2] = DFFEAS(G1L244, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[3] is Sdram_Control_4Port:u6|mDATAOUT[3] at LCFF_X18_Y16_N5
G1_mDATAOUT[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2),  ,  ,  , A1L44,  ,  , VCC);


--G1_mDATAOUT[4] is Sdram_Control_4Port:u6|mDATAOUT[4] at LCFF_X21_Y17_N3
G1_mDATAOUT[4] = DFFEAS(G1L247, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[5] is Sdram_Control_4Port:u6|mDATAOUT[5] at LCFF_X22_Y9_N23
G1_mDATAOUT[5] = DFFEAS(G1L249, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[6] is Sdram_Control_4Port:u6|mDATAOUT[6] at LCFF_X20_Y17_N11
G1_mDATAOUT[6] = DFFEAS(G1L251, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[7] is Sdram_Control_4Port:u6|mDATAOUT[7] at LCFF_X18_Y17_N3
G1_mDATAOUT[7] = DFFEAS(G1L253, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[8] is Sdram_Control_4Port:u6|mDATAOUT[8] at LCFF_X7_Y16_N25
G1_mDATAOUT[8] = DFFEAS(G1L255, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[9] is Sdram_Control_4Port:u6|mDATAOUT[9] at LCFF_X27_Y19_N23
G1_mDATAOUT[9] = DFFEAS(G1L257, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[10] is Sdram_Control_4Port:u6|mDATAOUT[10] at LCFF_X18_Y16_N1
G1_mDATAOUT[10] = DFFEAS(G1L259, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[11] is Sdram_Control_4Port:u6|mDATAOUT[11] at LCFF_X18_Y12_N27
G1_mDATAOUT[11] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2),  ,  ,  , A1L60,  ,  , VCC);


--G1_mDATAOUT[12] is Sdram_Control_4Port:u6|mDATAOUT[12] at LCFF_X10_Y17_N5
G1_mDATAOUT[12] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2),  ,  ,  , A1L62,  ,  , VCC);


--G1_mDATAOUT[13] is Sdram_Control_4Port:u6|mDATAOUT[13] at LCFF_X10_Y8_N21
G1_mDATAOUT[13] = DFFEAS(G1L263, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_mDATAOUT[14] is Sdram_Control_4Port:u6|mDATAOUT[14] at LCFF_X25_Y17_N11
G1_mDATAOUT[14] = DFFEAS(G1L265, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--X3_rdptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[7] at LCFF_X27_Y20_N29
X3_rdptr_g[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  , X3_valid_rdreq, Z3_power_modified_counter_values[7],  ,  , VCC);


--HB3_dffe7a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[7] at LCFF_X28_Y20_N25
HB3_dffe7a[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X3_delayed_wrptr_g[7],  ,  , VCC);


--X3_rdptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0] at LCFF_X27_Y20_N31
X3_rdptr_g[0] = DFFEAS(X3L25, GLOBAL(A1L9), GLOBAL(C1L78),  , X3_valid_rdreq,  ,  ,  ,  );


--X3_rdptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2] at LCFF_X27_Y19_N25
X3_rdptr_g[2] = DFFEAS(X3L29, GLOBAL(A1L9), GLOBAL(C1L78),  , X3_valid_rdreq,  ,  ,  ,  );


--HB3_dffe7a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[2] at LCFF_X28_Y20_N13
HB3_dffe7a[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X3_delayed_wrptr_g[2],  ,  , VCC);


--HB3_dffe7a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0] at LCFF_X28_Y20_N31
HB3_dffe7a[0] = DFFEAS(HB3L3, GLOBAL(A1L9), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X3L18 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~54 at LCCOMB_X28_Y20_N12
X3L18 = X3_rdptr_g[0] & HB3_dffe7a[0] & (X3_rdptr_g[2] $ !HB3_dffe7a[2]) # !X3_rdptr_g[0] & !HB3_dffe7a[0] & (X3_rdptr_g[2] $ !HB3_dffe7a[2]);


--X3_rdptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[6] at LCFF_X27_Y19_N29
X3_rdptr_g[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  , X3_valid_rdreq, Z3_power_modified_counter_values[6],  ,  , VCC);


--X3_rdptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[1] at LCFF_X27_Y20_N5
X3_rdptr_g[1] = DFFEAS(X3L27, GLOBAL(A1L9), GLOBAL(C1L78),  , X3_valid_rdreq,  ,  ,  ,  );


--HB3_dffe7a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1] at LCFF_X28_Y20_N19
HB3_dffe7a[1] = DFFEAS(HB3L5, GLOBAL(A1L9), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--HB3_dffe7a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[6] at LCFF_X28_Y20_N29
HB3_dffe7a[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X3_delayed_wrptr_g[6],  ,  , VCC);


--X3L19 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~55 at LCCOMB_X28_Y20_N28
X3L19 = X3_rdptr_g[6] & HB3_dffe7a[6] & (X3_rdptr_g[1] $ !HB3_dffe7a[1]) # !X3_rdptr_g[6] & !HB3_dffe7a[6] & (X3_rdptr_g[1] $ !HB3_dffe7a[1]);


--X3_rdptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[3] at LCFF_X27_Y19_N21
X3_rdptr_g[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  , X3_valid_rdreq, Z3_power_modified_counter_values[3],  ,  , VCC);


--X3_rdptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8] at LCFF_X27_Y19_N17
X3_rdptr_g[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  , X3_valid_rdreq, Z3_power_modified_counter_values[8],  ,  , VCC);


--HB3_dffe7a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[8] at LCFF_X28_Y20_N7
HB3_dffe7a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X3_delayed_wrptr_g[8],  ,  , VCC);


--HB3_dffe7a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[3] at LCFF_X28_Y20_N9
HB3_dffe7a[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X3_delayed_wrptr_g[3],  ,  , VCC);


--X3L20 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~56 at LCCOMB_X28_Y20_N8
X3L20 = X3_rdptr_g[3] & HB3_dffe7a[3] & (X3_rdptr_g[8] $ !HB3_dffe7a[8]) # !X3_rdptr_g[3] & !HB3_dffe7a[3] & (X3_rdptr_g[8] $ !HB3_dffe7a[8]);


--X3_rdptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[5] at LCFF_X27_Y19_N5
X3_rdptr_g[5] = DFFEAS(X3L34, GLOBAL(A1L9), GLOBAL(C1L78),  , X3_valid_rdreq,  ,  ,  ,  );


--X3_rdptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4] at LCFF_X27_Y20_N7
X3_rdptr_g[4] = DFFEAS(X3L32, GLOBAL(A1L9), GLOBAL(C1L78),  , X3_valid_rdreq,  ,  ,  ,  );


--HB3_dffe7a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4] at LCFF_X28_Y20_N23
HB3_dffe7a[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L9), GLOBAL(C1L78),  ,  , X3_delayed_wrptr_g[4],  ,  , VCC);


--HB3_dffe7a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[5] at LCFF_X28_Y20_N15
HB3_dffe7a[5] = DFFEAS(HB3L10, GLOBAL(A1L9), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X3L21 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~57 at LCCOMB_X28_Y20_N22
X3L21 = X3_rdptr_g[5] & HB3_dffe7a[5] & (HB3_dffe7a[4] $ !X3_rdptr_g[4]) # !X3_rdptr_g[5] & !HB3_dffe7a[5] & (HB3_dffe7a[4] $ !X3_rdptr_g[4]);


--X3L22 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~58 at LCCOMB_X28_Y20_N0
X3L22 = X3L18 & X3L21 & X3L20 & X3L19;


--X3_valid_rdreq is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq at LCCOMB_X28_Y20_N24
X3_valid_rdreq = B1_oRequest & (HB3_dffe7a[7] $ X3_rdptr_g[7] # !X3L22);


--X3_rdcnt_addr_ena is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdcnt_addr_ena at LCCOMB_X28_Y20_N16
X3_rdcnt_addr_ena = X3_valid_rdreq # !X4_p0addr;


--G1_RD_MASK[0] is Sdram_Control_4Port:u6|RD_MASK[0] at LCFF_X21_Y13_N13
G1_RD_MASK[0] = DFFEAS(G1L58, GLOBAL(KB1L2),  ,  , G1L273,  ,  ,  ,  );


--JB3_dffe9a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[7] at LCFF_X28_Y19_N7
JB3_dffe9a[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_rdptr_g[7],  ,  , VCC);


--EB3_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[7] at LCFF_X28_Y19_N29
EB3_power_modified_counter_values[7] = DFFEAS(EB3_countera7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X3L1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|_~16 at LCCOMB_X28_Y19_N6
X3L1 = JB3_dffe9a[7] $ EB3_power_modified_counter_values[7];


--JB3_dffe9a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[2] at LCFF_X27_Y19_N9
JB3_dffe9a[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_rdptr_g[2],  ,  , VCC);


--EB3_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[2] at LCFF_X28_Y19_N19
EB3_power_modified_counter_values[2] = DFFEAS(EB3_countera2, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB3_dffe9a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[0] at LCFF_X28_Y19_N11
JB3_dffe9a[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_rdptr_g[0],  ,  , VCC);


--EB3_counter_ffa[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|counter_ffa[0] at LCFF_X28_Y19_N15
EB3_counter_ffa[0] = DFFEAS(EB3_countera0, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X3L40 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~55 at LCCOMB_X28_Y19_N10
X3L40 = JB3_dffe9a[2] & EB3_power_modified_counter_values[2] & (EB3_counter_ffa[0] $ JB3_dffe9a[0]) # !JB3_dffe9a[2] & !EB3_power_modified_counter_values[2] & (EB3_counter_ffa[0] $ JB3_dffe9a[0]);


--JB3_dffe9a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[6] at LCFF_X27_Y19_N27
JB3_dffe9a[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_rdptr_g[6],  ,  , VCC);


--JB3_dffe9a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[1] at LCFF_X28_Y19_N9
JB3_dffe9a[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_rdptr_g[1],  ,  , VCC);


--EB3_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[1] at LCFF_X28_Y19_N17
EB3_power_modified_counter_values[1] = DFFEAS(EB3_countera1, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[6] at LCFF_X28_Y19_N27
EB3_power_modified_counter_values[6] = DFFEAS(EB3_countera6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X3L41 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~56 at LCCOMB_X28_Y19_N8
X3L41 = EB3_power_modified_counter_values[1] & JB3_dffe9a[1] & (JB3_dffe9a[6] $ !EB3_power_modified_counter_values[6]) # !EB3_power_modified_counter_values[1] & !JB3_dffe9a[1] & (JB3_dffe9a[6] $ !EB3_power_modified_counter_values[6]);


--JB3_dffe9a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[3] at LCFF_X27_Y19_N31
JB3_dffe9a[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_rdptr_g[3],  ,  , VCC);


--JB3_dffe9a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[8] at LCFF_X27_Y19_N3
JB3_dffe9a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_rdptr_g[8],  ,  , VCC);


--EB3_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[8] at LCFF_X28_Y19_N31
EB3_power_modified_counter_values[8] = DFFEAS(EB3_countera8, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[3] at LCFF_X28_Y19_N21
EB3_power_modified_counter_values[3] = DFFEAS(EB3_countera3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X3L42 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~57 at LCCOMB_X27_Y19_N2
X3L42 = EB3_power_modified_counter_values[8] & JB3_dffe9a[8] & (EB3_power_modified_counter_values[3] $ !JB3_dffe9a[3]) # !EB3_power_modified_counter_values[8] & !JB3_dffe9a[8] & (EB3_power_modified_counter_values[3] $ !JB3_dffe9a[3]);


--JB3_dffe9a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5] at LCFF_X27_Y19_N11
JB3_dffe9a[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_rdptr_g[5],  ,  , VCC);


--JB3_dffe9a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[4] at LCFF_X28_Y19_N1
JB3_dffe9a[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_rdptr_g[4],  ,  , VCC);


--EB3_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[4] at LCFF_X28_Y19_N23
EB3_power_modified_counter_values[4] = DFFEAS(EB3_countera4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB3_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[5] at LCFF_X28_Y19_N25
EB3_power_modified_counter_values[5] = DFFEAS(EB3_countera5, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X3L43 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~58 at LCCOMB_X28_Y19_N0
X3L43 = EB3_power_modified_counter_values[5] & JB3_dffe9a[5] & (EB3_power_modified_counter_values[4] $ !JB3_dffe9a[4]) # !EB3_power_modified_counter_values[5] & !JB3_dffe9a[5] & (EB3_power_modified_counter_values[4] $ !JB3_dffe9a[4]);


--X3L44 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~59 at LCCOMB_X28_Y19_N4
X3L44 = X3L42 & X3L43 & X3L41 & X3L40;


--X3_valid_wrreq is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_wrreq at LCCOMB_X28_Y19_N2
X3_valid_wrreq = G1_RD_MASK[0] & G1_OUT_VALID & (X3L1 # !X3L44);


--Z3_power_modified_counter_values[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[0] at LCFF_X27_Y20_N11
Z3_power_modified_counter_values[0] = DFFEAS(Z3_countera0, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[1] at LCFF_X27_Y20_N13
Z3_power_modified_counter_values[1] = DFFEAS(Z3_countera1, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[2] at LCFF_X27_Y20_N15
Z3_power_modified_counter_values[2] = DFFEAS(Z3_countera2, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[3] at LCFF_X27_Y20_N17
Z3_power_modified_counter_values[3] = DFFEAS(Z3_countera3, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[4] at LCFF_X27_Y20_N19
Z3_power_modified_counter_values[4] = DFFEAS(Z3_countera4, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[5] at LCFF_X27_Y20_N21
Z3_power_modified_counter_values[5] = DFFEAS(Z3_countera5, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[6] at LCFF_X27_Y20_N23
Z3_power_modified_counter_values[6] = DFFEAS(Z3_countera6, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[7] at LCFF_X27_Y20_N25
Z3_power_modified_counter_values[7] = DFFEAS(Z3_countera7, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z3_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8] at LCFF_X27_Y20_N27
Z3_power_modified_counter_values[8] = DFFEAS(Z3_countera8, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--X3_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0] at LCFF_X28_Y18_N31
X3_wrptr_g[0] = DFFEAS(X3L47, GLOBAL(KB1L2), GLOBAL(C1L78),  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[1] at LCFF_X28_Y18_N23
X3_wrptr_g[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X3_valid_wrreq, EB3_power_modified_counter_values[1],  ,  , VCC);


--X3_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2] at LCFF_X28_Y18_N7
X3_wrptr_g[2] = DFFEAS(X3L50, GLOBAL(KB1L2), GLOBAL(C1L78),  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[3] at LCFF_X28_Y18_N13
X3_wrptr_g[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X3_valid_wrreq, EB3_power_modified_counter_values[3],  ,  , VCC);


--X3_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[4] at LCFF_X28_Y18_N15
X3_wrptr_g[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X3_valid_wrreq, EB3_power_modified_counter_values[4],  ,  , VCC);


--X3_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5] at LCFF_X28_Y18_N21
X3_wrptr_g[5] = DFFEAS(X3L54, GLOBAL(KB1L2), GLOBAL(C1L78),  , X3_valid_wrreq,  ,  ,  ,  );


--X3_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6] at LCFF_X28_Y18_N3
X3_wrptr_g[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X3_valid_wrreq, EB3_power_modified_counter_values[6],  ,  , VCC);


--X3_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[7] at LCFF_X28_Y18_N11
X3_wrptr_g[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X3_valid_wrreq, EB3_power_modified_counter_values[7],  ,  , VCC);


--X3_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8] at LCFF_X28_Y18_N19
X3_wrptr_g[8] = DFFEAS(X3L58, GLOBAL(KB1L2), GLOBAL(C1L78),  , X3_valid_wrreq,  ,  ,  ,  );


--C1_Cont[21] is Reset_Delay:u2|Cont[21] at LCFF_X21_Y15_N21
C1_Cont[21] = DFFEAS(C1L66, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[20] is Reset_Delay:u2|Cont[20] at LCFF_X21_Y15_N19
C1_Cont[20] = DFFEAS(C1L63, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[0] is Reset_Delay:u2|Cont[0] at LCFF_X21_Y16_N11
C1_Cont[0] = DFFEAS(C1L3, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[1] is Reset_Delay:u2|Cont[1] at LCFF_X21_Y16_N13
C1_Cont[1] = DFFEAS(C1L6, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1L68 is Reset_Delay:u2|Equal~199 at LCCOMB_X21_Y16_N2
C1L68 = C1_Cont[1] & C1_Cont[0];


--C1_Cont[2] is Reset_Delay:u2|Cont[2] at LCFF_X21_Y16_N15
C1_Cont[2] = DFFEAS(C1L9, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[3] is Reset_Delay:u2|Cont[3] at LCFF_X21_Y16_N17
C1_Cont[3] = DFFEAS(C1L12, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[4] is Reset_Delay:u2|Cont[4] at LCFF_X21_Y16_N19
C1_Cont[4] = DFFEAS(C1L15, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[5] is Reset_Delay:u2|Cont[5] at LCFF_X21_Y16_N21
C1_Cont[5] = DFFEAS(C1L18, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[6] is Reset_Delay:u2|Cont[6] at LCFF_X21_Y16_N23
C1_Cont[6] = DFFEAS(C1L21, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[7] is Reset_Delay:u2|Cont[7] at LCFF_X21_Y16_N25
C1_Cont[7] = DFFEAS(C1L24, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1L69 is Reset_Delay:u2|Equal~200 at LCCOMB_X21_Y16_N0
C1L69 = C1_Cont[7] & C1_Cont[6] & C1_Cont[5] & C1_Cont[4];


--C1L70 is Reset_Delay:u2|Equal~201 at LCCOMB_X21_Y16_N8
C1L70 = C1_Cont[3] & C1L69 & C1_Cont[2] & C1L68;


--C1_Cont[8] is Reset_Delay:u2|Cont[8] at LCFF_X21_Y16_N27
C1_Cont[8] = DFFEAS(C1L27, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[9] is Reset_Delay:u2|Cont[9] at LCFF_X21_Y16_N29
C1_Cont[9] = DFFEAS(C1L30, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[10] is Reset_Delay:u2|Cont[10] at LCFF_X21_Y16_N31
C1_Cont[10] = DFFEAS(C1L33, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[11] is Reset_Delay:u2|Cont[11] at LCFF_X21_Y15_N1
C1_Cont[11] = DFFEAS(C1L36, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1L71 is Reset_Delay:u2|Equal~202 at LCCOMB_X21_Y16_N6
C1L71 = C1_Cont[10] & C1_Cont[9] & C1_Cont[11] & C1_Cont[8];


--C1_Cont[12] is Reset_Delay:u2|Cont[12] at LCFF_X21_Y15_N3
C1_Cont[12] = DFFEAS(C1L39, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[13] is Reset_Delay:u2|Cont[13] at LCFF_X21_Y15_N5
C1_Cont[13] = DFFEAS(C1L42, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[14] is Reset_Delay:u2|Cont[14] at LCFF_X21_Y15_N7
C1_Cont[14] = DFFEAS(C1L45, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[15] is Reset_Delay:u2|Cont[15] at LCFF_X21_Y15_N9
C1_Cont[15] = DFFEAS(C1L48, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1L72 is Reset_Delay:u2|Equal~203 at LCCOMB_X21_Y15_N22
C1L72 = C1_Cont[14] & C1_Cont[15] & C1_Cont[13] & C1_Cont[12];


--C1_Cont[16] is Reset_Delay:u2|Cont[16] at LCFF_X21_Y15_N11
C1_Cont[16] = DFFEAS(C1L51, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[17] is Reset_Delay:u2|Cont[17] at LCFF_X21_Y15_N13
C1_Cont[17] = DFFEAS(C1L54, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[18] is Reset_Delay:u2|Cont[18] at LCFF_X21_Y15_N15
C1_Cont[18] = DFFEAS(C1L57, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1_Cont[19] is Reset_Delay:u2|Cont[19] at LCFF_X21_Y15_N17
C1_Cont[19] = DFFEAS(C1L60, GLOBAL(A1L15), KEY[0],  , C1L75,  ,  ,  ,  );


--C1L73 is Reset_Delay:u2|Equal~204 at LCCOMB_X21_Y15_N26
C1L73 = C1_Cont[17] & C1_Cont[18] & C1_Cont[19] & C1_Cont[16];


--C1L74 is Reset_Delay:u2|Equal~205 at LCCOMB_X21_Y15_N30
C1L74 = C1L70 & C1L72 & C1L71 & C1L73;


--C1L80 is Reset_Delay:u2|oRST_1~54 at LCCOMB_X21_Y16_N4
C1L80 = C1_oRST_1 # C1_Cont[21] & (C1L74 # C1_Cont[20]);


--D1L191 is CCD_Capture:u3|mSTART~27 at LCCOMB_X57_Y10_N12
D1L191 = KEY[2] & (D1_mSTART # !KEY[3]);


--D1L105 is CCD_Capture:u3|X_Cont[0]~934 at LCCOMB_X57_Y2_N0
D1L105 = D1_X_Cont[0] $ VCC;

--D1L106 is CCD_Capture:u3|X_Cont[0]~935 at LCCOMB_X57_Y2_N0
D1L106 = CARRY(D1_X_Cont[0]);


--D1L109 is CCD_Capture:u3|X_Cont[1]~936 at LCCOMB_X57_Y2_N2
D1L109 = D1_X_Cont[1] & !D1L106 # !D1_X_Cont[1] & (D1L106 # GND);

--D1L110 is CCD_Capture:u3|X_Cont[1]~937 at LCCOMB_X57_Y2_N2
D1L110 = CARRY(!D1L106 # !D1_X_Cont[1]);


--D1L112 is CCD_Capture:u3|X_Cont[2]~938 at LCCOMB_X57_Y2_N4
D1L112 = D1_X_Cont[2] & (D1L110 $ GND) # !D1_X_Cont[2] & !D1L110 & VCC;

--D1L113 is CCD_Capture:u3|X_Cont[2]~939 at LCCOMB_X57_Y2_N4
D1L113 = CARRY(D1_X_Cont[2] & !D1L110);


--D1L115 is CCD_Capture:u3|X_Cont[3]~940 at LCCOMB_X57_Y2_N6
D1L115 = D1_X_Cont[3] & !D1L113 # !D1_X_Cont[3] & (D1L113 # GND);

--D1L116 is CCD_Capture:u3|X_Cont[3]~941 at LCCOMB_X57_Y2_N6
D1L116 = CARRY(!D1L113 # !D1_X_Cont[3]);


--D1L118 is CCD_Capture:u3|X_Cont[4]~942 at LCCOMB_X57_Y2_N8
D1L118 = D1_X_Cont[4] & (D1L116 $ GND) # !D1_X_Cont[4] & !D1L116 & VCC;

--D1L119 is CCD_Capture:u3|X_Cont[4]~943 at LCCOMB_X57_Y2_N8
D1L119 = CARRY(D1_X_Cont[4] & !D1L116);


--D1L121 is CCD_Capture:u3|X_Cont[5]~944 at LCCOMB_X57_Y2_N10
D1L121 = D1_X_Cont[5] & !D1L119 # !D1_X_Cont[5] & (D1L119 # GND);

--D1L122 is CCD_Capture:u3|X_Cont[5]~945 at LCCOMB_X57_Y2_N10
D1L122 = CARRY(!D1L119 # !D1_X_Cont[5]);


--D1L124 is CCD_Capture:u3|X_Cont[6]~946 at LCCOMB_X57_Y2_N12
D1L124 = D1_X_Cont[6] & (D1L122 $ GND) # !D1_X_Cont[6] & !D1L122 & VCC;

--D1L125 is CCD_Capture:u3|X_Cont[6]~947 at LCCOMB_X57_Y2_N12
D1L125 = CARRY(D1_X_Cont[6] & !D1L122);


--D1L127 is CCD_Capture:u3|X_Cont[7]~948 at LCCOMB_X57_Y2_N14
D1L127 = D1_X_Cont[7] & !D1L125 # !D1_X_Cont[7] & (D1L125 # GND);

--D1L128 is CCD_Capture:u3|X_Cont[7]~949 at LCCOMB_X57_Y2_N14
D1L128 = CARRY(!D1L125 # !D1_X_Cont[7]);


--D1L130 is CCD_Capture:u3|X_Cont[8]~950 at LCCOMB_X57_Y2_N16
D1L130 = D1_X_Cont[8] & (D1L128 $ GND) # !D1_X_Cont[8] & !D1L128 & VCC;

--D1L131 is CCD_Capture:u3|X_Cont[8]~951 at LCCOMB_X57_Y2_N16
D1L131 = CARRY(D1_X_Cont[8] & !D1L128);


--D1L107 is CCD_Capture:u3|X_Cont[0]~952 at LCCOMB_X57_Y2_N30
D1L107 = !D1_mCCD_FVAL # !D1L101;


--D1L133 is CCD_Capture:u3|X_Cont[9]~953 at LCCOMB_X57_Y2_N18
D1L133 = D1_X_Cont[9] & !D1L131 # !D1_X_Cont[9] & (D1L131 # GND);

--D1L134 is CCD_Capture:u3|X_Cont[9]~954 at LCCOMB_X57_Y2_N18
D1L134 = CARRY(!D1L131 # !D1_X_Cont[9]);


--D1L136 is CCD_Capture:u3|X_Cont[10]~955 at LCCOMB_X57_Y2_N20
D1L136 = D1_X_Cont[10] $ !D1L134;


--D1L188 is CCD_Capture:u3|mCCD_FVAL~40 at LCCOMB_X57_Y10_N22
D1L188 = rCCD_FVAL & (D1_mCCD_FVAL # D1_mSTART & !D1_Pre_FVAL) # !rCCD_FVAL & (D1_mCCD_FVAL & !D1_Pre_FVAL);


--R1_do_load_mode is Sdram_Control_4Port:u6|command:command1|do_load_mode at LCFF_X21_Y11_N17
R1_do_load_mode = DFFEAS(R1L51, GLOBAL(KB1L2),  ,  ,  ,  ,  , S1_INIT_REQ,  );


--S1_SADDR[8] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[8] at LCFF_X20_Y12_N31
S1_SADDR[8] = DFFEAS(S1L36, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1_do_writea is Sdram_Control_4Port:u6|command:command1|do_writea at LCFF_X19_Y10_N1
R1_do_writea = DFFEAS(R1L87, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1_do_reada is Sdram_Control_4Port:u6|command:command1|do_reada at LCFF_X20_Y11_N21
R1_do_reada = DFFEAS(R1L82, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L34 is Sdram_Control_4Port:u6|command:command1|SA~489 at LCCOMB_X20_Y12_N8
R1L34 = R1_do_load_mode # S1_SADDR[8] & (R1_do_writea # R1_do_reada);


--G1L23 is Sdram_Control_4Port:u6|Equal~1120 at LCCOMB_X18_Y10_N4
G1L23 = !G1_ST[8] & G1L19 & G1L18 & !G1_ST[2];


--G1L24 is Sdram_Control_4Port:u6|Equal~1121 at LCCOMB_X19_Y11_N20
G1L24 = G1_ST[8] & G1_ST[1];


--G1L25 is Sdram_Control_4Port:u6|Equal~1122 at LCCOMB_X18_Y10_N16
G1L25 = G1L24 & G1L19 & G1L18 & G1_ST[2];


--G1L92 is Sdram_Control_4Port:u6|ST[1]~2688 at LCCOMB_X18_Y10_N24
G1L92 = G1_ST[0] & !G1L25 # !G1_ST[0] & (G1_ST[1] # !G1L23);


--G1L126 is Sdram_Control_4Port:u6|add~2849 at LCCOMB_X17_Y10_N6
G1L126 = G1_ST[0] $ VCC;

--G1L127 is Sdram_Control_4Port:u6|add~2850 at LCCOMB_X17_Y10_N6
G1L127 = CARRY(G1_ST[0]);


--G1L128 is Sdram_Control_4Port:u6|add~2851 at LCCOMB_X17_Y10_N8
G1L128 = G1_ST[1] & !G1L127 # !G1_ST[1] & (G1L127 # GND);

--G1L129 is Sdram_Control_4Port:u6|add~2852 at LCCOMB_X17_Y10_N8
G1L129 = CARRY(!G1L127 # !G1_ST[1]);


--G1L130 is Sdram_Control_4Port:u6|add~2853 at LCCOMB_X17_Y10_N10
G1L130 = G1_ST[2] & (G1L129 $ GND) # !G1_ST[2] & !G1L129 & VCC;

--G1L131 is Sdram_Control_4Port:u6|add~2854 at LCCOMB_X17_Y10_N10
G1L131 = CARRY(G1_ST[2] & !G1L129);


--G1L26 is Sdram_Control_4Port:u6|Equal~1123 at LCCOMB_X18_Y10_N26
G1L26 = !G1_ST[1] & G1L23 & G1_ST[0];


--G1L27 is Sdram_Control_4Port:u6|Equal~1124 at LCCOMB_X18_Y10_N14
G1L27 = !G1_ST[1] & G1L23 & !G1_ST[0];


--G1_Pre_RD is Sdram_Control_4Port:u6|Pre_RD at LCFF_X22_Y13_N29
G1_Pre_RD = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2),  ,  ,  , G1_mRD,  ,  , VCC);


--G1_Pre_WR is Sdram_Control_4Port:u6|Pre_WR at LCFF_X22_Y13_N17
G1_Pre_WR = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2),  ,  ,  , G1_mWR,  ,  , VCC);


--G1_mWR is Sdram_Control_4Port:u6|mWR at LCFF_X22_Y13_N31
G1_mWR = DFFEAS(G1L280, GLOBAL(KB1L2),  ,  , G1L118,  ,  ,  ,  );


--G1_mRD is Sdram_Control_4Port:u6|mRD at LCFF_X21_Y13_N15
G1_mRD = DFFEAS(G1L274, GLOBAL(KB1L2),  ,  , G1L273,  ,  ,  ,  );


--G1L107 is Sdram_Control_4Port:u6|ST[8]~2689 at LCCOMB_X22_Y13_N16
G1L107 = G1_mRD & G1_Pre_RD & (G1_Pre_WR # !G1_mWR) # !G1_mRD & (G1_Pre_WR # !G1_mWR);


--S1_CMD_ACK is Sdram_Control_4Port:u6|control_interface:control1|CMD_ACK at LCFF_X17_Y11_N17
S1_CMD_ACK = DFFEAS(S1L65, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L108 is Sdram_Control_4Port:u6|ST[8]~2690 at LCCOMB_X18_Y10_N30
G1L108 = S1_CMD_ACK & (G1L27 & G1L107) # !S1_CMD_ACK & (G1L26 # G1L27 & G1L107);


--G1L95 is Sdram_Control_4Port:u6|ST[2]~2691 at LCCOMB_X18_Y10_N28
G1L95 = G1L130 & !G1L26 & G1L92 & !G1L108;


--G1L89 is Sdram_Control_4Port:u6|ST[0]~2692 at LCCOMB_X18_Y10_N22
G1L89 = G1L27 # G1L126 & (!G1_ST[0] # !G1L25);


--G1L90 is Sdram_Control_4Port:u6|ST[0]~2693 at LCCOMB_X18_Y10_N10
G1L90 = G1L108 & (G1_ST[0]) # !G1L108 & !G1L26 & G1L89;


--G1L132 is Sdram_Control_4Port:u6|add~2855 at LCCOMB_X17_Y10_N12
G1L132 = G1_ST[3] & !G1L131 # !G1_ST[3] & (G1L131 # GND);

--G1L133 is Sdram_Control_4Port:u6|add~2856 at LCCOMB_X17_Y10_N12
G1L133 = CARRY(!G1L131 # !G1_ST[3]);


--G1L134 is Sdram_Control_4Port:u6|add~2857 at LCCOMB_X17_Y10_N14
G1L134 = G1_ST[4] & (G1L133 $ GND) # !G1_ST[4] & !G1L133 & VCC;

--G1L135 is Sdram_Control_4Port:u6|add~2858 at LCCOMB_X17_Y10_N14
G1L135 = CARRY(G1_ST[4] & !G1L133);


--G1L136 is Sdram_Control_4Port:u6|add~2859 at LCCOMB_X17_Y10_N16
G1L136 = G1_ST[5] & !G1L135 # !G1_ST[5] & (G1L135 # GND);

--G1L137 is Sdram_Control_4Port:u6|add~2860 at LCCOMB_X17_Y10_N16
G1L137 = CARRY(!G1L135 # !G1_ST[5]);


--G1L138 is Sdram_Control_4Port:u6|add~2861 at LCCOMB_X17_Y10_N18
G1L138 = G1_ST[6] & (G1L137 $ GND) # !G1_ST[6] & !G1L137 & VCC;

--G1L139 is Sdram_Control_4Port:u6|add~2862 at LCCOMB_X17_Y10_N18
G1L139 = CARRY(G1_ST[6] & !G1L137);


--G1L140 is Sdram_Control_4Port:u6|add~2863 at LCCOMB_X17_Y10_N20
G1L140 = G1_ST[7] & !G1L139 # !G1_ST[7] & (G1L139 # GND);

--G1L141 is Sdram_Control_4Port:u6|add~2864 at LCCOMB_X17_Y10_N20
G1L141 = CARRY(!G1L139 # !G1_ST[7]);


--G1L142 is Sdram_Control_4Port:u6|add~2865 at LCCOMB_X17_Y10_N22
G1L142 = G1_ST[8] & (G1L141 $ GND) # !G1_ST[8] & !G1L141 & VCC;

--G1L143 is Sdram_Control_4Port:u6|add~2866 at LCCOMB_X17_Y10_N22
G1L143 = CARRY(G1_ST[8] & !G1L141);


--G1L144 is Sdram_Control_4Port:u6|add~2867 at LCCOMB_X17_Y10_N24
G1L144 = G1L143 $ G1_ST[9];


--G1L111 is Sdram_Control_4Port:u6|ST[9]~2694 at LCCOMB_X17_Y10_N2
G1L111 = !G1L26 & G1L92 & G1L144 & !G1L108;


--G1L105 is Sdram_Control_4Port:u6|ST[7]~2695 at LCCOMB_X17_Y10_N26
G1L105 = !G1L26 & G1L92 & G1L140 & !G1L108;


--G1L103 is Sdram_Control_4Port:u6|ST[6]~2696 at LCCOMB_X17_Y10_N4
G1L103 = G1L138 & !G1L108 & !G1L26 & G1L92;


--G1L101 is Sdram_Control_4Port:u6|ST[5]~2697 at LCCOMB_X17_Y10_N28
G1L101 = !G1L26 & G1L92 & G1L136 & !G1L108;


--G1L99 is Sdram_Control_4Port:u6|ST[4]~2698 at LCCOMB_X18_Y10_N2
G1L99 = G1L134 & !G1L26 & G1L92 & !G1L108;


--G1L97 is Sdram_Control_4Port:u6|ST[3]~2699 at LCCOMB_X18_Y10_N8
G1L97 = G1L132 & !G1L26 & G1L92 & !G1L108;


--G1L109 is Sdram_Control_4Port:u6|ST[8]~2700 at LCCOMB_X17_Y10_N0
G1L109 = G1L92 & !G1L108 & !G1L26 & G1L142;


--G1L93 is Sdram_Control_4Port:u6|ST[1]~2701 at LCCOMB_X18_Y10_N20
G1L93 = !G1L108 & (G1L26 # G1L128 & G1L92);


--S1_SADDR[9] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[9] at LCFF_X20_Y14_N9
S1_SADDR[9] = DFFEAS(S1L38, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L35 is Sdram_Control_4Port:u6|command:command1|SA~490 at LCCOMB_X20_Y12_N20
R1L35 = R1_do_load_mode # S1_SADDR[9] & (R1_do_writea # R1_do_reada);


--S1_SADDR[10] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[10] at LCFF_X20_Y14_N5
S1_SADDR[10] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2),  ,  ,  , G1_mADDR[10],  ,  , VCC);


--R1L36 is Sdram_Control_4Port:u6|command:command1|SA~491 at LCCOMB_X19_Y12_N4
R1L36 = R1_do_load_mode # S1_SADDR[10] & (R1_do_writea # R1_do_reada);


--S1_SADDR[11] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[11] at LCFF_X20_Y14_N23
S1_SADDR[11] = DFFEAS(S1L41, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L37 is Sdram_Control_4Port:u6|command:command1|SA~492 at LCCOMB_X19_Y12_N30
R1L37 = S1_SADDR[11] & !R1_do_load_mode & (R1_do_writea # R1_do_reada);


--S1_SADDR[12] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[12] at LCFF_X19_Y14_N29
S1_SADDR[12] = DFFEAS(S1L43, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L38 is Sdram_Control_4Port:u6|command:command1|SA~493 at LCCOMB_X19_Y12_N8
R1L38 = R1_do_load_mode # S1_SADDR[12] & (R1_do_writea # R1_do_reada);


--S1_SADDR[13] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[13] at LCFF_X20_Y14_N27
S1_SADDR[13] = DFFEAS(S1L45, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L39 is Sdram_Control_4Port:u6|command:command1|SA~494 at LCCOMB_X19_Y12_N14
R1L39 = R1_do_load_mode # S1_SADDR[13] & (R1_do_reada # R1_do_writea);


--S1_SADDR[14] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[14] at LCFF_X20_Y12_N19
S1_SADDR[14] = DFFEAS(S1L47, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L40 is Sdram_Control_4Port:u6|command:command1|SA~495 at LCCOMB_X20_Y12_N24
R1L40 = !R1_do_load_mode & S1_SADDR[14] & (R1_do_writea # R1_do_reada);


--S1_SADDR[15] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[15] at LCFF_X19_Y14_N23
S1_SADDR[15] = DFFEAS(S1L49, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L41 is Sdram_Control_4Port:u6|command:command1|SA~496 at LCCOMB_X19_Y12_N26
R1L41 = S1_SADDR[15] & !R1_do_load_mode & (R1_do_writea # R1_do_reada);


--S1_SADDR[16] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[16] at LCFF_X20_Y12_N15
S1_SADDR[16] = DFFEAS(S1L51, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L42 is Sdram_Control_4Port:u6|command:command1|SA~497 at LCCOMB_X20_Y12_N16
R1L42 = !R1_do_load_mode & S1_SADDR[16] & (R1_do_reada # R1_do_writea);


--S1_SADDR[17] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[17] at LCFF_X19_Y14_N1
S1_SADDR[17] = DFFEAS(S1L53, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L43 is Sdram_Control_4Port:u6|command:command1|SA~498 at LCCOMB_X19_Y12_N24
R1L43 = S1_SADDR[17] & !R1_do_load_mode & (R1_do_writea # R1_do_reada);


--R1L58 is Sdram_Control_4Port:u6|command:command1|always4~0 at LCCOMB_X19_Y12_N16
R1L58 = R1_do_writea # R1_do_reada;


--S1_SADDR[18] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[18] at LCFF_X20_Y15_N7
S1_SADDR[18] = DFFEAS(S1L55, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1_do_precharge is Sdram_Control_4Port:u6|command:command1|do_precharge at LCFF_X21_Y11_N7
R1_do_precharge = DFFEAS(R1L54, GLOBAL(KB1L2),  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1_do_rw is Sdram_Control_4Port:u6|command:command1|do_rw at LCFF_X19_Y12_N19
R1_do_rw = DFFEAS(R1L85, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L44 is Sdram_Control_4Port:u6|command:command1|SA~499 at LCCOMB_X19_Y12_N12
R1L44 = R1L58 & !R1_do_precharge & !R1_do_rw & S1_SADDR[18];


--S1_SADDR[19] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[19] at LCFF_X20_Y15_N11
S1_SADDR[19] = DFFEAS(S1L57, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L45 is Sdram_Control_4Port:u6|command:command1|SA~500 at LCCOMB_X19_Y12_N10
R1L45 = S1_SADDR[19] & !R1_do_load_mode & (R1_do_writea # R1_do_reada);


--G1L28 is Sdram_Control_4Port:u6|Equal~1125 at LCCOMB_X22_Y13_N28
G1L28 = !G1_Pre_RD & G1_mRD;


--G1L60 is Sdram_Control_4Port:u6|Read~463 at LCCOMB_X19_Y11_N4
G1L60 = !G1_ST[1] & G1L28 & !G1_ST[0] & G1L23;


--G1L123 is Sdram_Control_4Port:u6|Write~320 at LCCOMB_X19_Y11_N2
G1L123 = !G1L60 & G1_Write & (G1_ST[0] # !G1L25);


--G1L124 is Sdram_Control_4Port:u6|Write~321 at LCCOMB_X22_Y13_N26
G1L124 = !G1_Pre_WR & G1_mWR & G1L27;


--G1L125 is Sdram_Control_4Port:u6|Write~322 at LCCOMB_X19_Y11_N6
G1L125 = G1L123 # G1L124 & !G1_Write & !G1L28;


--G1L29 is Sdram_Control_4Port:u6|Equal~1126 at LCCOMB_X18_Y11_N14
G1L29 = !G1L21 # !G1_ST[2] # !G1L24 # !G1_ST[0];


--G1L61 is Sdram_Control_4Port:u6|Read~464 at LCCOMB_X19_Y11_N22
G1L61 = G1_Read & (G1L29 $ (G1L124 & !G1L60)) # !G1_Read & (G1L60);


--R1_do_refresh is Sdram_Control_4Port:u6|command:command1|do_refresh at LCFF_X20_Y11_N3
R1_do_refresh = DFFEAS(R1L56, GLOBAL(KB1L2),  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1L110 is Sdram_Control_4Port:u6|command:command1|rw_flag~24 at LCCOMB_X19_Y10_N20
R1L110 = !R1_do_load_mode & !R1_do_precharge;


--R1_rw_flag is Sdram_Control_4Port:u6|command:command1|rw_flag at LCFF_X20_Y11_N15
R1_rw_flag = DFFEAS(R1L111, GLOBAL(KB1L2),  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1L47 is Sdram_Control_4Port:u6|command:command1|WE_N~73 at LCCOMB_X19_Y12_N28
R1L47 = !R1_do_writea & R1_do_rw & !R1_do_reada;


--R1L48 is Sdram_Control_4Port:u6|command:command1|WE_N~74 at LCCOMB_X19_Y10_N10
R1L48 = R1_do_refresh # R1L110 & (R1_rw_flag # !R1L47);


--R1L7 is Sdram_Control_4Port:u6|command:command1|CAS_N~114 at LCCOMB_X19_Y10_N6
R1L7 = !R1_do_refresh & (R1_do_precharge # !R1_do_load_mode & !R1L47);


--R1_oe4 is Sdram_Control_4Port:u6|command:command1|oe4 at LCFF_X19_Y10_N3
R1_oe4 = DFFEAS(R1L94, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L16 is Sdram_Control_4Port:u6|command:command1|RAS_N~164 at LCCOMB_X19_Y10_N24
R1L16 = R1_do_precharge & (R1_rw_flag # R1_oe4);


--R1L17 is Sdram_Control_4Port:u6|command:command1|RAS_N~165 at LCCOMB_X19_Y10_N18
R1L17 = !R1_do_refresh & (R1L16 # !R1L58 & R1L110);


--S1_SADDR[22] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[22] at LCFF_X20_Y15_N17
S1_SADDR[22] = DFFEAS(S1L63, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1_do_initial is Sdram_Control_4Port:u6|command:command1|do_initial at LCFF_X19_Y10_N13
R1_do_initial = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2),  ,  ,  , S1_INIT_REQ,  ,  , VCC);


--R1L12 is Sdram_Control_4Port:u6|command:command1|CS_N~22 at LCCOMB_X19_Y10_N30
R1L12 = R1L110 & !R1_do_refresh & S1_SADDR[22] & !R1_do_initial;


--S1_SADDR[20] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[20] at LCFF_X20_Y12_N11
S1_SADDR[20] = DFFEAS(S1L59, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L4 is Sdram_Control_4Port:u6|command:command1|BA~32 at LCCOMB_X20_Y12_N12
R1L4 = S1_SADDR[20] & !R1_do_load_mode & !R1_do_precharge;


--S1_SADDR[21] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[21] at LCFF_X19_Y12_N1
S1_SADDR[21] = DFFEAS(S1L61, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L5 is Sdram_Control_4Port:u6|command:command1|BA~33 at LCCOMB_X19_Y12_N2
R1L5 = !R1_do_precharge & !R1_do_load_mode & S1_SADDR[21];


--C1L83 is Reset_Delay:u2|oRST_2~15 at LCCOMB_X21_Y15_N28
C1L83 = C1_oRST_2 # C1_Cont[21] & C1L74 & C1_Cont[20];


--B1L47 is VGA_Controller:u1|LessThan~1096 at LCCOMB_X18_Y35_N24
B1L47 = B1L1 & (!B1_H_Cont[1] # !B1_H_Cont[2] # !B1_H_Cont[3]);


--B1L79 is VGA_Controller:u1|always0~225 at LCCOMB_X19_Y35_N24
B1L79 = B1_H_Cont[8] & (!B1_H_Cont[7] & B1L47 # !B1_H_Cont[9]) # !B1_H_Cont[8] & (B1_H_Cont[9] # B1_H_Cont[7] & !B1L47);


--B1L80 is VGA_Controller:u1|always0~226 at LCCOMB_X24_Y16_N22
B1L80 = B1L79 & B1L114;


--X4_delayed_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7] at LCFF_X24_Y16_N21
X4_delayed_wrptr_g[7] = DFFEAS(X4L14, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[2] at LCFF_X23_Y15_N1
X4_delayed_wrptr_g[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_wrptr_g[2],  ,  , VCC);


--X4_delayed_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0] at LCFF_X24_Y16_N5
X4_delayed_wrptr_g[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_wrptr_g[0],  ,  , VCC);


--X4_delayed_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[1] at LCFF_X23_Y15_N17
X4_delayed_wrptr_g[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_wrptr_g[1],  ,  , VCC);


--X4_delayed_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6] at LCFF_X23_Y15_N13
X4_delayed_wrptr_g[6] = DFFEAS(X4L12, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[8] at LCFF_X24_Y16_N9
X4_delayed_wrptr_g[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_wrptr_g[8],  ,  , VCC);


--X4_delayed_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3] at LCFF_X23_Y15_N25
X4_delayed_wrptr_g[3] = DFFEAS(X4L7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X4_delayed_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[4] at LCFF_X24_Y16_N11
X4_delayed_wrptr_g[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X4_wrptr_g[4],  ,  , VCC);


--X4_delayed_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5] at LCFF_X23_Y17_N17
X4_delayed_wrptr_g[5] = DFFEAS(X4L10, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X4_rdaclr is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdaclr at LCFF_X31_Y35_N1
X4_rdaclr = DFFEAS(X4L20, !GLOBAL(A1L9), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--G1L30 is Sdram_Control_4Port:u6|Equal~1127 at LCCOMB_X19_Y11_N14
G1L30 = G1_ST[2] & G1L21 & !G1_ST[8] & G1L35;


--G1L48 is Sdram_Control_4Port:u6|OUT_VALID~138 at LCCOMB_X19_Y11_N28
G1L48 = G1_Read & (G1L30 # G1L29 & G1_OUT_VALID) # !G1_Read & (G1_OUT_VALID);


--CB11_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[8] at LCFF_X27_Y18_N23
CB11_dffe5a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , JB3_dffe9a[8],  ,  , VCC);


--X3_delayed_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[8] at LCFF_X27_Y21_N17
X3_delayed_wrptr_g[8] = DFFEAS(X3L16, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB12_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[7] at LCFF_X27_Y18_N29
CB12_dffe5a[7] = DFFEAS(AB11_xor7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB11_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[7] at LCFF_X27_Y19_N7
CB11_dffe5a[7] = DFFEAS(AB12_xor7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB12_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[6] at LCFF_X27_Y18_N27
CB12_dffe5a[6] = DFFEAS(AB11_xor6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB11_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6] at LCFF_X27_Y19_N13
CB11_dffe5a[6] = DFFEAS(AB12_xor6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB12_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[5] at LCFF_X27_Y18_N17
CB12_dffe5a[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , AB11_xor5,  ,  , VCC);


--CB11_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[5] at LCFF_X27_Y19_N15
CB11_dffe5a[5] = DFFEAS(AB12_xor5, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB12_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4] at LCFF_X27_Y18_N5
CB12_dffe5a[4] = DFFEAS(AB11_xor4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB11_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] at LCFF_X28_Y18_N17
CB11_dffe5a[4] = DFFEAS(AB12_xor4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB12_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3] at LCFF_X28_Y18_N29
CB12_dffe5a[3] = DFFEAS(AB11_xor3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB11_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3] at LCFF_X28_Y18_N27
CB11_dffe5a[3] = DFFEAS(AB12_xor3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB12_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] at LCFF_X27_Y18_N11
CB12_dffe5a[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , AB11_xor2,  ,  , VCC);


--CB11_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2] at LCFF_X28_Y18_N9
CB11_dffe5a[2] = DFFEAS(AB12_xor2, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB12_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1] at LCFF_X27_Y18_N1
CB12_dffe5a[1] = DFFEAS(AB11_xor1, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB11_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[1] at LCFF_X27_Y18_N3
CB11_dffe5a[1] = DFFEAS(AB12_xor1, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB12_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[0] at LCFF_X27_Y18_N25
CB12_dffe5a[0] = DFFEAS(AB11_xor0, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB11_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[0] at LCFF_X27_Y18_N31
CB11_dffe5a[0] = DFFEAS(AB12_xor0, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--BB6L2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~260 at LCCOMB_X27_Y18_N6
BB6L2 = CARRY(CB12_dffe5a[0] # !CB11_dffe5a[0]);


--BB6L4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~262 at LCCOMB_X27_Y18_N8
BB6L4 = CARRY(CB12_dffe5a[1] & CB11_dffe5a[1] & !BB6L2 # !CB12_dffe5a[1] & (CB11_dffe5a[1] # !BB6L2));


--BB6L6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~264 at LCCOMB_X27_Y18_N10
BB6L6 = CARRY(CB12_dffe5a[2] & (!BB6L4 # !CB11_dffe5a[2]) # !CB12_dffe5a[2] & !CB11_dffe5a[2] & !BB6L4);


--BB6L8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~266 at LCCOMB_X27_Y18_N12
BB6L8 = CARRY(CB11_dffe5a[3] & (!BB6L6 # !CB12_dffe5a[3]) # !CB11_dffe5a[3] & !CB12_dffe5a[3] & !BB6L6);


--BB6L10 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~268 at LCCOMB_X27_Y18_N14
BB6L10 = CARRY(CB11_dffe5a[4] & CB12_dffe5a[4] & !BB6L8 # !CB11_dffe5a[4] & (CB12_dffe5a[4] # !BB6L8));


--BB6L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~270 at LCCOMB_X27_Y18_N16
BB6L12 = CARRY(CB12_dffe5a[5] & CB11_dffe5a[5] & !BB6L10 # !CB12_dffe5a[5] & (CB11_dffe5a[5] # !BB6L10));


--BB6L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~272 at LCCOMB_X27_Y18_N18
BB6L14 = CARRY(CB11_dffe5a[6] & CB12_dffe5a[6] & !BB6L12 # !CB11_dffe5a[6] & (CB12_dffe5a[6] # !BB6L12));


--BB6L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~274 at LCCOMB_X27_Y18_N20
BB6L16 = CARRY(CB11_dffe5a[7] & (!BB6L14 # !CB12_dffe5a[7]) # !CB11_dffe5a[7] & !CB12_dffe5a[7] & !BB6L14);


--BB6L17 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~275 at LCCOMB_X27_Y18_N22
BB6L17 = X3_delayed_wrptr_g[8] $ BB6L16 $ !CB11_dffe5a[8];


--CB2_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[8] at LCFF_X17_Y13_N19
CB2_dffe5a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , HB1_dffe7a[8],  ,  , VCC);


--CB1_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[8] at LCFF_X16_Y14_N17
CB1_dffe5a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X1_rdptr_g[8],  ,  , VCC);


--CB2_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[7] at LCFF_X16_Y13_N27
CB2_dffe5a[7] = DFFEAS(AB2_xor7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB1_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[7] at LCFF_X16_Y13_N13
CB1_dffe5a[7] = DFFEAS(AB1_xor7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB2_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[6] at LCFF_X16_Y13_N25
CB2_dffe5a[6] = DFFEAS(AB2_xor6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB1_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[6] at LCFF_X16_Y13_N15
CB1_dffe5a[6] = DFFEAS(AB1_xor6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB2_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[5] at LCFF_X17_Y13_N13
CB2_dffe5a[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , AB2_xor5,  ,  , VCC);


--CB1_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[5] at LCFF_X16_Y13_N23
CB1_dffe5a[5] = DFFEAS(AB1_xor5, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB2_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[4] at LCFF_X25_Y13_N21
CB2_dffe5a[4] = DFFEAS(AB2_xor4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB1_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[4] at LCFF_X17_Y13_N27
CB1_dffe5a[4] = DFFEAS(AB1_xor4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB2_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[3] at LCFF_X17_Y13_N31
CB2_dffe5a[3] = DFFEAS(AB2_xor3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB1_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[3] at LCFF_X17_Y13_N23
CB1_dffe5a[3] = DFFEAS(AB1_xor3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB2_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[2] at LCFF_X17_Y13_N7
CB2_dffe5a[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , AB2_xor2,  ,  , VCC);


--CB1_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[2] at LCFF_X16_Y12_N11
CB1_dffe5a[2] = DFFEAS(AB1_xor2, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB2_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[1] at LCFF_X17_Y13_N21
CB2_dffe5a[1] = DFFEAS(AB2_xor1, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB1_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[1] at LCFF_X17_Y13_N29
CB1_dffe5a[1] = DFFEAS(AB1_xor1, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB2_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[0] at LCFF_X17_Y13_N25
CB2_dffe5a[0] = DFFEAS(AB2_xor0, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB1_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[0] at LCFF_X17_Y13_N1
CB1_dffe5a[0] = DFFEAS(AB1_xor0, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--BB1L2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~274 at LCCOMB_X17_Y13_N2
BB1L2 = CARRY(CB2_dffe5a[0] # !CB1_dffe5a[0]);


--BB1L4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~276 at LCCOMB_X17_Y13_N4
BB1L4 = CARRY(CB2_dffe5a[1] & CB1_dffe5a[1] & !BB1L2 # !CB2_dffe5a[1] & (CB1_dffe5a[1] # !BB1L2));


--BB1L6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~278 at LCCOMB_X17_Y13_N6
BB1L6 = CARRY(CB2_dffe5a[2] & (!BB1L4 # !CB1_dffe5a[2]) # !CB2_dffe5a[2] & !CB1_dffe5a[2] & !BB1L4);


--BB1L8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~280 at LCCOMB_X17_Y13_N8
BB1L8 = CARRY(CB2_dffe5a[3] & CB1_dffe5a[3] & !BB1L6 # !CB2_dffe5a[3] & (CB1_dffe5a[3] # !BB1L6));


--BB1L10 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~282 at LCCOMB_X17_Y13_N10
BB1L10 = CARRY(CB2_dffe5a[4] & (!BB1L8 # !CB1_dffe5a[4]) # !CB2_dffe5a[4] & !CB1_dffe5a[4] & !BB1L8);


--BB1L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~284 at LCCOMB_X17_Y13_N12
BB1L12 = CARRY(CB2_dffe5a[5] & CB1_dffe5a[5] & !BB1L10 # !CB2_dffe5a[5] & (CB1_dffe5a[5] # !BB1L10));


--BB1L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~286 at LCCOMB_X17_Y13_N14
BB1L14 = CARRY(CB1_dffe5a[6] & CB2_dffe5a[6] & !BB1L12 # !CB1_dffe5a[6] & (CB2_dffe5a[6] # !BB1L12));


--BB1L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~288 at LCCOMB_X17_Y13_N16
BB1L16 = CARRY(CB1_dffe5a[7] & (!BB1L14 # !CB2_dffe5a[7]) # !CB1_dffe5a[7] & !CB2_dffe5a[7] & !BB1L14);


--BB1L17 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~289 at LCCOMB_X17_Y13_N18
BB1L17 = CB1_dffe5a[8] $ BB1L16 $ CB2_dffe5a[8];


--G1_mRD_DONE is Sdram_Control_4Port:u6|mRD_DONE at LCFF_X19_Y11_N1
G1_mRD_DONE = DFFEAS(G1L268, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--CB6_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[8] at LCFF_X23_Y13_N27
CB6_dffe5a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , HB2_dffe7a[8],  ,  , VCC);


--CB5_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[8] at LCFF_X25_Y13_N9
CB5_dffe5a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X2_rdptr_g[8],  ,  , VCC);


--CB6_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[7] at LCFF_X24_Y14_N5
CB6_dffe5a[7] = DFFEAS(AB6_xor7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB5_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[7] at LCFF_X25_Y13_N23
CB5_dffe5a[7] = DFFEAS(AB5_xor7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB6_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[6] at LCFF_X24_Y14_N25
CB6_dffe5a[6] = DFFEAS(AB6_xor6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB5_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[6] at LCFF_X22_Y14_N17
CB5_dffe5a[6] = DFFEAS(AB5_xor6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB6_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[5] at LCFF_X23_Y13_N21
CB6_dffe5a[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , AB6_xor5,  ,  , VCC);


--CB5_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[5] at LCFF_X23_Y13_N1
CB5_dffe5a[5] = DFFEAS(AB5_xor5, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB6_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[4] at LCFF_X23_Y13_N9
CB6_dffe5a[4] = DFFEAS(AB6_xor4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB5_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[4] at LCFF_X23_Y13_N29
CB5_dffe5a[4] = DFFEAS(AB5_xor4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB6_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[3] at LCFF_X23_Y14_N25
CB6_dffe5a[3] = DFFEAS(AB6_xor3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB5_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[3] at LCFF_X24_Y13_N31
CB5_dffe5a[3] = DFFEAS(AB5_xor3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB6_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[2] at LCFF_X23_Y13_N15
CB6_dffe5a[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , AB6_xor2,  ,  , VCC);


--CB5_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[2] at LCFF_X24_Y13_N23
CB5_dffe5a[2] = DFFEAS(AB5_xor2, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB6_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[1] at LCFF_X23_Y13_N31
CB6_dffe5a[1] = DFFEAS(AB6_xor1, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB5_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[1] at LCFF_X23_Y13_N5
CB5_dffe5a[1] = DFFEAS(AB5_xor1, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB6_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_bwp|dffe5a[0] at LCFF_X23_Y13_N7
CB6_dffe5a[0] = DFFEAS(AB6_xor0, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB5_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:rs_brp|dffe5a[0] at LCFF_X23_Y13_N3
CB5_dffe5a[0] = DFFEAS(AB5_xor0, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--BB3L2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~267 at LCCOMB_X23_Y13_N10
BB3L2 = CARRY(CB6_dffe5a[0] # !CB5_dffe5a[0]);


--BB3L4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~269 at LCCOMB_X23_Y13_N12
BB3L4 = CARRY(CB6_dffe5a[1] & CB5_dffe5a[1] & !BB3L2 # !CB6_dffe5a[1] & (CB5_dffe5a[1] # !BB3L2));


--BB3L6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~271 at LCCOMB_X23_Y13_N14
BB3L6 = CARRY(CB5_dffe5a[2] & CB6_dffe5a[2] & !BB3L4 # !CB5_dffe5a[2] & (CB6_dffe5a[2] # !BB3L4));


--BB3L8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~273 at LCCOMB_X23_Y13_N16
BB3L8 = CARRY(CB6_dffe5a[3] & CB5_dffe5a[3] & !BB3L6 # !CB6_dffe5a[3] & (CB5_dffe5a[3] # !BB3L6));


--BB3L10 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~275 at LCCOMB_X23_Y13_N18
BB3L10 = CARRY(CB6_dffe5a[4] & (!BB3L8 # !CB5_dffe5a[4]) # !CB6_dffe5a[4] & !CB5_dffe5a[4] & !BB3L8);


--BB3L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~277 at LCCOMB_X23_Y13_N20
BB3L12 = CARRY(CB6_dffe5a[5] & CB5_dffe5a[5] & !BB3L10 # !CB6_dffe5a[5] & (CB5_dffe5a[5] # !BB3L10));


--BB3L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~279 at LCCOMB_X23_Y13_N22
BB3L14 = CARRY(CB5_dffe5a[6] & CB6_dffe5a[6] & !BB3L12 # !CB5_dffe5a[6] & (CB6_dffe5a[6] # !BB3L12));


--BB3L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~281 at LCCOMB_X23_Y13_N24
BB3L16 = CARRY(CB5_dffe5a[7] & (!BB3L14 # !CB6_dffe5a[7]) # !CB5_dffe5a[7] & !CB6_dffe5a[7] & !BB3L14);


--BB3L17 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:rdusedw_sub|add_sub_cella[0]~282 at LCCOMB_X23_Y13_N26
BB3L17 = CB5_dffe5a[8] $ BB3L16 $ !CB6_dffe5a[8];


--G1L57 is Sdram_Control_4Port:u6|RD_MASK~98 at LCCOMB_X21_Y13_N8
G1L57 = !G1_mRD_DONE & !BB6L17 & !BB1L17 & BB3L17;


--CB15_dffe5a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[8] at LCFF_X22_Y15_N17
CB15_dffe5a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , JB4_dffe9a[8],  ,  , VCC);


--CB16_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[7] at LCFF_X23_Y15_N9
CB16_dffe5a[7] = DFFEAS(AB15_xor7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB15_dffe5a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[7] at LCFF_X23_Y16_N27
CB15_dffe5a[7] = DFFEAS(AB16_xor7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB16_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[6] at LCFF_X23_Y15_N29
CB16_dffe5a[6] = DFFEAS(AB15_xor6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB15_dffe5a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6] at LCFF_X22_Y15_N23
CB15_dffe5a[6] = DFFEAS(AB16_xor6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB16_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[5] at LCFF_X22_Y15_N11
CB16_dffe5a[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , AB15_xor5,  ,  , VCC);


--CB15_dffe5a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[5] at LCFF_X23_Y16_N9
CB15_dffe5a[5] = DFFEAS(AB16_xor5, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB16_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4] at LCFF_X23_Y15_N19
CB16_dffe5a[4] = DFFEAS(AB15_xor4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB15_dffe5a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4] at LCFF_X23_Y16_N21
CB15_dffe5a[4] = DFFEAS(AB16_xor4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB16_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3] at LCFF_X22_Y15_N19
CB16_dffe5a[3] = DFFEAS(AB15_xor3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB15_dffe5a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3] at LCFF_X22_Y15_N29
CB15_dffe5a[3] = DFFEAS(AB16_xor3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB16_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[2] at LCFF_X22_Y15_N5
CB16_dffe5a[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , AB15_xor2,  ,  , VCC);


--CB15_dffe5a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2] at LCFF_X22_Y15_N25
CB15_dffe5a[2] = DFFEAS(AB16_xor2, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB16_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1] at LCFF_X23_Y15_N27
CB16_dffe5a[1] = DFFEAS(AB15_xor1, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB15_dffe5a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[1] at LCFF_X22_Y15_N31
CB15_dffe5a[1] = DFFEAS(AB16_xor1, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB16_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[0] at LCFF_X22_Y15_N21
CB16_dffe5a[0] = DFFEAS(AB15_xor0, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--CB15_dffe5a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[0] at LCFF_X22_Y15_N27
CB15_dffe5a[0] = DFFEAS(AB16_xor0, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--BB8L2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~331 at LCCOMB_X22_Y15_N0
BB8L2 = CARRY(CB16_dffe5a[0] # !CB15_dffe5a[0]);


--BB8L4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~333 at LCCOMB_X22_Y15_N2
BB8L4 = CARRY(CB16_dffe5a[1] & CB15_dffe5a[1] & !BB8L2 # !CB16_dffe5a[1] & (CB15_dffe5a[1] # !BB8L2));


--BB8L6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~335 at LCCOMB_X22_Y15_N4
BB8L6 = CARRY(CB15_dffe5a[2] & CB16_dffe5a[2] & !BB8L4 # !CB15_dffe5a[2] & (CB16_dffe5a[2] # !BB8L4));


--BB8L8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~337 at LCCOMB_X22_Y15_N6
BB8L8 = CARRY(CB16_dffe5a[3] & CB15_dffe5a[3] & !BB8L6 # !CB16_dffe5a[3] & (CB15_dffe5a[3] # !BB8L6));


--BB8L10 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~339 at LCCOMB_X22_Y15_N8
BB8L10 = CARRY(CB15_dffe5a[4] & CB16_dffe5a[4] & !BB8L8 # !CB15_dffe5a[4] & (CB16_dffe5a[4] # !BB8L8));


--BB8L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~341 at LCCOMB_X22_Y15_N10
BB8L12 = CARRY(CB16_dffe5a[5] & CB15_dffe5a[5] & !BB8L10 # !CB16_dffe5a[5] & (CB15_dffe5a[5] # !BB8L10));


--BB8L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~343 at LCCOMB_X22_Y15_N12
BB8L14 = CARRY(CB16_dffe5a[6] & (!BB8L12 # !CB15_dffe5a[6]) # !CB16_dffe5a[6] & !CB15_dffe5a[6] & !BB8L12);


--BB8L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~345 at LCCOMB_X22_Y15_N14
BB8L16 = CARRY(CB15_dffe5a[7] & (!BB8L14 # !CB16_dffe5a[7]) # !CB15_dffe5a[7] & !CB16_dffe5a[7] & !BB8L14);


--BB8L17 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~346 at LCCOMB_X22_Y15_N16
BB8L17 = CB15_dffe5a[8] $ X4_delayed_wrptr_g[8] $ BB8L16;


--BB8L19 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|add_sub_26c:wrusedw_sub|add_sub_cella[0]~348 at LCCOMB_X21_Y13_N6
BB8L19 = !BB1L17 & !BB6L17 & BB8L17 & BB3L17;


--G1L269 is Sdram_Control_4Port:u6|mRD~732 at LCCOMB_X21_Y13_N28
G1L269 = G1_RD_MASK[0] # G1_RD_MASK[1] # G1_mWR # !C1_oRST_0;


--G1_WR_MASK[1] is Sdram_Control_4Port:u6|WR_MASK[1] at LCFF_X22_Y13_N13
G1_WR_MASK[1] = DFFEAS(G1L120, GLOBAL(KB1L2),  ,  , G1L118,  ,  ,  ,  );


--G1_WR_MASK[0] is Sdram_Control_4Port:u6|WR_MASK[0] at LCFF_X20_Y13_N5
G1_WR_MASK[0] = DFFEAS(G1L121, GLOBAL(KB1L2),  ,  , G1L118,  ,  ,  ,  );


--G1L270 is Sdram_Control_4Port:u6|mRD~733 at LCCOMB_X22_Y13_N22
G1L270 = G1_WR_MASK[1] # G1_WR_MASK[0] # G1_mRD;


--G1L271 is Sdram_Control_4Port:u6|mRD~734 at LCCOMB_X21_Y13_N24
G1L271 = BB8L19 # G1L269 # G1L270;


--G1L272 is Sdram_Control_4Port:u6|mRD~735 at LCCOMB_X21_Y13_N16
G1L272 = !G1_ST[1] & G1L23 & !G1L271 & !G1_ST[0];


--G1L273 is Sdram_Control_4Port:u6|mRD~736 at LCCOMB_X21_Y13_N26
G1L273 = G1L272 # G1_mRD_DONE;


--EB4_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity_ff at LCFF_X24_Y15_N9
EB4_parity_ff = DFFEAS(EB4_parity, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB4_parity is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity at LCCOMB_X24_Y15_N8
EB4_parity = EB4_parity_ff & !X4_valid_wrreq & VCC # !EB4_parity_ff & X4_valid_wrreq;

--EB4L31 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity~COUT at LCCOMB_X24_Y15_N8
EB4L31 = CARRY(!EB4_parity_ff & X4_valid_wrreq);


--EB4_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0 at LCCOMB_X24_Y15_N10
EB4_countera0 = X4_valid_wrreq & (EB4L31 $ (GND # !EB4_counter_ffa[0])) # !X4_valid_wrreq & (EB4_counter_ffa[0] # GND);

--EB4L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0~COUT at LCCOMB_X24_Y15_N10
EB4L12 = CARRY(!EB4L31 # !X4_valid_wrreq);


--EB4_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1 at LCCOMB_X24_Y15_N12
EB4_countera1 = EB4L12 & (EB4_power_modified_counter_values[1] & VCC) # !EB4L12 & (EB4_counter_ffa[0] $ (!EB4_power_modified_counter_values[1] & VCC));

--EB4L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1~COUT at LCCOMB_X24_Y15_N12
EB4L14 = CARRY(EB4_counter_ffa[0] & !EB4L12);


--EB4_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2 at LCCOMB_X24_Y15_N14
EB4_countera2 = EB4L14 & (EB4_power_modified_counter_values[1] $ (EB4_power_modified_counter_values[2] & VCC)) # !EB4L14 & (EB4_power_modified_counter_values[2] # GND);

--EB4L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2~COUT at LCCOMB_X24_Y15_N14
EB4L16 = CARRY(EB4_power_modified_counter_values[1] # !EB4L14);


--EB4_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3 at LCCOMB_X24_Y15_N16
EB4_countera3 = EB4L16 & EB4_power_modified_counter_values[3] & (VCC) # !EB4L16 & (EB4_power_modified_counter_values[2] $ (EB4_power_modified_counter_values[3] # GND));

--EB4L18 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3~COUT at LCCOMB_X24_Y15_N16
EB4L18 = CARRY(!EB4_power_modified_counter_values[2] & !EB4L16);


--EB4_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4 at LCCOMB_X24_Y15_N18
EB4_countera4 = EB4L18 & (EB4_power_modified_counter_values[3] $ (EB4_power_modified_counter_values[4] & VCC)) # !EB4L18 & (EB4_power_modified_counter_values[4] # GND);

--EB4L20 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4~COUT at LCCOMB_X24_Y15_N18
EB4L20 = CARRY(EB4_power_modified_counter_values[3] # !EB4L18);


--EB4_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5 at LCCOMB_X24_Y15_N20
EB4_countera5 = EB4L20 & EB4_power_modified_counter_values[5] & (VCC) # !EB4L20 & (EB4_power_modified_counter_values[4] $ (EB4_power_modified_counter_values[5] # GND));

--EB4L22 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5~COUT at LCCOMB_X24_Y15_N20
EB4L22 = CARRY(!EB4_power_modified_counter_values[4] & !EB4L20);


--EB4_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6 at LCCOMB_X24_Y15_N22
EB4_countera6 = EB4L22 & (EB4_power_modified_counter_values[5] $ (EB4_power_modified_counter_values[6] & VCC)) # !EB4L22 & (EB4_power_modified_counter_values[6] # GND);

--EB4L24 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6~COUT at LCCOMB_X24_Y15_N22
EB4L24 = CARRY(EB4_power_modified_counter_values[5] # !EB4L22);


--EB4_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7 at LCCOMB_X24_Y15_N24
EB4_countera7 = EB4L24 & EB4_power_modified_counter_values[7] & (VCC) # !EB4L24 & (EB4_power_modified_counter_values[6] $ (EB4_power_modified_counter_values[7] # GND));

--EB4L26 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7~COUT at LCCOMB_X24_Y15_N24
EB4L26 = CARRY(!EB4_power_modified_counter_values[6] & !EB4L24);


--EB4_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera8 at LCCOMB_X24_Y15_N26
EB4_countera8 = EB4L26 $ EB4_power_modified_counter_values[8];


--C1L77 is Reset_Delay:u2|oRST_0~31 at LCCOMB_X21_Y13_N22
C1L77 = C1_Cont[21] # C1_oRST_0 # C1L74 & C1_Cont[20];


--Z4_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity_ff at LCFF_X25_Y16_N11
Z4_parity_ff = DFFEAS(Z4_parity, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z4_parity is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity at LCCOMB_X25_Y16_N10
Z4_parity = Z4_parity_ff & (X4_rdcnt_addr_ena $ VCC) # !Z4_parity_ff & X4_rdcnt_addr_ena & VCC;

--Z4L31 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity~COUT at LCCOMB_X25_Y16_N10
Z4L31 = CARRY(Z4_parity_ff & X4_rdcnt_addr_ena);


--Z4_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0 at LCCOMB_X25_Y16_N12
Z4_countera0 = X4_rdcnt_addr_ena & (Z4L31 $ (GND # !Z4_power_modified_counter_values[0])) # !X4_rdcnt_addr_ena & (Z4_power_modified_counter_values[0] # GND);

--Z4L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0~COUT at LCCOMB_X25_Y16_N12
Z4L12 = CARRY(!Z4L31 # !X4_rdcnt_addr_ena);


--Z4_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1 at LCCOMB_X25_Y16_N14
Z4_countera1 = Z4L12 & (Z4_power_modified_counter_values[1] & VCC) # !Z4L12 & (Z4_power_modified_counter_values[0] $ (Z4_power_modified_counter_values[1] # GND));

--Z4L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1~COUT at LCCOMB_X25_Y16_N14
Z4L14 = CARRY(!Z4_power_modified_counter_values[0] & !Z4L12);


--Z4_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2 at LCCOMB_X25_Y16_N16
Z4_countera2 = Z4L14 & (Z4_power_modified_counter_values[1] $ (Z4_power_modified_counter_values[2] & VCC)) # !Z4L14 & (Z4_power_modified_counter_values[2] # GND);

--Z4L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2~COUT at LCCOMB_X25_Y16_N16
Z4L16 = CARRY(Z4_power_modified_counter_values[1] # !Z4L14);


--Z4_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3 at LCCOMB_X25_Y16_N18
Z4_countera3 = Z4L16 & (Z4_power_modified_counter_values[3] & VCC) # !Z4L16 & (Z4_power_modified_counter_values[2] $ (Z4_power_modified_counter_values[3] # GND));

--Z4L18 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3~COUT at LCCOMB_X25_Y16_N18
Z4L18 = CARRY(!Z4_power_modified_counter_values[2] & !Z4L16);


--Z4_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4 at LCCOMB_X25_Y16_N20
Z4_countera4 = Z4L18 & (Z4_power_modified_counter_values[3] $ (Z4_power_modified_counter_values[4] & VCC)) # !Z4L18 & (Z4_power_modified_counter_values[4] # GND);

--Z4L20 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4~COUT at LCCOMB_X25_Y16_N20
Z4L20 = CARRY(Z4_power_modified_counter_values[3] # !Z4L18);


--Z4_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5 at LCCOMB_X25_Y16_N22
Z4_countera5 = Z4L20 & (Z4_power_modified_counter_values[5] & VCC) # !Z4L20 & (Z4_power_modified_counter_values[4] $ (Z4_power_modified_counter_values[5] # GND));

--Z4L22 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5~COUT at LCCOMB_X25_Y16_N22
Z4L22 = CARRY(!Z4_power_modified_counter_values[4] & !Z4L20);


--Z4_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6 at LCCOMB_X25_Y16_N24
Z4_countera6 = Z4L22 & (Z4_power_modified_counter_values[5] $ (Z4_power_modified_counter_values[6] & VCC)) # !Z4L22 & (Z4_power_modified_counter_values[6] # GND);

--Z4L24 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6~COUT at LCCOMB_X25_Y16_N24
Z4L24 = CARRY(Z4_power_modified_counter_values[5] # !Z4L22);


--Z4_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7 at LCCOMB_X25_Y16_N26
Z4_countera7 = Z4L24 & (Z4_power_modified_counter_values[7] & VCC) # !Z4L24 & (Z4_power_modified_counter_values[6] $ (Z4_power_modified_counter_values[7] # GND));

--Z4L26 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7~COUT at LCCOMB_X25_Y16_N26
Z4L26 = CARRY(!Z4_power_modified_counter_values[6] & !Z4L24);


--Z4_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera8 at LCCOMB_X25_Y16_N28
Z4_countera8 = Z4L26 $ Z4_power_modified_counter_values[8];


--X3_delayed_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7] at LCFF_X28_Y20_N21
X3_delayed_wrptr_g[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_wrptr_g[7],  ,  , VCC);


--X3_delayed_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[2] at LCFF_X28_Y18_N5
X3_delayed_wrptr_g[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_wrptr_g[2],  ,  , VCC);


--X3_delayed_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0] at LCFF_X28_Y18_N1
X3_delayed_wrptr_g[0] = DFFEAS(X3L4, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[1] at LCFF_X28_Y20_N27
X3_delayed_wrptr_g[1] = DFFEAS(X3L6, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6] at LCFF_X28_Y17_N1
X3_delayed_wrptr_g[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_wrptr_g[6],  ,  , VCC);


--X3_delayed_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3] at LCFF_X28_Y20_N5
X3_delayed_wrptr_g[3] = DFFEAS(X3L9, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X3_delayed_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[4] at LCFF_X28_Y18_N25
X3_delayed_wrptr_g[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X3_wrptr_g[4],  ,  , VCC);


--X3_delayed_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5] at LCFF_X28_Y20_N3
X3_delayed_wrptr_g[5] = DFFEAS(X3L12, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--G1L58 is Sdram_Control_4Port:u6|RD_MASK~99 at LCCOMB_X21_Y13_N12
G1L58 = !G1_mRD_DONE & BB6L17 & !BB1L17 & BB3L17;


--EB3_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity_ff at LCFF_X28_Y19_N13
EB3_parity_ff = DFFEAS(EB3_parity, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB3_parity is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity at LCCOMB_X28_Y19_N12
EB3_parity = EB3_parity_ff & !X3_valid_wrreq & VCC # !EB3_parity_ff & X3_valid_wrreq;

--EB3L31 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity~COUT at LCCOMB_X28_Y19_N12
EB3L31 = CARRY(!EB3_parity_ff & X3_valid_wrreq);


--EB3_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0 at LCCOMB_X28_Y19_N14
EB3_countera0 = X3_valid_wrreq & (EB3L31 $ (GND # !EB3_counter_ffa[0])) # !X3_valid_wrreq & (EB3_counter_ffa[0] # GND);

--EB3L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0~COUT at LCCOMB_X28_Y19_N14
EB3L12 = CARRY(!EB3L31 # !X3_valid_wrreq);


--EB3_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1 at LCCOMB_X28_Y19_N16
EB3_countera1 = EB3L12 & EB3_power_modified_counter_values[1] & (VCC) # !EB3L12 & (EB3_counter_ffa[0] $ (!EB3_power_modified_counter_values[1] & VCC));

--EB3L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1~COUT at LCCOMB_X28_Y19_N16
EB3L14 = CARRY(EB3_counter_ffa[0] & !EB3L12);


--EB3_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2 at LCCOMB_X28_Y19_N18
EB3_countera2 = EB3L14 & (EB3_power_modified_counter_values[1] $ (EB3_power_modified_counter_values[2] & VCC)) # !EB3L14 & (EB3_power_modified_counter_values[2] # GND);

--EB3L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2~COUT at LCCOMB_X28_Y19_N18
EB3L16 = CARRY(EB3_power_modified_counter_values[1] # !EB3L14);


--EB3_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3 at LCCOMB_X28_Y19_N20
EB3_countera3 = EB3L16 & EB3_power_modified_counter_values[3] & (VCC) # !EB3L16 & (EB3_power_modified_counter_values[2] $ (EB3_power_modified_counter_values[3] # GND));

--EB3L18 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3~COUT at LCCOMB_X28_Y19_N20
EB3L18 = CARRY(!EB3_power_modified_counter_values[2] & !EB3L16);


--EB3_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4 at LCCOMB_X28_Y19_N22
EB3_countera4 = EB3L18 & (EB3_power_modified_counter_values[3] $ (EB3_power_modified_counter_values[4] & VCC)) # !EB3L18 & (EB3_power_modified_counter_values[4] # GND);

--EB3L20 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4~COUT at LCCOMB_X28_Y19_N22
EB3L20 = CARRY(EB3_power_modified_counter_values[3] # !EB3L18);


--EB3_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5 at LCCOMB_X28_Y19_N24
EB3_countera5 = EB3L20 & EB3_power_modified_counter_values[5] & (VCC) # !EB3L20 & (EB3_power_modified_counter_values[4] $ (EB3_power_modified_counter_values[5] # GND));

--EB3L22 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5~COUT at LCCOMB_X28_Y19_N24
EB3L22 = CARRY(!EB3_power_modified_counter_values[4] & !EB3L20);


--EB3_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6 at LCCOMB_X28_Y19_N26
EB3_countera6 = EB3L22 & (EB3_power_modified_counter_values[5] $ (EB3_power_modified_counter_values[6] & VCC)) # !EB3L22 & (EB3_power_modified_counter_values[6] # GND);

--EB3L24 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6~COUT at LCCOMB_X28_Y19_N26
EB3L24 = CARRY(EB3_power_modified_counter_values[5] # !EB3L22);


--EB3_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7 at LCCOMB_X28_Y19_N28
EB3_countera7 = EB3L24 & EB3_power_modified_counter_values[7] & (VCC) # !EB3L24 & (EB3_power_modified_counter_values[6] $ (EB3_power_modified_counter_values[7] # GND));

--EB3L26 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7~COUT at LCCOMB_X28_Y19_N28
EB3L26 = CARRY(!EB3_power_modified_counter_values[6] & !EB3L24);


--EB3_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera8 at LCCOMB_X28_Y19_N30
EB3_countera8 = EB3L26 $ EB3_power_modified_counter_values[8];


--Z3_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity_ff at LCFF_X27_Y20_N9
Z3_parity_ff = DFFEAS(Z3_parity, GLOBAL(A1L9), GLOBAL(X4L19),  ,  ,  ,  ,  ,  );


--Z3_parity is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity at LCCOMB_X27_Y20_N8
Z3_parity = X3_rdcnt_addr_ena & (Z3_parity_ff $ VCC) # !X3_rdcnt_addr_ena & Z3_parity_ff & VCC;

--Z3L31 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity~COUT at LCCOMB_X27_Y20_N8
Z3L31 = CARRY(X3_rdcnt_addr_ena & Z3_parity_ff);


--Z3_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0 at LCCOMB_X27_Y20_N10
Z3_countera0 = X3_rdcnt_addr_ena & (Z3L31 $ (GND # !Z3_power_modified_counter_values[0])) # !X3_rdcnt_addr_ena & (Z3_power_modified_counter_values[0] # GND);

--Z3L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0~COUT at LCCOMB_X27_Y20_N10
Z3L12 = CARRY(!Z3L31 # !X3_rdcnt_addr_ena);


--Z3_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1 at LCCOMB_X27_Y20_N12
Z3_countera1 = Z3L12 & Z3_power_modified_counter_values[1] & (VCC) # !Z3L12 & (Z3_power_modified_counter_values[0] $ (Z3_power_modified_counter_values[1] # GND));

--Z3L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1~COUT at LCCOMB_X27_Y20_N12
Z3L14 = CARRY(!Z3_power_modified_counter_values[0] & !Z3L12);


--Z3_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2 at LCCOMB_X27_Y20_N14
Z3_countera2 = Z3L14 & (Z3_power_modified_counter_values[1] $ (Z3_power_modified_counter_values[2] & VCC)) # !Z3L14 & (Z3_power_modified_counter_values[2] # GND);

--Z3L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2~COUT at LCCOMB_X27_Y20_N14
Z3L16 = CARRY(Z3_power_modified_counter_values[1] # !Z3L14);


--Z3_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3 at LCCOMB_X27_Y20_N16
Z3_countera3 = Z3L16 & Z3_power_modified_counter_values[3] & (VCC) # !Z3L16 & (Z3_power_modified_counter_values[2] $ (Z3_power_modified_counter_values[3] # GND));

--Z3L18 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3~COUT at LCCOMB_X27_Y20_N16
Z3L18 = CARRY(!Z3_power_modified_counter_values[2] & !Z3L16);


--Z3_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4 at LCCOMB_X27_Y20_N18
Z3_countera4 = Z3L18 & (Z3_power_modified_counter_values[3] $ (Z3_power_modified_counter_values[4] & VCC)) # !Z3L18 & (Z3_power_modified_counter_values[4] # GND);

--Z3L20 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4~COUT at LCCOMB_X27_Y20_N18
Z3L20 = CARRY(Z3_power_modified_counter_values[3] # !Z3L18);


--Z3_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5 at LCCOMB_X27_Y20_N20
Z3_countera5 = Z3L20 & Z3_power_modified_counter_values[5] & (VCC) # !Z3L20 & (Z3_power_modified_counter_values[4] $ (Z3_power_modified_counter_values[5] # GND));

--Z3L22 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5~COUT at LCCOMB_X27_Y20_N20
Z3L22 = CARRY(!Z3_power_modified_counter_values[4] & !Z3L20);


--Z3_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6 at LCCOMB_X27_Y20_N22
Z3_countera6 = Z3L22 & (Z3_power_modified_counter_values[5] $ (Z3_power_modified_counter_values[6] & VCC)) # !Z3L22 & (Z3_power_modified_counter_values[6] # GND);

--Z3L24 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6~COUT at LCCOMB_X27_Y20_N22
Z3L24 = CARRY(Z3_power_modified_counter_values[5] # !Z3L22);


--Z3_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7 at LCCOMB_X27_Y20_N24
Z3_countera7 = Z3L24 & Z3_power_modified_counter_values[7] & (VCC) # !Z3L24 & (Z3_power_modified_counter_values[6] $ (Z3_power_modified_counter_values[7] # GND));

--Z3L26 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7~COUT at LCCOMB_X27_Y20_N24
Z3L26 = CARRY(!Z3_power_modified_counter_values[6] & !Z3L24);


--Z3_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera8 at LCCOMB_X27_Y20_N26
Z3_countera8 = Z3L26 $ Z3_power_modified_counter_values[8];


--GB1_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0] at M4K_X13_Y13
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 9, Port B Depth: 512, Port B Width: 9
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[0]_PORT_A_data_in_reg = DFFE(GB1_q_a[0]_PORT_A_data_in, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_data_in = BUS(PB3_q_b[0], PB3_q_b[3], PB3_q_b[5], PB3_q_b[6], PB3_q_b[7], PB2_q_b[6], PB2_q_b[7], PB2_q_b[9], ~GND);
GB1_q_a[0]_PORT_B_data_in_reg = DFFE(GB1_q_a[0]_PORT_B_data_in, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[0]_PORT_B_address_reg = DFFE(GB1_q_a[0]_PORT_B_address, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_write_enable = GND;
GB1_q_a[0]_PORT_A_write_enable_reg = DFFE(GB1_q_a[0]_PORT_A_write_enable, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[0]_PORT_B_write_enable_reg = DFFE(GB1_q_a[0]_PORT_B_write_enable, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[0]_clock_1 = GLOBAL(A1L11);
GB1_q_a[0]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[0]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[0]_PORT_A_data_out = MEMORY(GB1_q_a[0]_PORT_A_data_in_reg, GB1_q_a[0]_PORT_B_data_in_reg, GB1_q_a[0]_PORT_A_address_reg, GB1_q_a[0]_PORT_B_address_reg, GB1_q_a[0]_PORT_A_write_enable_reg, GB1_q_a[0]_PORT_B_write_enable_reg, , , GB1_q_a[0]_clock_0, GB1_q_a[0]_clock_1, GB1_q_a[0]_clock_enable_0, GB1_q_a[0]_clock_enable_1, , GB1_q_a[0]_clear_1);
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, GB1_q_a[0]_clear_1, , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0] = GB1_q_a[0]_PORT_A_data_out_reg[0];

--GB1_q_a[15] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[15] at M4K_X13_Y13
GB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[0]_PORT_A_data_in_reg = DFFE(GB1_q_a[0]_PORT_A_data_in, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_data_in = BUS(PB3_q_b[0], PB3_q_b[3], PB3_q_b[5], PB3_q_b[6], PB3_q_b[7], PB2_q_b[6], PB2_q_b[7], PB2_q_b[9], ~GND);
GB1_q_a[0]_PORT_B_data_in_reg = DFFE(GB1_q_a[0]_PORT_B_data_in, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[0]_PORT_B_address_reg = DFFE(GB1_q_a[0]_PORT_B_address, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_write_enable = GND;
GB1_q_a[0]_PORT_A_write_enable_reg = DFFE(GB1_q_a[0]_PORT_A_write_enable, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[0]_PORT_B_write_enable_reg = DFFE(GB1_q_a[0]_PORT_B_write_enable, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[0]_clock_1 = GLOBAL(A1L11);
GB1_q_a[0]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[0]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[0]_PORT_A_data_out = MEMORY(GB1_q_a[0]_PORT_A_data_in_reg, GB1_q_a[0]_PORT_B_data_in_reg, GB1_q_a[0]_PORT_A_address_reg, GB1_q_a[0]_PORT_B_address_reg, GB1_q_a[0]_PORT_A_write_enable_reg, GB1_q_a[0]_PORT_B_write_enable_reg, , , GB1_q_a[0]_clock_0, GB1_q_a[0]_clock_1, GB1_q_a[0]_clock_enable_0, GB1_q_a[0]_clock_enable_1, , GB1_q_a[0]_clear_1);
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, GB1_q_a[0]_clear_1, , GB1_q_a[0]_clock_enable_0);
GB1_q_a[15] = GB1_q_a[0]_PORT_A_data_out_reg[8];

--GB1_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14] at M4K_X13_Y13
GB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[0]_PORT_A_data_in_reg = DFFE(GB1_q_a[0]_PORT_A_data_in, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_data_in = BUS(PB3_q_b[0], PB3_q_b[3], PB3_q_b[5], PB3_q_b[6], PB3_q_b[7], PB2_q_b[6], PB2_q_b[7], PB2_q_b[9], ~GND);
GB1_q_a[0]_PORT_B_data_in_reg = DFFE(GB1_q_a[0]_PORT_B_data_in, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[0]_PORT_B_address_reg = DFFE(GB1_q_a[0]_PORT_B_address, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_write_enable = GND;
GB1_q_a[0]_PORT_A_write_enable_reg = DFFE(GB1_q_a[0]_PORT_A_write_enable, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[0]_PORT_B_write_enable_reg = DFFE(GB1_q_a[0]_PORT_B_write_enable, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[0]_clock_1 = GLOBAL(A1L11);
GB1_q_a[0]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[0]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[0]_PORT_A_data_out = MEMORY(GB1_q_a[0]_PORT_A_data_in_reg, GB1_q_a[0]_PORT_B_data_in_reg, GB1_q_a[0]_PORT_A_address_reg, GB1_q_a[0]_PORT_B_address_reg, GB1_q_a[0]_PORT_A_write_enable_reg, GB1_q_a[0]_PORT_B_write_enable_reg, , , GB1_q_a[0]_clock_0, GB1_q_a[0]_clock_1, GB1_q_a[0]_clock_enable_0, GB1_q_a[0]_clock_enable_1, , GB1_q_a[0]_clear_1);
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, GB1_q_a[0]_clear_1, , GB1_q_a[0]_clock_enable_0);
GB1_q_a[14] = GB1_q_a[0]_PORT_A_data_out_reg[7];

--GB1_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12] at M4K_X13_Y13
GB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[0]_PORT_A_data_in_reg = DFFE(GB1_q_a[0]_PORT_A_data_in, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_data_in = BUS(PB3_q_b[0], PB3_q_b[3], PB3_q_b[5], PB3_q_b[6], PB3_q_b[7], PB2_q_b[6], PB2_q_b[7], PB2_q_b[9], ~GND);
GB1_q_a[0]_PORT_B_data_in_reg = DFFE(GB1_q_a[0]_PORT_B_data_in, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[0]_PORT_B_address_reg = DFFE(GB1_q_a[0]_PORT_B_address, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_write_enable = GND;
GB1_q_a[0]_PORT_A_write_enable_reg = DFFE(GB1_q_a[0]_PORT_A_write_enable, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[0]_PORT_B_write_enable_reg = DFFE(GB1_q_a[0]_PORT_B_write_enable, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[0]_clock_1 = GLOBAL(A1L11);
GB1_q_a[0]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[0]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[0]_PORT_A_data_out = MEMORY(GB1_q_a[0]_PORT_A_data_in_reg, GB1_q_a[0]_PORT_B_data_in_reg, GB1_q_a[0]_PORT_A_address_reg, GB1_q_a[0]_PORT_B_address_reg, GB1_q_a[0]_PORT_A_write_enable_reg, GB1_q_a[0]_PORT_B_write_enable_reg, , , GB1_q_a[0]_clock_0, GB1_q_a[0]_clock_1, GB1_q_a[0]_clock_enable_0, GB1_q_a[0]_clock_enable_1, , GB1_q_a[0]_clear_1);
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, GB1_q_a[0]_clear_1, , GB1_q_a[0]_clock_enable_0);
GB1_q_a[12] = GB1_q_a[0]_PORT_A_data_out_reg[6];

--GB1_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11] at M4K_X13_Y13
GB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[0]_PORT_A_data_in_reg = DFFE(GB1_q_a[0]_PORT_A_data_in, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_data_in = BUS(PB3_q_b[0], PB3_q_b[3], PB3_q_b[5], PB3_q_b[6], PB3_q_b[7], PB2_q_b[6], PB2_q_b[7], PB2_q_b[9], ~GND);
GB1_q_a[0]_PORT_B_data_in_reg = DFFE(GB1_q_a[0]_PORT_B_data_in, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[0]_PORT_B_address_reg = DFFE(GB1_q_a[0]_PORT_B_address, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_write_enable = GND;
GB1_q_a[0]_PORT_A_write_enable_reg = DFFE(GB1_q_a[0]_PORT_A_write_enable, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[0]_PORT_B_write_enable_reg = DFFE(GB1_q_a[0]_PORT_B_write_enable, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[0]_clock_1 = GLOBAL(A1L11);
GB1_q_a[0]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[0]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[0]_PORT_A_data_out = MEMORY(GB1_q_a[0]_PORT_A_data_in_reg, GB1_q_a[0]_PORT_B_data_in_reg, GB1_q_a[0]_PORT_A_address_reg, GB1_q_a[0]_PORT_B_address_reg, GB1_q_a[0]_PORT_A_write_enable_reg, GB1_q_a[0]_PORT_B_write_enable_reg, , , GB1_q_a[0]_clock_0, GB1_q_a[0]_clock_1, GB1_q_a[0]_clock_enable_0, GB1_q_a[0]_clock_enable_1, , GB1_q_a[0]_clear_1);
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, GB1_q_a[0]_clear_1, , GB1_q_a[0]_clock_enable_0);
GB1_q_a[11] = GB1_q_a[0]_PORT_A_data_out_reg[5];

--GB1_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7] at M4K_X13_Y13
GB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[0]_PORT_A_data_in_reg = DFFE(GB1_q_a[0]_PORT_A_data_in, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_data_in = BUS(PB3_q_b[0], PB3_q_b[3], PB3_q_b[5], PB3_q_b[6], PB3_q_b[7], PB2_q_b[6], PB2_q_b[7], PB2_q_b[9], ~GND);
GB1_q_a[0]_PORT_B_data_in_reg = DFFE(GB1_q_a[0]_PORT_B_data_in, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[0]_PORT_B_address_reg = DFFE(GB1_q_a[0]_PORT_B_address, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_write_enable = GND;
GB1_q_a[0]_PORT_A_write_enable_reg = DFFE(GB1_q_a[0]_PORT_A_write_enable, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[0]_PORT_B_write_enable_reg = DFFE(GB1_q_a[0]_PORT_B_write_enable, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[0]_clock_1 = GLOBAL(A1L11);
GB1_q_a[0]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[0]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[0]_PORT_A_data_out = MEMORY(GB1_q_a[0]_PORT_A_data_in_reg, GB1_q_a[0]_PORT_B_data_in_reg, GB1_q_a[0]_PORT_A_address_reg, GB1_q_a[0]_PORT_B_address_reg, GB1_q_a[0]_PORT_A_write_enable_reg, GB1_q_a[0]_PORT_B_write_enable_reg, , , GB1_q_a[0]_clock_0, GB1_q_a[0]_clock_1, GB1_q_a[0]_clock_enable_0, GB1_q_a[0]_clock_enable_1, , GB1_q_a[0]_clear_1);
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, GB1_q_a[0]_clear_1, , GB1_q_a[0]_clock_enable_0);
GB1_q_a[7] = GB1_q_a[0]_PORT_A_data_out_reg[4];

--GB1_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6] at M4K_X13_Y13
GB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[0]_PORT_A_data_in_reg = DFFE(GB1_q_a[0]_PORT_A_data_in, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_data_in = BUS(PB3_q_b[0], PB3_q_b[3], PB3_q_b[5], PB3_q_b[6], PB3_q_b[7], PB2_q_b[6], PB2_q_b[7], PB2_q_b[9], ~GND);
GB1_q_a[0]_PORT_B_data_in_reg = DFFE(GB1_q_a[0]_PORT_B_data_in, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[0]_PORT_B_address_reg = DFFE(GB1_q_a[0]_PORT_B_address, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_write_enable = GND;
GB1_q_a[0]_PORT_A_write_enable_reg = DFFE(GB1_q_a[0]_PORT_A_write_enable, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[0]_PORT_B_write_enable_reg = DFFE(GB1_q_a[0]_PORT_B_write_enable, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[0]_clock_1 = GLOBAL(A1L11);
GB1_q_a[0]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[0]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[0]_PORT_A_data_out = MEMORY(GB1_q_a[0]_PORT_A_data_in_reg, GB1_q_a[0]_PORT_B_data_in_reg, GB1_q_a[0]_PORT_A_address_reg, GB1_q_a[0]_PORT_B_address_reg, GB1_q_a[0]_PORT_A_write_enable_reg, GB1_q_a[0]_PORT_B_write_enable_reg, , , GB1_q_a[0]_clock_0, GB1_q_a[0]_clock_1, GB1_q_a[0]_clock_enable_0, GB1_q_a[0]_clock_enable_1, , GB1_q_a[0]_clear_1);
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, GB1_q_a[0]_clear_1, , GB1_q_a[0]_clock_enable_0);
GB1_q_a[6] = GB1_q_a[0]_PORT_A_data_out_reg[3];

--GB1_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5] at M4K_X13_Y13
GB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[0]_PORT_A_data_in_reg = DFFE(GB1_q_a[0]_PORT_A_data_in, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_data_in = BUS(PB3_q_b[0], PB3_q_b[3], PB3_q_b[5], PB3_q_b[6], PB3_q_b[7], PB2_q_b[6], PB2_q_b[7], PB2_q_b[9], ~GND);
GB1_q_a[0]_PORT_B_data_in_reg = DFFE(GB1_q_a[0]_PORT_B_data_in, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[0]_PORT_B_address_reg = DFFE(GB1_q_a[0]_PORT_B_address, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_write_enable = GND;
GB1_q_a[0]_PORT_A_write_enable_reg = DFFE(GB1_q_a[0]_PORT_A_write_enable, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[0]_PORT_B_write_enable_reg = DFFE(GB1_q_a[0]_PORT_B_write_enable, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[0]_clock_1 = GLOBAL(A1L11);
GB1_q_a[0]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[0]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[0]_PORT_A_data_out = MEMORY(GB1_q_a[0]_PORT_A_data_in_reg, GB1_q_a[0]_PORT_B_data_in_reg, GB1_q_a[0]_PORT_A_address_reg, GB1_q_a[0]_PORT_B_address_reg, GB1_q_a[0]_PORT_A_write_enable_reg, GB1_q_a[0]_PORT_B_write_enable_reg, , , GB1_q_a[0]_clock_0, GB1_q_a[0]_clock_1, GB1_q_a[0]_clock_enable_0, GB1_q_a[0]_clock_enable_1, , GB1_q_a[0]_clear_1);
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, GB1_q_a[0]_clear_1, , GB1_q_a[0]_clock_enable_0);
GB1_q_a[5] = GB1_q_a[0]_PORT_A_data_out_reg[2];

--GB1_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3] at M4K_X13_Y13
GB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[0]_PORT_A_data_in_reg = DFFE(GB1_q_a[0]_PORT_A_data_in, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_data_in = BUS(PB3_q_b[0], PB3_q_b[3], PB3_q_b[5], PB3_q_b[6], PB3_q_b[7], PB2_q_b[6], PB2_q_b[7], PB2_q_b[9], ~GND);
GB1_q_a[0]_PORT_B_data_in_reg = DFFE(GB1_q_a[0]_PORT_B_data_in, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[0]_PORT_B_address_reg = DFFE(GB1_q_a[0]_PORT_B_address, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_PORT_A_write_enable = GND;
GB1_q_a[0]_PORT_A_write_enable_reg = DFFE(GB1_q_a[0]_PORT_A_write_enable, GB1_q_a[0]_clock_0, , , GB1_q_a[0]_clock_enable_0);
GB1_q_a[0]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[0]_PORT_B_write_enable_reg = DFFE(GB1_q_a[0]_PORT_B_write_enable, GB1_q_a[0]_clock_1, , , GB1_q_a[0]_clock_enable_1);
GB1_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[0]_clock_1 = GLOBAL(A1L11);
GB1_q_a[0]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[0]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[0]_PORT_A_data_out = MEMORY(GB1_q_a[0]_PORT_A_data_in_reg, GB1_q_a[0]_PORT_B_data_in_reg, GB1_q_a[0]_PORT_A_address_reg, GB1_q_a[0]_PORT_B_address_reg, GB1_q_a[0]_PORT_A_write_enable_reg, GB1_q_a[0]_PORT_B_write_enable_reg, , , GB1_q_a[0]_clock_0, GB1_q_a[0]_clock_1, GB1_q_a[0]_clock_enable_0, GB1_q_a[0]_clock_enable_1, , GB1_q_a[0]_clear_1);
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, GB1_q_a[0]_clear_1, , GB1_q_a[0]_clock_enable_0);
GB1_q_a[3] = GB1_q_a[0]_PORT_A_data_out_reg[1];


--GB2_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0] at M4K_X26_Y14
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 7, Port B Depth: 512, Port B Width: 7
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[0]_PORT_A_data_in_reg = DFFE(GB2_q_a[0]_PORT_A_data_in, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_data_in = BUS(PB1_q_b[0], PB1_q_b[3], PB1_q_b[4], PB1_q_b[5], PB1_q_b[7], PB2_q_b[1], PB2_q_b[2]);
GB2_q_a[0]_PORT_B_data_in_reg = DFFE(GB2_q_a[0]_PORT_B_data_in, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[0]_PORT_A_address_reg = DFFE(GB2_q_a[0]_PORT_A_address, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[0]_PORT_B_address_reg = DFFE(GB2_q_a[0]_PORT_B_address, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_write_enable = GND;
GB2_q_a[0]_PORT_A_write_enable_reg = DFFE(GB2_q_a[0]_PORT_A_write_enable, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[0]_PORT_B_write_enable_reg = DFFE(GB2_q_a[0]_PORT_B_write_enable, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[0]_clock_1 = GLOBAL(A1L11);
GB2_q_a[0]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[0]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[0]_PORT_A_data_out = MEMORY(GB2_q_a[0]_PORT_A_data_in_reg, GB2_q_a[0]_PORT_B_data_in_reg, GB2_q_a[0]_PORT_A_address_reg, GB2_q_a[0]_PORT_B_address_reg, GB2_q_a[0]_PORT_A_write_enable_reg, GB2_q_a[0]_PORT_B_write_enable_reg, , , GB2_q_a[0]_clock_0, GB2_q_a[0]_clock_1, GB2_q_a[0]_clock_enable_0, GB2_q_a[0]_clock_enable_1, , GB2_q_a[0]_clear_1);
GB2_q_a[0]_PORT_A_data_out_reg = DFFE(GB2_q_a[0]_PORT_A_data_out, GB2_q_a[0]_clock_0, GB2_q_a[0]_clear_1, , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0] = GB2_q_a[0]_PORT_A_data_out_reg[0];

--GB2_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12] at M4K_X26_Y14
GB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[0]_PORT_A_data_in_reg = DFFE(GB2_q_a[0]_PORT_A_data_in, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_data_in = BUS(PB1_q_b[0], PB1_q_b[3], PB1_q_b[4], PB1_q_b[5], PB1_q_b[7], PB2_q_b[1], PB2_q_b[2]);
GB2_q_a[0]_PORT_B_data_in_reg = DFFE(GB2_q_a[0]_PORT_B_data_in, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[0]_PORT_A_address_reg = DFFE(GB2_q_a[0]_PORT_A_address, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[0]_PORT_B_address_reg = DFFE(GB2_q_a[0]_PORT_B_address, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_write_enable = GND;
GB2_q_a[0]_PORT_A_write_enable_reg = DFFE(GB2_q_a[0]_PORT_A_write_enable, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[0]_PORT_B_write_enable_reg = DFFE(GB2_q_a[0]_PORT_B_write_enable, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[0]_clock_1 = GLOBAL(A1L11);
GB2_q_a[0]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[0]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[0]_PORT_A_data_out = MEMORY(GB2_q_a[0]_PORT_A_data_in_reg, GB2_q_a[0]_PORT_B_data_in_reg, GB2_q_a[0]_PORT_A_address_reg, GB2_q_a[0]_PORT_B_address_reg, GB2_q_a[0]_PORT_A_write_enable_reg, GB2_q_a[0]_PORT_B_write_enable_reg, , , GB2_q_a[0]_clock_0, GB2_q_a[0]_clock_1, GB2_q_a[0]_clock_enable_0, GB2_q_a[0]_clock_enable_1, , GB2_q_a[0]_clear_1);
GB2_q_a[0]_PORT_A_data_out_reg = DFFE(GB2_q_a[0]_PORT_A_data_out, GB2_q_a[0]_clock_0, GB2_q_a[0]_clear_1, , GB2_q_a[0]_clock_enable_0);
GB2_q_a[12] = GB2_q_a[0]_PORT_A_data_out_reg[6];

--GB2_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11] at M4K_X26_Y14
GB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[0]_PORT_A_data_in_reg = DFFE(GB2_q_a[0]_PORT_A_data_in, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_data_in = BUS(PB1_q_b[0], PB1_q_b[3], PB1_q_b[4], PB1_q_b[5], PB1_q_b[7], PB2_q_b[1], PB2_q_b[2]);
GB2_q_a[0]_PORT_B_data_in_reg = DFFE(GB2_q_a[0]_PORT_B_data_in, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[0]_PORT_A_address_reg = DFFE(GB2_q_a[0]_PORT_A_address, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[0]_PORT_B_address_reg = DFFE(GB2_q_a[0]_PORT_B_address, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_write_enable = GND;
GB2_q_a[0]_PORT_A_write_enable_reg = DFFE(GB2_q_a[0]_PORT_A_write_enable, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[0]_PORT_B_write_enable_reg = DFFE(GB2_q_a[0]_PORT_B_write_enable, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[0]_clock_1 = GLOBAL(A1L11);
GB2_q_a[0]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[0]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[0]_PORT_A_data_out = MEMORY(GB2_q_a[0]_PORT_A_data_in_reg, GB2_q_a[0]_PORT_B_data_in_reg, GB2_q_a[0]_PORT_A_address_reg, GB2_q_a[0]_PORT_B_address_reg, GB2_q_a[0]_PORT_A_write_enable_reg, GB2_q_a[0]_PORT_B_write_enable_reg, , , GB2_q_a[0]_clock_0, GB2_q_a[0]_clock_1, GB2_q_a[0]_clock_enable_0, GB2_q_a[0]_clock_enable_1, , GB2_q_a[0]_clear_1);
GB2_q_a[0]_PORT_A_data_out_reg = DFFE(GB2_q_a[0]_PORT_A_data_out, GB2_q_a[0]_clock_0, GB2_q_a[0]_clear_1, , GB2_q_a[0]_clock_enable_0);
GB2_q_a[11] = GB2_q_a[0]_PORT_A_data_out_reg[5];

--GB2_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7] at M4K_X26_Y14
GB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[0]_PORT_A_data_in_reg = DFFE(GB2_q_a[0]_PORT_A_data_in, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_data_in = BUS(PB1_q_b[0], PB1_q_b[3], PB1_q_b[4], PB1_q_b[5], PB1_q_b[7], PB2_q_b[1], PB2_q_b[2]);
GB2_q_a[0]_PORT_B_data_in_reg = DFFE(GB2_q_a[0]_PORT_B_data_in, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[0]_PORT_A_address_reg = DFFE(GB2_q_a[0]_PORT_A_address, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[0]_PORT_B_address_reg = DFFE(GB2_q_a[0]_PORT_B_address, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_write_enable = GND;
GB2_q_a[0]_PORT_A_write_enable_reg = DFFE(GB2_q_a[0]_PORT_A_write_enable, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[0]_PORT_B_write_enable_reg = DFFE(GB2_q_a[0]_PORT_B_write_enable, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[0]_clock_1 = GLOBAL(A1L11);
GB2_q_a[0]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[0]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[0]_PORT_A_data_out = MEMORY(GB2_q_a[0]_PORT_A_data_in_reg, GB2_q_a[0]_PORT_B_data_in_reg, GB2_q_a[0]_PORT_A_address_reg, GB2_q_a[0]_PORT_B_address_reg, GB2_q_a[0]_PORT_A_write_enable_reg, GB2_q_a[0]_PORT_B_write_enable_reg, , , GB2_q_a[0]_clock_0, GB2_q_a[0]_clock_1, GB2_q_a[0]_clock_enable_0, GB2_q_a[0]_clock_enable_1, , GB2_q_a[0]_clear_1);
GB2_q_a[0]_PORT_A_data_out_reg = DFFE(GB2_q_a[0]_PORT_A_data_out, GB2_q_a[0]_clock_0, GB2_q_a[0]_clear_1, , GB2_q_a[0]_clock_enable_0);
GB2_q_a[7] = GB2_q_a[0]_PORT_A_data_out_reg[4];

--GB2_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5] at M4K_X26_Y14
GB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[0]_PORT_A_data_in_reg = DFFE(GB2_q_a[0]_PORT_A_data_in, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_data_in = BUS(PB1_q_b[0], PB1_q_b[3], PB1_q_b[4], PB1_q_b[5], PB1_q_b[7], PB2_q_b[1], PB2_q_b[2]);
GB2_q_a[0]_PORT_B_data_in_reg = DFFE(GB2_q_a[0]_PORT_B_data_in, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[0]_PORT_A_address_reg = DFFE(GB2_q_a[0]_PORT_A_address, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[0]_PORT_B_address_reg = DFFE(GB2_q_a[0]_PORT_B_address, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_write_enable = GND;
GB2_q_a[0]_PORT_A_write_enable_reg = DFFE(GB2_q_a[0]_PORT_A_write_enable, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[0]_PORT_B_write_enable_reg = DFFE(GB2_q_a[0]_PORT_B_write_enable, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[0]_clock_1 = GLOBAL(A1L11);
GB2_q_a[0]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[0]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[0]_PORT_A_data_out = MEMORY(GB2_q_a[0]_PORT_A_data_in_reg, GB2_q_a[0]_PORT_B_data_in_reg, GB2_q_a[0]_PORT_A_address_reg, GB2_q_a[0]_PORT_B_address_reg, GB2_q_a[0]_PORT_A_write_enable_reg, GB2_q_a[0]_PORT_B_write_enable_reg, , , GB2_q_a[0]_clock_0, GB2_q_a[0]_clock_1, GB2_q_a[0]_clock_enable_0, GB2_q_a[0]_clock_enable_1, , GB2_q_a[0]_clear_1);
GB2_q_a[0]_PORT_A_data_out_reg = DFFE(GB2_q_a[0]_PORT_A_data_out, GB2_q_a[0]_clock_0, GB2_q_a[0]_clear_1, , GB2_q_a[0]_clock_enable_0);
GB2_q_a[5] = GB2_q_a[0]_PORT_A_data_out_reg[3];

--GB2_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4] at M4K_X26_Y14
GB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[0]_PORT_A_data_in_reg = DFFE(GB2_q_a[0]_PORT_A_data_in, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_data_in = BUS(PB1_q_b[0], PB1_q_b[3], PB1_q_b[4], PB1_q_b[5], PB1_q_b[7], PB2_q_b[1], PB2_q_b[2]);
GB2_q_a[0]_PORT_B_data_in_reg = DFFE(GB2_q_a[0]_PORT_B_data_in, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[0]_PORT_A_address_reg = DFFE(GB2_q_a[0]_PORT_A_address, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[0]_PORT_B_address_reg = DFFE(GB2_q_a[0]_PORT_B_address, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_write_enable = GND;
GB2_q_a[0]_PORT_A_write_enable_reg = DFFE(GB2_q_a[0]_PORT_A_write_enable, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[0]_PORT_B_write_enable_reg = DFFE(GB2_q_a[0]_PORT_B_write_enable, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[0]_clock_1 = GLOBAL(A1L11);
GB2_q_a[0]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[0]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[0]_PORT_A_data_out = MEMORY(GB2_q_a[0]_PORT_A_data_in_reg, GB2_q_a[0]_PORT_B_data_in_reg, GB2_q_a[0]_PORT_A_address_reg, GB2_q_a[0]_PORT_B_address_reg, GB2_q_a[0]_PORT_A_write_enable_reg, GB2_q_a[0]_PORT_B_write_enable_reg, , , GB2_q_a[0]_clock_0, GB2_q_a[0]_clock_1, GB2_q_a[0]_clock_enable_0, GB2_q_a[0]_clock_enable_1, , GB2_q_a[0]_clear_1);
GB2_q_a[0]_PORT_A_data_out_reg = DFFE(GB2_q_a[0]_PORT_A_data_out, GB2_q_a[0]_clock_0, GB2_q_a[0]_clear_1, , GB2_q_a[0]_clock_enable_0);
GB2_q_a[4] = GB2_q_a[0]_PORT_A_data_out_reg[2];

--GB2_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3] at M4K_X26_Y14
GB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[0]_PORT_A_data_in_reg = DFFE(GB2_q_a[0]_PORT_A_data_in, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_data_in = BUS(PB1_q_b[0], PB1_q_b[3], PB1_q_b[4], PB1_q_b[5], PB1_q_b[7], PB2_q_b[1], PB2_q_b[2]);
GB2_q_a[0]_PORT_B_data_in_reg = DFFE(GB2_q_a[0]_PORT_B_data_in, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[0]_PORT_A_address_reg = DFFE(GB2_q_a[0]_PORT_A_address, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[0]_PORT_B_address_reg = DFFE(GB2_q_a[0]_PORT_B_address, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_PORT_A_write_enable = GND;
GB2_q_a[0]_PORT_A_write_enable_reg = DFFE(GB2_q_a[0]_PORT_A_write_enable, GB2_q_a[0]_clock_0, , , GB2_q_a[0]_clock_enable_0);
GB2_q_a[0]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[0]_PORT_B_write_enable_reg = DFFE(GB2_q_a[0]_PORT_B_write_enable, GB2_q_a[0]_clock_1, , , GB2_q_a[0]_clock_enable_1);
GB2_q_a[0]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[0]_clock_1 = GLOBAL(A1L11);
GB2_q_a[0]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[0]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[0]_PORT_A_data_out = MEMORY(GB2_q_a[0]_PORT_A_data_in_reg, GB2_q_a[0]_PORT_B_data_in_reg, GB2_q_a[0]_PORT_A_address_reg, GB2_q_a[0]_PORT_B_address_reg, GB2_q_a[0]_PORT_A_write_enable_reg, GB2_q_a[0]_PORT_B_write_enable_reg, , , GB2_q_a[0]_clock_0, GB2_q_a[0]_clock_1, GB2_q_a[0]_clock_enable_0, GB2_q_a[0]_clock_enable_1, , GB2_q_a[0]_clear_1);
GB2_q_a[0]_PORT_A_data_out_reg = DFFE(GB2_q_a[0]_PORT_A_data_out, GB2_q_a[0]_clock_0, GB2_q_a[0]_clear_1, , GB2_q_a[0]_clock_enable_0);
GB2_q_a[3] = GB2_q_a[0]_PORT_A_data_out_reg[1];


--G1L223 is Sdram_Control_4Port:u6|mDATAIN[0]~160 at LCCOMB_X12_Y13_N16
G1L223 = G1_WR_MASK[0] & (GB1_q_a[0]) # !G1_WR_MASK[0] & GB2_q_a[0];


--R1_OE is Sdram_Control_4Port:u6|command:command1|OE at LCFF_X19_Y10_N29
R1_OE = DFFEAS(R1L14, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--GB1_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1] at M4K_X13_Y12
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 7, Port B Depth: 512, Port B Width: 7
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB1_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[1]_PORT_A_data_in_reg = DFFE(GB1_q_a[1]_PORT_A_data_in, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_data_in = BUS(PB3_q_b[1], PB3_q_b[2], PB3_q_b[4], PB3_q_b[8], PB3_q_b[9], PB2_q_b[5], PB2_q_b[8]);
GB1_q_a[1]_PORT_B_data_in_reg = DFFE(GB1_q_a[1]_PORT_B_data_in, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[1]_PORT_B_address_reg = DFFE(GB1_q_a[1]_PORT_B_address, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_write_enable = GND;
GB1_q_a[1]_PORT_A_write_enable_reg = DFFE(GB1_q_a[1]_PORT_A_write_enable, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[1]_PORT_B_write_enable_reg = DFFE(GB1_q_a[1]_PORT_B_write_enable, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[1]_clock_1 = GLOBAL(A1L11);
GB1_q_a[1]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[1]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[1]_PORT_A_data_out = MEMORY(GB1_q_a[1]_PORT_A_data_in_reg, GB1_q_a[1]_PORT_B_data_in_reg, GB1_q_a[1]_PORT_A_address_reg, GB1_q_a[1]_PORT_B_address_reg, GB1_q_a[1]_PORT_A_write_enable_reg, GB1_q_a[1]_PORT_B_write_enable_reg, , , GB1_q_a[1]_clock_0, GB1_q_a[1]_clock_1, GB1_q_a[1]_clock_enable_0, GB1_q_a[1]_clock_enable_1, , GB1_q_a[1]_clear_1);
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, GB1_q_a[1]_clear_1, , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1] = GB1_q_a[1]_PORT_A_data_out_reg[0];

--GB1_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13] at M4K_X13_Y12
GB1_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[1]_PORT_A_data_in_reg = DFFE(GB1_q_a[1]_PORT_A_data_in, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_data_in = BUS(PB3_q_b[1], PB3_q_b[2], PB3_q_b[4], PB3_q_b[8], PB3_q_b[9], PB2_q_b[5], PB2_q_b[8]);
GB1_q_a[1]_PORT_B_data_in_reg = DFFE(GB1_q_a[1]_PORT_B_data_in, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[1]_PORT_B_address_reg = DFFE(GB1_q_a[1]_PORT_B_address, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_write_enable = GND;
GB1_q_a[1]_PORT_A_write_enable_reg = DFFE(GB1_q_a[1]_PORT_A_write_enable, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[1]_PORT_B_write_enable_reg = DFFE(GB1_q_a[1]_PORT_B_write_enable, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[1]_clock_1 = GLOBAL(A1L11);
GB1_q_a[1]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[1]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[1]_PORT_A_data_out = MEMORY(GB1_q_a[1]_PORT_A_data_in_reg, GB1_q_a[1]_PORT_B_data_in_reg, GB1_q_a[1]_PORT_A_address_reg, GB1_q_a[1]_PORT_B_address_reg, GB1_q_a[1]_PORT_A_write_enable_reg, GB1_q_a[1]_PORT_B_write_enable_reg, , , GB1_q_a[1]_clock_0, GB1_q_a[1]_clock_1, GB1_q_a[1]_clock_enable_0, GB1_q_a[1]_clock_enable_1, , GB1_q_a[1]_clear_1);
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, GB1_q_a[1]_clear_1, , GB1_q_a[1]_clock_enable_0);
GB1_q_a[13] = GB1_q_a[1]_PORT_A_data_out_reg[6];

--GB1_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10] at M4K_X13_Y12
GB1_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[1]_PORT_A_data_in_reg = DFFE(GB1_q_a[1]_PORT_A_data_in, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_data_in = BUS(PB3_q_b[1], PB3_q_b[2], PB3_q_b[4], PB3_q_b[8], PB3_q_b[9], PB2_q_b[5], PB2_q_b[8]);
GB1_q_a[1]_PORT_B_data_in_reg = DFFE(GB1_q_a[1]_PORT_B_data_in, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[1]_PORT_B_address_reg = DFFE(GB1_q_a[1]_PORT_B_address, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_write_enable = GND;
GB1_q_a[1]_PORT_A_write_enable_reg = DFFE(GB1_q_a[1]_PORT_A_write_enable, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[1]_PORT_B_write_enable_reg = DFFE(GB1_q_a[1]_PORT_B_write_enable, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[1]_clock_1 = GLOBAL(A1L11);
GB1_q_a[1]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[1]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[1]_PORT_A_data_out = MEMORY(GB1_q_a[1]_PORT_A_data_in_reg, GB1_q_a[1]_PORT_B_data_in_reg, GB1_q_a[1]_PORT_A_address_reg, GB1_q_a[1]_PORT_B_address_reg, GB1_q_a[1]_PORT_A_write_enable_reg, GB1_q_a[1]_PORT_B_write_enable_reg, , , GB1_q_a[1]_clock_0, GB1_q_a[1]_clock_1, GB1_q_a[1]_clock_enable_0, GB1_q_a[1]_clock_enable_1, , GB1_q_a[1]_clear_1);
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, GB1_q_a[1]_clear_1, , GB1_q_a[1]_clock_enable_0);
GB1_q_a[10] = GB1_q_a[1]_PORT_A_data_out_reg[5];

--GB1_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9] at M4K_X13_Y12
GB1_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[1]_PORT_A_data_in_reg = DFFE(GB1_q_a[1]_PORT_A_data_in, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_data_in = BUS(PB3_q_b[1], PB3_q_b[2], PB3_q_b[4], PB3_q_b[8], PB3_q_b[9], PB2_q_b[5], PB2_q_b[8]);
GB1_q_a[1]_PORT_B_data_in_reg = DFFE(GB1_q_a[1]_PORT_B_data_in, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[1]_PORT_B_address_reg = DFFE(GB1_q_a[1]_PORT_B_address, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_write_enable = GND;
GB1_q_a[1]_PORT_A_write_enable_reg = DFFE(GB1_q_a[1]_PORT_A_write_enable, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[1]_PORT_B_write_enable_reg = DFFE(GB1_q_a[1]_PORT_B_write_enable, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[1]_clock_1 = GLOBAL(A1L11);
GB1_q_a[1]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[1]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[1]_PORT_A_data_out = MEMORY(GB1_q_a[1]_PORT_A_data_in_reg, GB1_q_a[1]_PORT_B_data_in_reg, GB1_q_a[1]_PORT_A_address_reg, GB1_q_a[1]_PORT_B_address_reg, GB1_q_a[1]_PORT_A_write_enable_reg, GB1_q_a[1]_PORT_B_write_enable_reg, , , GB1_q_a[1]_clock_0, GB1_q_a[1]_clock_1, GB1_q_a[1]_clock_enable_0, GB1_q_a[1]_clock_enable_1, , GB1_q_a[1]_clear_1);
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, GB1_q_a[1]_clear_1, , GB1_q_a[1]_clock_enable_0);
GB1_q_a[9] = GB1_q_a[1]_PORT_A_data_out_reg[4];

--GB1_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8] at M4K_X13_Y12
GB1_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[1]_PORT_A_data_in_reg = DFFE(GB1_q_a[1]_PORT_A_data_in, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_data_in = BUS(PB3_q_b[1], PB3_q_b[2], PB3_q_b[4], PB3_q_b[8], PB3_q_b[9], PB2_q_b[5], PB2_q_b[8]);
GB1_q_a[1]_PORT_B_data_in_reg = DFFE(GB1_q_a[1]_PORT_B_data_in, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[1]_PORT_B_address_reg = DFFE(GB1_q_a[1]_PORT_B_address, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_write_enable = GND;
GB1_q_a[1]_PORT_A_write_enable_reg = DFFE(GB1_q_a[1]_PORT_A_write_enable, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[1]_PORT_B_write_enable_reg = DFFE(GB1_q_a[1]_PORT_B_write_enable, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[1]_clock_1 = GLOBAL(A1L11);
GB1_q_a[1]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[1]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[1]_PORT_A_data_out = MEMORY(GB1_q_a[1]_PORT_A_data_in_reg, GB1_q_a[1]_PORT_B_data_in_reg, GB1_q_a[1]_PORT_A_address_reg, GB1_q_a[1]_PORT_B_address_reg, GB1_q_a[1]_PORT_A_write_enable_reg, GB1_q_a[1]_PORT_B_write_enable_reg, , , GB1_q_a[1]_clock_0, GB1_q_a[1]_clock_1, GB1_q_a[1]_clock_enable_0, GB1_q_a[1]_clock_enable_1, , GB1_q_a[1]_clear_1);
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, GB1_q_a[1]_clear_1, , GB1_q_a[1]_clock_enable_0);
GB1_q_a[8] = GB1_q_a[1]_PORT_A_data_out_reg[3];

--GB1_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4] at M4K_X13_Y12
GB1_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[1]_PORT_A_data_in_reg = DFFE(GB1_q_a[1]_PORT_A_data_in, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_data_in = BUS(PB3_q_b[1], PB3_q_b[2], PB3_q_b[4], PB3_q_b[8], PB3_q_b[9], PB2_q_b[5], PB2_q_b[8]);
GB1_q_a[1]_PORT_B_data_in_reg = DFFE(GB1_q_a[1]_PORT_B_data_in, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[1]_PORT_B_address_reg = DFFE(GB1_q_a[1]_PORT_B_address, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_write_enable = GND;
GB1_q_a[1]_PORT_A_write_enable_reg = DFFE(GB1_q_a[1]_PORT_A_write_enable, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[1]_PORT_B_write_enable_reg = DFFE(GB1_q_a[1]_PORT_B_write_enable, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[1]_clock_1 = GLOBAL(A1L11);
GB1_q_a[1]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[1]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[1]_PORT_A_data_out = MEMORY(GB1_q_a[1]_PORT_A_data_in_reg, GB1_q_a[1]_PORT_B_data_in_reg, GB1_q_a[1]_PORT_A_address_reg, GB1_q_a[1]_PORT_B_address_reg, GB1_q_a[1]_PORT_A_write_enable_reg, GB1_q_a[1]_PORT_B_write_enable_reg, , , GB1_q_a[1]_clock_0, GB1_q_a[1]_clock_1, GB1_q_a[1]_clock_enable_0, GB1_q_a[1]_clock_enable_1, , GB1_q_a[1]_clear_1);
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, GB1_q_a[1]_clear_1, , GB1_q_a[1]_clock_enable_0);
GB1_q_a[4] = GB1_q_a[1]_PORT_A_data_out_reg[2];

--GB1_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2] at M4K_X13_Y12
GB1_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB1_q_a[1]_PORT_A_data_in_reg = DFFE(GB1_q_a[1]_PORT_A_data_in, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_data_in = BUS(PB3_q_b[1], PB3_q_b[2], PB3_q_b[4], PB3_q_b[8], PB3_q_b[9], PB2_q_b[5], PB2_q_b[8]);
GB1_q_a[1]_PORT_B_data_in_reg = DFFE(GB1_q_a[1]_PORT_B_data_in, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_address = BUS(Z1_power_modified_counter_values[0], Z1_power_modified_counter_values[1], Z1_power_modified_counter_values[2], Z1_power_modified_counter_values[3], Z1_power_modified_counter_values[4], Z1_power_modified_counter_values[5], Z1_power_modified_counter_values[6], Z1_power_modified_counter_values[7], Z1_power_modified_counter_values[8]);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_address = BUS(X1_wrptr_g[0], X1_wrptr_g[1], X1_wrptr_g[2], X1_wrptr_g[3], X1_wrptr_g[4], X1_wrptr_g[5], X1_wrptr_g[6], X1_wrptr_g[7], X1_wrptr_g[8]);
GB1_q_a[1]_PORT_B_address_reg = DFFE(GB1_q_a[1]_PORT_B_address, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_PORT_A_write_enable = GND;
GB1_q_a[1]_PORT_A_write_enable_reg = DFFE(GB1_q_a[1]_PORT_A_write_enable, GB1_q_a[1]_clock_0, , , GB1_q_a[1]_clock_enable_0);
GB1_q_a[1]_PORT_B_write_enable = X1_valid_wrreq;
GB1_q_a[1]_PORT_B_write_enable_reg = DFFE(GB1_q_a[1]_PORT_B_write_enable, GB1_q_a[1]_clock_1, , , GB1_q_a[1]_clock_enable_1);
GB1_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB1_q_a[1]_clock_1 = GLOBAL(A1L11);
GB1_q_a[1]_clock_enable_0 = X1_valid_rdreq;
GB1_q_a[1]_clock_enable_1 = X1_valid_wrreq;
GB1_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB1_q_a[1]_PORT_A_data_out = MEMORY(GB1_q_a[1]_PORT_A_data_in_reg, GB1_q_a[1]_PORT_B_data_in_reg, GB1_q_a[1]_PORT_A_address_reg, GB1_q_a[1]_PORT_B_address_reg, GB1_q_a[1]_PORT_A_write_enable_reg, GB1_q_a[1]_PORT_B_write_enable_reg, , , GB1_q_a[1]_clock_0, GB1_q_a[1]_clock_1, GB1_q_a[1]_clock_enable_0, GB1_q_a[1]_clock_enable_1, , GB1_q_a[1]_clear_1);
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, GB1_q_a[1]_clear_1, , GB1_q_a[1]_clock_enable_0);
GB1_q_a[2] = GB1_q_a[1]_PORT_A_data_out_reg[1];


--GB2_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1] at M4K_X26_Y13
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 9, Port B Depth: 512, Port B Width: 9
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB2_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[1]_PORT_A_data_in_reg = DFFE(GB2_q_a[1]_PORT_A_data_in, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_data_in = BUS(PB1_q_b[1], PB1_q_b[2], PB1_q_b[6], PB1_q_b[8], PB1_q_b[9], PB2_q_b[0], PB2_q_b[3], PB2_q_b[4], ~GND);
GB2_q_a[1]_PORT_B_data_in_reg = DFFE(GB2_q_a[1]_PORT_B_data_in, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[1]_PORT_A_address_reg = DFFE(GB2_q_a[1]_PORT_A_address, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[1]_PORT_B_address_reg = DFFE(GB2_q_a[1]_PORT_B_address, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_write_enable = GND;
GB2_q_a[1]_PORT_A_write_enable_reg = DFFE(GB2_q_a[1]_PORT_A_write_enable, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[1]_PORT_B_write_enable_reg = DFFE(GB2_q_a[1]_PORT_B_write_enable, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[1]_clock_1 = GLOBAL(A1L11);
GB2_q_a[1]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[1]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[1]_PORT_A_data_out = MEMORY(GB2_q_a[1]_PORT_A_data_in_reg, GB2_q_a[1]_PORT_B_data_in_reg, GB2_q_a[1]_PORT_A_address_reg, GB2_q_a[1]_PORT_B_address_reg, GB2_q_a[1]_PORT_A_write_enable_reg, GB2_q_a[1]_PORT_B_write_enable_reg, , , GB2_q_a[1]_clock_0, GB2_q_a[1]_clock_1, GB2_q_a[1]_clock_enable_0, GB2_q_a[1]_clock_enable_1, , GB2_q_a[1]_clear_1);
GB2_q_a[1]_PORT_A_data_out_reg = DFFE(GB2_q_a[1]_PORT_A_data_out, GB2_q_a[1]_clock_0, GB2_q_a[1]_clear_1, , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1] = GB2_q_a[1]_PORT_A_data_out_reg[0];

--GB2_q_a[15] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[15] at M4K_X26_Y13
GB2_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[1]_PORT_A_data_in_reg = DFFE(GB2_q_a[1]_PORT_A_data_in, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_data_in = BUS(PB1_q_b[1], PB1_q_b[2], PB1_q_b[6], PB1_q_b[8], PB1_q_b[9], PB2_q_b[0], PB2_q_b[3], PB2_q_b[4], ~GND);
GB2_q_a[1]_PORT_B_data_in_reg = DFFE(GB2_q_a[1]_PORT_B_data_in, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[1]_PORT_A_address_reg = DFFE(GB2_q_a[1]_PORT_A_address, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[1]_PORT_B_address_reg = DFFE(GB2_q_a[1]_PORT_B_address, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_write_enable = GND;
GB2_q_a[1]_PORT_A_write_enable_reg = DFFE(GB2_q_a[1]_PORT_A_write_enable, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[1]_PORT_B_write_enable_reg = DFFE(GB2_q_a[1]_PORT_B_write_enable, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[1]_clock_1 = GLOBAL(A1L11);
GB2_q_a[1]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[1]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[1]_PORT_A_data_out = MEMORY(GB2_q_a[1]_PORT_A_data_in_reg, GB2_q_a[1]_PORT_B_data_in_reg, GB2_q_a[1]_PORT_A_address_reg, GB2_q_a[1]_PORT_B_address_reg, GB2_q_a[1]_PORT_A_write_enable_reg, GB2_q_a[1]_PORT_B_write_enable_reg, , , GB2_q_a[1]_clock_0, GB2_q_a[1]_clock_1, GB2_q_a[1]_clock_enable_0, GB2_q_a[1]_clock_enable_1, , GB2_q_a[1]_clear_1);
GB2_q_a[1]_PORT_A_data_out_reg = DFFE(GB2_q_a[1]_PORT_A_data_out, GB2_q_a[1]_clock_0, GB2_q_a[1]_clear_1, , GB2_q_a[1]_clock_enable_0);
GB2_q_a[15] = GB2_q_a[1]_PORT_A_data_out_reg[8];

--GB2_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14] at M4K_X26_Y13
GB2_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[1]_PORT_A_data_in_reg = DFFE(GB2_q_a[1]_PORT_A_data_in, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_data_in = BUS(PB1_q_b[1], PB1_q_b[2], PB1_q_b[6], PB1_q_b[8], PB1_q_b[9], PB2_q_b[0], PB2_q_b[3], PB2_q_b[4], ~GND);
GB2_q_a[1]_PORT_B_data_in_reg = DFFE(GB2_q_a[1]_PORT_B_data_in, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[1]_PORT_A_address_reg = DFFE(GB2_q_a[1]_PORT_A_address, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[1]_PORT_B_address_reg = DFFE(GB2_q_a[1]_PORT_B_address, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_write_enable = GND;
GB2_q_a[1]_PORT_A_write_enable_reg = DFFE(GB2_q_a[1]_PORT_A_write_enable, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[1]_PORT_B_write_enable_reg = DFFE(GB2_q_a[1]_PORT_B_write_enable, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[1]_clock_1 = GLOBAL(A1L11);
GB2_q_a[1]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[1]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[1]_PORT_A_data_out = MEMORY(GB2_q_a[1]_PORT_A_data_in_reg, GB2_q_a[1]_PORT_B_data_in_reg, GB2_q_a[1]_PORT_A_address_reg, GB2_q_a[1]_PORT_B_address_reg, GB2_q_a[1]_PORT_A_write_enable_reg, GB2_q_a[1]_PORT_B_write_enable_reg, , , GB2_q_a[1]_clock_0, GB2_q_a[1]_clock_1, GB2_q_a[1]_clock_enable_0, GB2_q_a[1]_clock_enable_1, , GB2_q_a[1]_clear_1);
GB2_q_a[1]_PORT_A_data_out_reg = DFFE(GB2_q_a[1]_PORT_A_data_out, GB2_q_a[1]_clock_0, GB2_q_a[1]_clear_1, , GB2_q_a[1]_clock_enable_0);
GB2_q_a[14] = GB2_q_a[1]_PORT_A_data_out_reg[7];

--GB2_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13] at M4K_X26_Y13
GB2_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[1]_PORT_A_data_in_reg = DFFE(GB2_q_a[1]_PORT_A_data_in, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_data_in = BUS(PB1_q_b[1], PB1_q_b[2], PB1_q_b[6], PB1_q_b[8], PB1_q_b[9], PB2_q_b[0], PB2_q_b[3], PB2_q_b[4], ~GND);
GB2_q_a[1]_PORT_B_data_in_reg = DFFE(GB2_q_a[1]_PORT_B_data_in, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[1]_PORT_A_address_reg = DFFE(GB2_q_a[1]_PORT_A_address, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[1]_PORT_B_address_reg = DFFE(GB2_q_a[1]_PORT_B_address, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_write_enable = GND;
GB2_q_a[1]_PORT_A_write_enable_reg = DFFE(GB2_q_a[1]_PORT_A_write_enable, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[1]_PORT_B_write_enable_reg = DFFE(GB2_q_a[1]_PORT_B_write_enable, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[1]_clock_1 = GLOBAL(A1L11);
GB2_q_a[1]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[1]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[1]_PORT_A_data_out = MEMORY(GB2_q_a[1]_PORT_A_data_in_reg, GB2_q_a[1]_PORT_B_data_in_reg, GB2_q_a[1]_PORT_A_address_reg, GB2_q_a[1]_PORT_B_address_reg, GB2_q_a[1]_PORT_A_write_enable_reg, GB2_q_a[1]_PORT_B_write_enable_reg, , , GB2_q_a[1]_clock_0, GB2_q_a[1]_clock_1, GB2_q_a[1]_clock_enable_0, GB2_q_a[1]_clock_enable_1, , GB2_q_a[1]_clear_1);
GB2_q_a[1]_PORT_A_data_out_reg = DFFE(GB2_q_a[1]_PORT_A_data_out, GB2_q_a[1]_clock_0, GB2_q_a[1]_clear_1, , GB2_q_a[1]_clock_enable_0);
GB2_q_a[13] = GB2_q_a[1]_PORT_A_data_out_reg[6];

--GB2_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10] at M4K_X26_Y13
GB2_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[1]_PORT_A_data_in_reg = DFFE(GB2_q_a[1]_PORT_A_data_in, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_data_in = BUS(PB1_q_b[1], PB1_q_b[2], PB1_q_b[6], PB1_q_b[8], PB1_q_b[9], PB2_q_b[0], PB2_q_b[3], PB2_q_b[4], ~GND);
GB2_q_a[1]_PORT_B_data_in_reg = DFFE(GB2_q_a[1]_PORT_B_data_in, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[1]_PORT_A_address_reg = DFFE(GB2_q_a[1]_PORT_A_address, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[1]_PORT_B_address_reg = DFFE(GB2_q_a[1]_PORT_B_address, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_write_enable = GND;
GB2_q_a[1]_PORT_A_write_enable_reg = DFFE(GB2_q_a[1]_PORT_A_write_enable, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[1]_PORT_B_write_enable_reg = DFFE(GB2_q_a[1]_PORT_B_write_enable, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[1]_clock_1 = GLOBAL(A1L11);
GB2_q_a[1]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[1]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[1]_PORT_A_data_out = MEMORY(GB2_q_a[1]_PORT_A_data_in_reg, GB2_q_a[1]_PORT_B_data_in_reg, GB2_q_a[1]_PORT_A_address_reg, GB2_q_a[1]_PORT_B_address_reg, GB2_q_a[1]_PORT_A_write_enable_reg, GB2_q_a[1]_PORT_B_write_enable_reg, , , GB2_q_a[1]_clock_0, GB2_q_a[1]_clock_1, GB2_q_a[1]_clock_enable_0, GB2_q_a[1]_clock_enable_1, , GB2_q_a[1]_clear_1);
GB2_q_a[1]_PORT_A_data_out_reg = DFFE(GB2_q_a[1]_PORT_A_data_out, GB2_q_a[1]_clock_0, GB2_q_a[1]_clear_1, , GB2_q_a[1]_clock_enable_0);
GB2_q_a[10] = GB2_q_a[1]_PORT_A_data_out_reg[5];

--GB2_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9] at M4K_X26_Y13
GB2_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[1]_PORT_A_data_in_reg = DFFE(GB2_q_a[1]_PORT_A_data_in, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_data_in = BUS(PB1_q_b[1], PB1_q_b[2], PB1_q_b[6], PB1_q_b[8], PB1_q_b[9], PB2_q_b[0], PB2_q_b[3], PB2_q_b[4], ~GND);
GB2_q_a[1]_PORT_B_data_in_reg = DFFE(GB2_q_a[1]_PORT_B_data_in, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[1]_PORT_A_address_reg = DFFE(GB2_q_a[1]_PORT_A_address, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[1]_PORT_B_address_reg = DFFE(GB2_q_a[1]_PORT_B_address, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_write_enable = GND;
GB2_q_a[1]_PORT_A_write_enable_reg = DFFE(GB2_q_a[1]_PORT_A_write_enable, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[1]_PORT_B_write_enable_reg = DFFE(GB2_q_a[1]_PORT_B_write_enable, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[1]_clock_1 = GLOBAL(A1L11);
GB2_q_a[1]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[1]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[1]_PORT_A_data_out = MEMORY(GB2_q_a[1]_PORT_A_data_in_reg, GB2_q_a[1]_PORT_B_data_in_reg, GB2_q_a[1]_PORT_A_address_reg, GB2_q_a[1]_PORT_B_address_reg, GB2_q_a[1]_PORT_A_write_enable_reg, GB2_q_a[1]_PORT_B_write_enable_reg, , , GB2_q_a[1]_clock_0, GB2_q_a[1]_clock_1, GB2_q_a[1]_clock_enable_0, GB2_q_a[1]_clock_enable_1, , GB2_q_a[1]_clear_1);
GB2_q_a[1]_PORT_A_data_out_reg = DFFE(GB2_q_a[1]_PORT_A_data_out, GB2_q_a[1]_clock_0, GB2_q_a[1]_clear_1, , GB2_q_a[1]_clock_enable_0);
GB2_q_a[9] = GB2_q_a[1]_PORT_A_data_out_reg[4];

--GB2_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8] at M4K_X26_Y13
GB2_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[1]_PORT_A_data_in_reg = DFFE(GB2_q_a[1]_PORT_A_data_in, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_data_in = BUS(PB1_q_b[1], PB1_q_b[2], PB1_q_b[6], PB1_q_b[8], PB1_q_b[9], PB2_q_b[0], PB2_q_b[3], PB2_q_b[4], ~GND);
GB2_q_a[1]_PORT_B_data_in_reg = DFFE(GB2_q_a[1]_PORT_B_data_in, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[1]_PORT_A_address_reg = DFFE(GB2_q_a[1]_PORT_A_address, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[1]_PORT_B_address_reg = DFFE(GB2_q_a[1]_PORT_B_address, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_write_enable = GND;
GB2_q_a[1]_PORT_A_write_enable_reg = DFFE(GB2_q_a[1]_PORT_A_write_enable, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[1]_PORT_B_write_enable_reg = DFFE(GB2_q_a[1]_PORT_B_write_enable, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[1]_clock_1 = GLOBAL(A1L11);
GB2_q_a[1]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[1]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[1]_PORT_A_data_out = MEMORY(GB2_q_a[1]_PORT_A_data_in_reg, GB2_q_a[1]_PORT_B_data_in_reg, GB2_q_a[1]_PORT_A_address_reg, GB2_q_a[1]_PORT_B_address_reg, GB2_q_a[1]_PORT_A_write_enable_reg, GB2_q_a[1]_PORT_B_write_enable_reg, , , GB2_q_a[1]_clock_0, GB2_q_a[1]_clock_1, GB2_q_a[1]_clock_enable_0, GB2_q_a[1]_clock_enable_1, , GB2_q_a[1]_clear_1);
GB2_q_a[1]_PORT_A_data_out_reg = DFFE(GB2_q_a[1]_PORT_A_data_out, GB2_q_a[1]_clock_0, GB2_q_a[1]_clear_1, , GB2_q_a[1]_clock_enable_0);
GB2_q_a[8] = GB2_q_a[1]_PORT_A_data_out_reg[3];

--GB2_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6] at M4K_X26_Y13
GB2_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[1]_PORT_A_data_in_reg = DFFE(GB2_q_a[1]_PORT_A_data_in, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_data_in = BUS(PB1_q_b[1], PB1_q_b[2], PB1_q_b[6], PB1_q_b[8], PB1_q_b[9], PB2_q_b[0], PB2_q_b[3], PB2_q_b[4], ~GND);
GB2_q_a[1]_PORT_B_data_in_reg = DFFE(GB2_q_a[1]_PORT_B_data_in, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[1]_PORT_A_address_reg = DFFE(GB2_q_a[1]_PORT_A_address, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[1]_PORT_B_address_reg = DFFE(GB2_q_a[1]_PORT_B_address, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_write_enable = GND;
GB2_q_a[1]_PORT_A_write_enable_reg = DFFE(GB2_q_a[1]_PORT_A_write_enable, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[1]_PORT_B_write_enable_reg = DFFE(GB2_q_a[1]_PORT_B_write_enable, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[1]_clock_1 = GLOBAL(A1L11);
GB2_q_a[1]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[1]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[1]_PORT_A_data_out = MEMORY(GB2_q_a[1]_PORT_A_data_in_reg, GB2_q_a[1]_PORT_B_data_in_reg, GB2_q_a[1]_PORT_A_address_reg, GB2_q_a[1]_PORT_B_address_reg, GB2_q_a[1]_PORT_A_write_enable_reg, GB2_q_a[1]_PORT_B_write_enable_reg, , , GB2_q_a[1]_clock_0, GB2_q_a[1]_clock_1, GB2_q_a[1]_clock_enable_0, GB2_q_a[1]_clock_enable_1, , GB2_q_a[1]_clear_1);
GB2_q_a[1]_PORT_A_data_out_reg = DFFE(GB2_q_a[1]_PORT_A_data_out, GB2_q_a[1]_clock_0, GB2_q_a[1]_clear_1, , GB2_q_a[1]_clock_enable_0);
GB2_q_a[6] = GB2_q_a[1]_PORT_A_data_out_reg[2];

--GB2_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2] at M4K_X26_Y13
GB2_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB2_q_a[1]_PORT_A_data_in_reg = DFFE(GB2_q_a[1]_PORT_A_data_in, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_data_in = BUS(PB1_q_b[1], PB1_q_b[2], PB1_q_b[6], PB1_q_b[8], PB1_q_b[9], PB2_q_b[0], PB2_q_b[3], PB2_q_b[4], ~GND);
GB2_q_a[1]_PORT_B_data_in_reg = DFFE(GB2_q_a[1]_PORT_B_data_in, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_address = BUS(Z2_power_modified_counter_values[0], Z2_power_modified_counter_values[1], Z2_power_modified_counter_values[2], Z2_power_modified_counter_values[3], Z2_power_modified_counter_values[4], Z2_power_modified_counter_values[5], Z2_power_modified_counter_values[6], Z2_power_modified_counter_values[7], Z2_power_modified_counter_values[8]);
GB2_q_a[1]_PORT_A_address_reg = DFFE(GB2_q_a[1]_PORT_A_address, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_address = BUS(X2_wrptr_g[0], X2_wrptr_g[1], X2_wrptr_g[2], X2_wrptr_g[3], X2_wrptr_g[4], X2_wrptr_g[5], X2_wrptr_g[6], X2_wrptr_g[7], X2_wrptr_g[8]);
GB2_q_a[1]_PORT_B_address_reg = DFFE(GB2_q_a[1]_PORT_B_address, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_PORT_A_write_enable = GND;
GB2_q_a[1]_PORT_A_write_enable_reg = DFFE(GB2_q_a[1]_PORT_A_write_enable, GB2_q_a[1]_clock_0, , , GB2_q_a[1]_clock_enable_0);
GB2_q_a[1]_PORT_B_write_enable = X2_valid_wrreq;
GB2_q_a[1]_PORT_B_write_enable_reg = DFFE(GB2_q_a[1]_PORT_B_write_enable, GB2_q_a[1]_clock_1, , , GB2_q_a[1]_clock_enable_1);
GB2_q_a[1]_clock_0 = GLOBAL(KB1L2);
GB2_q_a[1]_clock_1 = GLOBAL(A1L11);
GB2_q_a[1]_clock_enable_0 = X2_valid_rdreq;
GB2_q_a[1]_clock_enable_1 = X2_valid_wrreq;
GB2_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB2_q_a[1]_PORT_A_data_out = MEMORY(GB2_q_a[1]_PORT_A_data_in_reg, GB2_q_a[1]_PORT_B_data_in_reg, GB2_q_a[1]_PORT_A_address_reg, GB2_q_a[1]_PORT_B_address_reg, GB2_q_a[1]_PORT_A_write_enable_reg, GB2_q_a[1]_PORT_B_write_enable_reg, , , GB2_q_a[1]_clock_0, GB2_q_a[1]_clock_1, GB2_q_a[1]_clock_enable_0, GB2_q_a[1]_clock_enable_1, , GB2_q_a[1]_clear_1);
GB2_q_a[1]_PORT_A_data_out_reg = DFFE(GB2_q_a[1]_PORT_A_data_out, GB2_q_a[1]_clock_0, GB2_q_a[1]_clear_1, , GB2_q_a[1]_clock_enable_0);
GB2_q_a[2] = GB2_q_a[1]_PORT_A_data_out_reg[1];


--G1L224 is Sdram_Control_4Port:u6|mDATAIN[1]~161 at LCCOMB_X12_Y13_N14
G1L224 = G1_WR_MASK[0] & (GB1_q_a[1]) # !G1_WR_MASK[0] & GB2_q_a[1];


--G1L225 is Sdram_Control_4Port:u6|mDATAIN[2]~162 at LCCOMB_X12_Y13_N10
G1L225 = G1_WR_MASK[0] & (GB1_q_a[2]) # !G1_WR_MASK[0] & GB2_q_a[2];


--G1L226 is Sdram_Control_4Port:u6|mDATAIN[3]~163 at LCCOMB_X12_Y13_N24
G1L226 = G1_WR_MASK[0] & (GB1_q_a[3]) # !G1_WR_MASK[0] & GB2_q_a[3];


--G1L227 is Sdram_Control_4Port:u6|mDATAIN[4]~164 at LCCOMB_X12_Y13_N6
G1L227 = G1_WR_MASK[0] & GB1_q_a[4] # !G1_WR_MASK[0] & (GB2_q_a[4]);


--G1L228 is Sdram_Control_4Port:u6|mDATAIN[5]~165 at LCCOMB_X12_Y13_N4
G1L228 = G1_WR_MASK[0] & GB1_q_a[5] # !G1_WR_MASK[0] & (GB2_q_a[5]);


--G1L229 is Sdram_Control_4Port:u6|mDATAIN[6]~166 at LCCOMB_X12_Y13_N22
G1L229 = G1_WR_MASK[0] & GB1_q_a[6] # !G1_WR_MASK[0] & (GB2_q_a[6]);


--G1L230 is Sdram_Control_4Port:u6|mDATAIN[7]~167 at LCCOMB_X12_Y13_N18
G1L230 = G1_WR_MASK[0] & GB1_q_a[7] # !G1_WR_MASK[0] & (GB2_q_a[7]);


--G1L231 is Sdram_Control_4Port:u6|mDATAIN[8]~168 at LCCOMB_X12_Y13_N20
G1L231 = G1_WR_MASK[0] & (GB1_q_a[8]) # !G1_WR_MASK[0] & GB2_q_a[8];


--G1L232 is Sdram_Control_4Port:u6|mDATAIN[9]~169 at LCCOMB_X12_Y12_N10
G1L232 = G1_WR_MASK[0] & (GB1_q_a[9]) # !G1_WR_MASK[0] & GB2_q_a[9];


--G1L233 is Sdram_Control_4Port:u6|mDATAIN[10]~170 at LCCOMB_X12_Y12_N4
G1L233 = G1_WR_MASK[0] & (GB1_q_a[10]) # !G1_WR_MASK[0] & GB2_q_a[10];


--G1L234 is Sdram_Control_4Port:u6|mDATAIN[11]~171 at LCCOMB_X12_Y13_N28
G1L234 = G1_WR_MASK[0] & (GB1_q_a[11]) # !G1_WR_MASK[0] & GB2_q_a[11];


--G1L235 is Sdram_Control_4Port:u6|mDATAIN[12]~172 at LCCOMB_X12_Y13_N12
G1L235 = G1_WR_MASK[0] & GB1_q_a[12] # !G1_WR_MASK[0] & (GB2_q_a[12]);


--G1L236 is Sdram_Control_4Port:u6|mDATAIN[13]~173 at LCCOMB_X12_Y13_N30
G1L236 = G1_WR_MASK[0] & (GB1_q_a[13]) # !G1_WR_MASK[0] & GB2_q_a[13];


--G1L237 is Sdram_Control_4Port:u6|mDATAIN[14]~174 at LCCOMB_X12_Y13_N8
G1L237 = G1_WR_MASK[0] & GB1_q_a[14] # !G1_WR_MASK[0] & (GB2_q_a[14]);


--G1L238 is Sdram_Control_4Port:u6|mDATAIN[15]~175 at LCCOMB_X12_Y13_N26
G1L238 = G1_WR_MASK[0] & (GB1_q_a[15]) # !G1_WR_MASK[0] & GB2_q_a[15];


--LB1L51Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~reg0 at LCFF_X45_Y17_N7
LB1L51Q = DFFEAS(LB1L49, GLOBAL(H1L93), GLOBAL(A1L291),  ,  , VCC,  ,  , !H1_mI2C_GO);


--LB1L57Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~reg0 at LCFF_X45_Y17_N11
LB1L57Q = DFFEAS(LB1L55, GLOBAL(H1L93), GLOBAL(A1L291),  ,  , VCC,  ,  , !H1_mI2C_GO);


--LB1L60Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~reg0 at LCFF_X45_Y17_N13
LB1L60Q = DFFEAS(LB1L58, GLOBAL(H1L93), GLOBAL(A1L291),  ,  , VCC,  ,  , !H1_mI2C_GO);


--LB1L54Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~reg0 at LCFF_X45_Y17_N9
LB1L54Q = DFFEAS(LB1L52, GLOBAL(H1L93), GLOBAL(A1L291),  ,  , VCC,  ,  , !H1_mI2C_GO);


--LB1L15 is I2C_CCD_Config:u7|I2C_Controller:u0|I2C_SCLK~253 at LCCOMB_X45_Y17_N28
LB1L15 = LB1L60Q # LB1L51Q # LB1L54Q # LB1L57Q;


--LB1L63Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~reg0 at LCFF_X45_Y17_N15
LB1L63Q = DFFEAS(LB1L61, GLOBAL(H1L93), GLOBAL(A1L291),  ,  , VCC,  ,  , !H1_mI2C_GO);


--LB1L16 is I2C_CCD_Config:u7|I2C_Controller:u0|I2C_SCLK~254 at LCCOMB_X45_Y17_N2
LB1L16 = LB1L63Q & (!LB1L57Q # !LB1L60Q) # !LB1L63Q & (LB1L15);


--LB1L66Q is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[5]~reg0 at LCFF_X45_Y17_N17
LB1L66Q = DFFEAS(LB1L64, GLOBAL(H1L93), GLOBAL(A1L291),  ,  , VCC,  ,  , !H1_mI2C_GO);


--H1_mI2C_CTRL_CLK is I2C_CCD_Config:u7|mI2C_CTRL_CLK at LCFF_X44_Y16_N23
H1_mI2C_CTRL_CLK = DFFEAS(H1L92, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  ,  ,  );


--LB1_SCLK is I2C_CCD_Config:u7|I2C_Controller:u0|SCLK at LCFF_X45_Y17_N23
LB1_SCLK = DFFEAS(LB1L23, GLOBAL(H1L93), GLOBAL(A1L291),  ,  ,  ,  ,  ,  );


--LB1L17 is I2C_CCD_Config:u7|I2C_Controller:u0|I2C_SCLK~255 at LCCOMB_X45_Y17_N20
LB1L17 = !H1_mI2C_CTRL_CLK & LB1L66Q & LB1L16 # !LB1_SCLK;


--LB1L25Q is I2C_CCD_Config:u7|I2C_Controller:u0|SDO~reg0 at LCFF_X43_Y17_N1
LB1L25Q = DFFEAS(LB1L84, GLOBAL(H1L93), GLOBAL(A1L291),  ,  ,  ,  ,  ,  );


--C1L3 is Reset_Delay:u2|Cont[0]~1196 at LCCOMB_X21_Y16_N10
C1L3 = C1_Cont[0] $ VCC;

--C1L4 is Reset_Delay:u2|Cont[0]~1197 at LCCOMB_X21_Y16_N10
C1L4 = CARRY(C1_Cont[0]);


--C1L6 is Reset_Delay:u2|Cont[1]~1198 at LCCOMB_X21_Y16_N12
C1L6 = C1_Cont[1] & !C1L4 # !C1_Cont[1] & (C1L4 # GND);

--C1L7 is Reset_Delay:u2|Cont[1]~1199 at LCCOMB_X21_Y16_N12
C1L7 = CARRY(!C1L4 # !C1_Cont[1]);


--C1L9 is Reset_Delay:u2|Cont[2]~1200 at LCCOMB_X21_Y16_N14
C1L9 = C1_Cont[2] & (C1L7 $ GND) # !C1_Cont[2] & !C1L7 & VCC;

--C1L10 is Reset_Delay:u2|Cont[2]~1201 at LCCOMB_X21_Y16_N14
C1L10 = CARRY(C1_Cont[2] & !C1L7);


--C1L12 is Reset_Delay:u2|Cont[3]~1202 at LCCOMB_X21_Y16_N16
C1L12 = C1_Cont[3] & !C1L10 # !C1_Cont[3] & (C1L10 # GND);

--C1L13 is Reset_Delay:u2|Cont[3]~1203 at LCCOMB_X21_Y16_N16
C1L13 = CARRY(!C1L10 # !C1_Cont[3]);


--C1L15 is Reset_Delay:u2|Cont[4]~1204 at LCCOMB_X21_Y16_N18
C1L15 = C1_Cont[4] & (C1L13 $ GND) # !C1_Cont[4] & !C1L13 & VCC;

--C1L16 is Reset_Delay:u2|Cont[4]~1205 at LCCOMB_X21_Y16_N18
C1L16 = CARRY(C1_Cont[4] & !C1L13);


--C1L18 is Reset_Delay:u2|Cont[5]~1206 at LCCOMB_X21_Y16_N20
C1L18 = C1_Cont[5] & !C1L16 # !C1_Cont[5] & (C1L16 # GND);

--C1L19 is Reset_Delay:u2|Cont[5]~1207 at LCCOMB_X21_Y16_N20
C1L19 = CARRY(!C1L16 # !C1_Cont[5]);


--C1L21 is Reset_Delay:u2|Cont[6]~1208 at LCCOMB_X21_Y16_N22
C1L21 = C1_Cont[6] & (C1L19 $ GND) # !C1_Cont[6] & !C1L19 & VCC;

--C1L22 is Reset_Delay:u2|Cont[6]~1209 at LCCOMB_X21_Y16_N22
C1L22 = CARRY(C1_Cont[6] & !C1L19);


--C1L24 is Reset_Delay:u2|Cont[7]~1210 at LCCOMB_X21_Y16_N24
C1L24 = C1_Cont[7] & !C1L22 # !C1_Cont[7] & (C1L22 # GND);

--C1L25 is Reset_Delay:u2|Cont[7]~1211 at LCCOMB_X21_Y16_N24
C1L25 = CARRY(!C1L22 # !C1_Cont[7]);


--C1L27 is Reset_Delay:u2|Cont[8]~1212 at LCCOMB_X21_Y16_N26
C1L27 = C1_Cont[8] & (C1L25 $ GND) # !C1_Cont[8] & !C1L25 & VCC;

--C1L28 is Reset_Delay:u2|Cont[8]~1213 at LCCOMB_X21_Y16_N26
C1L28 = CARRY(C1_Cont[8] & !C1L25);


--C1L30 is Reset_Delay:u2|Cont[9]~1214 at LCCOMB_X21_Y16_N28
C1L30 = C1_Cont[9] & !C1L28 # !C1_Cont[9] & (C1L28 # GND);

--C1L31 is Reset_Delay:u2|Cont[9]~1215 at LCCOMB_X21_Y16_N28
C1L31 = CARRY(!C1L28 # !C1_Cont[9]);


--C1L33 is Reset_Delay:u2|Cont[10]~1216 at LCCOMB_X21_Y16_N30
C1L33 = C1_Cont[10] & (C1L31 $ GND) # !C1_Cont[10] & !C1L31 & VCC;

--C1L34 is Reset_Delay:u2|Cont[10]~1217 at LCCOMB_X21_Y16_N30
C1L34 = CARRY(C1_Cont[10] & !C1L31);


--C1L36 is Reset_Delay:u2|Cont[11]~1218 at LCCOMB_X21_Y15_N0
C1L36 = C1_Cont[11] & !C1L34 # !C1_Cont[11] & (C1L34 # GND);

--C1L37 is Reset_Delay:u2|Cont[11]~1219 at LCCOMB_X21_Y15_N0
C1L37 = CARRY(!C1L34 # !C1_Cont[11]);


--C1L39 is Reset_Delay:u2|Cont[12]~1220 at LCCOMB_X21_Y15_N2
C1L39 = C1_Cont[12] & (C1L37 $ GND) # !C1_Cont[12] & !C1L37 & VCC;

--C1L40 is Reset_Delay:u2|Cont[12]~1221 at LCCOMB_X21_Y15_N2
C1L40 = CARRY(C1_Cont[12] & !C1L37);


--C1L42 is Reset_Delay:u2|Cont[13]~1222 at LCCOMB_X21_Y15_N4
C1L42 = C1_Cont[13] & !C1L40 # !C1_Cont[13] & (C1L40 # GND);

--C1L43 is Reset_Delay:u2|Cont[13]~1223 at LCCOMB_X21_Y15_N4
C1L43 = CARRY(!C1L40 # !C1_Cont[13]);


--C1L45 is Reset_Delay:u2|Cont[14]~1224 at LCCOMB_X21_Y15_N6
C1L45 = C1_Cont[14] & (C1L43 $ GND) # !C1_Cont[14] & !C1L43 & VCC;

--C1L46 is Reset_Delay:u2|Cont[14]~1225 at LCCOMB_X21_Y15_N6
C1L46 = CARRY(C1_Cont[14] & !C1L43);


--C1L48 is Reset_Delay:u2|Cont[15]~1226 at LCCOMB_X21_Y15_N8
C1L48 = C1_Cont[15] & !C1L46 # !C1_Cont[15] & (C1L46 # GND);

--C1L49 is Reset_Delay:u2|Cont[15]~1227 at LCCOMB_X21_Y15_N8
C1L49 = CARRY(!C1L46 # !C1_Cont[15]);


--C1L51 is Reset_Delay:u2|Cont[16]~1228 at LCCOMB_X21_Y15_N10
C1L51 = C1_Cont[16] & (C1L49 $ GND) # !C1_Cont[16] & !C1L49 & VCC;

--C1L52 is Reset_Delay:u2|Cont[16]~1229 at LCCOMB_X21_Y15_N10
C1L52 = CARRY(C1_Cont[16] & !C1L49);


--C1L54 is Reset_Delay:u2|Cont[17]~1230 at LCCOMB_X21_Y15_N12
C1L54 = C1_Cont[17] & !C1L52 # !C1_Cont[17] & (C1L52 # GND);

--C1L55 is Reset_Delay:u2|Cont[17]~1231 at LCCOMB_X21_Y15_N12
C1L55 = CARRY(!C1L52 # !C1_Cont[17]);


--C1L57 is Reset_Delay:u2|Cont[18]~1232 at LCCOMB_X21_Y15_N14
C1L57 = C1_Cont[18] & (C1L55 $ GND) # !C1_Cont[18] & !C1L55 & VCC;

--C1L58 is Reset_Delay:u2|Cont[18]~1233 at LCCOMB_X21_Y15_N14
C1L58 = CARRY(C1_Cont[18] & !C1L55);


--C1L60 is Reset_Delay:u2|Cont[19]~1234 at LCCOMB_X21_Y15_N16
C1L60 = C1_Cont[19] & !C1L58 # !C1_Cont[19] & (C1L58 # GND);

--C1L61 is Reset_Delay:u2|Cont[19]~1235 at LCCOMB_X21_Y15_N16
C1L61 = CARRY(!C1L58 # !C1_Cont[19]);


--C1L63 is Reset_Delay:u2|Cont[20]~1236 at LCCOMB_X21_Y15_N18
C1L63 = C1_Cont[20] & (C1L61 $ GND) # !C1_Cont[20] & !C1L61 & VCC;

--C1L64 is Reset_Delay:u2|Cont[20]~1237 at LCCOMB_X21_Y15_N18
C1L64 = CARRY(C1_Cont[20] & !C1L61);


--C1L66 is Reset_Delay:u2|Cont[21]~1238 at LCCOMB_X21_Y15_N20
C1L66 = C1_Cont[21] $ C1L64;


--C1L75 is Reset_Delay:u2|Equal~206 at LCCOMB_X21_Y15_N24
C1L75 = !C1_Cont[20] # !C1_Cont[21] # !C1L74;


--S1_LOAD_MODE is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE at LCFF_X32_Y19_N29
S1_LOAD_MODE = DFFEAS(S1L16, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1_command_done is Sdram_Control_4Port:u6|command:command1|command_done at LCFF_X20_Y10_N15
R1_command_done = DFFEAS(R1L77, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L51 is Sdram_Control_4Port:u6|command:command1|always0~155 at LCCOMB_X21_Y11_N16
R1L51 = !R1_command_done & !R1_do_load_mode & S1_LOAD_MODE;


--S1_INIT_REQ is Sdram_Control_4Port:u6|control_interface:control1|INIT_REQ at LCFF_X32_Y19_N21
S1_INIT_REQ = DFFEAS(S1L19, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_mADDR[8] is Sdram_Control_4Port:u6|mADDR[8] at LCFF_X20_Y12_N27
G1_mADDR[8] = DFFEAS(G1L194, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--S1_WRITEA is Sdram_Control_4Port:u6|control_interface:control1|WRITEA at LCFF_X19_Y11_N31
S1_WRITEA = DFFEAS(S1L2, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1_rp_done is Sdram_Control_4Port:u6|command:command1|rp_done at LCFF_X20_Y10_N21
R1_rp_done = DFFEAS(R1L96, GLOBAL(KB1L2),  ,  , R1L100,  ,  ,  ,  );


--R1L52 is Sdram_Control_4Port:u6|command:command1|always0~156 at LCCOMB_X20_Y10_N8
R1L52 = !R1_rp_done & !R1_command_done;


--S1_REF_REQ is Sdram_Control_4Port:u6|control_interface:control1|REF_REQ at LCFF_X20_Y11_N23
S1_REF_REQ = DFFEAS(S1L32, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L50 is Sdram_Control_4Port:u6|command:command1|always0~13 at LCCOMB_X20_Y11_N8
R1L50 = R1L52 & !R1_do_writea & S1_WRITEA & !S1_REF_REQ;


--R1L87 is Sdram_Control_4Port:u6|command:command1|do_writea~38 at LCCOMB_X19_Y10_N0
R1L87 = R1L50 & !S1_INIT_REQ;


--S1_READA is Sdram_Control_4Port:u6|control_interface:control1|READA at LCFF_X19_Y11_N27
S1_READA = DFFEAS(S1L8, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L53 is Sdram_Control_4Port:u6|command:command1|always0~157 at LCCOMB_X20_Y10_N24
R1L53 = !R1_rp_done & !R1_command_done & !R1_do_reada;


--R1L82 is Sdram_Control_4Port:u6|command:command1|do_reada~36 at LCCOMB_X20_Y11_N20
R1L82 = R1L53 & S1_READA & !S1_REF_REQ & !S1_INIT_REQ;


--G1_mWR_DONE is Sdram_Control_4Port:u6|mWR_DONE at LCFF_X18_Y11_N11
G1_mWR_DONE = DFFEAS(G1L279, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1L280 is Sdram_Control_4Port:u6|mWR~611 at LCCOMB_X22_Y13_N30
G1L280 = !G1_mWR_DONE & (BB1L17 # !BB3L17);


--G1L118 is Sdram_Control_4Port:u6|WR_MASK[0]~150 at LCCOMB_X21_Y13_N30
G1L118 = G1L272 # G1_mWR_DONE;


--G1L274 is Sdram_Control_4Port:u6|mRD~737 at LCCOMB_X21_Y13_N14
G1L274 = BB3L17 & !BB1L17 & !G1_mRD_DONE;


--R1_CM_ACK is Sdram_Control_4Port:u6|command:command1|CM_ACK at LCFF_X20_Y11_N29
R1_CM_ACK = DFFEAS(R1L9, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--S1L65 is Sdram_Control_4Port:u6|control_interface:control1|always1~0 at LCCOMB_X17_Y11_N16
S1L65 = !S1_CMD_ACK & R1_CM_ACK;


--G1_mADDR[9] is Sdram_Control_4Port:u6|mADDR[9] at LCFF_X20_Y14_N19
G1_mADDR[9] = DFFEAS(G1L196, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[10] is Sdram_Control_4Port:u6|mADDR[10] at LCFF_X20_Y14_N21
G1_mADDR[10] = DFFEAS(G1L198, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[11] is Sdram_Control_4Port:u6|mADDR[11] at LCFF_X20_Y14_N3
G1_mADDR[11] = DFFEAS(G1L200, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[12] is Sdram_Control_4Port:u6|mADDR[12] at LCFF_X19_Y14_N31
G1_mADDR[12] = DFFEAS(G1L202, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[13] is Sdram_Control_4Port:u6|mADDR[13] at LCFF_X20_Y14_N29
G1_mADDR[13] = DFFEAS(G1L204, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[14] is Sdram_Control_4Port:u6|mADDR[14] at LCFF_X20_Y12_N29
G1_mADDR[14] = DFFEAS(G1L206, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[15] is Sdram_Control_4Port:u6|mADDR[15] at LCFF_X19_Y14_N27
G1_mADDR[15] = DFFEAS(G1L208, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[16] is Sdram_Control_4Port:u6|mADDR[16] at LCFF_X20_Y12_N23
G1_mADDR[16] = DFFEAS(G1L210, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[17] is Sdram_Control_4Port:u6|mADDR[17] at LCFF_X19_Y14_N7
G1_mADDR[17] = DFFEAS(G1L212, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[18] is Sdram_Control_4Port:u6|mADDR[18] at LCFF_X20_Y15_N31
G1_mADDR[18] = DFFEAS(G1L214, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--S1_PRECHARGE is Sdram_Control_4Port:u6|control_interface:control1|PRECHARGE at LCFF_X32_Y19_N1
S1_PRECHARGE = DFFEAS(S1L27, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L54 is Sdram_Control_4Port:u6|command:command1|always0~158 at LCCOMB_X21_Y11_N6
R1L54 = !R1_command_done & S1_PRECHARGE & !R1_do_precharge;


--R1_rw_shift[0] is Sdram_Control_4Port:u6|command:command1|rw_shift[0] at LCFF_X19_Y12_N7
R1_rw_shift[0] = DFFEAS(R1L115, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L85 is Sdram_Control_4Port:u6|command:command1|do_rw~49 at LCCOMB_X19_Y12_N18
R1L85 = R1_do_reada & (R1_do_rw) # !R1_do_reada & (R1_do_writea & (R1_do_rw) # !R1_do_writea & R1_rw_shift[0]);


--G1_mADDR[19] is Sdram_Control_4Port:u6|mADDR[19] at LCFF_X20_Y15_N19
G1_mADDR[19] = DFFEAS(G1L216, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--R1L55 is Sdram_Control_4Port:u6|command:command1|always0~159 at LCCOMB_X20_Y11_N12
R1L55 = !R1_do_writea & !R1_do_refresh;


--S1_REFRESH is Sdram_Control_4Port:u6|control_interface:control1|REFRESH at LCFF_X32_Y19_N23
S1_REFRESH = DFFEAS(S1L30, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L56 is Sdram_Control_4Port:u6|command:command1|always0~160 at LCCOMB_X20_Y11_N2
R1L56 = R1L55 & R1L53 & (S1_REF_REQ # S1_REFRESH);


--R1L111 is Sdram_Control_4Port:u6|command:command1|rw_flag~25 at LCCOMB_X20_Y11_N14
R1L111 = R1_do_reada # R1L110 & R1_rw_flag & R1L55;


--R1L93 is Sdram_Control_4Port:u6|command:command1|oe4~33 at LCCOMB_X19_Y10_N12
R1L93 = !R1_do_reada & !R1_do_precharge & !R1_do_initial & !R1_do_refresh;


--G1_PM_STOP is Sdram_Control_4Port:u6|PM_STOP at LCFF_X19_Y11_N17
G1_PM_STOP = DFFEAS(G1L22, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L94 is Sdram_Control_4Port:u6|command:command1|oe4~34 at LCCOMB_X19_Y10_N2
R1L94 = R1_do_writea # R1L93 & !G1_PM_STOP & R1_oe4;


--G1_mADDR[22] is Sdram_Control_4Port:u6|mADDR[22] at LCFF_X20_Y15_N29
G1_mADDR[22] = DFFEAS(G1L218, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[20] is Sdram_Control_4Port:u6|mADDR[20] at LCFF_X20_Y12_N3
G1_mADDR[20] = DFFEAS(G1L220, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--G1_mADDR[21] is Sdram_Control_4Port:u6|mADDR[21] at LCFF_X20_Y15_N23
G1_mADDR[21] = DFFEAS(G1L222, GLOBAL(KB1L2),  ,  , G1L272,  ,  ,  ,  );


--AB11_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor7 at LCCOMB_X27_Y18_N28
AB11_xor7 = X3_wrptr_g[8] $ X3_wrptr_g[7];


--AB12_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor7 at LCCOMB_X27_Y19_N6
AB12_xor7 = JB3_dffe9a[7] $ JB3_dffe9a[8];


--AB11_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor6 at LCCOMB_X27_Y18_N26
AB11_xor6 = X3_wrptr_g[6] $ X3_wrptr_g[8] $ X3_wrptr_g[7];


--AB12_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor6 at LCCOMB_X27_Y19_N12
AB12_xor6 = JB3_dffe9a[6] $ JB3_dffe9a[7] $ JB3_dffe9a[8];


--AB11_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor5 at LCCOMB_X28_Y18_N10
AB11_xor5 = X3_wrptr_g[5] $ X3_wrptr_g[8] $ X3_wrptr_g[7] $ X3_wrptr_g[6];


--AB12_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor5 at LCCOMB_X27_Y19_N14
AB12_xor5 = JB3_dffe9a[5] $ JB3_dffe9a[6] $ JB3_dffe9a[7] $ JB3_dffe9a[8];


--AB11_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor4 at LCCOMB_X27_Y18_N4
AB11_xor4 = AB11_xor5 $ X3_wrptr_g[4];


--AB12_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor4 at LCCOMB_X28_Y18_N16
AB12_xor4 = AB12_xor5 $ JB3_dffe9a[4];


--AB11_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor3 at LCCOMB_X28_Y18_N28
AB11_xor3 = AB11_xor5 $ X3_wrptr_g[4] $ X3_wrptr_g[3];


--AB12_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor3 at LCCOMB_X28_Y18_N26
AB12_xor3 = AB12_xor5 $ JB3_dffe9a[3] $ JB3_dffe9a[4];


--AB11_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor2 at LCCOMB_X28_Y18_N14
AB11_xor2 = AB11_xor5 $ X3_wrptr_g[2] $ X3_wrptr_g[4] $ X3_wrptr_g[3];


--AB12_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor2 at LCCOMB_X28_Y18_N8
AB12_xor2 = JB3_dffe9a[2] $ AB12_xor5 $ JB3_dffe9a[3] $ JB3_dffe9a[4];


--AB11_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor1 at LCCOMB_X27_Y18_N0
AB11_xor1 = AB11_xor2 $ X3_wrptr_g[1];


--AB12_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor1 at LCCOMB_X27_Y18_N2
AB12_xor1 = AB12_xor2 $ JB3_dffe9a[1];


--AB11_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor0 at LCCOMB_X27_Y18_N24
AB11_xor0 = X3_wrptr_g[1] $ AB11_xor2 $ X3_wrptr_g[0];


--AB12_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor0 at LCCOMB_X27_Y18_N30
AB12_xor0 = AB12_xor2 $ JB3_dffe9a[0] $ JB3_dffe9a[1];


--HB1_dffe7a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[8] at LCFF_X16_Y13_N3
HB1_dffe7a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X1_delayed_wrptr_g[8],  ,  , VCC);


--X1_rdptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8] at LCFF_X15_Y13_N27
X1_rdptr_g[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X1_valid_rdreq, Z1_power_modified_counter_values[8],  ,  , VCC);


--HB1_dffe7a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[7] at LCFF_X16_Y13_N29
HB1_dffe7a[7] = DFFEAS(HB1L15, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB2_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor7 at LCCOMB_X16_Y13_N26
AB2_xor7 = HB1_dffe7a[8] $ HB1_dffe7a[7];


--X1_rdptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[7] at LCFF_X16_Y13_N1
X1_rdptr_g[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X1_valid_rdreq, Z1_power_modified_counter_values[7],  ,  , VCC);


--AB1_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor7 at LCCOMB_X16_Y13_N12
AB1_xor7 = X1_rdptr_g[8] $ X1_rdptr_g[7];


--HB1_dffe7a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[6] at LCFF_X16_Y13_N31
HB1_dffe7a[6] = DFFEAS(HB1L13, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB2_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor6 at LCCOMB_X16_Y13_N24
AB2_xor6 = HB1_dffe7a[6] $ HB1_dffe7a[8] $ HB1_dffe7a[7];


--X1_rdptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[6] at LCFF_X16_Y13_N21
X1_rdptr_g[6] = DFFEAS(X1L35, GLOBAL(KB1L2), GLOBAL(C1L78),  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor6 at LCCOMB_X16_Y13_N14
AB1_xor6 = X1_rdptr_g[8] $ X1_rdptr_g[6] $ X1_rdptr_g[7];


--HB1_dffe7a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[5] at LCFF_X16_Y13_N5
HB1_dffe7a[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X1_delayed_wrptr_g[5],  ,  , VCC);


--AB2_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor5 at LCCOMB_X16_Y13_N2
AB2_xor5 = HB1_dffe7a[5] $ HB1_dffe7a[6] $ HB1_dffe7a[8] $ HB1_dffe7a[7];


--X1_rdptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[5] at LCFF_X15_Y13_N21
X1_rdptr_g[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X1_valid_rdreq, Z1_power_modified_counter_values[5],  ,  , VCC);


--AB1_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor5 at LCCOMB_X16_Y13_N22
AB1_xor5 = X1_rdptr_g[5] $ X1_rdptr_g[8] $ X1_rdptr_g[6] $ X1_rdptr_g[7];


--HB1_dffe7a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4] at LCFF_X25_Y13_N5
HB1_dffe7a[4] = DFFEAS(HB1L10, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB2_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor4 at LCCOMB_X25_Y13_N20
AB2_xor4 = AB2_xor5 $ HB1_dffe7a[4];


--X1_rdptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4] at LCFF_X16_Y12_N9
X1_rdptr_g[4] = DFFEAS(X1L32, GLOBAL(KB1L2), GLOBAL(C1L78),  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor4 at LCCOMB_X17_Y13_N26
AB1_xor4 = X1_rdptr_g[4] $ AB1_xor5;


--HB1_dffe7a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[3] at LCFF_X16_Y13_N9
HB1_dffe7a[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X1_delayed_wrptr_g[3],  ,  , VCC);


--AB2_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor3 at LCCOMB_X17_Y13_N30
AB2_xor3 = HB1_dffe7a[3] $ AB2_xor5 $ HB1_dffe7a[4];


--X1_rdptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[3] at LCFF_X16_Y12_N27
X1_rdptr_g[3] = DFFEAS(X1L30, GLOBAL(KB1L2), GLOBAL(C1L78),  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor3 at LCCOMB_X17_Y13_N22
AB1_xor3 = X1_rdptr_g[4] $ AB1_xor5 $ X1_rdptr_g[3];


--HB1_dffe7a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[2] at LCFF_X16_Y13_N11
HB1_dffe7a[2] = DFFEAS(HB1L7, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB2_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor2 at LCCOMB_X16_Y13_N8
AB2_xor2 = HB1_dffe7a[2] $ HB1_dffe7a[4] $ HB1_dffe7a[3] $ AB2_xor5;


--X1_rdptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2] at LCFF_X16_Y13_N17
X1_rdptr_g[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X1_valid_rdreq, Z1_power_modified_counter_values[2],  ,  , VCC);


--AB1_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor2 at LCCOMB_X16_Y12_N10
AB1_xor2 = AB1_xor5 $ X1_rdptr_g[4] $ X1_rdptr_g[2] $ X1_rdptr_g[3];


--HB1_dffe7a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1] at LCFF_X15_Y14_N17
HB1_dffe7a[1] = DFFEAS(HB1L5, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB2_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor1 at LCCOMB_X17_Y13_N20
AB2_xor1 = AB2_xor2 $ HB1_dffe7a[1];


--X1_rdptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[1] at LCFF_X15_Y13_N31
X1_rdptr_g[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X1_valid_rdreq, Z1_power_modified_counter_values[1],  ,  , VCC);


--AB1_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor1 at LCCOMB_X17_Y13_N28
AB1_xor1 = X1_rdptr_g[1] $ AB1_xor2;


--HB1_dffe7a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0] at LCFF_X16_Y13_N19
HB1_dffe7a[0] = DFFEAS(HB1L3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB2_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor0 at LCCOMB_X17_Y13_N24
AB2_xor0 = AB2_xor2 $ HB1_dffe7a[1] $ HB1_dffe7a[0];


--X1_rdptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0] at LCFF_X16_Y13_N7
X1_rdptr_g[0] = DFFEAS(X1L26, GLOBAL(KB1L2), GLOBAL(C1L78),  , X1_valid_rdreq,  ,  ,  ,  );


--AB1_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor0 at LCCOMB_X17_Y13_N0
AB1_xor0 = X1_rdptr_g[0] $ X1_rdptr_g[1] $ AB1_xor2;


--G1L268 is Sdram_Control_4Port:u6|mRD_DONE~77 at LCCOMB_X19_Y11_N0
G1L268 = G1_Read & (G1_mRD_DONE # !G1L29 & !G1L30);


--HB2_dffe7a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[8] at LCFF_X24_Y14_N23
HB2_dffe7a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X2_delayed_wrptr_g[8],  ,  , VCC);


--X2_rdptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8] at LCFF_X24_Y13_N7
X2_rdptr_g[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X2_valid_rdreq, Z2_power_modified_counter_values[8],  ,  , VCC);


--HB2_dffe7a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[7] at LCFF_X24_Y14_N11
HB2_dffe7a[7] = DFFEAS(HB2L16, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB6_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor7 at LCCOMB_X24_Y14_N4
AB6_xor7 = HB2_dffe7a[8] $ HB2_dffe7a[7];


--X2_rdptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[7] at LCFF_X24_Y13_N3
X2_rdptr_g[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X2_valid_rdreq, Z2_power_modified_counter_values[7],  ,  , VCC);


--AB5_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor7 at LCCOMB_X25_Y13_N22
AB5_xor7 = X2_rdptr_g[7] $ X2_rdptr_g[8];


--HB2_dffe7a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[6] at LCFF_X24_Y14_N9
HB2_dffe7a[6] = DFFEAS(HB2L14, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB6_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor6 at LCCOMB_X24_Y14_N24
AB6_xor6 = HB2_dffe7a[8] $ HB2_dffe7a[6] $ HB2_dffe7a[7];


--X2_rdptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[6] at LCFF_X24_Y13_N19
X2_rdptr_g[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X2_valid_rdreq, Z2_power_modified_counter_values[6],  ,  , VCC);


--AB5_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor6 at LCCOMB_X22_Y14_N16
AB5_xor6 = X2_rdptr_g[8] $ X2_rdptr_g[7] $ X2_rdptr_g[6];


--HB2_dffe7a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[5] at LCFF_X24_Y14_N21
HB2_dffe7a[5] = DFFEAS(HB2L12, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB6_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor5 at LCCOMB_X24_Y14_N22
AB6_xor5 = HB2_dffe7a[5] $ HB2_dffe7a[6] $ HB2_dffe7a[8] $ HB2_dffe7a[7];


--X2_rdptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[5] at LCFF_X24_Y13_N13
X2_rdptr_g[5] = DFFEAS(X2L38, GLOBAL(KB1L2), GLOBAL(C1L78),  , X2_valid_rdreq,  ,  ,  ,  );


--AB5_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor5 at LCCOMB_X23_Y13_N0
AB5_xor5 = X2_rdptr_g[8] $ X2_rdptr_g[6] $ X2_rdptr_g[5] $ X2_rdptr_g[7];


--HB2_dffe7a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4] at LCFF_X23_Y14_N9
HB2_dffe7a[4] = DFFEAS(HB2L10, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB6_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor4 at LCCOMB_X23_Y13_N8
AB6_xor4 = AB6_xor5 $ HB2_dffe7a[4];


--X2_rdptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4] at LCFF_X24_Y13_N15
X2_rdptr_g[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X2_valid_rdreq, Z2_power_modified_counter_values[4],  ,  , VCC);


--AB5_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor4 at LCCOMB_X23_Y13_N28
AB5_xor4 = AB5_xor5 $ X2_rdptr_g[4];


--HB2_dffe7a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[3] at LCFF_X23_Y14_N21
HB2_dffe7a[3] = DFFEAS(HB2L8, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB6_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor3 at LCCOMB_X23_Y14_N24
AB6_xor3 = AB6_xor5 $ HB2_dffe7a[3] $ HB2_dffe7a[4];


--X2_rdptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[3] at LCFF_X24_Y13_N25
X2_rdptr_g[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X2_valid_rdreq, Z2_power_modified_counter_values[3],  ,  , VCC);


--AB5_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor3 at LCCOMB_X24_Y13_N30
AB5_xor3 = AB5_xor5 $ X2_rdptr_g[3] $ X2_rdptr_g[4];


--HB2_dffe7a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[2] at LCFF_X23_Y14_N17
HB2_dffe7a[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  , X2_delayed_wrptr_g[2],  ,  , VCC);


--AB6_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor2 at LCCOMB_X23_Y14_N16
AB6_xor2 = HB2_dffe7a[3] $ AB6_xor5 $ HB2_dffe7a[2] $ HB2_dffe7a[4];


--X2_rdptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2] at LCFF_X24_Y13_N11
X2_rdptr_g[2] = DFFEAS(X2L34, GLOBAL(KB1L2), GLOBAL(C1L78),  , X2_valid_rdreq,  ,  ,  ,  );


--AB5_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor2 at LCCOMB_X24_Y13_N22
AB5_xor2 = AB5_xor5 $ X2_rdptr_g[3] $ X2_rdptr_g[4] $ X2_rdptr_g[2];


--HB2_dffe7a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1] at LCFF_X25_Y12_N1
HB2_dffe7a[1] = DFFEAS(HB2L5, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB6_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor1 at LCCOMB_X23_Y13_N30
AB6_xor1 = HB2_dffe7a[1] $ AB6_xor2;


--X2_rdptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[1] at LCFF_X24_Y13_N9
X2_rdptr_g[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X2_valid_rdreq, Z2_power_modified_counter_values[1],  ,  , VCC);


--AB5_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor1 at LCCOMB_X23_Y13_N4
AB5_xor1 = X2_rdptr_g[1] $ AB5_xor2;


--HB2_dffe7a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0] at LCFF_X24_Y12_N1
HB2_dffe7a[0] = DFFEAS(HB2L3, GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--AB6_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rs_dgwp_gray2bin|xor0 at LCCOMB_X23_Y13_N6
AB6_xor0 = HB2_dffe7a[1] $ HB2_dffe7a[0] $ AB6_xor2;


--X2_rdptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0] at LCFF_X24_Y13_N27
X2_rdptr_g[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(KB1L2), GLOBAL(C1L78),  , X2_valid_rdreq, Z2_power_modified_counter_values[0],  ,  , VCC);


--AB5_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:rdptr_g_gray2bin|xor0 at LCCOMB_X23_Y13_N2
AB5_xor0 = X2_rdptr_g[0] $ X2_rdptr_g[1] $ AB5_xor2;


--AB15_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor7 at LCCOMB_X23_Y15_N8
AB15_xor7 = X4_wrptr_g[7] $ X4_wrptr_g[8];


--AB16_xor7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor7 at LCCOMB_X23_Y16_N26
AB16_xor7 = JB4_dffe9a[7] $ JB4_dffe9a[8];


--AB15_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor6 at LCCOMB_X23_Y15_N28
AB15_xor6 = X4_wrptr_g[7] $ X4_wrptr_g[6] $ X4_wrptr_g[8];


--AB16_xor6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor6 at LCCOMB_X22_Y15_N22
AB16_xor6 = JB4_dffe9a[8] $ JB4_dffe9a[7] $ JB4_dffe9a[6];


--AB15_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor5 at LCCOMB_X23_Y15_N4
AB15_xor5 = X4_wrptr_g[7] $ X4_wrptr_g[5] $ X4_wrptr_g[8] $ X4_wrptr_g[6];


--AB16_xor5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor5 at LCCOMB_X23_Y16_N8
AB16_xor5 = JB4_dffe9a[5] $ JB4_dffe9a[6] $ JB4_dffe9a[7] $ JB4_dffe9a[8];


--AB15_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor4 at LCCOMB_X23_Y15_N18
AB15_xor4 = AB15_xor5 $ X4_wrptr_g[4];


--AB16_xor4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor4 at LCCOMB_X23_Y16_N20
AB16_xor4 = AB16_xor5 $ JB4_dffe9a[4];


--AB15_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor3 at LCCOMB_X22_Y15_N18
AB15_xor3 = X4_wrptr_g[3] $ AB15_xor5 $ X4_wrptr_g[4];


--AB16_xor3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor3 at LCCOMB_X22_Y15_N28
AB16_xor3 = JB4_dffe9a[3] $ AB16_xor5 $ JB4_dffe9a[4];


--AB15_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor2 at LCCOMB_X23_Y15_N30
AB15_xor2 = X4_wrptr_g[2] $ AB15_xor5 $ X4_wrptr_g[4] $ X4_wrptr_g[3];


--AB16_xor2 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor2 at LCCOMB_X22_Y15_N24
AB16_xor2 = JB4_dffe9a[3] $ JB4_dffe9a[2] $ AB16_xor5 $ JB4_dffe9a[4];


--AB15_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor1 at LCCOMB_X23_Y15_N26
AB15_xor1 = X4_wrptr_g[1] $ AB15_xor2;


--AB16_xor1 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor1 at LCCOMB_X22_Y15_N30
AB16_xor1 = JB4_dffe9a[1] $ AB16_xor2;


--AB15_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:wrptr_g_gray2bin|xor0 at LCCOMB_X22_Y15_N20
AB15_xor0 = X4_wrptr_g[0] $ AB15_xor2 $ X4_wrptr_g[1];


--AB16_xor0 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_gray2bin_ccb:ws_dgrp_gray2bin|xor0 at LCCOMB_X22_Y15_N26
AB16_xor0 = JB4_dffe9a[1] $ AB16_xor2 $ JB4_dffe9a[0];


--G1L120 is Sdram_Control_4Port:u6|WR_MASK~151 at LCCOMB_X22_Y13_N12
G1L120 = !BB1L17 & !BB3L17 & !G1_mWR_DONE;


--G1L121 is Sdram_Control_4Port:u6|WR_MASK~152 at LCCOMB_X20_Y13_N4
G1L121 = BB1L17 & !G1_mWR_DONE;


--G1_IN_REQ is Sdram_Control_4Port:u6|IN_REQ at LCFF_X18_Y11_N23
G1_IN_REQ = DFFEAS(G1L34, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--X1L1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|_~7 at LCCOMB_X16_Y13_N0
X1L1 = X1_rdptr_g[7] $ HB1_dffe7a[7];


--X1L19 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~55 at LCCOMB_X16_Y13_N16
X1L19 = X1_rdptr_g[0] & HB1_dffe7a[0] & (X1_rdptr_g[2] $ !HB1_dffe7a[2]) # !X1_rdptr_g[0] & !HB1_dffe7a[0] & (X1_rdptr_g[2] $ !HB1_dffe7a[2]);


--X1L20 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~56 at LCCOMB_X15_Y13_N30
X1L20 = HB1_dffe7a[1] & X1_rdptr_g[1] & (X1_rdptr_g[6] $ !HB1_dffe7a[6]) # !HB1_dffe7a[1] & !X1_rdptr_g[1] & (X1_rdptr_g[6] $ !HB1_dffe7a[6]);


--X1L21 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~57 at LCCOMB_X15_Y13_N26
X1L21 = X1_rdptr_g[3] & HB1_dffe7a[3] & (HB1_dffe7a[8] $ !X1_rdptr_g[8]) # !X1_rdptr_g[3] & !HB1_dffe7a[3] & (HB1_dffe7a[8] $ !X1_rdptr_g[8]);


--X1L22 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~58 at LCCOMB_X15_Y13_N20
X1L22 = X1_rdptr_g[4] & HB1_dffe7a[4] & (X1_rdptr_g[5] $ !HB1_dffe7a[5]) # !X1_rdptr_g[4] & !HB1_dffe7a[4] & (X1_rdptr_g[5] $ !HB1_dffe7a[5]);


--X1L23 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~59 at LCCOMB_X15_Y13_N22
X1L23 = X1L19 & X1L21 & X1L22 & X1L20;


--X1_valid_rdreq is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq at LCCOMB_X15_Y13_N24
X1_valid_rdreq = G1_IN_REQ & G1_WR_MASK[0] & (X1L1 # !X1L23);


--X2_p0addr is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|p0addr at LCFF_X24_Y13_N21
X2_p0addr = DFFEAS(X2L20, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--X1_rdcnt_addr_ena is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdcnt_addr_ena at LCCOMB_X15_Y13_N28
X1_rdcnt_addr_ena = X1_valid_rdreq # !X2_p0addr;


--J1_mCCD_DVAL is Mirror_Col:u8|mCCD_DVAL at LCFF_X25_Y13_N17
J1_mCCD_DVAL = DFFEAS(J1L43, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--JB1_dffe9a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[7] at LCFF_X14_Y12_N1
JB1_dffe9a[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X1_rdptr_g[7],  ,  , VCC);


--EB1_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[7] at LCFF_X14_Y12_N27
EB1_power_modified_counter_values[7] = DFFEAS(EB1_countera7, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB1_dffe9a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[2] at LCFF_X15_Y11_N1
JB1_dffe9a[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X1_rdptr_g[2],  ,  , VCC);


--EB1_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[2] at LCFF_X14_Y12_N17
EB1_power_modified_counter_values[2] = DFFEAS(EB1_countera2, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB1_dffe9a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[0] at LCFF_X14_Y12_N7
JB1_dffe9a[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X1_rdptr_g[0],  ,  , VCC);


--EB1_counter_ffa[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|counter_ffa[0] at LCFF_X14_Y12_N13
EB1_counter_ffa[0] = DFFEAS(EB1_countera0, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X1L40 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~54 at LCCOMB_X14_Y12_N6
X1L40 = EB1_power_modified_counter_values[2] & JB1_dffe9a[2] & (JB1_dffe9a[0] $ EB1_counter_ffa[0]) # !EB1_power_modified_counter_values[2] & !JB1_dffe9a[2] & (JB1_dffe9a[0] $ EB1_counter_ffa[0]);


--JB1_dffe9a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[6] at LCFF_X14_Y12_N31
JB1_dffe9a[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X1_rdptr_g[6],  ,  , VCC);


--JB1_dffe9a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[1] at LCFF_X14_Y12_N3
JB1_dffe9a[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X1_rdptr_g[1],  ,  , VCC);


--EB1_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[1] at LCFF_X14_Y12_N15
EB1_power_modified_counter_values[1] = DFFEAS(EB1_countera1, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[6] at LCFF_X14_Y12_N25
EB1_power_modified_counter_values[6] = DFFEAS(EB1_countera6, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X1L41 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~55 at LCCOMB_X14_Y12_N2
X1L41 = EB1_power_modified_counter_values[6] & JB1_dffe9a[6] & (EB1_power_modified_counter_values[1] $ !JB1_dffe9a[1]) # !EB1_power_modified_counter_values[6] & !JB1_dffe9a[6] & (EB1_power_modified_counter_values[1] $ !JB1_dffe9a[1]);


--JB1_dffe9a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[3] at LCFF_X17_Y12_N17
JB1_dffe9a[3] = DFFEAS(JB1L6, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB1_dffe9a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[8] at LCFF_X14_Y12_N9
JB1_dffe9a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X1_rdptr_g[8],  ,  , VCC);


--EB1_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[8] at LCFF_X14_Y12_N29
EB1_power_modified_counter_values[8] = DFFEAS(EB1_countera8, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[3] at LCFF_X14_Y12_N19
EB1_power_modified_counter_values[3] = DFFEAS(EB1_countera3, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X1L42 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~56 at LCCOMB_X14_Y12_N8
X1L42 = JB1_dffe9a[3] & EB1_power_modified_counter_values[3] & (EB1_power_modified_counter_values[8] $ !JB1_dffe9a[8]) # !JB1_dffe9a[3] & !EB1_power_modified_counter_values[3] & (EB1_power_modified_counter_values[8] $ !JB1_dffe9a[8]);


--JB1_dffe9a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5] at LCFF_X15_Y12_N27
JB1_dffe9a[5] = DFFEAS(JB1L9, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB1_dffe9a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[4] at LCFF_X15_Y12_N25
JB1_dffe9a[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X1_rdptr_g[4],  ,  , VCC);


--EB1_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[4] at LCFF_X14_Y12_N21
EB1_power_modified_counter_values[4] = DFFEAS(EB1_countera4, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB1_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[5] at LCFF_X14_Y12_N23
EB1_power_modified_counter_values[5] = DFFEAS(EB1_countera5, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X1L43 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~57 at LCCOMB_X15_Y12_N24
X1L43 = EB1_power_modified_counter_values[4] & JB1_dffe9a[4] & (EB1_power_modified_counter_values[5] $ !JB1_dffe9a[5]) # !EB1_power_modified_counter_values[4] & !JB1_dffe9a[4] & (EB1_power_modified_counter_values[5] $ !JB1_dffe9a[5]);


--X1L44 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~58 at LCCOMB_X14_Y12_N4
X1L44 = X1L40 & X1L43 & X1L42 & X1L41;


--X1_valid_wrreq is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_wrreq at LCCOMB_X14_Y12_N0
X1_valid_wrreq = J1_mCCD_DVAL & (JB1_dffe9a[7] $ EB1_power_modified_counter_values[7] # !X1L44);


--Z1_power_modified_counter_values[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[0] at LCFF_X15_Y13_N3
Z1_power_modified_counter_values[0] = DFFEAS(Z1_countera0, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[1] at LCFF_X15_Y13_N5
Z1_power_modified_counter_values[1] = DFFEAS(Z1_countera1, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[2] at LCFF_X15_Y13_N7
Z1_power_modified_counter_values[2] = DFFEAS(Z1_countera2, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[3] at LCFF_X15_Y13_N9
Z1_power_modified_counter_values[3] = DFFEAS(Z1_countera3, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[4] at LCFF_X15_Y13_N11
Z1_power_modified_counter_values[4] = DFFEAS(Z1_countera4, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[5] at LCFF_X15_Y13_N13
Z1_power_modified_counter_values[5] = DFFEAS(Z1_countera5, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[6] at LCFF_X15_Y13_N15
Z1_power_modified_counter_values[6] = DFFEAS(Z1_countera6, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[7] at LCFF_X15_Y13_N17
Z1_power_modified_counter_values[7] = DFFEAS(Z1_countera7, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z1_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8] at LCFF_X15_Y13_N19
Z1_power_modified_counter_values[8] = DFFEAS(Z1_countera8, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--X1_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0] at LCFF_X14_Y13_N7
X1_wrptr_g[0] = DFFEAS(X1L47, GLOBAL(A1L11), GLOBAL(C1L78),  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[1] at LCFF_X14_Y13_N17
X1_wrptr_g[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  , X1_valid_wrreq, EB1_power_modified_counter_values[1],  ,  , VCC);


--X1_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2] at LCFF_X14_Y13_N25
X1_wrptr_g[2] = DFFEAS(X1L50, GLOBAL(A1L11), GLOBAL(C1L78),  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[3] at LCFF_X14_Y13_N29
X1_wrptr_g[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  , X1_valid_wrreq, EB1_power_modified_counter_values[3],  ,  , VCC);


--X1_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[4] at LCFF_X15_Y12_N11
X1_wrptr_g[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  , X1_valid_wrreq, EB1_power_modified_counter_values[4],  ,  , VCC);


--X1_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5] at LCFF_X15_Y12_N9
X1_wrptr_g[5] = DFFEAS(X1L54, GLOBAL(A1L11), GLOBAL(C1L78),  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6] at LCFF_X14_Y13_N9
X1_wrptr_g[6] = DFFEAS(X1L56, GLOBAL(A1L11), GLOBAL(C1L78),  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[7] at LCFF_X15_Y12_N1
X1_wrptr_g[7] = DFFEAS(X1L58, GLOBAL(A1L11), GLOBAL(C1L78),  , X1_valid_wrreq,  ,  ,  ,  );


--X1_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8] at LCFF_X15_Y12_N21
X1_wrptr_g[8] = DFFEAS(X1L60, GLOBAL(A1L11), GLOBAL(C1L78),  , X1_valid_wrreq,  ,  ,  ,  );


--X2L1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|_~7 at LCCOMB_X24_Y13_N2
X2L1 = X2_rdptr_g[7] $ HB2_dffe7a[7];


--X2L25 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~55 at LCCOMB_X24_Y13_N26
X2L25 = HB2_dffe7a[2] & X2_rdptr_g[2] & (HB2_dffe7a[0] $ !X2_rdptr_g[0]) # !HB2_dffe7a[2] & !X2_rdptr_g[2] & (HB2_dffe7a[0] $ !X2_rdptr_g[0]);


--X2L26 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~56 at LCCOMB_X24_Y13_N8
X2L26 = HB2_dffe7a[1] & X2_rdptr_g[1] & (HB2_dffe7a[6] $ !X2_rdptr_g[6]) # !HB2_dffe7a[1] & !X2_rdptr_g[1] & (HB2_dffe7a[6] $ !X2_rdptr_g[6]);


--X2L27 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~57 at LCCOMB_X24_Y13_N24
X2L27 = X2_rdptr_g[8] & HB2_dffe7a[8] & (HB2_dffe7a[3] $ !X2_rdptr_g[3]) # !X2_rdptr_g[8] & !HB2_dffe7a[8] & (HB2_dffe7a[3] $ !X2_rdptr_g[3]);


--X2L28 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~58 at LCCOMB_X24_Y13_N14
X2L28 = HB2_dffe7a[5] & X2_rdptr_g[5] & (HB2_dffe7a[4] $ !X2_rdptr_g[4]) # !HB2_dffe7a[5] & !X2_rdptr_g[5] & (HB2_dffe7a[4] $ !X2_rdptr_g[4]);


--X2L29 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdempty_eq_comp_aeb_int~59 at LCCOMB_X24_Y13_N16
X2L29 = X2L27 & X2L26 & X2L28 & X2L25;


--X2_valid_rdreq is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq at LCCOMB_X24_Y13_N4
X2_valid_rdreq = G1_IN_REQ & G1_WR_MASK[1] & (X2L1 # !X2L29);


--X2_rdcnt_addr_ena is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdcnt_addr_ena at LCCOMB_X24_Y13_N28
X2_rdcnt_addr_ena = X2_valid_rdreq # !X2_p0addr;


--JB2_dffe9a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[7] at LCFF_X25_Y13_N25
JB2_dffe9a[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X2_rdptr_g[7],  ,  , VCC);


--EB2_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[7] at LCFF_X27_Y13_N29
EB2_power_modified_counter_values[7] = DFFEAS(EB2_countera7, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB2_dffe9a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[2] at LCFF_X25_Y13_N19
JB2_dffe9a[2] = DFFEAS(JB2L5, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[2] at LCFF_X27_Y13_N19
EB2_power_modified_counter_values[2] = DFFEAS(EB2_countera2, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB2_dffe9a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[0] at LCFF_X25_Y13_N13
JB2_dffe9a[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X2_rdptr_g[0],  ,  , VCC);


--EB2_counter_ffa[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|counter_ffa[0] at LCFF_X27_Y13_N15
EB2_counter_ffa[0] = DFFEAS(EB2_countera0, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2L44 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~54 at LCCOMB_X25_Y13_N12
X2L44 = EB2_counter_ffa[0] & !JB2_dffe9a[0] & (EB2_power_modified_counter_values[2] $ !JB2_dffe9a[2]) # !EB2_counter_ffa[0] & JB2_dffe9a[0] & (EB2_power_modified_counter_values[2] $ !JB2_dffe9a[2]);


--JB2_dffe9a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[6] at LCFF_X25_Y13_N11
JB2_dffe9a[6] = DFFEAS(JB2L11, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB2_dffe9a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[1] at LCFF_X25_Y13_N7
JB2_dffe9a[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X2_rdptr_g[1],  ,  , VCC);


--EB2_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[1] at LCFF_X27_Y13_N17
EB2_power_modified_counter_values[1] = DFFEAS(EB2_countera1, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[6] at LCFF_X27_Y13_N27
EB2_power_modified_counter_values[6] = DFFEAS(EB2_countera6, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2L45 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~55 at LCCOMB_X25_Y13_N6
X2L45 = EB2_power_modified_counter_values[1] & JB2_dffe9a[1] & (EB2_power_modified_counter_values[6] $ !JB2_dffe9a[6]) # !EB2_power_modified_counter_values[1] & !JB2_dffe9a[1] & (EB2_power_modified_counter_values[6] $ !JB2_dffe9a[6]);


--JB2_dffe9a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[3] at LCFF_X25_Y13_N27
JB2_dffe9a[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X2_rdptr_g[3],  ,  , VCC);


--JB2_dffe9a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[8] at LCFF_X25_Y13_N31
JB2_dffe9a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X2_rdptr_g[8],  ,  , VCC);


--EB2_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[8] at LCFF_X27_Y13_N31
EB2_power_modified_counter_values[8] = DFFEAS(EB2_countera8, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[3] at LCFF_X27_Y13_N21
EB2_power_modified_counter_values[3] = DFFEAS(EB2_countera3, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2L46 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~56 at LCCOMB_X25_Y13_N30
X2L46 = EB2_power_modified_counter_values[8] & JB2_dffe9a[8] & (EB2_power_modified_counter_values[3] $ !JB2_dffe9a[3]) # !EB2_power_modified_counter_values[8] & !JB2_dffe9a[8] & (EB2_power_modified_counter_values[3] $ !JB2_dffe9a[3]);


--JB2_dffe9a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5] at LCFF_X25_Y13_N29
JB2_dffe9a[5] = DFFEAS(JB2L9, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--JB2_dffe9a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[4] at LCFF_X25_Y13_N15
JB2_dffe9a[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X2_rdptr_g[4],  ,  , VCC);


--EB2_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[4] at LCFF_X27_Y13_N23
EB2_power_modified_counter_values[4] = DFFEAS(EB2_countera4, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB2_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|power_modified_counter_values[5] at LCFF_X27_Y13_N25
EB2_power_modified_counter_values[5] = DFFEAS(EB2_countera5, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2L47 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~57 at LCCOMB_X25_Y13_N14
X2L47 = EB2_power_modified_counter_values[4] & JB2_dffe9a[4] & (EB2_power_modified_counter_values[5] $ !JB2_dffe9a[5]) # !EB2_power_modified_counter_values[4] & !JB2_dffe9a[4] & (EB2_power_modified_counter_values[5] $ !JB2_dffe9a[5]);


--X2L48 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrfull_eq_comp_aeb_int~58 at LCCOMB_X25_Y13_N0
X2L48 = X2L45 & X2L46 & X2L47 & X2L44;


--X2_valid_wrreq is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_wrreq at LCCOMB_X25_Y13_N24
X2_valid_wrreq = J1_mCCD_DVAL & (JB2_dffe9a[7] $ EB2_power_modified_counter_values[7] # !X2L48);


--Z2_power_modified_counter_values[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[0] at LCFF_X25_Y14_N13
Z2_power_modified_counter_values[0] = DFFEAS(Z2_countera0, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[1] at LCFF_X25_Y14_N15
Z2_power_modified_counter_values[1] = DFFEAS(Z2_countera1, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[2] at LCFF_X25_Y14_N17
Z2_power_modified_counter_values[2] = DFFEAS(Z2_countera2, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[3] at LCFF_X25_Y14_N19
Z2_power_modified_counter_values[3] = DFFEAS(Z2_countera3, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[4] at LCFF_X25_Y14_N21
Z2_power_modified_counter_values[4] = DFFEAS(Z2_countera4, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[5] at LCFF_X25_Y14_N23
Z2_power_modified_counter_values[5] = DFFEAS(Z2_countera5, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[6] at LCFF_X25_Y14_N25
Z2_power_modified_counter_values[6] = DFFEAS(Z2_countera6, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[7] at LCFF_X25_Y14_N27
Z2_power_modified_counter_values[7] = DFFEAS(Z2_countera7, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z2_power_modified_counter_values[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8] at LCFF_X25_Y14_N29
Z2_power_modified_counter_values[8] = DFFEAS(Z2_countera8, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--PB1_q_b[0] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[0] at M4K_X13_Y8
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[0]_PORT_A_data_in = BUS(E1_mCCD_R[0], E1_mCCD_B[0], E1_mCCD_B[2], E1_mCCD_B[3]);
PB1_q_b[0]_PORT_A_data_in_reg = DFFE(PB1_q_b[0]_PORT_A_data_in, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[0]_PORT_A_address_reg = DFFE(PB1_q_b[0]_PORT_A_address, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[0]_PORT_B_address_reg = DFFE(PB1_q_b[0]_PORT_B_address, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0]_PORT_A_write_enable = VCC;
PB1_q_b[0]_PORT_A_write_enable_reg = DFFE(PB1_q_b[0]_PORT_A_write_enable, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_B_read_enable = VCC;
PB1_q_b[0]_PORT_B_read_enable_reg = DFFE(PB1_q_b[0]_PORT_B_read_enable, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0]_clock_0 = GLOBAL(A1L11);
PB1_q_b[0]_clock_1 = GLOBAL(A1L11);
PB1_q_b[0]_clock_enable_0 = E1_mDVAL;
PB1_q_b[0]_PORT_B_data_out = MEMORY(PB1_q_b[0]_PORT_A_data_in_reg, , PB1_q_b[0]_PORT_A_address_reg, PB1_q_b[0]_PORT_B_address_reg, PB1_q_b[0]_PORT_A_write_enable_reg, PB1_q_b[0]_PORT_B_read_enable_reg, , , PB1_q_b[0]_clock_0, PB1_q_b[0]_clock_1, PB1_q_b[0]_clock_enable_0, , , );
PB1_q_b[0]_PORT_B_data_out_reg = DFFE(PB1_q_b[0]_PORT_B_data_out, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0] = PB1_q_b[0]_PORT_B_data_out_reg[0];

--PB3_q_b[3] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[3] at M4K_X13_Y8
PB1_q_b[0]_PORT_A_data_in = BUS(E1_mCCD_R[0], E1_mCCD_B[0], E1_mCCD_B[2], E1_mCCD_B[3]);
PB1_q_b[0]_PORT_A_data_in_reg = DFFE(PB1_q_b[0]_PORT_A_data_in, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[0]_PORT_A_address_reg = DFFE(PB1_q_b[0]_PORT_A_address, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[0]_PORT_B_address_reg = DFFE(PB1_q_b[0]_PORT_B_address, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0]_PORT_A_write_enable = VCC;
PB1_q_b[0]_PORT_A_write_enable_reg = DFFE(PB1_q_b[0]_PORT_A_write_enable, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_B_read_enable = VCC;
PB1_q_b[0]_PORT_B_read_enable_reg = DFFE(PB1_q_b[0]_PORT_B_read_enable, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0]_clock_0 = GLOBAL(A1L11);
PB1_q_b[0]_clock_1 = GLOBAL(A1L11);
PB1_q_b[0]_clock_enable_0 = E1_mDVAL;
PB1_q_b[0]_PORT_B_data_out = MEMORY(PB1_q_b[0]_PORT_A_data_in_reg, , PB1_q_b[0]_PORT_A_address_reg, PB1_q_b[0]_PORT_B_address_reg, PB1_q_b[0]_PORT_A_write_enable_reg, PB1_q_b[0]_PORT_B_read_enable_reg, , , PB1_q_b[0]_clock_0, PB1_q_b[0]_clock_1, PB1_q_b[0]_clock_enable_0, , , );
PB1_q_b[0]_PORT_B_data_out_reg = DFFE(PB1_q_b[0]_PORT_B_data_out, PB1_q_b[0]_clock_1, , , );
PB3_q_b[3] = PB1_q_b[0]_PORT_B_data_out_reg[3];

--PB3_q_b[2] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[2] at M4K_X13_Y8
PB1_q_b[0]_PORT_A_data_in = BUS(E1_mCCD_R[0], E1_mCCD_B[0], E1_mCCD_B[2], E1_mCCD_B[3]);
PB1_q_b[0]_PORT_A_data_in_reg = DFFE(PB1_q_b[0]_PORT_A_data_in, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[0]_PORT_A_address_reg = DFFE(PB1_q_b[0]_PORT_A_address, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[0]_PORT_B_address_reg = DFFE(PB1_q_b[0]_PORT_B_address, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0]_PORT_A_write_enable = VCC;
PB1_q_b[0]_PORT_A_write_enable_reg = DFFE(PB1_q_b[0]_PORT_A_write_enable, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_B_read_enable = VCC;
PB1_q_b[0]_PORT_B_read_enable_reg = DFFE(PB1_q_b[0]_PORT_B_read_enable, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0]_clock_0 = GLOBAL(A1L11);
PB1_q_b[0]_clock_1 = GLOBAL(A1L11);
PB1_q_b[0]_clock_enable_0 = E1_mDVAL;
PB1_q_b[0]_PORT_B_data_out = MEMORY(PB1_q_b[0]_PORT_A_data_in_reg, , PB1_q_b[0]_PORT_A_address_reg, PB1_q_b[0]_PORT_B_address_reg, PB1_q_b[0]_PORT_A_write_enable_reg, PB1_q_b[0]_PORT_B_read_enable_reg, , , PB1_q_b[0]_clock_0, PB1_q_b[0]_clock_1, PB1_q_b[0]_clock_enable_0, , , );
PB1_q_b[0]_PORT_B_data_out_reg = DFFE(PB1_q_b[0]_PORT_B_data_out, PB1_q_b[0]_clock_1, , , );
PB3_q_b[2] = PB1_q_b[0]_PORT_B_data_out_reg[2];

--PB3_q_b[0] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[0] at M4K_X13_Y8
PB1_q_b[0]_PORT_A_data_in = BUS(E1_mCCD_R[0], E1_mCCD_B[0], E1_mCCD_B[2], E1_mCCD_B[3]);
PB1_q_b[0]_PORT_A_data_in_reg = DFFE(PB1_q_b[0]_PORT_A_data_in, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[0]_PORT_A_address_reg = DFFE(PB1_q_b[0]_PORT_A_address, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[0]_PORT_B_address_reg = DFFE(PB1_q_b[0]_PORT_B_address, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0]_PORT_A_write_enable = VCC;
PB1_q_b[0]_PORT_A_write_enable_reg = DFFE(PB1_q_b[0]_PORT_A_write_enable, PB1_q_b[0]_clock_0, , , PB1_q_b[0]_clock_enable_0);
PB1_q_b[0]_PORT_B_read_enable = VCC;
PB1_q_b[0]_PORT_B_read_enable_reg = DFFE(PB1_q_b[0]_PORT_B_read_enable, PB1_q_b[0]_clock_1, , , );
PB1_q_b[0]_clock_0 = GLOBAL(A1L11);
PB1_q_b[0]_clock_1 = GLOBAL(A1L11);
PB1_q_b[0]_clock_enable_0 = E1_mDVAL;
PB1_q_b[0]_PORT_B_data_out = MEMORY(PB1_q_b[0]_PORT_A_data_in_reg, , PB1_q_b[0]_PORT_A_address_reg, PB1_q_b[0]_PORT_B_address_reg, PB1_q_b[0]_PORT_A_write_enable_reg, PB1_q_b[0]_PORT_B_read_enable_reg, , , PB1_q_b[0]_clock_0, PB1_q_b[0]_clock_1, PB1_q_b[0]_clock_enable_0, , , );
PB1_q_b[0]_PORT_B_data_out_reg = DFFE(PB1_q_b[0]_PORT_B_data_out, PB1_q_b[0]_clock_1, , , );
PB3_q_b[0] = PB1_q_b[0]_PORT_B_data_out_reg[1];


--X2_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0] at LCFF_X27_Y13_N5
X2_wrptr_g[0] = DFFEAS(X2L51, GLOBAL(A1L11), GLOBAL(C1L78),  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[1] at LCFF_X27_Y13_N1
X2_wrptr_g[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  , X2_valid_wrreq, EB2_power_modified_counter_values[1],  ,  , VCC);


--X2_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2] at LCFF_X27_Y13_N3
X2_wrptr_g[2] = DFFEAS(X2L54, GLOBAL(A1L11), GLOBAL(C1L78),  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[3] at LCFF_X27_Y13_N11
X2_wrptr_g[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  , X2_valid_wrreq, EB2_power_modified_counter_values[3],  ,  , VCC);


--X2_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[4] at LCFF_X27_Y14_N17
X2_wrptr_g[4] = DFFEAS(X2L57, GLOBAL(A1L11), GLOBAL(C1L78),  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5] at LCFF_X27_Y14_N11
X2_wrptr_g[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  , X2_valid_wrreq, EB2_power_modified_counter_values[5],  ,  , VCC);


--X2_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6] at LCFF_X27_Y13_N7
X2_wrptr_g[6] = DFFEAS(X2L60, GLOBAL(A1L11), GLOBAL(C1L78),  , X2_valid_wrreq,  ,  ,  ,  );


--X2_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[7] at LCFF_X27_Y14_N5
X2_wrptr_g[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  , X2_valid_wrreq, EB2_power_modified_counter_values[7],  ,  , VCC);


--X2_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8] at LCFF_X27_Y13_N9
X2_wrptr_g[8] = DFFEAS(X2L63, GLOBAL(A1L11), GLOBAL(C1L78),  , X2_valid_wrreq,  ,  ,  ,  );


--PB1_q_b[1] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[1] at M4K_X13_Y16
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[1]_PORT_A_data_in = BUS(E1_mCCD_R[1], E1_mCCD_R[5], E1_mCCD_R[6], E1_mCCD_B[5]);
PB1_q_b[1]_PORT_A_data_in_reg = DFFE(PB1_q_b[1]_PORT_A_data_in, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[1]_PORT_A_address_reg = DFFE(PB1_q_b[1]_PORT_A_address, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[1]_PORT_B_address_reg = DFFE(PB1_q_b[1]_PORT_B_address, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1]_PORT_A_write_enable = VCC;
PB1_q_b[1]_PORT_A_write_enable_reg = DFFE(PB1_q_b[1]_PORT_A_write_enable, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_B_read_enable = VCC;
PB1_q_b[1]_PORT_B_read_enable_reg = DFFE(PB1_q_b[1]_PORT_B_read_enable, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1]_clock_0 = GLOBAL(A1L11);
PB1_q_b[1]_clock_1 = GLOBAL(A1L11);
PB1_q_b[1]_clock_enable_0 = E1_mDVAL;
PB1_q_b[1]_PORT_B_data_out = MEMORY(PB1_q_b[1]_PORT_A_data_in_reg, , PB1_q_b[1]_PORT_A_address_reg, PB1_q_b[1]_PORT_B_address_reg, PB1_q_b[1]_PORT_A_write_enable_reg, PB1_q_b[1]_PORT_B_read_enable_reg, , , PB1_q_b[1]_clock_0, PB1_q_b[1]_clock_1, PB1_q_b[1]_clock_enable_0, , , );
PB1_q_b[1]_PORT_B_data_out_reg = DFFE(PB1_q_b[1]_PORT_B_data_out, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1] = PB1_q_b[1]_PORT_B_data_out_reg[0];

--PB3_q_b[5] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[5] at M4K_X13_Y16
PB1_q_b[1]_PORT_A_data_in = BUS(E1_mCCD_R[1], E1_mCCD_R[5], E1_mCCD_R[6], E1_mCCD_B[5]);
PB1_q_b[1]_PORT_A_data_in_reg = DFFE(PB1_q_b[1]_PORT_A_data_in, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[1]_PORT_A_address_reg = DFFE(PB1_q_b[1]_PORT_A_address, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[1]_PORT_B_address_reg = DFFE(PB1_q_b[1]_PORT_B_address, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1]_PORT_A_write_enable = VCC;
PB1_q_b[1]_PORT_A_write_enable_reg = DFFE(PB1_q_b[1]_PORT_A_write_enable, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_B_read_enable = VCC;
PB1_q_b[1]_PORT_B_read_enable_reg = DFFE(PB1_q_b[1]_PORT_B_read_enable, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1]_clock_0 = GLOBAL(A1L11);
PB1_q_b[1]_clock_1 = GLOBAL(A1L11);
PB1_q_b[1]_clock_enable_0 = E1_mDVAL;
PB1_q_b[1]_PORT_B_data_out = MEMORY(PB1_q_b[1]_PORT_A_data_in_reg, , PB1_q_b[1]_PORT_A_address_reg, PB1_q_b[1]_PORT_B_address_reg, PB1_q_b[1]_PORT_A_write_enable_reg, PB1_q_b[1]_PORT_B_read_enable_reg, , , PB1_q_b[1]_clock_0, PB1_q_b[1]_clock_1, PB1_q_b[1]_clock_enable_0, , , );
PB1_q_b[1]_PORT_B_data_out_reg = DFFE(PB1_q_b[1]_PORT_B_data_out, PB1_q_b[1]_clock_1, , , );
PB3_q_b[5] = PB1_q_b[1]_PORT_B_data_out_reg[3];

--PB1_q_b[6] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[6] at M4K_X13_Y16
PB1_q_b[1]_PORT_A_data_in = BUS(E1_mCCD_R[1], E1_mCCD_R[5], E1_mCCD_R[6], E1_mCCD_B[5]);
PB1_q_b[1]_PORT_A_data_in_reg = DFFE(PB1_q_b[1]_PORT_A_data_in, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[1]_PORT_A_address_reg = DFFE(PB1_q_b[1]_PORT_A_address, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[1]_PORT_B_address_reg = DFFE(PB1_q_b[1]_PORT_B_address, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1]_PORT_A_write_enable = VCC;
PB1_q_b[1]_PORT_A_write_enable_reg = DFFE(PB1_q_b[1]_PORT_A_write_enable, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_B_read_enable = VCC;
PB1_q_b[1]_PORT_B_read_enable_reg = DFFE(PB1_q_b[1]_PORT_B_read_enable, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1]_clock_0 = GLOBAL(A1L11);
PB1_q_b[1]_clock_1 = GLOBAL(A1L11);
PB1_q_b[1]_clock_enable_0 = E1_mDVAL;
PB1_q_b[1]_PORT_B_data_out = MEMORY(PB1_q_b[1]_PORT_A_data_in_reg, , PB1_q_b[1]_PORT_A_address_reg, PB1_q_b[1]_PORT_B_address_reg, PB1_q_b[1]_PORT_A_write_enable_reg, PB1_q_b[1]_PORT_B_read_enable_reg, , , PB1_q_b[1]_clock_0, PB1_q_b[1]_clock_1, PB1_q_b[1]_clock_enable_0, , , );
PB1_q_b[1]_PORT_B_data_out_reg = DFFE(PB1_q_b[1]_PORT_B_data_out, PB1_q_b[1]_clock_1, , , );
PB1_q_b[6] = PB1_q_b[1]_PORT_B_data_out_reg[2];

--PB1_q_b[5] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[5] at M4K_X13_Y16
PB1_q_b[1]_PORT_A_data_in = BUS(E1_mCCD_R[1], E1_mCCD_R[5], E1_mCCD_R[6], E1_mCCD_B[5]);
PB1_q_b[1]_PORT_A_data_in_reg = DFFE(PB1_q_b[1]_PORT_A_data_in, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[1]_PORT_A_address_reg = DFFE(PB1_q_b[1]_PORT_A_address, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[1]_PORT_B_address_reg = DFFE(PB1_q_b[1]_PORT_B_address, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1]_PORT_A_write_enable = VCC;
PB1_q_b[1]_PORT_A_write_enable_reg = DFFE(PB1_q_b[1]_PORT_A_write_enable, PB1_q_b[1]_clock_0, , , PB1_q_b[1]_clock_enable_0);
PB1_q_b[1]_PORT_B_read_enable = VCC;
PB1_q_b[1]_PORT_B_read_enable_reg = DFFE(PB1_q_b[1]_PORT_B_read_enable, PB1_q_b[1]_clock_1, , , );
PB1_q_b[1]_clock_0 = GLOBAL(A1L11);
PB1_q_b[1]_clock_1 = GLOBAL(A1L11);
PB1_q_b[1]_clock_enable_0 = E1_mDVAL;
PB1_q_b[1]_PORT_B_data_out = MEMORY(PB1_q_b[1]_PORT_A_data_in_reg, , PB1_q_b[1]_PORT_A_address_reg, PB1_q_b[1]_PORT_B_address_reg, PB1_q_b[1]_PORT_A_write_enable_reg, PB1_q_b[1]_PORT_B_read_enable_reg, , , PB1_q_b[1]_clock_0, PB1_q_b[1]_clock_1, PB1_q_b[1]_clock_enable_0, , , );
PB1_q_b[1]_PORT_B_data_out_reg = DFFE(PB1_q_b[1]_PORT_B_data_out, PB1_q_b[1]_clock_1, , , );
PB1_q_b[5] = PB1_q_b[1]_PORT_B_data_out_reg[1];


--PB1_q_b[2] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[2] at M4K_X13_Y11
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[2]_PORT_A_data_in = BUS(E1_mCCD_R[2], E1_mCCD_R[3], E1_mCCD_B[1], E1_mCCD_B[6]);
PB1_q_b[2]_PORT_A_data_in_reg = DFFE(PB1_q_b[2]_PORT_A_data_in, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[2]_PORT_A_address_reg = DFFE(PB1_q_b[2]_PORT_A_address, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[2]_PORT_B_address_reg = DFFE(PB1_q_b[2]_PORT_B_address, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2]_PORT_A_write_enable = VCC;
PB1_q_b[2]_PORT_A_write_enable_reg = DFFE(PB1_q_b[2]_PORT_A_write_enable, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_B_read_enable = VCC;
PB1_q_b[2]_PORT_B_read_enable_reg = DFFE(PB1_q_b[2]_PORT_B_read_enable, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2]_clock_0 = GLOBAL(A1L11);
PB1_q_b[2]_clock_1 = GLOBAL(A1L11);
PB1_q_b[2]_clock_enable_0 = E1_mDVAL;
PB1_q_b[2]_PORT_B_data_out = MEMORY(PB1_q_b[2]_PORT_A_data_in_reg, , PB1_q_b[2]_PORT_A_address_reg, PB1_q_b[2]_PORT_B_address_reg, PB1_q_b[2]_PORT_A_write_enable_reg, PB1_q_b[2]_PORT_B_read_enable_reg, , , PB1_q_b[2]_clock_0, PB1_q_b[2]_clock_1, PB1_q_b[2]_clock_enable_0, , , );
PB1_q_b[2]_PORT_B_data_out_reg = DFFE(PB1_q_b[2]_PORT_B_data_out, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2] = PB1_q_b[2]_PORT_B_data_out_reg[0];

--PB3_q_b[6] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[6] at M4K_X13_Y11
PB1_q_b[2]_PORT_A_data_in = BUS(E1_mCCD_R[2], E1_mCCD_R[3], E1_mCCD_B[1], E1_mCCD_B[6]);
PB1_q_b[2]_PORT_A_data_in_reg = DFFE(PB1_q_b[2]_PORT_A_data_in, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[2]_PORT_A_address_reg = DFFE(PB1_q_b[2]_PORT_A_address, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[2]_PORT_B_address_reg = DFFE(PB1_q_b[2]_PORT_B_address, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2]_PORT_A_write_enable = VCC;
PB1_q_b[2]_PORT_A_write_enable_reg = DFFE(PB1_q_b[2]_PORT_A_write_enable, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_B_read_enable = VCC;
PB1_q_b[2]_PORT_B_read_enable_reg = DFFE(PB1_q_b[2]_PORT_B_read_enable, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2]_clock_0 = GLOBAL(A1L11);
PB1_q_b[2]_clock_1 = GLOBAL(A1L11);
PB1_q_b[2]_clock_enable_0 = E1_mDVAL;
PB1_q_b[2]_PORT_B_data_out = MEMORY(PB1_q_b[2]_PORT_A_data_in_reg, , PB1_q_b[2]_PORT_A_address_reg, PB1_q_b[2]_PORT_B_address_reg, PB1_q_b[2]_PORT_A_write_enable_reg, PB1_q_b[2]_PORT_B_read_enable_reg, , , PB1_q_b[2]_clock_0, PB1_q_b[2]_clock_1, PB1_q_b[2]_clock_enable_0, , , );
PB1_q_b[2]_PORT_B_data_out_reg = DFFE(PB1_q_b[2]_PORT_B_data_out, PB1_q_b[2]_clock_1, , , );
PB3_q_b[6] = PB1_q_b[2]_PORT_B_data_out_reg[3];

--PB3_q_b[1] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[1] at M4K_X13_Y11
PB1_q_b[2]_PORT_A_data_in = BUS(E1_mCCD_R[2], E1_mCCD_R[3], E1_mCCD_B[1], E1_mCCD_B[6]);
PB1_q_b[2]_PORT_A_data_in_reg = DFFE(PB1_q_b[2]_PORT_A_data_in, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[2]_PORT_A_address_reg = DFFE(PB1_q_b[2]_PORT_A_address, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[2]_PORT_B_address_reg = DFFE(PB1_q_b[2]_PORT_B_address, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2]_PORT_A_write_enable = VCC;
PB1_q_b[2]_PORT_A_write_enable_reg = DFFE(PB1_q_b[2]_PORT_A_write_enable, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_B_read_enable = VCC;
PB1_q_b[2]_PORT_B_read_enable_reg = DFFE(PB1_q_b[2]_PORT_B_read_enable, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2]_clock_0 = GLOBAL(A1L11);
PB1_q_b[2]_clock_1 = GLOBAL(A1L11);
PB1_q_b[2]_clock_enable_0 = E1_mDVAL;
PB1_q_b[2]_PORT_B_data_out = MEMORY(PB1_q_b[2]_PORT_A_data_in_reg, , PB1_q_b[2]_PORT_A_address_reg, PB1_q_b[2]_PORT_B_address_reg, PB1_q_b[2]_PORT_A_write_enable_reg, PB1_q_b[2]_PORT_B_read_enable_reg, , , PB1_q_b[2]_clock_0, PB1_q_b[2]_clock_1, PB1_q_b[2]_clock_enable_0, , , );
PB1_q_b[2]_PORT_B_data_out_reg = DFFE(PB1_q_b[2]_PORT_B_data_out, PB1_q_b[2]_clock_1, , , );
PB3_q_b[1] = PB1_q_b[2]_PORT_B_data_out_reg[2];

--PB1_q_b[3] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[3] at M4K_X13_Y11
PB1_q_b[2]_PORT_A_data_in = BUS(E1_mCCD_R[2], E1_mCCD_R[3], E1_mCCD_B[1], E1_mCCD_B[6]);
PB1_q_b[2]_PORT_A_data_in_reg = DFFE(PB1_q_b[2]_PORT_A_data_in, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[2]_PORT_A_address_reg = DFFE(PB1_q_b[2]_PORT_A_address, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[2]_PORT_B_address_reg = DFFE(PB1_q_b[2]_PORT_B_address, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2]_PORT_A_write_enable = VCC;
PB1_q_b[2]_PORT_A_write_enable_reg = DFFE(PB1_q_b[2]_PORT_A_write_enable, PB1_q_b[2]_clock_0, , , PB1_q_b[2]_clock_enable_0);
PB1_q_b[2]_PORT_B_read_enable = VCC;
PB1_q_b[2]_PORT_B_read_enable_reg = DFFE(PB1_q_b[2]_PORT_B_read_enable, PB1_q_b[2]_clock_1, , , );
PB1_q_b[2]_clock_0 = GLOBAL(A1L11);
PB1_q_b[2]_clock_1 = GLOBAL(A1L11);
PB1_q_b[2]_clock_enable_0 = E1_mDVAL;
PB1_q_b[2]_PORT_B_data_out = MEMORY(PB1_q_b[2]_PORT_A_data_in_reg, , PB1_q_b[2]_PORT_A_address_reg, PB1_q_b[2]_PORT_B_address_reg, PB1_q_b[2]_PORT_A_write_enable_reg, PB1_q_b[2]_PORT_B_read_enable_reg, , , PB1_q_b[2]_clock_0, PB1_q_b[2]_clock_1, PB1_q_b[2]_clock_enable_0, , , );
PB1_q_b[2]_PORT_B_data_out_reg = DFFE(PB1_q_b[2]_PORT_B_data_out, PB1_q_b[2]_clock_1, , , );
PB1_q_b[3] = PB1_q_b[2]_PORT_B_data_out_reg[1];


--PB1_q_b[4] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[4] at M4K_X13_Y9
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[4]_PORT_A_data_in = BUS(E1_mCCD_R[4], E1_mCCD_R[8], E1_mCCD_B[4], E1_mCCD_B[8]);
PB1_q_b[4]_PORT_A_data_in_reg = DFFE(PB1_q_b[4]_PORT_A_data_in, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[4]_PORT_A_address_reg = DFFE(PB1_q_b[4]_PORT_A_address, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[4]_PORT_B_address_reg = DFFE(PB1_q_b[4]_PORT_B_address, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4]_PORT_A_write_enable = VCC;
PB1_q_b[4]_PORT_A_write_enable_reg = DFFE(PB1_q_b[4]_PORT_A_write_enable, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_B_read_enable = VCC;
PB1_q_b[4]_PORT_B_read_enable_reg = DFFE(PB1_q_b[4]_PORT_B_read_enable, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4]_clock_0 = GLOBAL(A1L11);
PB1_q_b[4]_clock_1 = GLOBAL(A1L11);
PB1_q_b[4]_clock_enable_0 = E1_mDVAL;
PB1_q_b[4]_PORT_B_data_out = MEMORY(PB1_q_b[4]_PORT_A_data_in_reg, , PB1_q_b[4]_PORT_A_address_reg, PB1_q_b[4]_PORT_B_address_reg, PB1_q_b[4]_PORT_A_write_enable_reg, PB1_q_b[4]_PORT_B_read_enable_reg, , , PB1_q_b[4]_clock_0, PB1_q_b[4]_clock_1, PB1_q_b[4]_clock_enable_0, , , );
PB1_q_b[4]_PORT_B_data_out_reg = DFFE(PB1_q_b[4]_PORT_B_data_out, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4] = PB1_q_b[4]_PORT_B_data_out_reg[0];

--PB3_q_b[8] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[8] at M4K_X13_Y9
PB1_q_b[4]_PORT_A_data_in = BUS(E1_mCCD_R[4], E1_mCCD_R[8], E1_mCCD_B[4], E1_mCCD_B[8]);
PB1_q_b[4]_PORT_A_data_in_reg = DFFE(PB1_q_b[4]_PORT_A_data_in, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[4]_PORT_A_address_reg = DFFE(PB1_q_b[4]_PORT_A_address, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[4]_PORT_B_address_reg = DFFE(PB1_q_b[4]_PORT_B_address, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4]_PORT_A_write_enable = VCC;
PB1_q_b[4]_PORT_A_write_enable_reg = DFFE(PB1_q_b[4]_PORT_A_write_enable, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_B_read_enable = VCC;
PB1_q_b[4]_PORT_B_read_enable_reg = DFFE(PB1_q_b[4]_PORT_B_read_enable, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4]_clock_0 = GLOBAL(A1L11);
PB1_q_b[4]_clock_1 = GLOBAL(A1L11);
PB1_q_b[4]_clock_enable_0 = E1_mDVAL;
PB1_q_b[4]_PORT_B_data_out = MEMORY(PB1_q_b[4]_PORT_A_data_in_reg, , PB1_q_b[4]_PORT_A_address_reg, PB1_q_b[4]_PORT_B_address_reg, PB1_q_b[4]_PORT_A_write_enable_reg, PB1_q_b[4]_PORT_B_read_enable_reg, , , PB1_q_b[4]_clock_0, PB1_q_b[4]_clock_1, PB1_q_b[4]_clock_enable_0, , , );
PB1_q_b[4]_PORT_B_data_out_reg = DFFE(PB1_q_b[4]_PORT_B_data_out, PB1_q_b[4]_clock_1, , , );
PB3_q_b[8] = PB1_q_b[4]_PORT_B_data_out_reg[3];

--PB3_q_b[4] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[4] at M4K_X13_Y9
PB1_q_b[4]_PORT_A_data_in = BUS(E1_mCCD_R[4], E1_mCCD_R[8], E1_mCCD_B[4], E1_mCCD_B[8]);
PB1_q_b[4]_PORT_A_data_in_reg = DFFE(PB1_q_b[4]_PORT_A_data_in, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[4]_PORT_A_address_reg = DFFE(PB1_q_b[4]_PORT_A_address, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[4]_PORT_B_address_reg = DFFE(PB1_q_b[4]_PORT_B_address, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4]_PORT_A_write_enable = VCC;
PB1_q_b[4]_PORT_A_write_enable_reg = DFFE(PB1_q_b[4]_PORT_A_write_enable, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_B_read_enable = VCC;
PB1_q_b[4]_PORT_B_read_enable_reg = DFFE(PB1_q_b[4]_PORT_B_read_enable, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4]_clock_0 = GLOBAL(A1L11);
PB1_q_b[4]_clock_1 = GLOBAL(A1L11);
PB1_q_b[4]_clock_enable_0 = E1_mDVAL;
PB1_q_b[4]_PORT_B_data_out = MEMORY(PB1_q_b[4]_PORT_A_data_in_reg, , PB1_q_b[4]_PORT_A_address_reg, PB1_q_b[4]_PORT_B_address_reg, PB1_q_b[4]_PORT_A_write_enable_reg, PB1_q_b[4]_PORT_B_read_enable_reg, , , PB1_q_b[4]_clock_0, PB1_q_b[4]_clock_1, PB1_q_b[4]_clock_enable_0, , , );
PB1_q_b[4]_PORT_B_data_out_reg = DFFE(PB1_q_b[4]_PORT_B_data_out, PB1_q_b[4]_clock_1, , , );
PB3_q_b[4] = PB1_q_b[4]_PORT_B_data_out_reg[2];

--PB1_q_b[8] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[8] at M4K_X13_Y9
PB1_q_b[4]_PORT_A_data_in = BUS(E1_mCCD_R[4], E1_mCCD_R[8], E1_mCCD_B[4], E1_mCCD_B[8]);
PB1_q_b[4]_PORT_A_data_in_reg = DFFE(PB1_q_b[4]_PORT_A_data_in, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[4]_PORT_A_address_reg = DFFE(PB1_q_b[4]_PORT_A_address, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[4]_PORT_B_address_reg = DFFE(PB1_q_b[4]_PORT_B_address, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4]_PORT_A_write_enable = VCC;
PB1_q_b[4]_PORT_A_write_enable_reg = DFFE(PB1_q_b[4]_PORT_A_write_enable, PB1_q_b[4]_clock_0, , , PB1_q_b[4]_clock_enable_0);
PB1_q_b[4]_PORT_B_read_enable = VCC;
PB1_q_b[4]_PORT_B_read_enable_reg = DFFE(PB1_q_b[4]_PORT_B_read_enable, PB1_q_b[4]_clock_1, , , );
PB1_q_b[4]_clock_0 = GLOBAL(A1L11);
PB1_q_b[4]_clock_1 = GLOBAL(A1L11);
PB1_q_b[4]_clock_enable_0 = E1_mDVAL;
PB1_q_b[4]_PORT_B_data_out = MEMORY(PB1_q_b[4]_PORT_A_data_in_reg, , PB1_q_b[4]_PORT_A_address_reg, PB1_q_b[4]_PORT_B_address_reg, PB1_q_b[4]_PORT_A_write_enable_reg, PB1_q_b[4]_PORT_B_read_enable_reg, , , PB1_q_b[4]_clock_0, PB1_q_b[4]_clock_1, PB1_q_b[4]_clock_enable_0, , , );
PB1_q_b[4]_PORT_B_data_out_reg = DFFE(PB1_q_b[4]_PORT_B_data_out, PB1_q_b[4]_clock_1, , , );
PB1_q_b[8] = PB1_q_b[4]_PORT_B_data_out_reg[1];


--PB1_q_b[7] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[7] at M4K_X13_Y14
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB1_q_b[7]_PORT_A_data_in = BUS(E1_mCCD_R[7], E1_mCCD_R[9], E1_mCCD_B[7], E1_mCCD_B[9]);
PB1_q_b[7]_PORT_A_data_in_reg = DFFE(PB1_q_b[7]_PORT_A_data_in, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[7]_PORT_A_address_reg = DFFE(PB1_q_b[7]_PORT_A_address, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[7]_PORT_B_address_reg = DFFE(PB1_q_b[7]_PORT_B_address, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7]_PORT_A_write_enable = VCC;
PB1_q_b[7]_PORT_A_write_enable_reg = DFFE(PB1_q_b[7]_PORT_A_write_enable, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_B_read_enable = VCC;
PB1_q_b[7]_PORT_B_read_enable_reg = DFFE(PB1_q_b[7]_PORT_B_read_enable, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7]_clock_0 = GLOBAL(A1L11);
PB1_q_b[7]_clock_1 = GLOBAL(A1L11);
PB1_q_b[7]_clock_enable_0 = E1_mDVAL;
PB1_q_b[7]_PORT_B_data_out = MEMORY(PB1_q_b[7]_PORT_A_data_in_reg, , PB1_q_b[7]_PORT_A_address_reg, PB1_q_b[7]_PORT_B_address_reg, PB1_q_b[7]_PORT_A_write_enable_reg, PB1_q_b[7]_PORT_B_read_enable_reg, , , PB1_q_b[7]_clock_0, PB1_q_b[7]_clock_1, PB1_q_b[7]_clock_enable_0, , , );
PB1_q_b[7]_PORT_B_data_out_reg = DFFE(PB1_q_b[7]_PORT_B_data_out, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7] = PB1_q_b[7]_PORT_B_data_out_reg[0];

--PB3_q_b[9] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[9] at M4K_X13_Y14
PB1_q_b[7]_PORT_A_data_in = BUS(E1_mCCD_R[7], E1_mCCD_R[9], E1_mCCD_B[7], E1_mCCD_B[9]);
PB1_q_b[7]_PORT_A_data_in_reg = DFFE(PB1_q_b[7]_PORT_A_data_in, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[7]_PORT_A_address_reg = DFFE(PB1_q_b[7]_PORT_A_address, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[7]_PORT_B_address_reg = DFFE(PB1_q_b[7]_PORT_B_address, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7]_PORT_A_write_enable = VCC;
PB1_q_b[7]_PORT_A_write_enable_reg = DFFE(PB1_q_b[7]_PORT_A_write_enable, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_B_read_enable = VCC;
PB1_q_b[7]_PORT_B_read_enable_reg = DFFE(PB1_q_b[7]_PORT_B_read_enable, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7]_clock_0 = GLOBAL(A1L11);
PB1_q_b[7]_clock_1 = GLOBAL(A1L11);
PB1_q_b[7]_clock_enable_0 = E1_mDVAL;
PB1_q_b[7]_PORT_B_data_out = MEMORY(PB1_q_b[7]_PORT_A_data_in_reg, , PB1_q_b[7]_PORT_A_address_reg, PB1_q_b[7]_PORT_B_address_reg, PB1_q_b[7]_PORT_A_write_enable_reg, PB1_q_b[7]_PORT_B_read_enable_reg, , , PB1_q_b[7]_clock_0, PB1_q_b[7]_clock_1, PB1_q_b[7]_clock_enable_0, , , );
PB1_q_b[7]_PORT_B_data_out_reg = DFFE(PB1_q_b[7]_PORT_B_data_out, PB1_q_b[7]_clock_1, , , );
PB3_q_b[9] = PB1_q_b[7]_PORT_B_data_out_reg[3];

--PB3_q_b[7] is Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[7] at M4K_X13_Y14
PB1_q_b[7]_PORT_A_data_in = BUS(E1_mCCD_R[7], E1_mCCD_R[9], E1_mCCD_B[7], E1_mCCD_B[9]);
PB1_q_b[7]_PORT_A_data_in_reg = DFFE(PB1_q_b[7]_PORT_A_data_in, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[7]_PORT_A_address_reg = DFFE(PB1_q_b[7]_PORT_A_address, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[7]_PORT_B_address_reg = DFFE(PB1_q_b[7]_PORT_B_address, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7]_PORT_A_write_enable = VCC;
PB1_q_b[7]_PORT_A_write_enable_reg = DFFE(PB1_q_b[7]_PORT_A_write_enable, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_B_read_enable = VCC;
PB1_q_b[7]_PORT_B_read_enable_reg = DFFE(PB1_q_b[7]_PORT_B_read_enable, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7]_clock_0 = GLOBAL(A1L11);
PB1_q_b[7]_clock_1 = GLOBAL(A1L11);
PB1_q_b[7]_clock_enable_0 = E1_mDVAL;
PB1_q_b[7]_PORT_B_data_out = MEMORY(PB1_q_b[7]_PORT_A_data_in_reg, , PB1_q_b[7]_PORT_A_address_reg, PB1_q_b[7]_PORT_B_address_reg, PB1_q_b[7]_PORT_A_write_enable_reg, PB1_q_b[7]_PORT_B_read_enable_reg, , , PB1_q_b[7]_clock_0, PB1_q_b[7]_clock_1, PB1_q_b[7]_clock_enable_0, , , );
PB1_q_b[7]_PORT_B_data_out_reg = DFFE(PB1_q_b[7]_PORT_B_data_out, PB1_q_b[7]_clock_1, , , );
PB3_q_b[7] = PB1_q_b[7]_PORT_B_data_out_reg[2];

--PB1_q_b[9] is Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[9] at M4K_X13_Y14
PB1_q_b[7]_PORT_A_data_in = BUS(E1_mCCD_R[7], E1_mCCD_R[9], E1_mCCD_B[7], E1_mCCD_B[9]);
PB1_q_b[7]_PORT_A_data_in_reg = DFFE(PB1_q_b[7]_PORT_A_data_in, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB1_q_b[7]_PORT_A_address_reg = DFFE(PB1_q_b[7]_PORT_A_address, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB1_q_b[7]_PORT_B_address_reg = DFFE(PB1_q_b[7]_PORT_B_address, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7]_PORT_A_write_enable = VCC;
PB1_q_b[7]_PORT_A_write_enable_reg = DFFE(PB1_q_b[7]_PORT_A_write_enable, PB1_q_b[7]_clock_0, , , PB1_q_b[7]_clock_enable_0);
PB1_q_b[7]_PORT_B_read_enable = VCC;
PB1_q_b[7]_PORT_B_read_enable_reg = DFFE(PB1_q_b[7]_PORT_B_read_enable, PB1_q_b[7]_clock_1, , , );
PB1_q_b[7]_clock_0 = GLOBAL(A1L11);
PB1_q_b[7]_clock_1 = GLOBAL(A1L11);
PB1_q_b[7]_clock_enable_0 = E1_mDVAL;
PB1_q_b[7]_PORT_B_data_out = MEMORY(PB1_q_b[7]_PORT_A_data_in_reg, , PB1_q_b[7]_PORT_A_address_reg, PB1_q_b[7]_PORT_B_address_reg, PB1_q_b[7]_PORT_A_write_enable_reg, PB1_q_b[7]_PORT_B_read_enable_reg, , , PB1_q_b[7]_clock_0, PB1_q_b[7]_clock_1, PB1_q_b[7]_clock_enable_0, , , );
PB1_q_b[7]_PORT_B_data_out_reg = DFFE(PB1_q_b[7]_PORT_B_data_out, PB1_q_b[7]_clock_1, , , );
PB1_q_b[9] = PB1_q_b[7]_PORT_B_data_out_reg[1];


--PB2_q_b[0] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[0] at M4K_X13_Y15
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[0]_PORT_A_data_in = BUS(E1_mCCD_G[1], E1_mCCD_G[2], E1_mCCD_G[7], E1_mCCD_G[8]);
PB2_q_b[0]_PORT_A_data_in_reg = DFFE(PB2_q_b[0]_PORT_A_data_in, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[0]_PORT_A_address_reg = DFFE(PB2_q_b[0]_PORT_A_address, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[0]_PORT_B_address_reg = DFFE(PB2_q_b[0]_PORT_B_address, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0]_PORT_A_write_enable = VCC;
PB2_q_b[0]_PORT_A_write_enable_reg = DFFE(PB2_q_b[0]_PORT_A_write_enable, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_B_read_enable = VCC;
PB2_q_b[0]_PORT_B_read_enable_reg = DFFE(PB2_q_b[0]_PORT_B_read_enable, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0]_clock_0 = GLOBAL(A1L11);
PB2_q_b[0]_clock_1 = GLOBAL(A1L11);
PB2_q_b[0]_clock_enable_0 = E1_mDVAL;
PB2_q_b[0]_PORT_B_data_out = MEMORY(PB2_q_b[0]_PORT_A_data_in_reg, , PB2_q_b[0]_PORT_A_address_reg, PB2_q_b[0]_PORT_B_address_reg, PB2_q_b[0]_PORT_A_write_enable_reg, PB2_q_b[0]_PORT_B_read_enable_reg, , , PB2_q_b[0]_clock_0, PB2_q_b[0]_clock_1, PB2_q_b[0]_clock_enable_0, , , );
PB2_q_b[0]_PORT_B_data_out_reg = DFFE(PB2_q_b[0]_PORT_B_data_out, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0] = PB2_q_b[0]_PORT_B_data_out_reg[0];

--PB2_q_b[7] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[7] at M4K_X13_Y15
PB2_q_b[0]_PORT_A_data_in = BUS(E1_mCCD_G[1], E1_mCCD_G[2], E1_mCCD_G[7], E1_mCCD_G[8]);
PB2_q_b[0]_PORT_A_data_in_reg = DFFE(PB2_q_b[0]_PORT_A_data_in, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[0]_PORT_A_address_reg = DFFE(PB2_q_b[0]_PORT_A_address, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[0]_PORT_B_address_reg = DFFE(PB2_q_b[0]_PORT_B_address, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0]_PORT_A_write_enable = VCC;
PB2_q_b[0]_PORT_A_write_enable_reg = DFFE(PB2_q_b[0]_PORT_A_write_enable, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_B_read_enable = VCC;
PB2_q_b[0]_PORT_B_read_enable_reg = DFFE(PB2_q_b[0]_PORT_B_read_enable, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0]_clock_0 = GLOBAL(A1L11);
PB2_q_b[0]_clock_1 = GLOBAL(A1L11);
PB2_q_b[0]_clock_enable_0 = E1_mDVAL;
PB2_q_b[0]_PORT_B_data_out = MEMORY(PB2_q_b[0]_PORT_A_data_in_reg, , PB2_q_b[0]_PORT_A_address_reg, PB2_q_b[0]_PORT_B_address_reg, PB2_q_b[0]_PORT_A_write_enable_reg, PB2_q_b[0]_PORT_B_read_enable_reg, , , PB2_q_b[0]_clock_0, PB2_q_b[0]_clock_1, PB2_q_b[0]_clock_enable_0, , , );
PB2_q_b[0]_PORT_B_data_out_reg = DFFE(PB2_q_b[0]_PORT_B_data_out, PB2_q_b[0]_clock_1, , , );
PB2_q_b[7] = PB2_q_b[0]_PORT_B_data_out_reg[3];

--PB2_q_b[6] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[6] at M4K_X13_Y15
PB2_q_b[0]_PORT_A_data_in = BUS(E1_mCCD_G[1], E1_mCCD_G[2], E1_mCCD_G[7], E1_mCCD_G[8]);
PB2_q_b[0]_PORT_A_data_in_reg = DFFE(PB2_q_b[0]_PORT_A_data_in, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[0]_PORT_A_address_reg = DFFE(PB2_q_b[0]_PORT_A_address, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[0]_PORT_B_address_reg = DFFE(PB2_q_b[0]_PORT_B_address, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0]_PORT_A_write_enable = VCC;
PB2_q_b[0]_PORT_A_write_enable_reg = DFFE(PB2_q_b[0]_PORT_A_write_enable, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_B_read_enable = VCC;
PB2_q_b[0]_PORT_B_read_enable_reg = DFFE(PB2_q_b[0]_PORT_B_read_enable, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0]_clock_0 = GLOBAL(A1L11);
PB2_q_b[0]_clock_1 = GLOBAL(A1L11);
PB2_q_b[0]_clock_enable_0 = E1_mDVAL;
PB2_q_b[0]_PORT_B_data_out = MEMORY(PB2_q_b[0]_PORT_A_data_in_reg, , PB2_q_b[0]_PORT_A_address_reg, PB2_q_b[0]_PORT_B_address_reg, PB2_q_b[0]_PORT_A_write_enable_reg, PB2_q_b[0]_PORT_B_read_enable_reg, , , PB2_q_b[0]_clock_0, PB2_q_b[0]_clock_1, PB2_q_b[0]_clock_enable_0, , , );
PB2_q_b[0]_PORT_B_data_out_reg = DFFE(PB2_q_b[0]_PORT_B_data_out, PB2_q_b[0]_clock_1, , , );
PB2_q_b[6] = PB2_q_b[0]_PORT_B_data_out_reg[2];

--PB2_q_b[1] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[1] at M4K_X13_Y15
PB2_q_b[0]_PORT_A_data_in = BUS(E1_mCCD_G[1], E1_mCCD_G[2], E1_mCCD_G[7], E1_mCCD_G[8]);
PB2_q_b[0]_PORT_A_data_in_reg = DFFE(PB2_q_b[0]_PORT_A_data_in, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[0]_PORT_A_address_reg = DFFE(PB2_q_b[0]_PORT_A_address, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[0]_PORT_B_address_reg = DFFE(PB2_q_b[0]_PORT_B_address, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0]_PORT_A_write_enable = VCC;
PB2_q_b[0]_PORT_A_write_enable_reg = DFFE(PB2_q_b[0]_PORT_A_write_enable, PB2_q_b[0]_clock_0, , , PB2_q_b[0]_clock_enable_0);
PB2_q_b[0]_PORT_B_read_enable = VCC;
PB2_q_b[0]_PORT_B_read_enable_reg = DFFE(PB2_q_b[0]_PORT_B_read_enable, PB2_q_b[0]_clock_1, , , );
PB2_q_b[0]_clock_0 = GLOBAL(A1L11);
PB2_q_b[0]_clock_1 = GLOBAL(A1L11);
PB2_q_b[0]_clock_enable_0 = E1_mDVAL;
PB2_q_b[0]_PORT_B_data_out = MEMORY(PB2_q_b[0]_PORT_A_data_in_reg, , PB2_q_b[0]_PORT_A_address_reg, PB2_q_b[0]_PORT_B_address_reg, PB2_q_b[0]_PORT_A_write_enable_reg, PB2_q_b[0]_PORT_B_read_enable_reg, , , PB2_q_b[0]_clock_0, PB2_q_b[0]_clock_1, PB2_q_b[0]_clock_enable_0, , , );
PB2_q_b[0]_PORT_B_data_out_reg = DFFE(PB2_q_b[0]_PORT_B_data_out, PB2_q_b[0]_clock_1, , , );
PB2_q_b[1] = PB2_q_b[0]_PORT_B_data_out_reg[1];


--PB2_q_b[2] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[2] at M4K_X13_Y7
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 2, Port B Depth: 1024, Port B Width: 2
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[2]_PORT_A_data_in = BUS(E1_mCCD_G[3], E1_mCCD_G[6]);
PB2_q_b[2]_PORT_A_data_in_reg = DFFE(PB2_q_b[2]_PORT_A_data_in, PB2_q_b[2]_clock_0, , , PB2_q_b[2]_clock_enable_0);
PB2_q_b[2]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[2]_PORT_A_address_reg = DFFE(PB2_q_b[2]_PORT_A_address, PB2_q_b[2]_clock_0, , , PB2_q_b[2]_clock_enable_0);
PB2_q_b[2]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[2]_PORT_B_address_reg = DFFE(PB2_q_b[2]_PORT_B_address, PB2_q_b[2]_clock_1, , , );
PB2_q_b[2]_PORT_A_write_enable = VCC;
PB2_q_b[2]_PORT_A_write_enable_reg = DFFE(PB2_q_b[2]_PORT_A_write_enable, PB2_q_b[2]_clock_0, , , PB2_q_b[2]_clock_enable_0);
PB2_q_b[2]_PORT_B_read_enable = VCC;
PB2_q_b[2]_PORT_B_read_enable_reg = DFFE(PB2_q_b[2]_PORT_B_read_enable, PB2_q_b[2]_clock_1, , , );
PB2_q_b[2]_clock_0 = GLOBAL(A1L11);
PB2_q_b[2]_clock_1 = GLOBAL(A1L11);
PB2_q_b[2]_clock_enable_0 = E1_mDVAL;
PB2_q_b[2]_PORT_B_data_out = MEMORY(PB2_q_b[2]_PORT_A_data_in_reg, , PB2_q_b[2]_PORT_A_address_reg, PB2_q_b[2]_PORT_B_address_reg, PB2_q_b[2]_PORT_A_write_enable_reg, PB2_q_b[2]_PORT_B_read_enable_reg, , , PB2_q_b[2]_clock_0, PB2_q_b[2]_clock_1, PB2_q_b[2]_clock_enable_0, , , );
PB2_q_b[2]_PORT_B_data_out_reg = DFFE(PB2_q_b[2]_PORT_B_data_out, PB2_q_b[2]_clock_1, , , );
PB2_q_b[2] = PB2_q_b[2]_PORT_B_data_out_reg[0];

--PB2_q_b[5] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[5] at M4K_X13_Y7
PB2_q_b[2]_PORT_A_data_in = BUS(E1_mCCD_G[3], E1_mCCD_G[6]);
PB2_q_b[2]_PORT_A_data_in_reg = DFFE(PB2_q_b[2]_PORT_A_data_in, PB2_q_b[2]_clock_0, , , PB2_q_b[2]_clock_enable_0);
PB2_q_b[2]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[2]_PORT_A_address_reg = DFFE(PB2_q_b[2]_PORT_A_address, PB2_q_b[2]_clock_0, , , PB2_q_b[2]_clock_enable_0);
PB2_q_b[2]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[2]_PORT_B_address_reg = DFFE(PB2_q_b[2]_PORT_B_address, PB2_q_b[2]_clock_1, , , );
PB2_q_b[2]_PORT_A_write_enable = VCC;
PB2_q_b[2]_PORT_A_write_enable_reg = DFFE(PB2_q_b[2]_PORT_A_write_enable, PB2_q_b[2]_clock_0, , , PB2_q_b[2]_clock_enable_0);
PB2_q_b[2]_PORT_B_read_enable = VCC;
PB2_q_b[2]_PORT_B_read_enable_reg = DFFE(PB2_q_b[2]_PORT_B_read_enable, PB2_q_b[2]_clock_1, , , );
PB2_q_b[2]_clock_0 = GLOBAL(A1L11);
PB2_q_b[2]_clock_1 = GLOBAL(A1L11);
PB2_q_b[2]_clock_enable_0 = E1_mDVAL;
PB2_q_b[2]_PORT_B_data_out = MEMORY(PB2_q_b[2]_PORT_A_data_in_reg, , PB2_q_b[2]_PORT_A_address_reg, PB2_q_b[2]_PORT_B_address_reg, PB2_q_b[2]_PORT_A_write_enable_reg, PB2_q_b[2]_PORT_B_read_enable_reg, , , PB2_q_b[2]_clock_0, PB2_q_b[2]_clock_1, PB2_q_b[2]_clock_enable_0, , , );
PB2_q_b[2]_PORT_B_data_out_reg = DFFE(PB2_q_b[2]_PORT_B_data_out, PB2_q_b[2]_clock_1, , , );
PB2_q_b[5] = PB2_q_b[2]_PORT_B_data_out_reg[1];


--PB2_q_b[3] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[3] at M4K_X13_Y10
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 640, Port A Logical Width: 10, Port B Logical Depth: 640, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
PB2_q_b[3]_PORT_A_data_in = BUS(E1_mCCD_G[4], E1_mCCD_G[5], E1_mCCD_G[9], E1_mCCD_G[10]);
PB2_q_b[3]_PORT_A_data_in_reg = DFFE(PB2_q_b[3]_PORT_A_data_in, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[3]_PORT_A_address_reg = DFFE(PB2_q_b[3]_PORT_A_address, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[3]_PORT_B_address_reg = DFFE(PB2_q_b[3]_PORT_B_address, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3]_PORT_A_write_enable = VCC;
PB2_q_b[3]_PORT_A_write_enable_reg = DFFE(PB2_q_b[3]_PORT_A_write_enable, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_B_read_enable = VCC;
PB2_q_b[3]_PORT_B_read_enable_reg = DFFE(PB2_q_b[3]_PORT_B_read_enable, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3]_clock_0 = GLOBAL(A1L11);
PB2_q_b[3]_clock_1 = GLOBAL(A1L11);
PB2_q_b[3]_clock_enable_0 = E1_mDVAL;
PB2_q_b[3]_PORT_B_data_out = MEMORY(PB2_q_b[3]_PORT_A_data_in_reg, , PB2_q_b[3]_PORT_A_address_reg, PB2_q_b[3]_PORT_B_address_reg, PB2_q_b[3]_PORT_A_write_enable_reg, PB2_q_b[3]_PORT_B_read_enable_reg, , , PB2_q_b[3]_clock_0, PB2_q_b[3]_clock_1, PB2_q_b[3]_clock_enable_0, , , );
PB2_q_b[3]_PORT_B_data_out_reg = DFFE(PB2_q_b[3]_PORT_B_data_out, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3] = PB2_q_b[3]_PORT_B_data_out_reg[0];

--PB2_q_b[9] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[9] at M4K_X13_Y10
PB2_q_b[3]_PORT_A_data_in = BUS(E1_mCCD_G[4], E1_mCCD_G[5], E1_mCCD_G[9], E1_mCCD_G[10]);
PB2_q_b[3]_PORT_A_data_in_reg = DFFE(PB2_q_b[3]_PORT_A_data_in, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[3]_PORT_A_address_reg = DFFE(PB2_q_b[3]_PORT_A_address, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[3]_PORT_B_address_reg = DFFE(PB2_q_b[3]_PORT_B_address, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3]_PORT_A_write_enable = VCC;
PB2_q_b[3]_PORT_A_write_enable_reg = DFFE(PB2_q_b[3]_PORT_A_write_enable, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_B_read_enable = VCC;
PB2_q_b[3]_PORT_B_read_enable_reg = DFFE(PB2_q_b[3]_PORT_B_read_enable, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3]_clock_0 = GLOBAL(A1L11);
PB2_q_b[3]_clock_1 = GLOBAL(A1L11);
PB2_q_b[3]_clock_enable_0 = E1_mDVAL;
PB2_q_b[3]_PORT_B_data_out = MEMORY(PB2_q_b[3]_PORT_A_data_in_reg, , PB2_q_b[3]_PORT_A_address_reg, PB2_q_b[3]_PORT_B_address_reg, PB2_q_b[3]_PORT_A_write_enable_reg, PB2_q_b[3]_PORT_B_read_enable_reg, , , PB2_q_b[3]_clock_0, PB2_q_b[3]_clock_1, PB2_q_b[3]_clock_enable_0, , , );
PB2_q_b[3]_PORT_B_data_out_reg = DFFE(PB2_q_b[3]_PORT_B_data_out, PB2_q_b[3]_clock_1, , , );
PB2_q_b[9] = PB2_q_b[3]_PORT_B_data_out_reg[3];

--PB2_q_b[8] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[8] at M4K_X13_Y10
PB2_q_b[3]_PORT_A_data_in = BUS(E1_mCCD_G[4], E1_mCCD_G[5], E1_mCCD_G[9], E1_mCCD_G[10]);
PB2_q_b[3]_PORT_A_data_in_reg = DFFE(PB2_q_b[3]_PORT_A_data_in, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[3]_PORT_A_address_reg = DFFE(PB2_q_b[3]_PORT_A_address, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[3]_PORT_B_address_reg = DFFE(PB2_q_b[3]_PORT_B_address, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3]_PORT_A_write_enable = VCC;
PB2_q_b[3]_PORT_A_write_enable_reg = DFFE(PB2_q_b[3]_PORT_A_write_enable, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_B_read_enable = VCC;
PB2_q_b[3]_PORT_B_read_enable_reg = DFFE(PB2_q_b[3]_PORT_B_read_enable, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3]_clock_0 = GLOBAL(A1L11);
PB2_q_b[3]_clock_1 = GLOBAL(A1L11);
PB2_q_b[3]_clock_enable_0 = E1_mDVAL;
PB2_q_b[3]_PORT_B_data_out = MEMORY(PB2_q_b[3]_PORT_A_data_in_reg, , PB2_q_b[3]_PORT_A_address_reg, PB2_q_b[3]_PORT_B_address_reg, PB2_q_b[3]_PORT_A_write_enable_reg, PB2_q_b[3]_PORT_B_read_enable_reg, , , PB2_q_b[3]_clock_0, PB2_q_b[3]_clock_1, PB2_q_b[3]_clock_enable_0, , , );
PB2_q_b[3]_PORT_B_data_out_reg = DFFE(PB2_q_b[3]_PORT_B_data_out, PB2_q_b[3]_clock_1, , , );
PB2_q_b[8] = PB2_q_b[3]_PORT_B_data_out_reg[2];

--PB2_q_b[4] is Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component|altsyncram_p9g1:auto_generated|q_b[4] at M4K_X13_Y10
PB2_q_b[3]_PORT_A_data_in = BUS(E1_mCCD_G[4], E1_mCCD_G[5], E1_mCCD_G[9], E1_mCCD_G[10]);
PB2_q_b[3]_PORT_A_data_in_reg = DFFE(PB2_q_b[3]_PORT_A_data_in, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_A_address = BUS(J1_Z_Cont[0], J1_Z_Cont[1], J1_Z_Cont[2], J1_Z_Cont[3], J1_Z_Cont[4], J1_Z_Cont[5], J1_Z_Cont[6], J1_Z_Cont[7], J1_Z_Cont[8], J1_Z_Cont[9]);
PB2_q_b[3]_PORT_A_address_reg = DFFE(PB2_q_b[3]_PORT_A_address, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_B_address = BUS(J1L6, J1L10, J1L14, J1L18, J1L22, J1L26, J1L30, J1_Z_Cont[7], J1L40, J1L41);
PB2_q_b[3]_PORT_B_address_reg = DFFE(PB2_q_b[3]_PORT_B_address, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3]_PORT_A_write_enable = VCC;
PB2_q_b[3]_PORT_A_write_enable_reg = DFFE(PB2_q_b[3]_PORT_A_write_enable, PB2_q_b[3]_clock_0, , , PB2_q_b[3]_clock_enable_0);
PB2_q_b[3]_PORT_B_read_enable = VCC;
PB2_q_b[3]_PORT_B_read_enable_reg = DFFE(PB2_q_b[3]_PORT_B_read_enable, PB2_q_b[3]_clock_1, , , );
PB2_q_b[3]_clock_0 = GLOBAL(A1L11);
PB2_q_b[3]_clock_1 = GLOBAL(A1L11);
PB2_q_b[3]_clock_enable_0 = E1_mDVAL;
PB2_q_b[3]_PORT_B_data_out = MEMORY(PB2_q_b[3]_PORT_A_data_in_reg, , PB2_q_b[3]_PORT_A_address_reg, PB2_q_b[3]_PORT_B_address_reg, PB2_q_b[3]_PORT_A_write_enable_reg, PB2_q_b[3]_PORT_B_read_enable_reg, , , PB2_q_b[3]_clock_0, PB2_q_b[3]_clock_1, PB2_q_b[3]_clock_enable_0, , , );
PB2_q_b[3]_PORT_B_data_out_reg = DFFE(PB2_q_b[3]_PORT_B_data_out, PB2_q_b[3]_clock_1, , , );
PB2_q_b[4] = PB2_q_b[3]_PORT_B_data_out_reg[1];


--LB1L67 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1081 at LCCOMB_X45_Y17_N0
LB1L67 = !LB1L60Q & !LB1L54Q & !LB1L63Q & !LB1L57Q;


--LB1L18 is I2C_CCD_Config:u7|I2C_Controller:u0|LessThan~163 at LCCOMB_X45_Y17_N4
LB1L18 = LB1L51Q # LB1L66Q # !LB1L67;


--LB1L49 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~302 at LCCOMB_X45_Y17_N6
LB1L49 = LB1L51Q & !LB1L18 & VCC # !LB1L51Q & LB1L18;

--LB1L50 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~303 at LCCOMB_X45_Y17_N6
LB1L50 = CARRY(!LB1L51Q & LB1L18);


--H1_mI2C_GO is I2C_CCD_Config:u7|mI2C_GO at LCFF_X44_Y16_N1
H1_mI2C_GO = DFFEAS(H1L39, GLOBAL(H1L93), GLOBAL(A1L291),  , H1L38,  ,  ,  ,  );


--LB1L52 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~304 at LCCOMB_X45_Y17_N8
LB1L52 = LB1L54Q & (GND # !LB1L50) # !LB1L54Q & (LB1L50 $ GND);

--LB1L53 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~305 at LCCOMB_X45_Y17_N8
LB1L53 = CARRY(LB1L54Q # !LB1L50);


--LB1L55 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~306 at LCCOMB_X45_Y17_N10
LB1L55 = LB1L57Q & LB1L53 & VCC # !LB1L57Q & !LB1L53;

--LB1L56 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~307 at LCCOMB_X45_Y17_N10
LB1L56 = CARRY(!LB1L57Q & !LB1L53);


--LB1L58 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~308 at LCCOMB_X45_Y17_N12
LB1L58 = LB1L60Q & (GND # !LB1L56) # !LB1L60Q & (LB1L56 $ GND);

--LB1L59 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~309 at LCCOMB_X45_Y17_N12
LB1L59 = CARRY(LB1L60Q # !LB1L56);


--LB1L61 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~310 at LCCOMB_X45_Y17_N14
LB1L61 = LB1L63Q & LB1L59 & VCC # !LB1L63Q & !LB1L59;

--LB1L62 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~311 at LCCOMB_X45_Y17_N14
LB1L62 = CARRY(!LB1L63Q & !LB1L59);


--LB1L64 is I2C_CCD_Config:u7|I2C_Controller:u0|SD_COUNTER[5]~312 at LCCOMB_X45_Y17_N16
LB1L64 = LB1L66Q $ LB1L62;


--H1_mI2C_CLK_DIV[12] is I2C_CCD_Config:u7|mI2C_CLK_DIV[12] at LCFF_X45_Y16_N25
H1_mI2C_CLK_DIV[12] = DFFEAS(H1L80, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[13] is I2C_CCD_Config:u7|mI2C_CLK_DIV[13] at LCFF_X45_Y16_N27
H1_mI2C_CLK_DIV[13] = DFFEAS(H1L83, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[14] is I2C_CCD_Config:u7|mI2C_CLK_DIV[14] at LCFF_X45_Y16_N29
H1_mI2C_CLK_DIV[14] = DFFEAS(H1L86, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[15] is I2C_CCD_Config:u7|mI2C_CLK_DIV[15] at LCFF_X45_Y16_N31
H1_mI2C_CLK_DIV[15] = DFFEAS(H1L89, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1L32 is I2C_CCD_Config:u7|LessThan~303 at LCCOMB_X44_Y16_N28
H1L32 = !H1_mI2C_CLK_DIV[12] & !H1_mI2C_CLK_DIV[14] & !H1_mI2C_CLK_DIV[13] & !H1_mI2C_CLK_DIV[15];


--H1_mI2C_CLK_DIV[2] is I2C_CCD_Config:u7|mI2C_CLK_DIV[2] at LCFF_X45_Y16_N5
H1_mI2C_CLK_DIV[2] = DFFEAS(H1L50, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[3] is I2C_CCD_Config:u7|mI2C_CLK_DIV[3] at LCFF_X45_Y16_N7
H1_mI2C_CLK_DIV[3] = DFFEAS(H1L53, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[4] is I2C_CCD_Config:u7|mI2C_CLK_DIV[4] at LCFF_X45_Y16_N9
H1_mI2C_CLK_DIV[4] = DFFEAS(H1L56, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[5] is I2C_CCD_Config:u7|mI2C_CLK_DIV[5] at LCFF_X45_Y16_N11
H1_mI2C_CLK_DIV[5] = DFFEAS(H1L59, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1L33 is I2C_CCD_Config:u7|LessThan~304 at LCCOMB_X44_Y16_N10
H1L33 = !H1_mI2C_CLK_DIV[2] & !H1_mI2C_CLK_DIV[5] & !H1_mI2C_CLK_DIV[4] & !H1_mI2C_CLK_DIV[3];


--H1_mI2C_CLK_DIV[6] is I2C_CCD_Config:u7|mI2C_CLK_DIV[6] at LCFF_X45_Y16_N13
H1_mI2C_CLK_DIV[6] = DFFEAS(H1L62, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[7] is I2C_CCD_Config:u7|mI2C_CLK_DIV[7] at LCFF_X45_Y16_N15
H1_mI2C_CLK_DIV[7] = DFFEAS(H1L65, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[8] is I2C_CCD_Config:u7|mI2C_CLK_DIV[8] at LCFF_X45_Y16_N17
H1_mI2C_CLK_DIV[8] = DFFEAS(H1L68, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1L34 is I2C_CCD_Config:u7|LessThan~305 at LCCOMB_X44_Y16_N26
H1L34 = H1L33 # !H1_mI2C_CLK_DIV[7] # !H1_mI2C_CLK_DIV[6] # !H1_mI2C_CLK_DIV[8];


--H1_mI2C_CLK_DIV[9] is I2C_CCD_Config:u7|mI2C_CLK_DIV[9] at LCFF_X45_Y16_N19
H1_mI2C_CLK_DIV[9] = DFFEAS(H1L71, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[10] is I2C_CCD_Config:u7|mI2C_CLK_DIV[10] at LCFF_X45_Y16_N21
H1_mI2C_CLK_DIV[10] = DFFEAS(H1L74, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1L35 is I2C_CCD_Config:u7|LessThan~306 at LCCOMB_X44_Y16_N12
H1L35 = !H1_mI2C_CLK_DIV[10] & !H1_mI2C_CLK_DIV[9];


--H1_mI2C_CLK_DIV[11] is I2C_CCD_Config:u7|mI2C_CLK_DIV[11] at LCFF_X45_Y16_N23
H1_mI2C_CLK_DIV[11] = DFFEAS(H1L77, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1L36 is I2C_CCD_Config:u7|LessThan~307 at LCCOMB_X44_Y16_N14
H1L36 = H1_mI2C_CLK_DIV[11] & (!H1L34 # !H1L35) # !H1L32;


--H1L92 is I2C_CCD_Config:u7|mI2C_CTRL_CLK~79 at LCCOMB_X44_Y16_N22
H1L92 = H1L36 $ H1_mI2C_CTRL_CLK;


--LB1L20 is I2C_CCD_Config:u7|I2C_Controller:u0|SCLK~145 at LCCOMB_X44_Y17_N0
LB1L20 = LB1L54Q & (!LB1L60Q) # !LB1L54Q & LB1L57Q;


--LB1L21 is I2C_CCD_Config:u7|I2C_Controller:u0|SCLK~146 at LCCOMB_X44_Y17_N14
LB1L21 = LB1L60Q & (!LB1L20 # !LB1L63Q # !LB1L51Q) # !LB1L60Q & (LB1L63Q # LB1L20);


--LB1L47 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[15]~777 at LCCOMB_X45_Y17_N26
LB1L47 = LB1L60Q & LB1L54Q & LB1L63Q & LB1L57Q;


--LB1L22 is I2C_CCD_Config:u7|I2C_Controller:u0|SCLK~147 at LCCOMB_X45_Y17_N18
LB1L22 = LB1L51Q & (LB1L47 $ !LB1L21);


--LB1L23 is I2C_CCD_Config:u7|I2C_Controller:u0|SCLK~148 at LCCOMB_X45_Y17_N22
LB1L23 = LB1L66Q & (LB1L22 & (!LB1L21) # !LB1L22 & LB1_SCLK & LB1L21) # !LB1L66Q & (LB1_SCLK);


--LB1L68 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1082 at LCCOMB_X43_Y17_N12
LB1L68 = LB1L60Q & LB1L54Q & LB1L51Q & LB1L57Q;


--LB1_SD[2] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[2] at LCFF_X43_Y16_N25
LB1_SD[2] = DFFEAS(LB1L29, GLOBAL(H1L93),  ,  , LB1L46,  ,  ,  ,  );


--LB1_SD[8] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[8] at LCFF_X43_Y17_N31
LB1_SD[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(H1L93),  ,  , LB1L46, H1_mI2C_DATA[8],  ,  , VCC);


--LB1_SD[9] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[9] at LCFF_X42_Y17_N25
LB1_SD[9] = DFFEAS(LB1L40, GLOBAL(H1L93),  ,  , LB1L46,  ,  ,  ,  );


--LB1L69 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1083 at LCCOMB_X43_Y17_N30
LB1L69 = LB1L60Q & (LB1L51Q & (LB1_SD[9]) # !LB1L51Q & LB1_SD[8]) # !LB1L60Q & !LB1L51Q;


--LB1_SD[1] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[1] at LCFF_X43_Y17_N25
LB1_SD[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(H1L93),  ,  , LB1L46, H1_mI2C_DATA[1],  ,  , VCC);


--LB1L70 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1084 at LCCOMB_X43_Y17_N24
LB1L70 = LB1L60Q & LB1L69 # !LB1L60Q & (LB1L69 & LB1_SD[1] # !LB1L69 & (LB1_SD[2]));


--LB1_SD[7] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[7] at LCFF_X42_Y17_N23
LB1_SD[7] = DFFEAS(LB1L37, GLOBAL(H1L93),  ,  , LB1L46,  ,  ,  ,  );


--LB1_SD[0] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[0] at LCFF_X43_Y17_N19
LB1_SD[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(H1L93),  ,  , LB1L46, H1_mI2C_DATA[0],  ,  , VCC);


--LB1L71 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1085 at LCCOMB_X43_Y17_N18
LB1L71 = LB1L60Q & (LB1L51Q # LB1_SD[7]) # !LB1L60Q & (LB1_SD[0] # !LB1L51Q);


--LB1_SD[4] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[4] at LCFF_X43_Y17_N23
LB1_SD[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(H1L93),  ,  , LB1L46, H1_mI2C_DATA[4],  ,  , VCC);


--LB1_SD[10] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[10] at LCFF_X43_Y17_N27
LB1_SD[10] = DFFEAS(LB1L42, GLOBAL(H1L93),  ,  , LB1L46,  ,  ,  ,  );


--LB1_SD[11] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[11] at LCFF_X43_Y17_N7
LB1_SD[11] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(H1L93),  ,  , LB1L46, H1_mI2C_DATA[11],  ,  , VCC);


--LB1L72 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1086 at LCCOMB_X43_Y17_N6
LB1L72 = LB1L60Q & (LB1L51Q & LB1_SD[11] # !LB1L51Q & (LB1_SD[10])) # !LB1L60Q & !LB1L51Q;


--LB1_SD[3] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[3] at LCFF_X43_Y16_N1
LB1_SD[3] = DFFEAS(LB1L31, GLOBAL(H1L93),  ,  , LB1L46,  ,  ,  ,  );


--LB1L73 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1087 at LCCOMB_X43_Y17_N22
LB1L73 = LB1L72 & (LB1_SD[3] # LB1L60Q) # !LB1L72 & (LB1_SD[4] & !LB1L60Q);


--LB1L74 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1088 at LCCOMB_X43_Y17_N20
LB1L74 = LB1L57Q & LB1L73 & LB1L54Q # !LB1L57Q & (LB1L71 # !LB1L54Q);


--LB1_SD[6] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[6] at LCFF_X44_Y17_N5
LB1_SD[6] = DFFEAS(LB1L35, GLOBAL(H1L93),  ,  , LB1L46,  ,  ,  ,  );


--LB1_SD[5] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[5] at LCFF_X44_Y17_N25
LB1_SD[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(H1L93),  ,  , LB1L46, H1_mI2C_DATA[5],  ,  , VCC);


--LB1L75 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1089 at LCCOMB_X44_Y17_N24
LB1L75 = LB1L51Q & LB1_SD[6] # !LB1L51Q & (LB1_SD[5]);


--LB1L76 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1090 at LCCOMB_X43_Y17_N2
LB1L76 = LB1L60Q & LB1L75 # !LB1L60Q & (!LB1L51Q & !LB1L25Q);


--LB1L77 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1091 at LCCOMB_X43_Y17_N28
LB1L77 = LB1L54Q & (LB1L74) # !LB1L54Q & (LB1L74 & (LB1L76) # !LB1L74 & LB1L70);


--LB1L78 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1092 at LCCOMB_X44_Y17_N30
LB1L78 = LB1L54Q & LB1L51Q;


--LB1L79 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1093 at LCCOMB_X43_Y17_N14
LB1L79 = LB1L54Q & LB1L51Q # !LB1L54Q & (!LB1L25Q # !LB1L51Q);


--LB1L80 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1094 at LCCOMB_X43_Y17_N16
LB1L80 = LB1L60Q & LB1L79 & (LB1L57Q) # !LB1L60Q & (!LB1L57Q # !LB1L51Q);


--LB1_SD[15] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[15] at LCFF_X42_Y17_N29
LB1_SD[15] = DFFEAS(LB1L48, GLOBAL(H1L93),  ,  , LB1L46,  ,  ,  ,  );


--LB1_SD[13] is I2C_CCD_Config:u7|I2C_Controller:u0|SD[13] at LCFF_X43_Y17_N11
LB1_SD[13] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(H1L93),  ,  , LB1L46, H1_mI2C_DATA[13],  ,  , VCC);


--LB1L81 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1095 at LCCOMB_X43_Y17_N10
LB1L81 = LB1L51Q & (LB1L54Q & (LB1_SD[15]) # !LB1L54Q & LB1_SD[13]) # !LB1L51Q & (LB1_SD[15]);


--LB1L82 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1096 at LCCOMB_X43_Y17_N4
LB1L82 = LB1L57Q & (LB1L80) # !LB1L57Q & (LB1L80 & (LB1L81) # !LB1L80 & !LB1L78);


--LB1L83 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1097 at LCCOMB_X43_Y17_N8
LB1L83 = LB1L63Q & (LB1L82 & LB1L66Q) # !LB1L63Q & (LB1L77 # !LB1L66Q);


--LB1L84 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1098 at LCCOMB_X43_Y17_N0
LB1L84 = LB1L66Q & (!LB1L83) # !LB1L66Q & LB1L25Q & (LB1L83 # !LB1L68);


--S1_init_timer[10] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[10] at LCFF_X33_Y19_N21
S1_init_timer[10] = DFFEAS(S1L102, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[11] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[11] at LCFF_X33_Y19_N23
S1_init_timer[11] = DFFEAS(S1L105, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[12] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[12] at LCFF_X33_Y19_N25
S1_init_timer[12] = DFFEAS(S1L108, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1L17 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~421 at LCCOMB_X32_Y19_N16
S1L17 = S1_init_timer[12] & S1_init_timer[10] & S1_init_timer[11];


--S1_init_timer[14] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[14] at LCFF_X33_Y19_N29
S1_init_timer[14] = DFFEAS(S1L114, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[0] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[0] at LCFF_X33_Y19_N1
S1_init_timer[0] = DFFEAS(S1L72, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[1] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[1] at LCFF_X33_Y19_N3
S1_init_timer[1] = DFFEAS(S1L75, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[15] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[15] at LCFF_X33_Y19_N31
S1_init_timer[15] = DFFEAS(S1L117, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1L11 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~91 at LCCOMB_X32_Y19_N10
S1L11 = !S1_init_timer[15] & !S1_init_timer[1] & !S1_init_timer[0] & S1_init_timer[14];


--S1_init_timer[13] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[13] at LCFF_X33_Y19_N27
S1_init_timer[13] = DFFEAS(S1L111, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1L12 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~92 at LCCOMB_X32_Y19_N18
S1L12 = S1L17 & !S1_init_timer[13] & S1L11;


--S1_init_timer[9] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[9] at LCFF_X33_Y19_N19
S1_init_timer[9] = DFFEAS(S1L99, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[3] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[3] at LCFF_X33_Y19_N7
S1_init_timer[3] = DFFEAS(S1L81, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[6] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[6] at LCFF_X33_Y19_N13
S1_init_timer[6] = DFFEAS(S1L90, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[2] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[2] at LCFF_X33_Y19_N5
S1_init_timer[2] = DFFEAS(S1L78, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[4] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[4] at LCFF_X33_Y19_N9
S1_init_timer[4] = DFFEAS(S1L84, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1L66 is Sdram_Control_4Port:u6|control_interface:control1|always3~649 at LCCOMB_X33_Y20_N10
S1L66 = S1_init_timer[3] & (S1_init_timer[6] & !S1_init_timer[4] & S1_init_timer[2] # !S1_init_timer[6] & S1_init_timer[4] & !S1_init_timer[2]) # !S1_init_timer[3] & (S1_init_timer[6] $ S1_init_timer[4] $ S1_init_timer[2]);


--S1_init_timer[7] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[7] at LCFF_X33_Y19_N15
S1_init_timer[7] = DFFEAS(S1L93, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[8] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[8] at LCFF_X33_Y19_N17
S1_init_timer[8] = DFFEAS(S1L96, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1_init_timer[5] is Sdram_Control_4Port:u6|control_interface:control1|init_timer[5] at LCFF_X33_Y19_N11
S1_init_timer[5] = DFFEAS(S1L87, GLOBAL(KB1L2),  ,  , S1L23,  ,  ,  ,  );


--S1L67 is Sdram_Control_4Port:u6|control_interface:control1|always3~650 at LCCOMB_X33_Y20_N2
S1L67 = S1_init_timer[6] & S1_init_timer[3] & (S1_init_timer[2] # !S1_init_timer[4]) # !S1_init_timer[6] & !S1_init_timer[3] & S1_init_timer[4] & !S1_init_timer[2];


--S1L68 is Sdram_Control_4Port:u6|control_interface:control1|always3~651 at LCCOMB_X33_Y20_N0
S1L68 = S1_init_timer[7] & S1_init_timer[5] & S1_init_timer[8] & S1L67 # !S1_init_timer[7] & !S1_init_timer[8] & (S1_init_timer[5] $ S1L67);


--S1L69 is Sdram_Control_4Port:u6|control_interface:control1|always3~652 at LCCOMB_X33_Y20_N16
S1L69 = S1L68 & (S1L66 & !S1_init_timer[7] & S1_init_timer[9] # !S1L66 & S1_init_timer[7] & !S1_init_timer[9]);


--S1L25 is Sdram_Control_4Port:u6|control_interface:control1|PRECHARGE~49 at LCCOMB_X32_Y20_N16
S1L25 = S1_init_timer[7] & S1_init_timer[6] & S1_init_timer[8];


--S1L18 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~422 at LCCOMB_X32_Y19_N2
S1L18 = !S1L25 & !S1_init_timer[9] # !S1L17;


--S1L19 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~423 at LCCOMB_X32_Y19_N20
S1L19 = !S1_init_timer[15] & (!S1_init_timer[13] & S1L18 # !S1_init_timer[14]);


--S1L13 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~93 at LCCOMB_X32_Y19_N24
S1L13 = !S1_init_timer[5] & !S1_init_timer[4] & !S1_init_timer[6];


--S1L14 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~94 at LCCOMB_X32_Y19_N30
S1L14 = !S1_init_timer[2] & S1_init_timer[7] & S1_init_timer[9];


--S1L15 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~95 at LCCOMB_X32_Y19_N26
S1L15 = S1L13 & S1L14 & !S1_init_timer[8] & S1_init_timer[3];


--S1L16 is Sdram_Control_4Port:u6|control_interface:control1|LOAD_MODE~96 at LCCOMB_X32_Y19_N28
S1L16 = !S1L69 & S1L15 & !S1L19 & S1L12;


--R1L57 is Sdram_Control_4Port:u6|command:command1|always3~4 at LCCOMB_X19_Y10_N8
R1L57 = R1_do_reada # R1_do_writea # R1_do_refresh # !R1L110;


--R1_command_delay[0] is Sdram_Control_4Port:u6|command:command1|command_delay[0] at LCFF_X20_Y10_N23
R1_command_delay[0] = DFFEAS(R1L68, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L77 is Sdram_Control_4Port:u6|command:command1|command_done~132 at LCCOMB_X20_Y10_N14
R1L77 = !S1_INIT_REQ & (R1L57 # R1_command_delay[0]);


--G1_rWR1_ADDR[8] is Sdram_Control_4Port:u6|rWR1_ADDR[8] at LCFF_X19_Y13_N3
G1_rWR1_ADDR[8] = DFFEAS(G1L385, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1L186 is Sdram_Control_4Port:u6|mADDR[16]~361 at LCCOMB_X20_Y15_N24
G1L186 = BB1L17 # BB6L17 & BB3L17;


--G1_rRD2_ADDR[8] is Sdram_Control_4Port:u6|rRD2_ADDR[8] at LCFF_X19_Y15_N3
G1_rRD2_ADDR[8] = DFFEAS(G1L335, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1L275 is Sdram_Control_4Port:u6|mRD~738 at LCCOMB_X20_Y13_N22
G1L275 = !BB1L17 & BB3L17;


--G1_rWR2_ADDR[8] is Sdram_Control_4Port:u6|rWR2_ADDR[8] at LCFF_X18_Y13_N13
G1_rWR2_ADDR[8] = DFFEAS(G1L450, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L193 is Sdram_Control_4Port:u6|mADDR~362 at LCCOMB_X20_Y13_N12
G1L193 = G1L186 & (G1L275) # !G1L186 & (G1L275 & (G1_rRD2_ADDR[8]) # !G1L275 & G1_rWR2_ADDR[8]);


--G1_rRD1_ADDR[8] is Sdram_Control_4Port:u6|rRD1_ADDR[8] at LCFF_X21_Y14_N3
G1_rRD1_ADDR[8] = DFFEAS(G1L283, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L194 is Sdram_Control_4Port:u6|mADDR~363 at LCCOMB_X20_Y12_N26
G1L194 = G1L186 & (G1L193 & G1_rRD1_ADDR[8] # !G1L193 & (G1_rWR1_ADDR[8])) # !G1L186 & G1L193;


--G1_CMD[1] is Sdram_Control_4Port:u6|CMD[1] at LCFF_X19_Y11_N13
G1_CMD[1] = DFFEAS(G1L112, GLOBAL(KB1L2),  ,  , G1L10,  ,  ,  ,  );


--G1_CMD[0] is Sdram_Control_4Port:u6|CMD[0] at LCFF_X19_Y11_N19
G1_CMD[0] = DFFEAS(G1L113, GLOBAL(KB1L2),  ,  , G1L10,  ,  ,  ,  );


--S1L2 is Sdram_Control_4Port:u6|control_interface:control1|Equal~875 at LCCOMB_X19_Y11_N30
S1L2 = !G1_CMD[0] & G1_CMD[1];


--R1_rp_shift[0] is Sdram_Control_4Port:u6|command:command1|rp_shift[0] at LCFF_X20_Y10_N11
R1_rp_shift[0] = DFFEAS(R1L104, GLOBAL(KB1L2),  ,  , R1L100,  ,  ,  ,  );


--R1L96 is Sdram_Control_4Port:u6|command:command1|rp_done~76 at LCCOMB_X20_Y10_N20
R1L96 = !S1_INIT_REQ & (R1_rp_shift[0] # R1_command_done & !R1_command_delay[0]);


--R1_ex_read is Sdram_Control_4Port:u6|command:command1|ex_read at LCFF_X20_Y10_N1
R1_ex_read = DFFEAS(R1L89, GLOBAL(KB1L2),  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1_ex_write is Sdram_Control_4Port:u6|command:command1|ex_write at LCFF_X20_Y10_N17
R1_ex_write = DFFEAS(R1L91, GLOBAL(KB1L2),  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1L99 is Sdram_Control_4Port:u6|command:command1|rp_shift[0]~804 at LCCOMB_X20_Y10_N12
R1L99 = R1_ex_write & (R1_command_delay[0] # !R1_command_done) # !R1_ex_write & R1_ex_read & (R1_command_delay[0] # !R1_command_done);


--R1L100 is Sdram_Control_4Port:u6|command:command1|rp_shift[0]~805 at LCCOMB_X20_Y10_N4
R1L100 = S1_INIT_REQ # G1_PM_STOP # !R1L99;


--S1_timer[0] is Sdram_Control_4Port:u6|control_interface:control1|timer[0] at LCFF_X21_Y12_N1
S1_timer[0] = DFFEAS(S1L121, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[1] is Sdram_Control_4Port:u6|control_interface:control1|timer[1] at LCFF_X21_Y12_N3
S1_timer[1] = DFFEAS(S1L124, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[2] is Sdram_Control_4Port:u6|control_interface:control1|timer[2] at LCFF_X21_Y12_N5
S1_timer[2] = DFFEAS(S1L127, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[3] is Sdram_Control_4Port:u6|control_interface:control1|timer[3] at LCFF_X21_Y12_N7
S1_timer[3] = DFFEAS(S1L130, GLOBAL(KB1L2),  ,  ,  , R1L20,  ,  , S1L33);


--S1L3 is Sdram_Control_4Port:u6|control_interface:control1|Equal~876 at LCCOMB_X22_Y12_N12
S1L3 = !S1_timer[0] & !S1_timer[2] & !S1_timer[3] & !S1_timer[1];


--S1_timer[4] is Sdram_Control_4Port:u6|control_interface:control1|timer[4] at LCFF_X21_Y12_N9
S1_timer[4] = DFFEAS(S1L133, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[5] is Sdram_Control_4Port:u6|control_interface:control1|timer[5] at LCFF_X21_Y12_N11
S1_timer[5] = DFFEAS(S1L136, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[6] is Sdram_Control_4Port:u6|control_interface:control1|timer[6] at LCFF_X21_Y12_N13
S1_timer[6] = DFFEAS(S1L139, GLOBAL(KB1L2),  ,  ,  , R1L20,  ,  , S1L33);


--S1_timer[7] is Sdram_Control_4Port:u6|control_interface:control1|timer[7] at LCFF_X21_Y12_N15
S1_timer[7] = DFFEAS(S1L142, GLOBAL(KB1L2),  ,  ,  , R1L20,  ,  , S1L33);


--S1L4 is Sdram_Control_4Port:u6|control_interface:control1|Equal~877 at LCCOMB_X22_Y12_N10
S1L4 = !S1_timer[7] & !S1_timer[4] & !S1_timer[6] & !S1_timer[5];


--S1_timer[8] is Sdram_Control_4Port:u6|control_interface:control1|timer[8] at LCFF_X21_Y12_N17
S1_timer[8] = DFFEAS(S1L145, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[9] is Sdram_Control_4Port:u6|control_interface:control1|timer[9] at LCFF_X21_Y12_N19
S1_timer[9] = DFFEAS(S1L148, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[10] is Sdram_Control_4Port:u6|control_interface:control1|timer[10] at LCFF_X21_Y12_N21
S1_timer[10] = DFFEAS(S1L151, GLOBAL(KB1L2),  ,  ,  , VCC,  ,  , S1L33);


--S1_timer[11] is Sdram_Control_4Port:u6|control_interface:control1|timer[11] at LCFF_X21_Y12_N23
S1_timer[11] = DFFEAS(S1L154, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1L5 is Sdram_Control_4Port:u6|control_interface:control1|Equal~878 at LCCOMB_X22_Y12_N2
S1L5 = !S1_timer[11] & !S1_timer[8] & !S1_timer[10] & !S1_timer[9];


--S1_timer[12] is Sdram_Control_4Port:u6|control_interface:control1|timer[12] at LCFF_X21_Y12_N25
S1_timer[12] = DFFEAS(S1L157, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[13] is Sdram_Control_4Port:u6|control_interface:control1|timer[13] at LCFF_X21_Y12_N27
S1_timer[13] = DFFEAS(S1L160, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[14] is Sdram_Control_4Port:u6|control_interface:control1|timer[14] at LCFF_X21_Y12_N29
S1_timer[14] = DFFEAS(S1L163, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1_timer[15] is Sdram_Control_4Port:u6|control_interface:control1|timer[15] at LCFF_X21_Y12_N31
S1_timer[15] = DFFEAS(S1L166, GLOBAL(KB1L2),  ,  ,  , ~GND,  ,  , S1L33);


--S1L6 is Sdram_Control_4Port:u6|control_interface:control1|Equal~879 at LCCOMB_X22_Y12_N16
S1L6 = !S1_timer[14] & !S1_timer[12] & !S1_timer[15] & !S1_timer[13];


--S1L7 is Sdram_Control_4Port:u6|control_interface:control1|Equal~880 at LCCOMB_X22_Y12_N26
S1L7 = S1L4 & S1L5 & S1L6 & S1L3;


--R1_REF_ACK is Sdram_Control_4Port:u6|command:command1|REF_ACK at LCFF_X20_Y11_N11
R1_REF_ACK = DFFEAS(R1L19, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--S1L32 is Sdram_Control_4Port:u6|control_interface:control1|REF_REQ~22 at LCCOMB_X20_Y11_N22
S1L32 = S1L7 # !R1_REF_ACK & S1_REF_REQ & !S1_INIT_REQ;


--S1L8 is Sdram_Control_4Port:u6|control_interface:control1|Equal~881 at LCCOMB_X19_Y11_N26
S1L8 = G1_CMD[0] & !G1_CMD[1];


--G1L31 is Sdram_Control_4Port:u6|Equal~1128 at LCCOMB_X18_Y11_N18
G1L31 = G1_ST[1] & G1L23 & !G1_ST[0];


--G1L278 is Sdram_Control_4Port:u6|mWR_DONE~110 at LCCOMB_X18_Y11_N28
G1L278 = !G1_ST[0] & !G1L31 & G1_ST[2] & G1L20;


--G1L279 is Sdram_Control_4Port:u6|mWR_DONE~111 at LCCOMB_X18_Y11_N10
G1L279 = G1_Write & (G1L278 # G1_mWR_DONE);


--R1L9 is Sdram_Control_4Port:u6|command:command1|CM_ACK~102 at LCCOMB_X20_Y11_N28
R1L9 = R1_do_refresh & (S1_REF_REQ & (R1_CM_ACK) # !S1_REF_REQ & R1L57) # !R1_do_refresh & R1L57;


--G1_rRD2_ADDR[9] is Sdram_Control_4Port:u6|rRD2_ADDR[9] at LCFF_X19_Y15_N5
G1_rRD2_ADDR[9] = DFFEAS(G1L342, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR1_ADDR[9] is Sdram_Control_4Port:u6|rWR1_ADDR[9] at LCFF_X19_Y13_N5
G1_rWR1_ADDR[9] = DFFEAS(G1L392, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rWR2_ADDR[9] is Sdram_Control_4Port:u6|rWR2_ADDR[9] at LCFF_X18_Y13_N5
G1_rWR2_ADDR[9] = DFFEAS(G1L451, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L195 is Sdram_Control_4Port:u6|mADDR~364 at LCCOMB_X20_Y13_N0
G1L195 = G1L275 & (G1L186) # !G1L275 & (G1L186 & G1_rWR1_ADDR[9] # !G1L186 & (G1_rWR2_ADDR[9]));


--G1_rRD1_ADDR[9] is Sdram_Control_4Port:u6|rRD1_ADDR[9] at LCFF_X21_Y14_N5
G1_rRD1_ADDR[9] = DFFEAS(G1L286, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L196 is Sdram_Control_4Port:u6|mADDR~365 at LCCOMB_X20_Y14_N18
G1L196 = G1L275 & (G1L195 & G1_rRD1_ADDR[9] # !G1L195 & (G1_rRD2_ADDR[9])) # !G1L275 & (G1L195);


--G1_rWR1_ADDR[10] is Sdram_Control_4Port:u6|rWR1_ADDR[10] at LCFF_X19_Y13_N7
G1_rWR1_ADDR[10] = DFFEAS(G1L395, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rRD2_ADDR[10] is Sdram_Control_4Port:u6|rRD2_ADDR[10] at LCFF_X19_Y15_N7
G1_rRD2_ADDR[10] = DFFEAS(G1L345, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR2_ADDR[10] is Sdram_Control_4Port:u6|rWR2_ADDR[10] at LCFF_X18_Y13_N23
G1_rWR2_ADDR[10] = DFFEAS(G1L452, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L197 is Sdram_Control_4Port:u6|mADDR~366 at LCCOMB_X20_Y14_N10
G1L197 = G1L275 & (G1_rRD2_ADDR[10] # G1L186) # !G1L275 & (G1_rWR2_ADDR[10] & !G1L186);


--G1_rRD1_ADDR[10] is Sdram_Control_4Port:u6|rRD1_ADDR[10] at LCFF_X21_Y14_N7
G1_rRD1_ADDR[10] = DFFEAS(G1L289, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L198 is Sdram_Control_4Port:u6|mADDR~367 at LCCOMB_X20_Y14_N20
G1L198 = G1L186 & (G1L197 & (G1_rRD1_ADDR[10]) # !G1L197 & G1_rWR1_ADDR[10]) # !G1L186 & (G1L197);


--G1_rRD2_ADDR[11] is Sdram_Control_4Port:u6|rRD2_ADDR[11] at LCFF_X19_Y15_N9
G1_rRD2_ADDR[11] = DFFEAS(G1L348, GLOBAL(KB1L2),  ,  , G1L341, VCC,  ,  , G1L340);


--G1_rWR1_ADDR[11] is Sdram_Control_4Port:u6|rWR1_ADDR[11] at LCFF_X19_Y13_N9
G1_rWR1_ADDR[11] = DFFEAS(G1L398, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rWR2_ADDR[11] is Sdram_Control_4Port:u6|rWR2_ADDR[11] at LCFF_X18_Y13_N1
G1_rWR2_ADDR[11] = DFFEAS(G1L453, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L199 is Sdram_Control_4Port:u6|mADDR~368 at LCCOMB_X20_Y14_N6
G1L199 = G1L186 & (G1L275 # G1_rWR1_ADDR[11]) # !G1L186 & G1_rWR2_ADDR[11] & !G1L275;


--G1_rRD1_ADDR[11] is Sdram_Control_4Port:u6|rRD1_ADDR[11] at LCFF_X21_Y14_N9
G1_rRD1_ADDR[11] = DFFEAS(G1L292, GLOBAL(KB1L2),  ,  , G1L327, VCC,  ,  , G1L326);


--G1L200 is Sdram_Control_4Port:u6|mADDR~369 at LCCOMB_X20_Y14_N2
G1L200 = G1L275 & (G1L199 & (G1_rRD1_ADDR[11]) # !G1L199 & G1_rRD2_ADDR[11]) # !G1L275 & (G1L199);


--G1_rWR1_ADDR[12] is Sdram_Control_4Port:u6|rWR1_ADDR[12] at LCFF_X19_Y13_N11
G1_rWR1_ADDR[12] = DFFEAS(G1L401, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rRD2_ADDR[12] is Sdram_Control_4Port:u6|rRD2_ADDR[12] at LCFF_X19_Y15_N11
G1_rRD2_ADDR[12] = DFFEAS(G1L351, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR2_ADDR[12] is Sdram_Control_4Port:u6|rWR2_ADDR[12] at LCFF_X18_Y13_N11
G1_rWR2_ADDR[12] = DFFEAS(G1L454, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L201 is Sdram_Control_4Port:u6|mADDR~370 at LCCOMB_X19_Y14_N18
G1L201 = G1L275 & (G1_rRD2_ADDR[12] # G1L186) # !G1L275 & (!G1L186 & G1_rWR2_ADDR[12]);


--G1_rRD1_ADDR[12] is Sdram_Control_4Port:u6|rRD1_ADDR[12] at LCFF_X21_Y14_N11
G1_rRD1_ADDR[12] = DFFEAS(G1L295, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L202 is Sdram_Control_4Port:u6|mADDR~371 at LCCOMB_X19_Y14_N30
G1L202 = G1L201 & (G1_rRD1_ADDR[12] # !G1L186) # !G1L201 & G1_rWR1_ADDR[12] & G1L186;


--G1_rRD2_ADDR[13] is Sdram_Control_4Port:u6|rRD2_ADDR[13] at LCFF_X19_Y15_N13
G1_rRD2_ADDR[13] = DFFEAS(G1L354, GLOBAL(KB1L2),  ,  , G1L341, VCC,  ,  , G1L340);


--G1_rWR1_ADDR[13] is Sdram_Control_4Port:u6|rWR1_ADDR[13] at LCFF_X19_Y13_N13
G1_rWR1_ADDR[13] = DFFEAS(G1L404, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rWR2_ADDR[13] is Sdram_Control_4Port:u6|rWR2_ADDR[13] at LCFF_X18_Y13_N3
G1_rWR2_ADDR[13] = DFFEAS(G1L455, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L203 is Sdram_Control_4Port:u6|mADDR~372 at LCCOMB_X20_Y14_N24
G1L203 = G1L275 & G1L186 # !G1L275 & (G1L186 & (G1_rWR1_ADDR[13]) # !G1L186 & G1_rWR2_ADDR[13]);


--G1_rRD1_ADDR[13] is Sdram_Control_4Port:u6|rRD1_ADDR[13] at LCFF_X21_Y14_N13
G1_rRD1_ADDR[13] = DFFEAS(G1L298, GLOBAL(KB1L2),  ,  , G1L327, VCC,  ,  , G1L326);


--G1L204 is Sdram_Control_4Port:u6|mADDR~373 at LCCOMB_X20_Y14_N28
G1L204 = G1L203 & (G1_rRD1_ADDR[13] # !G1L275) # !G1L203 & (G1L275 & G1_rRD2_ADDR[13]);


--G1_rWR1_ADDR[14] is Sdram_Control_4Port:u6|rWR1_ADDR[14] at LCFF_X19_Y13_N15
G1_rWR1_ADDR[14] = DFFEAS(G1L407, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rRD2_ADDR[14] is Sdram_Control_4Port:u6|rRD2_ADDR[14] at LCFF_X19_Y15_N15
G1_rRD2_ADDR[14] = DFFEAS(G1L357, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR2_ADDR[14] is Sdram_Control_4Port:u6|rWR2_ADDR[14] at LCFF_X18_Y13_N31
G1_rWR2_ADDR[14] = DFFEAS(G1L456, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L205 is Sdram_Control_4Port:u6|mADDR~374 at LCCOMB_X19_Y14_N8
G1L205 = G1L275 & (G1_rRD2_ADDR[14] # G1L186) # !G1L275 & (!G1L186 & G1_rWR2_ADDR[14]);


--G1_rRD1_ADDR[14] is Sdram_Control_4Port:u6|rRD1_ADDR[14] at LCFF_X21_Y14_N15
G1_rRD1_ADDR[14] = DFFEAS(G1L301, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L206 is Sdram_Control_4Port:u6|mADDR~375 at LCCOMB_X20_Y12_N28
G1L206 = G1L205 & (G1_rRD1_ADDR[14] # !G1L186) # !G1L205 & G1_rWR1_ADDR[14] & G1L186;


--G1_rRD2_ADDR[15] is Sdram_Control_4Port:u6|rRD2_ADDR[15] at LCFF_X19_Y15_N17
G1_rRD2_ADDR[15] = DFFEAS(G1L360, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR1_ADDR[15] is Sdram_Control_4Port:u6|rWR1_ADDR[15] at LCFF_X19_Y13_N17
G1_rWR1_ADDR[15] = DFFEAS(G1L410, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rWR2_ADDR[15] is Sdram_Control_4Port:u6|rWR2_ADDR[15] at LCFF_X18_Y13_N29
G1_rWR2_ADDR[15] = DFFEAS(G1L457, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L207 is Sdram_Control_4Port:u6|mADDR~376 at LCCOMB_X19_Y14_N14
G1L207 = G1L275 & (G1L186) # !G1L275 & (G1L186 & (G1_rWR1_ADDR[15]) # !G1L186 & G1_rWR2_ADDR[15]);


--G1_rRD1_ADDR[15] is Sdram_Control_4Port:u6|rRD1_ADDR[15] at LCFF_X21_Y14_N17
G1_rRD1_ADDR[15] = DFFEAS(G1L304, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L208 is Sdram_Control_4Port:u6|mADDR~377 at LCCOMB_X19_Y14_N26
G1L208 = G1L275 & (G1L207 & (G1_rRD1_ADDR[15]) # !G1L207 & G1_rRD2_ADDR[15]) # !G1L275 & G1L207;


--G1_rWR1_ADDR[16] is Sdram_Control_4Port:u6|rWR1_ADDR[16] at LCFF_X19_Y13_N19
G1_rWR1_ADDR[16] = DFFEAS(G1L413, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rRD2_ADDR[16] is Sdram_Control_4Port:u6|rRD2_ADDR[16] at LCFF_X19_Y15_N19
G1_rRD2_ADDR[16] = DFFEAS(G1L363, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR2_ADDR[16] is Sdram_Control_4Port:u6|rWR2_ADDR[16] at LCFF_X18_Y13_N17
G1_rWR2_ADDR[16] = DFFEAS(G1L458, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L209 is Sdram_Control_4Port:u6|mADDR~378 at LCCOMB_X20_Y12_N0
G1L209 = G1L186 & (G1L275) # !G1L186 & (G1L275 & (G1_rRD2_ADDR[16]) # !G1L275 & G1_rWR2_ADDR[16]);


--G1_rRD1_ADDR[16] is Sdram_Control_4Port:u6|rRD1_ADDR[16] at LCFF_X21_Y14_N19
G1_rRD1_ADDR[16] = DFFEAS(G1L307, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L210 is Sdram_Control_4Port:u6|mADDR~379 at LCCOMB_X20_Y12_N22
G1L210 = G1L209 & (G1_rRD1_ADDR[16] # !G1L186) # !G1L209 & G1_rWR1_ADDR[16] & G1L186;


--G1_rRD2_ADDR[17] is Sdram_Control_4Port:u6|rRD2_ADDR[17] at LCFF_X19_Y15_N21
G1_rRD2_ADDR[17] = DFFEAS(G1L366, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR1_ADDR[17] is Sdram_Control_4Port:u6|rWR1_ADDR[17] at LCFF_X19_Y13_N21
G1_rWR1_ADDR[17] = DFFEAS(G1L416, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rWR2_ADDR[17] is Sdram_Control_4Port:u6|rWR2_ADDR[17] at LCFF_X18_Y13_N7
G1_rWR2_ADDR[17] = DFFEAS(G1L459, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L211 is Sdram_Control_4Port:u6|mADDR~380 at LCCOMB_X19_Y14_N10
G1L211 = G1L275 & (G1L186) # !G1L275 & (G1L186 & G1_rWR1_ADDR[17] # !G1L186 & (G1_rWR2_ADDR[17]));


--G1_rRD1_ADDR[17] is Sdram_Control_4Port:u6|rRD1_ADDR[17] at LCFF_X21_Y14_N21
G1_rRD1_ADDR[17] = DFFEAS(G1L310, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L212 is Sdram_Control_4Port:u6|mADDR~381 at LCCOMB_X19_Y14_N6
G1L212 = G1L211 & (G1_rRD1_ADDR[17] # !G1L275) # !G1L211 & G1_rRD2_ADDR[17] & G1L275;


--G1_rWR1_ADDR[18] is Sdram_Control_4Port:u6|rWR1_ADDR[18] at LCFF_X19_Y13_N23
G1_rWR1_ADDR[18] = DFFEAS(G1L419, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rRD2_ADDR[18] is Sdram_Control_4Port:u6|rRD2_ADDR[18] at LCFF_X19_Y15_N23
G1_rRD2_ADDR[18] = DFFEAS(G1L369, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR2_ADDR[18] is Sdram_Control_4Port:u6|rWR2_ADDR[18] at LCFF_X18_Y13_N19
G1_rWR2_ADDR[18] = DFFEAS(G1L460, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L213 is Sdram_Control_4Port:u6|mADDR~382 at LCCOMB_X20_Y15_N2
G1L213 = G1L186 & (G1L275) # !G1L186 & (G1L275 & G1_rRD2_ADDR[18] # !G1L275 & (G1_rWR2_ADDR[18]));


--G1_rRD1_ADDR[18] is Sdram_Control_4Port:u6|rRD1_ADDR[18] at LCFF_X21_Y14_N23
G1_rRD1_ADDR[18] = DFFEAS(G1L313, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L214 is Sdram_Control_4Port:u6|mADDR~383 at LCCOMB_X20_Y15_N30
G1L214 = G1L186 & (G1L213 & (G1_rRD1_ADDR[18]) # !G1L213 & G1_rWR1_ADDR[18]) # !G1L186 & G1L213;


--S1L26 is Sdram_Control_4Port:u6|control_interface:control1|PRECHARGE~50 at LCCOMB_X32_Y19_N6
S1L26 = S1_init_timer[2] & !S1_init_timer[5] & S1_init_timer[4] & !S1_init_timer[3];


--S1L27 is Sdram_Control_4Port:u6|control_interface:control1|PRECHARGE~51 at LCCOMB_X32_Y19_N0
S1L27 = S1L26 & !S1_init_timer[9] & S1L25 & S1L12;


--R1_rw_shift[1] is Sdram_Control_4Port:u6|command:command1|rw_shift[1] at LCFF_X19_Y12_N17
R1_rw_shift[1] = DFFEAS(R1L58, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L115 is Sdram_Control_4Port:u6|command:command1|rw_shift~15 at LCCOMB_X19_Y12_N6
R1L115 = !R1_do_reada & R1_rw_shift[1] & !R1_do_writea;


--G1_rRD2_ADDR[19] is Sdram_Control_4Port:u6|rRD2_ADDR[19] at LCFF_X19_Y15_N25
G1_rRD2_ADDR[19] = DFFEAS(G1L372, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR1_ADDR[19] is Sdram_Control_4Port:u6|rWR1_ADDR[19] at LCFF_X19_Y13_N25
G1_rWR1_ADDR[19] = DFFEAS(G1L422, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rWR2_ADDR[19] is Sdram_Control_4Port:u6|rWR2_ADDR[19] at LCFF_X18_Y13_N27
G1_rWR2_ADDR[19] = DFFEAS(G1L461, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L215 is Sdram_Control_4Port:u6|mADDR~384 at LCCOMB_X20_Y15_N0
G1L215 = G1L186 & (G1_rWR1_ADDR[19] # G1L275) # !G1L186 & (G1_rWR2_ADDR[19] & !G1L275);


--G1_rRD1_ADDR[19] is Sdram_Control_4Port:u6|rRD1_ADDR[19] at LCFF_X21_Y14_N25
G1_rRD1_ADDR[19] = DFFEAS(G1L316, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L216 is Sdram_Control_4Port:u6|mADDR~385 at LCCOMB_X20_Y15_N18
G1L216 = G1L275 & (G1L215 & G1_rRD1_ADDR[19] # !G1L215 & (G1_rRD2_ADDR[19])) # !G1L275 & G1L215;


--S1L30 is Sdram_Control_4Port:u6|control_interface:control1|REFRESH~81 at LCCOMB_X32_Y19_N22
S1L30 = S1L69 & !S1L19 & S1L12;


--G1_rWR1_ADDR[22] is Sdram_Control_4Port:u6|rWR1_ADDR[22] at LCFF_X19_Y13_N31
G1_rWR1_ADDR[22] = DFFEAS(G1L431, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rRD2_ADDR[22] is Sdram_Control_4Port:u6|rRD2_ADDR[22] at LCFF_X19_Y15_N31
G1_rRD2_ADDR[22] = DFFEAS(G1L381, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR2_ADDR[22] is Sdram_Control_4Port:u6|rWR2_ADDR[22] at LCFF_X18_Y13_N9
G1_rWR2_ADDR[22] = DFFEAS(G1L462, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L217 is Sdram_Control_4Port:u6|mADDR~386 at LCCOMB_X20_Y15_N4
G1L217 = G1L186 & (G1L275) # !G1L186 & (G1L275 & (G1_rRD2_ADDR[22]) # !G1L275 & G1_rWR2_ADDR[22]);


--G1_rRD1_ADDR[22] is Sdram_Control_4Port:u6|rRD1_ADDR[22] at LCFF_X21_Y14_N31
G1_rRD1_ADDR[22] = DFFEAS(G1L331, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L218 is Sdram_Control_4Port:u6|mADDR~387 at LCCOMB_X20_Y15_N28
G1L218 = G1L186 & (G1L217 & G1_rRD1_ADDR[22] # !G1L217 & (G1_rWR1_ADDR[22])) # !G1L186 & G1L217;


--G1_rRD2_ADDR[20] is Sdram_Control_4Port:u6|rRD2_ADDR[20] at LCFF_X19_Y15_N27
G1_rRD2_ADDR[20] = DFFEAS(G1L375, GLOBAL(KB1L2),  ,  , G1L341, VCC,  ,  , G1L340);


--G1_rWR1_ADDR[20] is Sdram_Control_4Port:u6|rWR1_ADDR[20] at LCFF_X19_Y13_N27
G1_rWR1_ADDR[20] = DFFEAS(G1L425, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rWR2_ADDR[20] is Sdram_Control_4Port:u6|rWR2_ADDR[20] at LCFF_X18_Y14_N31
G1_rWR2_ADDR[20] = DFFEAS(G1L464, GLOBAL(KB1L2),  ,  ,  , VCC,  ,  , !C1_oRST_0);


--G1L219 is Sdram_Control_4Port:u6|mADDR~388 at LCCOMB_X20_Y12_N4
G1L219 = G1L275 & (G1L186) # !G1L275 & (G1L186 & G1_rWR1_ADDR[20] # !G1L186 & (G1_rWR2_ADDR[20]));


--G1_rRD1_ADDR[20] is Sdram_Control_4Port:u6|rRD1_ADDR[20] at LCFF_X21_Y14_N27
G1_rRD1_ADDR[20] = DFFEAS(G1L319, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L220 is Sdram_Control_4Port:u6|mADDR~389 at LCCOMB_X20_Y12_N2
G1L220 = G1L219 & (G1_rRD1_ADDR[20] # !G1L275) # !G1L219 & (G1L275 & G1_rRD2_ADDR[20]);


--G1_rWR1_ADDR[21] is Sdram_Control_4Port:u6|rWR1_ADDR[21] at LCFF_X19_Y13_N29
G1_rWR1_ADDR[21] = DFFEAS(G1L428, GLOBAL(KB1L2),  ,  , G1L390,  ,  , G1L389,  );


--G1_rRD2_ADDR[21] is Sdram_Control_4Port:u6|rRD2_ADDR[21] at LCFF_X19_Y15_N29
G1_rRD2_ADDR[21] = DFFEAS(G1L378, GLOBAL(KB1L2),  ,  , G1L341, ~GND,  ,  , G1L340);


--G1_rWR2_ADDR[21] is Sdram_Control_4Port:u6|rWR2_ADDR[21] at LCFF_X18_Y13_N25
G1_rWR2_ADDR[21] = DFFEAS(G1L465, GLOBAL(KB1L2),  ,  , G1L435,  ,  ,  ,  );


--G1L221 is Sdram_Control_4Port:u6|mADDR~390 at LCCOMB_X20_Y13_N28
G1L221 = G1L186 & (G1L275) # !G1L186 & (G1L275 & (G1_rRD2_ADDR[21]) # !G1L275 & G1_rWR2_ADDR[21]);


--G1_rRD1_ADDR[21] is Sdram_Control_4Port:u6|rRD1_ADDR[21] at LCFF_X21_Y14_N29
G1_rRD1_ADDR[21] = DFFEAS(G1L328, GLOBAL(KB1L2),  ,  , G1L327, ~GND,  ,  , G1L326);


--G1L222 is Sdram_Control_4Port:u6|mADDR~391 at LCCOMB_X20_Y15_N22
G1L222 = G1L221 & (G1_rRD1_ADDR[21] # !G1L186) # !G1L221 & G1_rWR1_ADDR[21] & G1L186;


--X1_delayed_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[8] at LCFF_X15_Y12_N3
X1_delayed_wrptr_g[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X1_wrptr_g[8],  ,  , VCC);


--X1_delayed_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7] at LCFF_X15_Y12_N19
X1_delayed_wrptr_g[7] = DFFEAS(X1L16, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6] at LCFF_X14_Y14_N17
X1_delayed_wrptr_g[6] = DFFEAS(X1L14, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5] at LCFF_X15_Y12_N23
X1_delayed_wrptr_g[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X1_wrptr_g[5],  ,  , VCC);


--X1_delayed_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[4] at LCFF_X25_Y13_N3
X1_delayed_wrptr_g[4] = DFFEAS(X1L11, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3] at LCFF_X14_Y13_N3
X1_delayed_wrptr_g[3] = DFFEAS(X1L9, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[2] at LCFF_X14_Y13_N13
X1_delayed_wrptr_g[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X1_wrptr_g[2],  ,  , VCC);


--X1_delayed_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[1] at LCFF_X15_Y14_N1
X1_delayed_wrptr_g[1] = DFFEAS(X1L6, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X1_delayed_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0] at LCFF_X14_Y13_N27
X1_delayed_wrptr_g[0] = DFFEAS(X1L4, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[8] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[8] at LCFF_X24_Y14_N17
X2_delayed_wrptr_g[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X2_wrptr_g[8],  ,  , VCC);


--X2_delayed_wrptr_g[7] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7] at LCFF_X24_Y14_N13
X2_delayed_wrptr_g[7] = DFFEAS(X2L17, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[6] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6] at LCFF_X24_Y14_N29
X2_delayed_wrptr_g[6] = DFFEAS(X2L15, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[5] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5] at LCFF_X24_Y14_N27
X2_delayed_wrptr_g[5] = DFFEAS(X2L13, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[4] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[4] at LCFF_X23_Y14_N19
X2_delayed_wrptr_g[4] = DFFEAS(X2L11, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[3] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3] at LCFF_X23_Y14_N23
X2_delayed_wrptr_g[3] = DFFEAS(X2L9, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[2] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[2] at LCFF_X23_Y14_N5
X2_delayed_wrptr_g[2] = DFFEAS(X2L7, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--X2_delayed_wrptr_g[1] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[1] at LCFF_X25_Y12_N7
X2_delayed_wrptr_g[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L78),  ,  , X2_wrptr_g[1],  ,  , VCC);


--X2_delayed_wrptr_g[0] is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0] at LCFF_X24_Y12_N7
X2_delayed_wrptr_g[0] = DFFEAS(X2L4, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--G1L32 is Sdram_Control_4Port:u6|Equal~1129 at LCCOMB_X18_Y11_N12
G1L32 = !G1_ST[0] & G1L24 & !G1_ST[2] & G1L21;


--G1L34 is Sdram_Control_4Port:u6|IN_REQ~138 at LCCOMB_X18_Y11_N22
G1L34 = G1_Write & (G1L31 # !G1L32 & G1_IN_REQ) # !G1_Write & (G1_IN_REQ);


--X2_rdaclr is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdaclr at LCFF_X33_Y1_N17
X2_rdaclr = DFFEAS(X2L23, !GLOBAL(KB1L2), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--E1_mDVAL is RAW2RGB:u4|mDVAL at LCFF_X57_Y1_N5
E1_mDVAL = DFFEAS(E1L139, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--EB1_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity_ff at LCFF_X14_Y12_N11
EB1_parity_ff = DFFEAS(EB1_parity, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB1_parity is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity at LCCOMB_X14_Y12_N10
EB1_parity = EB1_parity_ff & !X1_valid_wrreq & VCC # !EB1_parity_ff & X1_valid_wrreq;

--EB1L31 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity~COUT at LCCOMB_X14_Y12_N10
EB1L31 = CARRY(!EB1_parity_ff & X1_valid_wrreq);


--EB1_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0 at LCCOMB_X14_Y12_N12
EB1_countera0 = X1_valid_wrreq & (EB1L31 $ (GND # !EB1_counter_ffa[0])) # !X1_valid_wrreq & (EB1_counter_ffa[0] # GND);

--EB1L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0~COUT at LCCOMB_X14_Y12_N12
EB1L12 = CARRY(!EB1L31 # !X1_valid_wrreq);


--EB1_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1 at LCCOMB_X14_Y12_N14
EB1_countera1 = EB1L12 & (EB1_power_modified_counter_values[1] & VCC) # !EB1L12 & (EB1_counter_ffa[0] $ (!EB1_power_modified_counter_values[1] & VCC));

--EB1L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1~COUT at LCCOMB_X14_Y12_N14
EB1L14 = CARRY(EB1_counter_ffa[0] & !EB1L12);


--EB1_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2 at LCCOMB_X14_Y12_N16
EB1_countera2 = EB1L14 & (EB1_power_modified_counter_values[1] $ (EB1_power_modified_counter_values[2] & VCC)) # !EB1L14 & (EB1_power_modified_counter_values[2] # GND);

--EB1L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2~COUT at LCCOMB_X14_Y12_N16
EB1L16 = CARRY(EB1_power_modified_counter_values[1] # !EB1L14);


--EB1_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3 at LCCOMB_X14_Y12_N18
EB1_countera3 = EB1L16 & (EB1_power_modified_counter_values[3] & VCC) # !EB1L16 & (EB1_power_modified_counter_values[2] $ (EB1_power_modified_counter_values[3] # GND));

--EB1L18 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3~COUT at LCCOMB_X14_Y12_N18
EB1L18 = CARRY(!EB1_power_modified_counter_values[2] & !EB1L16);


--EB1_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4 at LCCOMB_X14_Y12_N20
EB1_countera4 = EB1L18 & (EB1_power_modified_counter_values[3] $ (EB1_power_modified_counter_values[4] & VCC)) # !EB1L18 & (EB1_power_modified_counter_values[4] # GND);

--EB1L20 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4~COUT at LCCOMB_X14_Y12_N20
EB1L20 = CARRY(EB1_power_modified_counter_values[3] # !EB1L18);


--EB1_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5 at LCCOMB_X14_Y12_N22
EB1_countera5 = EB1L20 & (EB1_power_modified_counter_values[5] & VCC) # !EB1L20 & (EB1_power_modified_counter_values[4] $ (EB1_power_modified_counter_values[5] # GND));

--EB1L22 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5~COUT at LCCOMB_X14_Y12_N22
EB1L22 = CARRY(!EB1_power_modified_counter_values[4] & !EB1L20);


--EB1_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6 at LCCOMB_X14_Y12_N24
EB1_countera6 = EB1L22 & (EB1_power_modified_counter_values[5] $ (EB1_power_modified_counter_values[6] & VCC)) # !EB1L22 & (EB1_power_modified_counter_values[6] # GND);

--EB1L24 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6~COUT at LCCOMB_X14_Y12_N24
EB1L24 = CARRY(EB1_power_modified_counter_values[5] # !EB1L22);


--EB1_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7 at LCCOMB_X14_Y12_N26
EB1_countera7 = EB1L24 & (EB1_power_modified_counter_values[7] & VCC) # !EB1L24 & (EB1_power_modified_counter_values[6] $ (EB1_power_modified_counter_values[7] # GND));

--EB1L26 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7~COUT at LCCOMB_X14_Y12_N26
EB1L26 = CARRY(!EB1_power_modified_counter_values[6] & !EB1L24);


--EB1_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera8 at LCCOMB_X14_Y12_N28
EB1_countera8 = EB1L26 $ EB1_power_modified_counter_values[8];


--Z1_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity_ff at LCFF_X15_Y13_N1
Z1_parity_ff = DFFEAS(Z1_parity, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z1_parity is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity at LCCOMB_X15_Y13_N0
Z1_parity = X1_rdcnt_addr_ena & (Z1_parity_ff $ VCC) # !X1_rdcnt_addr_ena & Z1_parity_ff & VCC;

--Z1L31 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity~COUT at LCCOMB_X15_Y13_N0
Z1L31 = CARRY(X1_rdcnt_addr_ena & Z1_parity_ff);


--Z1_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0 at LCCOMB_X15_Y13_N2
Z1_countera0 = X1_rdcnt_addr_ena & (Z1L31 $ (GND # !Z1_power_modified_counter_values[0])) # !X1_rdcnt_addr_ena & (Z1_power_modified_counter_values[0] # GND);

--Z1L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0~COUT at LCCOMB_X15_Y13_N2
Z1L12 = CARRY(!Z1L31 # !X1_rdcnt_addr_ena);


--Z1_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1 at LCCOMB_X15_Y13_N4
Z1_countera1 = Z1L12 & (Z1_power_modified_counter_values[1] & VCC) # !Z1L12 & (Z1_power_modified_counter_values[0] $ (Z1_power_modified_counter_values[1] # GND));

--Z1L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1~COUT at LCCOMB_X15_Y13_N4
Z1L14 = CARRY(!Z1_power_modified_counter_values[0] & !Z1L12);


--Z1_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2 at LCCOMB_X15_Y13_N6
Z1_countera2 = Z1L14 & (Z1_power_modified_counter_values[1] $ (Z1_power_modified_counter_values[2] & VCC)) # !Z1L14 & (Z1_power_modified_counter_values[2] # GND);

--Z1L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2~COUT at LCCOMB_X15_Y13_N6
Z1L16 = CARRY(Z1_power_modified_counter_values[1] # !Z1L14);


--Z1_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3 at LCCOMB_X15_Y13_N8
Z1_countera3 = Z1L16 & (Z1_power_modified_counter_values[3] & VCC) # !Z1L16 & (Z1_power_modified_counter_values[2] $ (Z1_power_modified_counter_values[3] # GND));

--Z1L18 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3~COUT at LCCOMB_X15_Y13_N8
Z1L18 = CARRY(!Z1_power_modified_counter_values[2] & !Z1L16);


--Z1_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4 at LCCOMB_X15_Y13_N10
Z1_countera4 = Z1L18 & (Z1_power_modified_counter_values[3] $ (Z1_power_modified_counter_values[4] & VCC)) # !Z1L18 & (Z1_power_modified_counter_values[4] # GND);

--Z1L20 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4~COUT at LCCOMB_X15_Y13_N10
Z1L20 = CARRY(Z1_power_modified_counter_values[3] # !Z1L18);


--Z1_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5 at LCCOMB_X15_Y13_N12
Z1_countera5 = Z1L20 & (Z1_power_modified_counter_values[5] & VCC) # !Z1L20 & (Z1_power_modified_counter_values[4] $ (Z1_power_modified_counter_values[5] # GND));

--Z1L22 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5~COUT at LCCOMB_X15_Y13_N12
Z1L22 = CARRY(!Z1_power_modified_counter_values[4] & !Z1L20);


--Z1_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6 at LCCOMB_X15_Y13_N14
Z1_countera6 = Z1L22 & (Z1_power_modified_counter_values[5] $ (Z1_power_modified_counter_values[6] & VCC)) # !Z1L22 & (Z1_power_modified_counter_values[6] # GND);

--Z1L24 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6~COUT at LCCOMB_X15_Y13_N14
Z1L24 = CARRY(Z1_power_modified_counter_values[5] # !Z1L22);


--Z1_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7 at LCCOMB_X15_Y13_N16
Z1_countera7 = Z1L24 & Z1_power_modified_counter_values[7] & (VCC) # !Z1L24 & (Z1_power_modified_counter_values[6] $ (Z1_power_modified_counter_values[7] # GND));

--Z1L26 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7~COUT at LCCOMB_X15_Y13_N16
Z1L26 = CARRY(!Z1_power_modified_counter_values[6] & !Z1L24);


--Z1_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera8 at LCCOMB_X15_Y13_N18
Z1_countera8 = Z1_power_modified_counter_values[8] $ Z1L26;


--E1_mCCD_B[0] is RAW2RGB:u4|mCCD_B[0] at LCFF_X22_Y10_N17
E1_mCCD_B[0] = DFFEAS(E1L33, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--J1_Z_Cont[0] is Mirror_Col:u8|Z_Cont[0] at LCFF_X14_Y11_N13
J1_Z_Cont[0] = DFFEAS(J1L4, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[1] is Mirror_Col:u8|Z_Cont[1] at LCFF_X14_Y11_N15
J1_Z_Cont[1] = DFFEAS(J1L8, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[2] is Mirror_Col:u8|Z_Cont[2] at LCFF_X14_Y11_N17
J1_Z_Cont[2] = DFFEAS(J1L12, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[3] is Mirror_Col:u8|Z_Cont[3] at LCFF_X14_Y11_N19
J1_Z_Cont[3] = DFFEAS(J1L16, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[4] is Mirror_Col:u8|Z_Cont[4] at LCFF_X14_Y11_N21
J1_Z_Cont[4] = DFFEAS(J1L20, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[5] is Mirror_Col:u8|Z_Cont[5] at LCFF_X14_Y11_N23
J1_Z_Cont[5] = DFFEAS(J1L24, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[6] is Mirror_Col:u8|Z_Cont[6] at LCFF_X14_Y11_N25
J1_Z_Cont[6] = DFFEAS(J1L28, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[7] is Mirror_Col:u8|Z_Cont[7] at LCFF_X14_Y11_N27
J1_Z_Cont[7] = DFFEAS(J1L32, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[8] is Mirror_Col:u8|Z_Cont[8] at LCFF_X14_Y11_N29
J1_Z_Cont[8] = DFFEAS(J1L35, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  , J1L1,  );


--J1_Z_Cont[9] is Mirror_Col:u8|Z_Cont[9] at LCFF_X14_Y11_N31
J1_Z_Cont[9] = DFFEAS(J1L38, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  , J1L1,  );


--J1L40 is Mirror_Col:u8|add~271 at LCCOMB_X14_Y11_N6
J1L40 = J1_Z_Cont[7] $ J1_Z_Cont[8];


--J1L41 is Mirror_Col:u8|add~272 at LCCOMB_X14_Y11_N10
J1L41 = J1_Z_Cont[9] $ (!J1_Z_Cont[7] & !J1_Z_Cont[8]);


--EB2_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity_ff at LCFF_X27_Y13_N13
EB2_parity_ff = DFFEAS(EB2_parity, GLOBAL(A1L11), GLOBAL(C1L78),  ,  ,  ,  ,  ,  );


--EB2_parity is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity at LCCOMB_X27_Y13_N12
EB2_parity = EB2_parity_ff & !X2_valid_wrreq & VCC # !EB2_parity_ff & X2_valid_wrreq;

--EB2L31 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|parity~COUT at LCCOMB_X27_Y13_N12
EB2L31 = CARRY(!EB2_parity_ff & X2_valid_wrreq);


--EB2_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0 at LCCOMB_X27_Y13_N14
EB2_countera0 = X2_valid_wrreq & (EB2L31 $ (GND # !EB2_counter_ffa[0])) # !X2_valid_wrreq & (EB2_counter_ffa[0] # GND);

--EB2L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera0~COUT at LCCOMB_X27_Y13_N14
EB2L12 = CARRY(!EB2L31 # !X2_valid_wrreq);


--EB2_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1 at LCCOMB_X27_Y13_N16
EB2_countera1 = EB2L12 & EB2_power_modified_counter_values[1] & (VCC) # !EB2L12 & (EB2_counter_ffa[0] $ (!EB2_power_modified_counter_values[1] & VCC));

--EB2L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera1~COUT at LCCOMB_X27_Y13_N16
EB2L14 = CARRY(EB2_counter_ffa[0] & !EB2L12);


--EB2_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2 at LCCOMB_X27_Y13_N18
EB2_countera2 = EB2L14 & (EB2_power_modified_counter_values[1] $ (EB2_power_modified_counter_values[2] & VCC)) # !EB2L14 & (EB2_power_modified_counter_values[2] # GND);

--EB2L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera2~COUT at LCCOMB_X27_Y13_N18
EB2L16 = CARRY(EB2_power_modified_counter_values[1] # !EB2L14);


--EB2_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3 at LCCOMB_X27_Y13_N20
EB2_countera3 = EB2L16 & EB2_power_modified_counter_values[3] & (VCC) # !EB2L16 & (EB2_power_modified_counter_values[2] $ (EB2_power_modified_counter_values[3] # GND));

--EB2L18 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera3~COUT at LCCOMB_X27_Y13_N20
EB2L18 = CARRY(!EB2_power_modified_counter_values[2] & !EB2L16);


--EB2_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4 at LCCOMB_X27_Y13_N22
EB2_countera4 = EB2L18 & (EB2_power_modified_counter_values[3] $ (EB2_power_modified_counter_values[4] & VCC)) # !EB2L18 & (EB2_power_modified_counter_values[4] # GND);

--EB2L20 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera4~COUT at LCCOMB_X27_Y13_N22
EB2L20 = CARRY(EB2_power_modified_counter_values[3] # !EB2L18);


--EB2_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5 at LCCOMB_X27_Y13_N24
EB2_countera5 = EB2L20 & EB2_power_modified_counter_values[5] & (VCC) # !EB2L20 & (EB2_power_modified_counter_values[4] $ (EB2_power_modified_counter_values[5] # GND));

--EB2L22 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera5~COUT at LCCOMB_X27_Y13_N24
EB2L22 = CARRY(!EB2_power_modified_counter_values[4] & !EB2L20);


--EB2_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6 at LCCOMB_X27_Y13_N26
EB2_countera6 = EB2L22 & (EB2_power_modified_counter_values[5] $ (EB2_power_modified_counter_values[6] & VCC)) # !EB2L22 & (EB2_power_modified_counter_values[6] # GND);

--EB2L24 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera6~COUT at LCCOMB_X27_Y13_N26
EB2L24 = CARRY(EB2_power_modified_counter_values[5] # !EB2L22);


--EB2_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7 at LCCOMB_X27_Y13_N28
EB2_countera7 = EB2L24 & EB2_power_modified_counter_values[7] & (VCC) # !EB2L24 & (EB2_power_modified_counter_values[6] $ (EB2_power_modified_counter_values[7] # GND));

--EB2L26 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera7~COUT at LCCOMB_X27_Y13_N28
EB2L26 = CARRY(!EB2_power_modified_counter_values[6] & !EB2L24);


--EB2_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_b17:wrptr_g1p|countera8 at LCCOMB_X27_Y13_N30
EB2_countera8 = EB2L26 $ EB2_power_modified_counter_values[8];


--Z2_parity_ff is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity_ff at LCFF_X25_Y14_N11
Z2_parity_ff = DFFEAS(Z2_parity, GLOBAL(KB1L2), GLOBAL(X2L22),  ,  ,  ,  ,  ,  );


--Z2_parity is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity at LCCOMB_X25_Y14_N10
Z2_parity = Z2_parity_ff & (X2_rdcnt_addr_ena $ VCC) # !Z2_parity_ff & X2_rdcnt_addr_ena & VCC;

--Z2L31 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|parity~COUT at LCCOMB_X25_Y14_N10
Z2L31 = CARRY(Z2_parity_ff & X2_rdcnt_addr_ena);


--Z2_countera0 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0 at LCCOMB_X25_Y14_N12
Z2_countera0 = X2_rdcnt_addr_ena & (Z2L31 $ (GND # !Z2_power_modified_counter_values[0])) # !X2_rdcnt_addr_ena & (Z2_power_modified_counter_values[0] # GND);

--Z2L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera0~COUT at LCCOMB_X25_Y14_N12
Z2L12 = CARRY(!Z2L31 # !X2_rdcnt_addr_ena);


--Z2_countera1 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1 at LCCOMB_X25_Y14_N14
Z2_countera1 = Z2L12 & (Z2_power_modified_counter_values[1] & VCC) # !Z2L12 & (Z2_power_modified_counter_values[0] $ (Z2_power_modified_counter_values[1] # GND));

--Z2L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera1~COUT at LCCOMB_X25_Y14_N14
Z2L14 = CARRY(!Z2_power_modified_counter_values[0] & !Z2L12);


--Z2_countera2 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2 at LCCOMB_X25_Y14_N16
Z2_countera2 = Z2L14 & (Z2_power_modified_counter_values[1] $ (Z2_power_modified_counter_values[2] & VCC)) # !Z2L14 & (Z2_power_modified_counter_values[2] # GND);

--Z2L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera2~COUT at LCCOMB_X25_Y14_N16
Z2L16 = CARRY(Z2_power_modified_counter_values[1] # !Z2L14);


--Z2_countera3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3 at LCCOMB_X25_Y14_N18
Z2_countera3 = Z2L16 & (Z2_power_modified_counter_values[3] & VCC) # !Z2L16 & (Z2_power_modified_counter_values[2] $ (Z2_power_modified_counter_values[3] # GND));

--Z2L18 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera3~COUT at LCCOMB_X25_Y14_N18
Z2L18 = CARRY(!Z2_power_modified_counter_values[2] & !Z2L16);


--Z2_countera4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4 at LCCOMB_X25_Y14_N20
Z2_countera4 = Z2L18 & (Z2_power_modified_counter_values[3] $ (Z2_power_modified_counter_values[4] & VCC)) # !Z2L18 & (Z2_power_modified_counter_values[4] # GND);

--Z2L20 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera4~COUT at LCCOMB_X25_Y14_N20
Z2L20 = CARRY(Z2_power_modified_counter_values[3] # !Z2L18);


--Z2_countera5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5 at LCCOMB_X25_Y14_N22
Z2_countera5 = Z2L20 & (Z2_power_modified_counter_values[5] & VCC) # !Z2L20 & (Z2_power_modified_counter_values[4] $ (Z2_power_modified_counter_values[5] # GND));

--Z2L22 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera5~COUT at LCCOMB_X25_Y14_N22
Z2L22 = CARRY(!Z2_power_modified_counter_values[4] & !Z2L20);


--Z2_countera6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6 at LCCOMB_X25_Y14_N24
Z2_countera6 = Z2L22 & (Z2_power_modified_counter_values[5] $ (Z2_power_modified_counter_values[6] & VCC)) # !Z2L22 & (Z2_power_modified_counter_values[6] # GND);

--Z2L24 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera6~COUT at LCCOMB_X25_Y14_N24
Z2L24 = CARRY(Z2_power_modified_counter_values[5] # !Z2L22);


--Z2_countera7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7 at LCCOMB_X25_Y14_N26
Z2_countera7 = Z2L24 & (Z2_power_modified_counter_values[7] & VCC) # !Z2L24 & (Z2_power_modified_counter_values[6] $ (Z2_power_modified_counter_values[7] # GND));

--Z2L26 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera7~COUT at LCCOMB_X25_Y14_N26
Z2L26 = CARRY(!Z2_power_modified_counter_values[6] & !Z2L24);


--Z2_countera8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|countera8 at LCCOMB_X25_Y14_N28
Z2_countera8 = Z2L26 $ Z2_power_modified_counter_values[8];


--E1_mCCD_R[0] is RAW2RGB:u4|mCCD_R[0] at LCFF_X22_Y10_N23
E1_mCCD_R[0] = DFFEAS(E1L97, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_B[1] is RAW2RGB:u4|mCCD_B[1] at LCFF_X23_Y11_N27
E1_mCCD_B[1] = DFFEAS(E1L35, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_R[1] is RAW2RGB:u4|mCCD_R[1] at LCFF_X23_Y11_N29
E1_mCCD_R[1] = DFFEAS(E1L99, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_B[2] is RAW2RGB:u4|mCCD_B[2] at LCFF_X22_Y10_N31
E1_mCCD_B[2] = DFFEAS(E1L37, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_R[2] is RAW2RGB:u4|mCCD_R[2] at LCFF_X22_Y10_N1
E1_mCCD_R[2] = DFFEAS(E1L101, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_B[3] is RAW2RGB:u4|mCCD_B[3] at LCFF_X22_Y10_N9
E1_mCCD_B[3] = DFFEAS(E1L39, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_R[3] is RAW2RGB:u4|mCCD_R[3] at LCFF_X22_Y10_N13
E1_mCCD_R[3] = DFFEAS(E1L103, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_B[4] is RAW2RGB:u4|mCCD_B[4] at LCFF_X23_Y9_N9
E1_mCCD_B[4] = DFFEAS(E1L41, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_R[4] is RAW2RGB:u4|mCCD_R[4] at LCFF_X23_Y9_N29
E1_mCCD_R[4] = DFFEAS(E1L105, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_B[5] is RAW2RGB:u4|mCCD_B[5] at LCFF_X23_Y11_N3
E1_mCCD_B[5] = DFFEAS(E1L43, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_R[5] is RAW2RGB:u4|mCCD_R[5] at LCFF_X23_Y11_N9
E1_mCCD_R[5] = DFFEAS(E1L107, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_B[6] is RAW2RGB:u4|mCCD_B[6] at LCFF_X23_Y11_N19
E1_mCCD_B[6] = DFFEAS(E1L45, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_R[6] is RAW2RGB:u4|mCCD_R[6] at LCFF_X23_Y11_N1
E1_mCCD_R[6] = DFFEAS(E1L109, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_B[7] is RAW2RGB:u4|mCCD_B[7] at LCFF_X22_Y11_N25
E1_mCCD_B[7] = DFFEAS(E1L47, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_R[7] is RAW2RGB:u4|mCCD_R[7] at LCFF_X22_Y11_N29
E1_mCCD_R[7] = DFFEAS(E1L111, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_B[8] is RAW2RGB:u4|mCCD_B[8] at LCFF_X23_Y9_N1
E1_mCCD_B[8] = DFFEAS(E1L49, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_R[8] is RAW2RGB:u4|mCCD_R[8] at LCFF_X23_Y9_N19
E1_mCCD_R[8] = DFFEAS(E1L113, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_B[9] is RAW2RGB:u4|mCCD_B[9] at LCFF_X22_Y11_N21
E1_mCCD_B[9] = DFFEAS(E1L51, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_R[9] is RAW2RGB:u4|mCCD_R[9] at LCFF_X22_Y11_N9
E1_mCCD_R[9] = DFFEAS(E1L115, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_G[6] is RAW2RGB:u4|mCCD_G[6] at LCFF_X23_Y10_N21
E1_mCCD_G[6] = DFFEAS(E1L71, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_G[1] is RAW2RGB:u4|mCCD_G[1] at LCFF_X23_Y10_N11
E1_mCCD_G[1] = DFFEAS(E1L56, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_G[7] is RAW2RGB:u4|mCCD_G[7] at LCFF_X23_Y10_N23
E1_mCCD_G[7] = DFFEAS(E1L74, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_G[2] is RAW2RGB:u4|mCCD_G[2] at LCFF_X23_Y10_N13
E1_mCCD_G[2] = DFFEAS(E1L59, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_G[8] is RAW2RGB:u4|mCCD_G[8] at LCFF_X23_Y10_N25
E1_mCCD_G[8] = DFFEAS(E1L77, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_G[3] is RAW2RGB:u4|mCCD_G[3] at LCFF_X23_Y10_N15
E1_mCCD_G[3] = DFFEAS(E1L62, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_G[9] is RAW2RGB:u4|mCCD_G[9] at LCFF_X23_Y10_N27
E1_mCCD_G[9] = DFFEAS(E1L80, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_G[4] is RAW2RGB:u4|mCCD_G[4] at LCFF_X23_Y10_N17
E1_mCCD_G[4] = DFFEAS(E1L65, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_G[10] is RAW2RGB:u4|mCCD_G[10] at LCFF_X23_Y10_N29
E1_mCCD_G[10] = DFFEAS(E1L83, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--E1_mCCD_G[5] is RAW2RGB:u4|mCCD_G[5] at LCFF_X23_Y10_N19
E1_mCCD_G[5] = DFFEAS(E1L68, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--LB1_END is I2C_CCD_Config:u7|I2C_Controller:u0|END at LCFF_X44_Y17_N17
LB1_END = DFFEAS(LB1L14, GLOBAL(H1L93), GLOBAL(A1L291),  ,  ,  ,  ,  ,  );


--H1_mSetup_ST.0010 is I2C_CCD_Config:u7|mSetup_ST.0010 at LCFF_X44_Y16_N3
H1_mSetup_ST.0010 = DFFEAS(H1L130, GLOBAL(H1L93), GLOBAL(A1L291),  , H1L38,  ,  ,  ,  );


--H1_mSetup_ST.0001 is I2C_CCD_Config:u7|mSetup_ST.0001 at LCFF_X44_Y16_N7
H1_mSetup_ST.0001 = DFFEAS(H1L40, GLOBAL(H1L93), GLOBAL(A1L291),  , H1L38,  ,  ,  ,  );


--H1L39 is I2C_CCD_Config:u7|Select~135 at LCCOMB_X44_Y16_N0
H1L39 = H1_mI2C_GO & (LB1_END # !H1_mSetup_ST.0001) # !H1_mI2C_GO & (!H1_mSetup_ST.0010 & !H1_mSetup_ST.0001);


--H1_LUT_INDEX[2] is I2C_CCD_Config:u7|LUT_INDEX[2] at LCFF_X42_Y16_N13
H1_LUT_INDEX[2] = DFFEAS(H1L20, GLOBAL(H1L93), GLOBAL(A1L291),  , H1L29,  ,  ,  ,  );


--H1_LUT_INDEX[1] is I2C_CCD_Config:u7|LUT_INDEX[1] at LCFF_X42_Y16_N11
H1_LUT_INDEX[1] = DFFEAS(H1L17, GLOBAL(H1L93), GLOBAL(A1L291),  , H1L29,  ,  ,  ,  );


--H1_LUT_INDEX[3] is I2C_CCD_Config:u7|LUT_INDEX[3] at LCFF_X42_Y16_N15
H1_LUT_INDEX[3] = DFFEAS(H1L23, GLOBAL(H1L93), GLOBAL(A1L291),  , H1L29,  ,  ,  ,  );


--H1L37 is I2C_CCD_Config:u7|LessThan~308 at LCCOMB_X42_Y16_N22
H1L37 = !H1_LUT_INDEX[1] & !H1_LUT_INDEX[3] & !H1_LUT_INDEX[2];


--H1_LUT_INDEX[0] is I2C_CCD_Config:u7|LUT_INDEX[0] at LCFF_X42_Y16_N9
H1_LUT_INDEX[0] = DFFEAS(H1L14, GLOBAL(H1L93), GLOBAL(A1L291),  , H1L29,  ,  ,  ,  );


--H1_LUT_INDEX[4] is I2C_CCD_Config:u7|LUT_INDEX[4] at LCFF_X42_Y16_N17
H1_LUT_INDEX[4] = DFFEAS(H1L26, GLOBAL(H1L93), GLOBAL(A1L291),  , H1L29,  ,  ,  ,  );


--H1_LUT_INDEX[5] is I2C_CCD_Config:u7|LUT_INDEX[5] at LCFF_X42_Y16_N19
H1_LUT_INDEX[5] = DFFEAS(H1L30, GLOBAL(H1L93), GLOBAL(A1L291),  , H1L29,  ,  ,  ,  );


--H1L38 is I2C_CCD_Config:u7|LessThan~309 at LCCOMB_X42_Y16_N26
H1L38 = !H1_LUT_INDEX[5] & (H1L37 & !H1_LUT_INDEX[0] # !H1_LUT_INDEX[4]);


--H1_mI2C_CLK_DIV[1] is I2C_CCD_Config:u7|mI2C_CLK_DIV[1] at LCFF_X45_Y16_N3
H1_mI2C_CLK_DIV[1] = DFFEAS(H1L47, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1_mI2C_CLK_DIV[0] is I2C_CCD_Config:u7|mI2C_CLK_DIV[0] at LCFF_X45_Y16_N1
H1_mI2C_CLK_DIV[0] = DFFEAS(H1L44, GLOBAL(A1L15), GLOBAL(A1L291),  ,  ,  ,  , H1L36,  );


--H1L44 is I2C_CCD_Config:u7|mI2C_CLK_DIV[0]~239 at LCCOMB_X45_Y16_N0
H1L44 = H1_mI2C_CLK_DIV[0] $ VCC;

--H1L45 is I2C_CCD_Config:u7|mI2C_CLK_DIV[0]~240 at LCCOMB_X45_Y16_N0
H1L45 = CARRY(H1_mI2C_CLK_DIV[0]);


--H1L47 is I2C_CCD_Config:u7|mI2C_CLK_DIV[1]~241 at LCCOMB_X45_Y16_N2
H1L47 = H1_mI2C_CLK_DIV[1] & !H1L45 # !H1_mI2C_CLK_DIV[1] & (H1L45 # GND);

--H1L48 is I2C_CCD_Config:u7|mI2C_CLK_DIV[1]~242 at LCCOMB_X45_Y16_N2
H1L48 = CARRY(!H1L45 # !H1_mI2C_CLK_DIV[1]);


--H1L50 is I2C_CCD_Config:u7|mI2C_CLK_DIV[2]~243 at LCCOMB_X45_Y16_N4
H1L50 = H1_mI2C_CLK_DIV[2] & (H1L48 $ GND) # !H1_mI2C_CLK_DIV[2] & !H1L48 & VCC;

--H1L51 is I2C_CCD_Config:u7|mI2C_CLK_DIV[2]~244 at LCCOMB_X45_Y16_N4
H1L51 = CARRY(H1_mI2C_CLK_DIV[2] & !H1L48);


--H1L53 is I2C_CCD_Config:u7|mI2C_CLK_DIV[3]~245 at LCCOMB_X45_Y16_N6
H1L53 = H1_mI2C_CLK_DIV[3] & !H1L51 # !H1_mI2C_CLK_DIV[3] & (H1L51 # GND);

--H1L54 is I2C_CCD_Config:u7|mI2C_CLK_DIV[3]~246 at LCCOMB_X45_Y16_N6
H1L54 = CARRY(!H1L51 # !H1_mI2C_CLK_DIV[3]);


--H1L56 is I2C_CCD_Config:u7|mI2C_CLK_DIV[4]~247 at LCCOMB_X45_Y16_N8
H1L56 = H1_mI2C_CLK_DIV[4] & (H1L54 $ GND) # !H1_mI2C_CLK_DIV[4] & !H1L54 & VCC;

--H1L57 is I2C_CCD_Config:u7|mI2C_CLK_DIV[4]~248 at LCCOMB_X45_Y16_N8
H1L57 = CARRY(H1_mI2C_CLK_DIV[4] & !H1L54);


--H1L59 is I2C_CCD_Config:u7|mI2C_CLK_DIV[5]~249 at LCCOMB_X45_Y16_N10
H1L59 = H1_mI2C_CLK_DIV[5] & !H1L57 # !H1_mI2C_CLK_DIV[5] & (H1L57 # GND);

--H1L60 is I2C_CCD_Config:u7|mI2C_CLK_DIV[5]~250 at LCCOMB_X45_Y16_N10
H1L60 = CARRY(!H1L57 # !H1_mI2C_CLK_DIV[5]);


--H1L62 is I2C_CCD_Config:u7|mI2C_CLK_DIV[6]~251 at LCCOMB_X45_Y16_N12
H1L62 = H1_mI2C_CLK_DIV[6] & (H1L60 $ GND) # !H1_mI2C_CLK_DIV[6] & !H1L60 & VCC;

--H1L63 is I2C_CCD_Config:u7|mI2C_CLK_DIV[6]~252 at LCCOMB_X45_Y16_N12
H1L63 = CARRY(H1_mI2C_CLK_DIV[6] & !H1L60);


--H1L65 is I2C_CCD_Config:u7|mI2C_CLK_DIV[7]~253 at LCCOMB_X45_Y16_N14
H1L65 = H1_mI2C_CLK_DIV[7] & !H1L63 # !H1_mI2C_CLK_DIV[7] & (H1L63 # GND);

--H1L66 is I2C_CCD_Config:u7|mI2C_CLK_DIV[7]~254 at LCCOMB_X45_Y16_N14
H1L66 = CARRY(!H1L63 # !H1_mI2C_CLK_DIV[7]);


--H1L68 is I2C_CCD_Config:u7|mI2C_CLK_DIV[8]~255 at LCCOMB_X45_Y16_N16
H1L68 = H1_mI2C_CLK_DIV[8] & (H1L66 $ GND) # !H1_mI2C_CLK_DIV[8] & !H1L66 & VCC;

--H1L69 is I2C_CCD_Config:u7|mI2C_CLK_DIV[8]~256 at LCCOMB_X45_Y16_N16
H1L69 = CARRY(H1_mI2C_CLK_DIV[8] & !H1L66);


--H1L71 is I2C_CCD_Config:u7|mI2C_CLK_DIV[9]~257 at LCCOMB_X45_Y16_N18
H1L71 = H1_mI2C_CLK_DIV[9] & !H1L69 # !H1_mI2C_CLK_DIV[9] & (H1L69 # GND);

--H1L72 is I2C_CCD_Config:u7|mI2C_CLK_DIV[9]~258 at LCCOMB_X45_Y16_N18
H1L72 = CARRY(!H1L69 # !H1_mI2C_CLK_DIV[9]);


--H1L74 is I2C_CCD_Config:u7|mI2C_CLK_DIV[10]~259 at LCCOMB_X45_Y16_N20
H1L74 = H1_mI2C_CLK_DIV[10] & (H1L72 $ GND) # !H1_mI2C_CLK_DIV[10] & !H1L72 & VCC;

--H1L75 is I2C_CCD_Config:u7|mI2C_CLK_DIV[10]~260 at LCCOMB_X45_Y16_N20
H1L75 = CARRY(H1_mI2C_CLK_DIV[10] & !H1L72);


--H1L77 is I2C_CCD_Config:u7|mI2C_CLK_DIV[11]~261 at LCCOMB_X45_Y16_N22
H1L77 = H1_mI2C_CLK_DIV[11] & !H1L75 # !H1_mI2C_CLK_DIV[11] & (H1L75 # GND);

--H1L78 is I2C_CCD_Config:u7|mI2C_CLK_DIV[11]~262 at LCCOMB_X45_Y16_N22
H1L78 = CARRY(!H1L75 # !H1_mI2C_CLK_DIV[11]);


--H1L80 is I2C_CCD_Config:u7|mI2C_CLK_DIV[12]~263 at LCCOMB_X45_Y16_N24
H1L80 = H1_mI2C_CLK_DIV[12] & (H1L78 $ GND) # !H1_mI2C_CLK_DIV[12] & !H1L78 & VCC;

--H1L81 is I2C_CCD_Config:u7|mI2C_CLK_DIV[12]~264 at LCCOMB_X45_Y16_N24
H1L81 = CARRY(H1_mI2C_CLK_DIV[12] & !H1L78);


--H1L83 is I2C_CCD_Config:u7|mI2C_CLK_DIV[13]~265 at LCCOMB_X45_Y16_N26
H1L83 = H1_mI2C_CLK_DIV[13] & !H1L81 # !H1_mI2C_CLK_DIV[13] & (H1L81 # GND);

--H1L84 is I2C_CCD_Config:u7|mI2C_CLK_DIV[13]~266 at LCCOMB_X45_Y16_N26
H1L84 = CARRY(!H1L81 # !H1_mI2C_CLK_DIV[13]);


--H1L86 is I2C_CCD_Config:u7|mI2C_CLK_DIV[14]~267 at LCCOMB_X45_Y16_N28
H1L86 = H1_mI2C_CLK_DIV[14] & (H1L84 $ GND) # !H1_mI2C_CLK_DIV[14] & !H1L84 & VCC;

--H1L87 is I2C_CCD_Config:u7|mI2C_CLK_DIV[14]~268 at LCCOMB_X45_Y16_N28
H1L87 = CARRY(H1_mI2C_CLK_DIV[14] & !H1L84);


--H1L89 is I2C_CCD_Config:u7|mI2C_CLK_DIV[15]~269 at LCCOMB_X45_Y16_N30
H1L89 = H1L87 $ H1_mI2C_CLK_DIV[15];


--H1_mI2C_DATA[2] is I2C_CCD_Config:u7|mI2C_DATA[2] at LCFF_X43_Y16_N17
H1_mI2C_DATA[2] = DFFEAS(H1L102, GLOBAL(H1L93),  ,  , H1L124, SW[10],  , H1L112, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[8] is I2C_CCD_Config:u7|mI2C_DATA[8] at LCFF_X42_Y17_N31
H1_mI2C_DATA[8] = DFFEAS(H1L132, GLOBAL(H1L93),  ,  , H1L124,  ,  ,  ,  );


--H1_mI2C_DATA[9] is I2C_CCD_Config:u7|mI2C_DATA[9] at LCFF_X42_Y17_N3
H1_mI2C_DATA[9] = DFFEAS(H1L133, GLOBAL(H1L93),  ,  , H1L124,  ,  , H1_LUT_INDEX[4],  );


--H1_mI2C_DATA[1] is I2C_CCD_Config:u7|mI2C_DATA[1] at LCFF_X43_Y16_N13
H1_mI2C_DATA[1] = DFFEAS(H1L99, GLOBAL(H1L93),  ,  , H1L124, SW[9],  , H1L112, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[7] is I2C_CCD_Config:u7|mI2C_DATA[7] at LCFF_X42_Y16_N1
H1_mI2C_DATA[7] = DFFEAS(H1L11, GLOBAL(H1L93),  ,  , H1L124,  ,  ,  ,  );


--H1_mI2C_DATA[0] is I2C_CCD_Config:u7|mI2C_DATA[0] at LCFF_X43_Y16_N5
H1_mI2C_DATA[0] = DFFEAS(H1L96, GLOBAL(H1L93),  ,  , H1L124, SW[8],  , H1L112, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[4] is I2C_CCD_Config:u7|mI2C_DATA[4] at LCFF_X43_Y16_N31
H1_mI2C_DATA[4] = DFFEAS(H1L108, GLOBAL(H1L93),  ,  , H1L124, SW[12],  , H1L112, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[10] is I2C_CCD_Config:u7|mI2C_DATA[10] at LCFF_X42_Y17_N15
H1_mI2C_DATA[10] = DFFEAS(H1L134, GLOBAL(H1L93),  ,  , H1L124,  ,  , H1_LUT_INDEX[4],  );


--H1_mI2C_DATA[11] is I2C_CCD_Config:u7|mI2C_DATA[11] at LCFF_X42_Y17_N1
H1_mI2C_DATA[11] = DFFEAS(H1L135, GLOBAL(H1L93),  ,  , H1L124,  ,  , H1_LUT_INDEX[4],  );


--H1_mI2C_DATA[3] is I2C_CCD_Config:u7|mI2C_DATA[3] at LCFF_X43_Y16_N11
H1_mI2C_DATA[3] = DFFEAS(H1L105, GLOBAL(H1L93),  ,  , H1L124, SW[11],  , H1L112, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[6] is I2C_CCD_Config:u7|mI2C_DATA[6] at LCFF_X43_Y16_N15
H1_mI2C_DATA[6] = DFFEAS(H1L115, GLOBAL(H1L93),  ,  , H1L124, SW[14],  , H1L112, H1_LUT_INDEX[0]);


--H1_mI2C_DATA[5] is I2C_CCD_Config:u7|mI2C_DATA[5] at LCFF_X43_Y16_N3
H1_mI2C_DATA[5] = DFFEAS(H1L7, GLOBAL(H1L93),  ,  , H1L124,  ,  ,  ,  );


--H1_mI2C_DATA[15] is I2C_CCD_Config:u7|mI2C_DATA[15] at LCFF_X42_Y16_N21
H1_mI2C_DATA[15] = DFFEAS(H1L136, GLOBAL(H1L93),  ,  , H1L124,  ,  , H1_LUT_INDEX[0],  );


--H1_mI2C_DATA[13] is I2C_CCD_Config:u7|mI2C_DATA[13] at LCFF_X42_Y17_N21
H1_mI2C_DATA[13] = DFFEAS(H1L138, GLOBAL(H1L93),  ,  , H1L124,  ,  ,  ,  );


--S1L72 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[0]~959 at LCCOMB_X33_Y19_N0
S1L72 = S1_init_timer[0] $ VCC;

--S1L73 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[0]~960 at LCCOMB_X33_Y19_N0
S1L73 = CARRY(S1_init_timer[0]);


--S1L75 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[1]~961 at LCCOMB_X33_Y19_N2
S1L75 = S1_init_timer[1] & !S1L73 # !S1_init_timer[1] & (S1L73 # GND);

--S1L76 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[1]~962 at LCCOMB_X33_Y19_N2
S1L76 = CARRY(!S1L73 # !S1_init_timer[1]);


--S1L78 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[2]~963 at LCCOMB_X33_Y19_N4
S1L78 = S1_init_timer[2] & (S1L76 $ GND) # !S1_init_timer[2] & !S1L76 & VCC;

--S1L79 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[2]~964 at LCCOMB_X33_Y19_N4
S1L79 = CARRY(S1_init_timer[2] & !S1L76);


--S1L81 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[3]~965 at LCCOMB_X33_Y19_N6
S1L81 = S1_init_timer[3] & !S1L79 # !S1_init_timer[3] & (S1L79 # GND);

--S1L82 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[3]~966 at LCCOMB_X33_Y19_N6
S1L82 = CARRY(!S1L79 # !S1_init_timer[3]);


--S1L84 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[4]~967 at LCCOMB_X33_Y19_N8
S1L84 = S1_init_timer[4] & (S1L82 $ GND) # !S1_init_timer[4] & !S1L82 & VCC;

--S1L85 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[4]~968 at LCCOMB_X33_Y19_N8
S1L85 = CARRY(S1_init_timer[4] & !S1L82);


--S1L87 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[5]~969 at LCCOMB_X33_Y19_N10
S1L87 = S1_init_timer[5] & !S1L85 # !S1_init_timer[5] & (S1L85 # GND);

--S1L88 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[5]~970 at LCCOMB_X33_Y19_N10
S1L88 = CARRY(!S1L85 # !S1_init_timer[5]);


--S1L90 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[6]~971 at LCCOMB_X33_Y19_N12
S1L90 = S1_init_timer[6] & (S1L88 $ GND) # !S1_init_timer[6] & !S1L88 & VCC;

--S1L91 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[6]~972 at LCCOMB_X33_Y19_N12
S1L91 = CARRY(S1_init_timer[6] & !S1L88);


--S1L93 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[7]~973 at LCCOMB_X33_Y19_N14
S1L93 = S1_init_timer[7] & !S1L91 # !S1_init_timer[7] & (S1L91 # GND);

--S1L94 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[7]~974 at LCCOMB_X33_Y19_N14
S1L94 = CARRY(!S1L91 # !S1_init_timer[7]);


--S1L96 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[8]~975 at LCCOMB_X33_Y19_N16
S1L96 = S1_init_timer[8] & (S1L94 $ GND) # !S1_init_timer[8] & !S1L94 & VCC;

--S1L97 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[8]~976 at LCCOMB_X33_Y19_N16
S1L97 = CARRY(S1_init_timer[8] & !S1L94);


--S1L99 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[9]~977 at LCCOMB_X33_Y19_N18
S1L99 = S1_init_timer[9] & !S1L97 # !S1_init_timer[9] & (S1L97 # GND);

--S1L100 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[9]~978 at LCCOMB_X33_Y19_N18
S1L100 = CARRY(!S1L97 # !S1_init_timer[9]);


--S1L102 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[10]~979 at LCCOMB_X33_Y19_N20
S1L102 = S1_init_timer[10] & (S1L100 $ GND) # !S1_init_timer[10] & !S1L100 & VCC;

--S1L103 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[10]~980 at LCCOMB_X33_Y19_N20
S1L103 = CARRY(S1_init_timer[10] & !S1L100);


--S1L20 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~424 at LCCOMB_X32_Y19_N4
S1L20 = !S1_init_timer[1] & !S1_init_timer[0] & !S1_init_timer[2];


--S1L21 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~425 at LCCOMB_X32_Y19_N8
S1L21 = S1L13 & (S1L20 # !S1_init_timer[3]) # !S1_init_timer[7];


--S1L22 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~426 at LCCOMB_X32_Y19_N12
S1L22 = S1L21 & !S1_init_timer[8] # !S1_init_timer[9] # !S1L17;


--S1L23 is Sdram_Control_4Port:u6|control_interface:control1|LessThan~427 at LCCOMB_X32_Y19_N14
S1L23 = !S1_init_timer[15] & (S1L22 & !S1_init_timer[13] # !S1_init_timer[14]);


--S1L105 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[11]~981 at LCCOMB_X33_Y19_N22
S1L105 = S1_init_timer[11] & !S1L103 # !S1_init_timer[11] & (S1L103 # GND);

--S1L106 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[11]~982 at LCCOMB_X33_Y19_N22
S1L106 = CARRY(!S1L103 # !S1_init_timer[11]);


--S1L108 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[12]~983 at LCCOMB_X33_Y19_N24
S1L108 = S1_init_timer[12] & (S1L106 $ GND) # !S1_init_timer[12] & !S1L106 & VCC;

--S1L109 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[12]~984 at LCCOMB_X33_Y19_N24
S1L109 = CARRY(S1_init_timer[12] & !S1L106);


--S1L111 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[13]~985 at LCCOMB_X33_Y19_N26
S1L111 = S1_init_timer[13] & !S1L109 # !S1_init_timer[13] & (S1L109 # GND);

--S1L112 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[13]~986 at LCCOMB_X33_Y19_N26
S1L112 = CARRY(!S1L109 # !S1_init_timer[13]);


--S1L114 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[14]~987 at LCCOMB_X33_Y19_N28
S1L114 = S1_init_timer[14] & (S1L112 $ GND) # !S1_init_timer[14] & !S1L112 & VCC;

--S1L115 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[14]~988 at LCCOMB_X33_Y19_N28
S1L115 = CARRY(S1_init_timer[14] & !S1L112);


--S1L117 is Sdram_Control_4Port:u6|control_interface:control1|init_timer[15]~989 at LCCOMB_X33_Y19_N30
S1L117 = S1L115 $ S1_init_timer[15];


--R1_command_delay[1] is Sdram_Control_4Port:u6|command:command1|command_delay[1] at LCFF_X20_Y10_N19
R1_command_delay[1] = DFFEAS(R1L69, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L68 is Sdram_Control_4Port:u6|command:command1|command_delay~331 at LCCOMB_X20_Y10_N22
R1L68 = !S1_INIT_REQ & (R1L57 # R1_command_delay[1]);


--G1L385 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1098 at LCCOMB_X19_Y13_N2
G1L385 = G1_rWR1_ADDR[8] $ VCC;

--G1L386 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1099 at LCCOMB_X19_Y13_N2
G1L386 = CARRY(G1_rWR1_ADDR[8]);


--G1L387 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1100 at LCCOMB_X18_Y13_N20
G1L387 = !G1_rWR1_ADDR[22] & !G1_rWR1_ADDR[20] & C1_oRST_0 & !G1_rWR1_ADDR[19];


--G1L37 is Sdram_Control_4Port:u6|LessThan~1260 at LCCOMB_X19_Y13_N0
G1L37 = !G1_rWR1_ADDR[8] # !G1_rWR1_ADDR[11] # !G1_rWR1_ADDR[9] # !G1_rWR1_ADDR[10];


--G1L38 is Sdram_Control_4Port:u6|LessThan~1261 at LCCOMB_X19_Y14_N20
G1L38 = !G1_rWR1_ADDR[15] # !G1_rWR1_ADDR[14] # !G1_rWR1_ADDR[13] # !G1_rWR1_ADDR[12];


--G1L388 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1101 at LCCOMB_X19_Y14_N16
G1L388 = !G1_rWR1_ADDR[17] & !G1_rWR1_ADDR[16] & (G1L38 # G1L37);


--G1L389 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1102 at LCCOMB_X18_Y13_N14
G1L389 = G1_rWR1_ADDR[21] # !G1L388 & G1_rWR1_ADDR[18] # !G1L387;


--G1L390 is Sdram_Control_4Port:u6|rWR1_ADDR[8]~1103 at LCCOMB_X22_Y13_N24
G1L390 = G1_WR_MASK[0] & G1_mWR_DONE # !C1_oRST_0;


--G1L335 is Sdram_Control_4Port:u6|rRD2_ADDR[8]~1610 at LCCOMB_X19_Y15_N2
G1L335 = G1_rRD2_ADDR[8] $ VCC;

--G1L336 is Sdram_Control_4Port:u6|rRD2_ADDR[8]~1611 at LCCOMB_X19_Y15_N2
G1L336 = CARRY(G1_rRD2_ADDR[8]);


--G1L338 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1612 at LCCOMB_X20_Y15_N8
G1L338 = C1_oRST_0 & !G1_rRD2_ADDR[22] & !G1_rRD2_ADDR[21];


--G1L39 is Sdram_Control_4Port:u6|LessThan~1262 at LCCOMB_X19_Y16_N18
G1L39 = !G1_rRD2_ADDR[15] # !G1_rRD2_ADDR[14];


--G1L40 is Sdram_Control_4Port:u6|LessThan~1263 at LCCOMB_X20_Y14_N16
G1L40 = !G1_rRD2_ADDR[11] & (!G1_rRD2_ADDR[10] # !G1_rRD2_ADDR[9] # !G1_rRD2_ADDR[8]);


--G1L41 is Sdram_Control_4Port:u6|LessThan~1264 at LCCOMB_X20_Y14_N0
G1L41 = G1L39 # !G1_rRD2_ADDR[13] & (G1L40 # !G1_rRD2_ADDR[12]);


--G1L339 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1613 at LCCOMB_X20_Y15_N20
G1L339 = G1L41 & !G1_rRD2_ADDR[17] & !G1_rRD2_ADDR[16] # !G1_rRD2_ADDR[18];


--G1L340 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1614 at LCCOMB_X20_Y15_N14
G1L340 = G1_rRD2_ADDR[20] & (G1_rRD2_ADDR[19] # !G1L339) # !G1L338;


--G1L341 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1615 at LCCOMB_X21_Y13_N2
G1L341 = G1_RD_MASK[1] & G1_mRD_DONE # !C1_oRST_0;


--G1L146 is Sdram_Control_4Port:u6|add~2869 at LCCOMB_X18_Y14_N0
G1L146 = G1_rWR2_ADDR[8] $ VCC;

--G1L147 is Sdram_Control_4Port:u6|add~2870 at LCCOMB_X18_Y14_N0
G1L147 = CARRY(G1_rWR2_ADDR[8]);


--G1L42 is Sdram_Control_4Port:u6|LessThan~1265 at LCCOMB_X19_Y14_N24
G1L42 = !G1_rWR2_ADDR[11] # !G1_rWR2_ADDR[9] # !G1_rWR2_ADDR[8] # !G1_rWR2_ADDR[10];


--G1L43 is Sdram_Control_4Port:u6|LessThan~1266 at LCCOMB_X19_Y14_N12
G1L43 = !G1_rWR2_ADDR[12] # !G1_rWR2_ADDR[15] # !G1_rWR2_ADDR[14] # !G1_rWR2_ADDR[13];


--G1L44 is Sdram_Control_4Port:u6|LessThan~1267 at LCCOMB_X19_Y14_N2
G1L44 = !G1_rWR2_ADDR[17] & !G1_rWR2_ADDR[16] & (G1L43 # G1L42);


--G1L45 is Sdram_Control_4Port:u6|LessThan~1268 at LCCOMB_X20_Y15_N26
G1L45 = !G1_rWR2_ADDR[19] & (G1L44 # !G1_rWR2_ADDR[18]);


--G1L46 is Sdram_Control_4Port:u6|LessThan~1269 at LCCOMB_X20_Y15_N12
G1L46 = !G1_rWR2_ADDR[21] & !G1_rWR2_ADDR[22] & (G1L45 # !G1_rWR2_ADDR[20]);


--G1L450 is Sdram_Control_4Port:u6|rWR2_ADDR~1872 at LCCOMB_X18_Y13_N12
G1L450 = C1_oRST_0 & G1L46 & G1L146;


--G1L435 is Sdram_Control_4Port:u6|rWR2_ADDR[8]~1873 at LCCOMB_X22_Y13_N8
G1L435 = G1_WR_MASK[1] & G1_mWR_DONE # !C1_oRST_0;


--G1L283 is Sdram_Control_4Port:u6|rRD1_ADDR[8]~1622 at LCCOMB_X21_Y14_N2
G1L283 = G1_rRD1_ADDR[8] $ VCC;

--G1L284 is Sdram_Control_4Port:u6|rRD1_ADDR[8]~1623 at LCCOMB_X21_Y14_N2
G1L284 = CARRY(G1_rRD1_ADDR[8]);


--G1L322 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1624 at LCCOMB_X21_Y13_N18
G1L322 = !G1_rRD1_ADDR[22] & C1_oRST_0 & !G1_rRD1_ADDR[20] & !G1_rRD1_ADDR[19];


--G1L323 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1625 at LCCOMB_X20_Y14_N30
G1L323 = G1_rRD1_ADDR[11] # G1_rRD1_ADDR[9] & G1_rRD1_ADDR[10] & G1_rRD1_ADDR[8];


--G1L324 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1626 at LCCOMB_X20_Y14_N12
G1L324 = G1_rRD1_ADDR[15] & (G1_rRD1_ADDR[13] # G1_rRD1_ADDR[12] & G1L323);


--G1L325 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1627 at LCCOMB_X20_Y14_N14
G1L325 = !G1_rRD1_ADDR[17] & !G1_rRD1_ADDR[16] & (!G1_rRD1_ADDR[14] # !G1L324);


--G1L326 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1628 at LCCOMB_X21_Y14_N0
G1L326 = G1_rRD1_ADDR[21] # !G1L325 & G1_rRD1_ADDR[18] # !G1L322;


--G1L327 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1629 at LCCOMB_X21_Y13_N0
G1L327 = G1_RD_MASK[0] & G1_mRD_DONE # !C1_oRST_0;


--G1L112 is Sdram_Control_4Port:u6|Select~184 at LCCOMB_X19_Y11_N12
G1L112 = !G1L28 & (G1_ST[1] # !G1L23 # !G1_ST[0]);


--G1L10 is Sdram_Control_4Port:u6|CMD[0]~690 at LCCOMB_X18_Y10_N12
G1L10 = S1_CMD_ACK & (G1L26 # G1L27 & !G1L107) # !S1_CMD_ACK & (G1L27 & !G1L107);


--G1L113 is Sdram_Control_4Port:u6|Select~185 at LCCOMB_X19_Y11_N18
G1L113 = G1L28 & (G1_ST[1] # !G1L23 # !G1_ST[0]);


--R1_rp_shift[1] is Sdram_Control_4Port:u6|command:command1|rp_shift[1] at LCFF_X20_Y10_N3
R1_rp_shift[1] = DFFEAS(R1L105, GLOBAL(KB1L2),  ,  , R1L100,  ,  ,  ,  );


--R1L104 is Sdram_Control_4Port:u6|command:command1|rp_shift~806 at LCCOMB_X20_Y10_N10
R1L104 = !S1_INIT_REQ & (R1_rp_shift[1] # !R1_command_delay[0] & R1_command_done);


--R1L49 is Sdram_Control_4Port:u6|command:command1|always0~9 at LCCOMB_X20_Y11_N24
R1L49 = R1L52 & S1_READA & !R1_do_reada & !S1_REF_REQ;


--R1L89 is Sdram_Control_4Port:u6|command:command1|ex_read~107 at LCCOMB_X20_Y10_N0
R1L89 = R1L99 & !G1_PM_STOP & (R1L49 # R1_ex_read) # !R1L99 & (R1L49 # R1_ex_read);


--R1L91 is Sdram_Control_4Port:u6|command:command1|ex_write~107 at LCCOMB_X20_Y10_N16
R1L91 = R1L99 & !G1_PM_STOP & (R1L50 # R1_ex_write) # !R1L99 & (R1L50 # R1_ex_write);


--S1L121 is Sdram_Control_4Port:u6|control_interface:control1|timer[0]~251 at LCCOMB_X21_Y12_N0
S1L121 = S1_timer[0] $ VCC;

--S1L122 is Sdram_Control_4Port:u6|control_interface:control1|timer[0]~252 at LCCOMB_X21_Y12_N0
S1L122 = CARRY(S1_timer[0]);


--S1L33 is Sdram_Control_4Port:u6|control_interface:control1|REF_REQ~23 at LCCOMB_X20_Y11_N4
S1L33 = S1_INIT_REQ # R1_REF_ACK;


--S1L124 is Sdram_Control_4Port:u6|control_interface:control1|timer[1]~253 at LCCOMB_X21_Y12_N2
S1L124 = S1_timer[1] & S1L122 & VCC # !S1_timer[1] & !S1L122;

--S1L125 is Sdram_Control_4Port:u6|control_interface:control1|timer[1]~254 at LCCOMB_X21_Y12_N2
S1L125 = CARRY(!S1_timer[1] & !S1L122);


--S1L127 is Sdram_Control_4Port:u6|control_interface:control1|timer[2]~255 at LCCOMB_X21_Y12_N4
S1L127 = S1_timer[2] & (GND # !S1L125) # !S1_timer[2] & (S1L125 $ GND);

--S1L128 is Sdram_Control_4Port:u6|control_interface:control1|timer[2]~256 at LCCOMB_X21_Y12_N4
S1L128 = CARRY(S1_timer[2] # !S1L125);


--S1L130 is Sdram_Control_4Port:u6|control_interface:control1|timer[3]~257 at LCCOMB_X21_Y12_N6
S1L130 = S1_timer[3] & S1L128 & VCC # !S1_timer[3] & !S1L128;

--S1L131 is Sdram_Control_4Port:u6|control_interface:control1|timer[3]~258 at LCCOMB_X21_Y12_N6
S1L131 = CARRY(!S1_timer[3] & !S1L128);


--S1L133 is Sdram_Control_4Port:u6|control_interface:control1|timer[4]~259 at LCCOMB_X21_Y12_N8
S1L133 = S1_timer[4] & (GND # !S1L131) # !S1_timer[4] & (S1L131 $ GND);

--S1L134 is Sdram_Control_4Port:u6|control_interface:control1|timer[4]~260 at LCCOMB_X21_Y12_N8
S1L134 = CARRY(S1_timer[4] # !S1L131);


--S1L136 is Sdram_Control_4Port:u6|control_interface:control1|timer[5]~261 at LCCOMB_X21_Y12_N10
S1L136 = S1_timer[5] & S1L134 & VCC # !S1_timer[5] & !S1L134;

--S1L137 is Sdram_Control_4Port:u6|control_interface:control1|timer[5]~262 at LCCOMB_X21_Y12_N10
S1L137 = CARRY(!S1_timer[5] & !S1L134);


--S1L139 is Sdram_Control_4Port:u6|control_interface:control1|timer[6]~263 at LCCOMB_X21_Y12_N12
S1L139 = S1_timer[6] & (GND # !S1L137) # !S1_timer[6] & (S1L137 $ GND);

--S1L140 is Sdram_Control_4Port:u6|control_interface:control1|timer[6]~264 at LCCOMB_X21_Y12_N12
S1L140 = CARRY(S1_timer[6] # !S1L137);


--S1L142 is Sdram_Control_4Port:u6|control_interface:control1|timer[7]~265 at LCCOMB_X21_Y12_N14
S1L142 = S1_timer[7] & S1L140 & VCC # !S1_timer[7] & !S1L140;

--S1L143 is Sdram_Control_4Port:u6|control_interface:control1|timer[7]~266 at LCCOMB_X21_Y12_N14
S1L143 = CARRY(!S1_timer[7] & !S1L140);


--S1L145 is Sdram_Control_4Port:u6|control_interface:control1|timer[8]~267 at LCCOMB_X21_Y12_N16
S1L145 = S1_timer[8] & (GND # !S1L143) # !S1_timer[8] & (S1L143 $ GND);

--S1L146 is Sdram_Control_4Port:u6|control_interface:control1|timer[8]~268 at LCCOMB_X21_Y12_N16
S1L146 = CARRY(S1_timer[8] # !S1L143);


--S1L148 is Sdram_Control_4Port:u6|control_interface:control1|timer[9]~269 at LCCOMB_X21_Y12_N18
S1L148 = S1_timer[9] & S1L146 & VCC # !S1_timer[9] & !S1L146;

--S1L149 is Sdram_Control_4Port:u6|control_interface:control1|timer[9]~270 at LCCOMB_X21_Y12_N18
S1L149 = CARRY(!S1_timer[9] & !S1L146);


--S1L151 is Sdram_Control_4Port:u6|control_interface:control1|timer[10]~271 at LCCOMB_X21_Y12_N20
S1L151 = S1_timer[10] & (GND # !S1L149) # !S1_timer[10] & (S1L149 $ GND);

--S1L152 is Sdram_Control_4Port:u6|control_interface:control1|timer[10]~272 at LCCOMB_X21_Y12_N20
S1L152 = CARRY(S1_timer[10] # !S1L149);


--S1L154 is Sdram_Control_4Port:u6|control_interface:control1|timer[11]~273 at LCCOMB_X21_Y12_N22
S1L154 = S1_timer[11] & S1L152 & VCC # !S1_timer[11] & !S1L152;

--S1L155 is Sdram_Control_4Port:u6|control_interface:control1|timer[11]~274 at LCCOMB_X21_Y12_N22
S1L155 = CARRY(!S1_timer[11] & !S1L152);


--S1L157 is Sdram_Control_4Port:u6|control_interface:control1|timer[12]~275 at LCCOMB_X21_Y12_N24
S1L157 = S1_timer[12] & (GND # !S1L155) # !S1_timer[12] & (S1L155 $ GND);

--S1L158 is Sdram_Control_4Port:u6|control_interface:control1|timer[12]~276 at LCCOMB_X21_Y12_N24
S1L158 = CARRY(S1_timer[12] # !S1L155);


--S1L160 is Sdram_Control_4Port:u6|control_interface:control1|timer[13]~277 at LCCOMB_X21_Y12_N26
S1L160 = S1_timer[13] & S1L158 & VCC # !S1_timer[13] & !S1L158;

--S1L161 is Sdram_Control_4Port:u6|control_interface:control1|timer[13]~278 at LCCOMB_X21_Y12_N26
S1L161 = CARRY(!S1_timer[13] & !S1L158);


--S1L163 is Sdram_Control_4Port:u6|control_interface:control1|timer[14]~279 at LCCOMB_X21_Y12_N28
S1L163 = S1_timer[14] & (GND # !S1L161) # !S1_timer[14] & (S1L161 $ GND);

--S1L164 is Sdram_Control_4Port:u6|control_interface:control1|timer[14]~280 at LCCOMB_X21_Y12_N28
S1L164 = CARRY(S1_timer[14] # !S1L161);


--S1L166 is Sdram_Control_4Port:u6|control_interface:control1|timer[15]~281 at LCCOMB_X21_Y12_N30
S1L166 = S1L164 $ !S1_timer[15];


--R1L19 is Sdram_Control_4Port:u6|command:command1|REF_ACK~55 at LCCOMB_X20_Y11_N10
R1L19 = R1_do_refresh & (S1_REF_REQ # R1L57 & R1_REF_ACK) # !R1_do_refresh & R1L57 & R1_REF_ACK;


--G1L342 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1616 at LCCOMB_X19_Y15_N4
G1L342 = G1_rRD2_ADDR[9] & !G1L336 # !G1_rRD2_ADDR[9] & (G1L336 # GND);

--G1L343 is Sdram_Control_4Port:u6|rRD2_ADDR[9]~1617 at LCCOMB_X19_Y15_N4
G1L343 = CARRY(!G1L336 # !G1_rRD2_ADDR[9]);


--G1L392 is Sdram_Control_4Port:u6|rWR1_ADDR[9]~1104 at LCCOMB_X19_Y13_N4
G1L392 = G1_rWR1_ADDR[9] & !G1L386 # !G1_rWR1_ADDR[9] & (G1L386 # GND);

--G1L393 is Sdram_Control_4Port:u6|rWR1_ADDR[9]~1105 at LCCOMB_X19_Y13_N4
G1L393 = CARRY(!G1L386 # !G1_rWR1_ADDR[9]);


--G1L148 is Sdram_Control_4Port:u6|add~2871 at LCCOMB_X18_Y14_N2
G1L148 = G1_rWR2_ADDR[9] & !G1L147 # !G1_rWR2_ADDR[9] & (G1L147 # GND);

--G1L149 is Sdram_Control_4Port:u6|add~2872 at LCCOMB_X18_Y14_N2
G1L149 = CARRY(!G1L147 # !G1_rWR2_ADDR[9]);


--G1L451 is Sdram_Control_4Port:u6|rWR2_ADDR~1874 at LCCOMB_X18_Y13_N4
G1L451 = C1_oRST_0 & G1L46 & G1L148;


--G1L286 is Sdram_Control_4Port:u6|rRD1_ADDR[9]~1630 at LCCOMB_X21_Y14_N4
G1L286 = G1_rRD1_ADDR[9] & !G1L284 # !G1_rRD1_ADDR[9] & (G1L284 # GND);

--G1L287 is Sdram_Control_4Port:u6|rRD1_ADDR[9]~1631 at LCCOMB_X21_Y14_N4
G1L287 = CARRY(!G1L284 # !G1_rRD1_ADDR[9]);


--G1L395 is Sdram_Control_4Port:u6|rWR1_ADDR[10]~1106 at LCCOMB_X19_Y13_N6
G1L395 = G1_rWR1_ADDR[10] & (G1L393 $ GND) # !G1_rWR1_ADDR[10] & !G1L393 & VCC;

--G1L396 is Sdram_Control_4Port:u6|rWR1_ADDR[10]~1107 at LCCOMB_X19_Y13_N6
G1L396 = CARRY(G1_rWR1_ADDR[10] & !G1L393);


--G1L345 is Sdram_Control_4Port:u6|rRD2_ADDR[10]~1618 at LCCOMB_X19_Y15_N6
G1L345 = G1_rRD2_ADDR[10] & (G1L343 $ GND) # !G1_rRD2_ADDR[10] & !G1L343 & VCC;

--G1L346 is Sdram_Control_4Port:u6|rRD2_ADDR[10]~1619 at LCCOMB_X19_Y15_N6
G1L346 = CARRY(G1_rRD2_ADDR[10] & !G1L343);


--G1L150 is Sdram_Control_4Port:u6|add~2873 at LCCOMB_X18_Y14_N4
G1L150 = G1_rWR2_ADDR[10] & (G1L149 $ GND) # !G1_rWR2_ADDR[10] & !G1L149 & VCC;

--G1L151 is Sdram_Control_4Port:u6|add~2874 at LCCOMB_X18_Y14_N4
G1L151 = CARRY(G1_rWR2_ADDR[10] & !G1L149);


--G1L452 is Sdram_Control_4Port:u6|rWR2_ADDR~1875 at LCCOMB_X18_Y13_N22
G1L452 = C1_oRST_0 & G1L46 & G1L150;


--G1L289 is Sdram_Control_4Port:u6|rRD1_ADDR[10]~1632 at LCCOMB_X21_Y14_N6
G1L289 = G1_rRD1_ADDR[10] & (G1L287 $ GND) # !G1_rRD1_ADDR[10] & !G1L287 & VCC;

--G1L290 is Sdram_Control_4Port:u6|rRD1_ADDR[10]~1633 at LCCOMB_X21_Y14_N6
G1L290 = CARRY(G1_rRD1_ADDR[10] & !G1L287);


--G1L348 is Sdram_Control_4Port:u6|rRD2_ADDR[11]~1620 at LCCOMB_X19_Y15_N8
G1L348 = G1_rRD2_ADDR[11] & !G1L346 # !G1_rRD2_ADDR[11] & (G1L346 # GND);

--G1L349 is Sdram_Control_4Port:u6|rRD2_ADDR[11]~1621 at LCCOMB_X19_Y15_N8
G1L349 = CARRY(!G1L346 # !G1_rRD2_ADDR[11]);


--G1L398 is Sdram_Control_4Port:u6|rWR1_ADDR[11]~1108 at LCCOMB_X19_Y13_N8
G1L398 = G1_rWR1_ADDR[11] & !G1L396 # !G1_rWR1_ADDR[11] & (G1L396 # GND);

--G1L399 is Sdram_Control_4Port:u6|rWR1_ADDR[11]~1109 at LCCOMB_X19_Y13_N8
G1L399 = CARRY(!G1L396 # !G1_rWR1_ADDR[11]);


--G1L152 is Sdram_Control_4Port:u6|add~2875 at LCCOMB_X18_Y14_N6
G1L152 = G1_rWR2_ADDR[11] & !G1L151 # !G1_rWR2_ADDR[11] & (G1L151 # GND);

--G1L153 is Sdram_Control_4Port:u6|add~2876 at LCCOMB_X18_Y14_N6
G1L153 = CARRY(!G1L151 # !G1_rWR2_ADDR[11]);


--G1L453 is Sdram_Control_4Port:u6|rWR2_ADDR~1876 at LCCOMB_X18_Y13_N0
G1L453 = G1L152 & C1_oRST_0 & G1L46;


--G1L292 is Sdram_Control_4Port:u6|rRD1_ADDR[11]~1634 at LCCOMB_X21_Y14_N8
G1L292 = G1_rRD1_ADDR[11] & !G1L290 # !G1_rRD1_ADDR[11] & (G1L290 # GND);

--G1L293 is Sdram_Control_4Port:u6|rRD1_ADDR[11]~1635 at LCCOMB_X21_Y14_N8
G1L293 = CARRY(!G1L290 # !G1_rRD1_ADDR[11]);


--G1L401 is Sdram_Control_4Port:u6|rWR1_ADDR[12]~1110 at LCCOMB_X19_Y13_N10
G1L401 = G1_rWR1_ADDR[12] & (G1L399 $ GND) # !G1_rWR1_ADDR[12] & !G1L399 & VCC;

--G1L402 is Sdram_Control_4Port:u6|rWR1_ADDR[12]~1111 at LCCOMB_X19_Y13_N10
G1L402 = CARRY(G1_rWR1_ADDR[12] & !G1L399);


--G1L351 is Sdram_Control_4Port:u6|rRD2_ADDR[12]~1622 at LCCOMB_X19_Y15_N10
G1L351 = G1_rRD2_ADDR[12] & (G1L349 $ GND) # !G1_rRD2_ADDR[12] & !G1L349 & VCC;

--G1L352 is Sdram_Control_4Port:u6|rRD2_ADDR[12]~1623 at LCCOMB_X19_Y15_N10
G1L352 = CARRY(G1_rRD2_ADDR[12] & !G1L349);


--G1L154 is Sdram_Control_4Port:u6|add~2877 at LCCOMB_X18_Y14_N8
G1L154 = G1_rWR2_ADDR[12] & (G1L153 $ GND) # !G1_rWR2_ADDR[12] & !G1L153 & VCC;

--G1L155 is Sdram_Control_4Port:u6|add~2878 at LCCOMB_X18_Y14_N8
G1L155 = CARRY(G1_rWR2_ADDR[12] & !G1L153);


--G1L454 is Sdram_Control_4Port:u6|rWR2_ADDR~1877 at LCCOMB_X18_Y13_N10
G1L454 = G1L154 & C1_oRST_0 & G1L46;


--G1L295 is Sdram_Control_4Port:u6|rRD1_ADDR[12]~1636 at LCCOMB_X21_Y14_N10
G1L295 = G1_rRD1_ADDR[12] & (G1L293 $ GND) # !G1_rRD1_ADDR[12] & !G1L293 & VCC;

--G1L296 is Sdram_Control_4Port:u6|rRD1_ADDR[12]~1637 at LCCOMB_X21_Y14_N10
G1L296 = CARRY(G1_rRD1_ADDR[12] & !G1L293);


--G1L354 is Sdram_Control_4Port:u6|rRD2_ADDR[13]~1624 at LCCOMB_X19_Y15_N12
G1L354 = G1_rRD2_ADDR[13] & !G1L352 # !G1_rRD2_ADDR[13] & (G1L352 # GND);

--G1L355 is Sdram_Control_4Port:u6|rRD2_ADDR[13]~1625 at LCCOMB_X19_Y15_N12
G1L355 = CARRY(!G1L352 # !G1_rRD2_ADDR[13]);


--G1L404 is Sdram_Control_4Port:u6|rWR1_ADDR[13]~1112 at LCCOMB_X19_Y13_N12
G1L404 = G1_rWR1_ADDR[13] & !G1L402 # !G1_rWR1_ADDR[13] & (G1L402 # GND);

--G1L405 is Sdram_Control_4Port:u6|rWR1_ADDR[13]~1113 at LCCOMB_X19_Y13_N12
G1L405 = CARRY(!G1L402 # !G1_rWR1_ADDR[13]);


--G1L156 is Sdram_Control_4Port:u6|add~2879 at LCCOMB_X18_Y14_N10
G1L156 = G1_rWR2_ADDR[13] & !G1L155 # !G1_rWR2_ADDR[13] & (G1L155 # GND);

--G1L157 is Sdram_Control_4Port:u6|add~2880 at LCCOMB_X18_Y14_N10
G1L157 = CARRY(!G1L155 # !G1_rWR2_ADDR[13]);


--G1L455 is Sdram_Control_4Port:u6|rWR2_ADDR~1878 at LCCOMB_X18_Y13_N2
G1L455 = G1L156 & C1_oRST_0 & G1L46;


--G1L298 is Sdram_Control_4Port:u6|rRD1_ADDR[13]~1638 at LCCOMB_X21_Y14_N12
G1L298 = G1_rRD1_ADDR[13] & !G1L296 # !G1_rRD1_ADDR[13] & (G1L296 # GND);

--G1L299 is Sdram_Control_4Port:u6|rRD1_ADDR[13]~1639 at LCCOMB_X21_Y14_N12
G1L299 = CARRY(!G1L296 # !G1_rRD1_ADDR[13]);


--G1L407 is Sdram_Control_4Port:u6|rWR1_ADDR[14]~1114 at LCCOMB_X19_Y13_N14
G1L407 = G1_rWR1_ADDR[14] & (G1L405 $ GND) # !G1_rWR1_ADDR[14] & !G1L405 & VCC;

--G1L408 is Sdram_Control_4Port:u6|rWR1_ADDR[14]~1115 at LCCOMB_X19_Y13_N14
G1L408 = CARRY(G1_rWR1_ADDR[14] & !G1L405);


--G1L357 is Sdram_Control_4Port:u6|rRD2_ADDR[14]~1626 at LCCOMB_X19_Y15_N14
G1L357 = G1_rRD2_ADDR[14] & (G1L355 $ GND) # !G1_rRD2_ADDR[14] & !G1L355 & VCC;

--G1L358 is Sdram_Control_4Port:u6|rRD2_ADDR[14]~1627 at LCCOMB_X19_Y15_N14
G1L358 = CARRY(G1_rRD2_ADDR[14] & !G1L355);


--G1L158 is Sdram_Control_4Port:u6|add~2881 at LCCOMB_X18_Y14_N12
G1L158 = G1_rWR2_ADDR[14] & (G1L157 $ GND) # !G1_rWR2_ADDR[14] & !G1L157 & VCC;

--G1L159 is Sdram_Control_4Port:u6|add~2882 at LCCOMB_X18_Y14_N12
G1L159 = CARRY(G1_rWR2_ADDR[14] & !G1L157);


--G1L456 is Sdram_Control_4Port:u6|rWR2_ADDR~1879 at LCCOMB_X18_Y13_N30
G1L456 = G1L158 & C1_oRST_0 & G1L46;


--G1L301 is Sdram_Control_4Port:u6|rRD1_ADDR[14]~1640 at LCCOMB_X21_Y14_N14
G1L301 = G1_rRD1_ADDR[14] & (G1L299 $ GND) # !G1_rRD1_ADDR[14] & !G1L299 & VCC;

--G1L302 is Sdram_Control_4Port:u6|rRD1_ADDR[14]~1641 at LCCOMB_X21_Y14_N14
G1L302 = CARRY(G1_rRD1_ADDR[14] & !G1L299);


--G1L360 is Sdram_Control_4Port:u6|rRD2_ADDR[15]~1628 at LCCOMB_X19_Y15_N16
G1L360 = G1_rRD2_ADDR[15] & !G1L358 # !G1_rRD2_ADDR[15] & (G1L358 # GND);

--G1L361 is Sdram_Control_4Port:u6|rRD2_ADDR[15]~1629 at LCCOMB_X19_Y15_N16
G1L361 = CARRY(!G1L358 # !G1_rRD2_ADDR[15]);


--G1L410 is Sdram_Control_4Port:u6|rWR1_ADDR[15]~1116 at LCCOMB_X19_Y13_N16
G1L410 = G1_rWR1_ADDR[15] & !G1L408 # !G1_rWR1_ADDR[15] & (G1L408 # GND);

--G1L411 is Sdram_Control_4Port:u6|rWR1_ADDR[15]~1117 at LCCOMB_X19_Y13_N16
G1L411 = CARRY(!G1L408 # !G1_rWR1_ADDR[15]);


--G1L160 is Sdram_Control_4Port:u6|add~2883 at LCCOMB_X18_Y14_N14
G1L160 = G1_rWR2_ADDR[15] & !G1L159 # !G1_rWR2_ADDR[15] & (G1L159 # GND);

--G1L161 is Sdram_Control_4Port:u6|add~2884 at LCCOMB_X18_Y14_N14
G1L161 = CARRY(!G1L159 # !G1_rWR2_ADDR[15]);


--G1L457 is Sdram_Control_4Port:u6|rWR2_ADDR~1880 at LCCOMB_X18_Y13_N28
G1L457 = C1_oRST_0 & G1L46 & G1L160;


--G1L304 is Sdram_Control_4Port:u6|rRD1_ADDR[15]~1642 at LCCOMB_X21_Y14_N16
G1L304 = G1_rRD1_ADDR[15] & !G1L302 # !G1_rRD1_ADDR[15] & (G1L302 # GND);

--G1L305 is Sdram_Control_4Port:u6|rRD1_ADDR[15]~1643 at LCCOMB_X21_Y14_N16
G1L305 = CARRY(!G1L302 # !G1_rRD1_ADDR[15]);


--G1L413 is Sdram_Control_4Port:u6|rWR1_ADDR[16]~1118 at LCCOMB_X19_Y13_N18
G1L413 = G1_rWR1_ADDR[16] & (G1L411 $ GND) # !G1_rWR1_ADDR[16] & !G1L411 & VCC;

--G1L414 is Sdram_Control_4Port:u6|rWR1_ADDR[16]~1119 at LCCOMB_X19_Y13_N18
G1L414 = CARRY(G1_rWR1_ADDR[16] & !G1L411);


--G1L363 is Sdram_Control_4Port:u6|rRD2_ADDR[16]~1630 at LCCOMB_X19_Y15_N18
G1L363 = G1_rRD2_ADDR[16] & (G1L361 $ GND) # !G1_rRD2_ADDR[16] & !G1L361 & VCC;

--G1L364 is Sdram_Control_4Port:u6|rRD2_ADDR[16]~1631 at LCCOMB_X19_Y15_N18
G1L364 = CARRY(G1_rRD2_ADDR[16] & !G1L361);


--G1L162 is Sdram_Control_4Port:u6|add~2885 at LCCOMB_X18_Y14_N16
G1L162 = G1_rWR2_ADDR[16] & (G1L161 $ GND) # !G1_rWR2_ADDR[16] & !G1L161 & VCC;

--G1L163 is Sdram_Control_4Port:u6|add~2886 at LCCOMB_X18_Y14_N16
G1L163 = CARRY(G1_rWR2_ADDR[16] & !G1L161);


--G1L458 is Sdram_Control_4Port:u6|rWR2_ADDR~1881 at LCCOMB_X18_Y13_N16
G1L458 = G1L162 & C1_oRST_0 & G1L46;


--G1L307 is Sdram_Control_4Port:u6|rRD1_ADDR[16]~1644 at LCCOMB_X21_Y14_N18
G1L307 = G1_rRD1_ADDR[16] & (G1L305 $ GND) # !G1_rRD1_ADDR[16] & !G1L305 & VCC;

--G1L308 is Sdram_Control_4Port:u6|rRD1_ADDR[16]~1645 at LCCOMB_X21_Y14_N18
G1L308 = CARRY(G1_rRD1_ADDR[16] & !G1L305);


--G1L366 is Sdram_Control_4Port:u6|rRD2_ADDR[17]~1632 at LCCOMB_X19_Y15_N20
G1L366 = G1_rRD2_ADDR[17] & !G1L364 # !G1_rRD2_ADDR[17] & (G1L364 # GND);

--G1L367 is Sdram_Control_4Port:u6|rRD2_ADDR[17]~1633 at LCCOMB_X19_Y15_N20
G1L367 = CARRY(!G1L364 # !G1_rRD2_ADDR[17]);


--G1L416 is Sdram_Control_4Port:u6|rWR1_ADDR[17]~1120 at LCCOMB_X19_Y13_N20
G1L416 = G1_rWR1_ADDR[17] & !G1L414 # !G1_rWR1_ADDR[17] & (G1L414 # GND);

--G1L417 is Sdram_Control_4Port:u6|rWR1_ADDR[17]~1121 at LCCOMB_X19_Y13_N20
G1L417 = CARRY(!G1L414 # !G1_rWR1_ADDR[17]);


--G1L164 is Sdram_Control_4Port:u6|add~2887 at LCCOMB_X18_Y14_N18
G1L164 = G1_rWR2_ADDR[17] & !G1L163 # !G1_rWR2_ADDR[17] & (G1L163 # GND);

--G1L165 is Sdram_Control_4Port:u6|add~2888 at LCCOMB_X18_Y14_N18
G1L165 = CARRY(!G1L163 # !G1_rWR2_ADDR[17]);


--G1L459 is Sdram_Control_4Port:u6|rWR2_ADDR~1882 at LCCOMB_X18_Y13_N6
G1L459 = C1_oRST_0 & G1L46 & G1L164;


--G1L310 is Sdram_Control_4Port:u6|rRD1_ADDR[17]~1646 at LCCOMB_X21_Y14_N20
G1L310 = G1_rRD1_ADDR[17] & !G1L308 # !G1_rRD1_ADDR[17] & (G1L308 # GND);

--G1L311 is Sdram_Control_4Port:u6|rRD1_ADDR[17]~1647 at LCCOMB_X21_Y14_N20
G1L311 = CARRY(!G1L308 # !G1_rRD1_ADDR[17]);


--G1L419 is Sdram_Control_4Port:u6|rWR1_ADDR[18]~1122 at LCCOMB_X19_Y13_N22
G1L419 = G1_rWR1_ADDR[18] & (G1L417 $ GND) # !G1_rWR1_ADDR[18] & !G1L417 & VCC;

--G1L420 is Sdram_Control_4Port:u6|rWR1_ADDR[18]~1123 at LCCOMB_X19_Y13_N22
G1L420 = CARRY(G1_rWR1_ADDR[18] & !G1L417);


--G1L369 is Sdram_Control_4Port:u6|rRD2_ADDR[18]~1634 at LCCOMB_X19_Y15_N22
G1L369 = G1_rRD2_ADDR[18] & (G1L367 $ GND) # !G1_rRD2_ADDR[18] & !G1L367 & VCC;

--G1L370 is Sdram_Control_4Port:u6|rRD2_ADDR[18]~1635 at LCCOMB_X19_Y15_N22
G1L370 = CARRY(G1_rRD2_ADDR[18] & !G1L367);


--G1L166 is Sdram_Control_4Port:u6|add~2889 at LCCOMB_X18_Y14_N20
G1L166 = G1_rWR2_ADDR[18] & (G1L165 $ GND) # !G1_rWR2_ADDR[18] & !G1L165 & VCC;

--G1L167 is Sdram_Control_4Port:u6|add~2890 at LCCOMB_X18_Y14_N20
G1L167 = CARRY(G1_rWR2_ADDR[18] & !G1L165);


--G1L460 is Sdram_Control_4Port:u6|rWR2_ADDR~1883 at LCCOMB_X18_Y13_N18
G1L460 = G1L166 & C1_oRST_0 & G1L46;


--G1L313 is Sdram_Control_4Port:u6|rRD1_ADDR[18]~1648 at LCCOMB_X21_Y14_N22
G1L313 = G1_rRD1_ADDR[18] & (G1L311 $ GND) # !G1_rRD1_ADDR[18] & !G1L311 & VCC;

--G1L314 is Sdram_Control_4Port:u6|rRD1_ADDR[18]~1649 at LCCOMB_X21_Y14_N22
G1L314 = CARRY(G1_rRD1_ADDR[18] & !G1L311);


--G1L372 is Sdram_Control_4Port:u6|rRD2_ADDR[19]~1636 at LCCOMB_X19_Y15_N24
G1L372 = G1_rRD2_ADDR[19] & !G1L370 # !G1_rRD2_ADDR[19] & (G1L370 # GND);

--G1L373 is Sdram_Control_4Port:u6|rRD2_ADDR[19]~1637 at LCCOMB_X19_Y15_N24
G1L373 = CARRY(!G1L370 # !G1_rRD2_ADDR[19]);


--G1L422 is Sdram_Control_4Port:u6|rWR1_ADDR[19]~1124 at LCCOMB_X19_Y13_N24
G1L422 = G1_rWR1_ADDR[19] & !G1L420 # !G1_rWR1_ADDR[19] & (G1L420 # GND);

--G1L423 is Sdram_Control_4Port:u6|rWR1_ADDR[19]~1125 at LCCOMB_X19_Y13_N24
G1L423 = CARRY(!G1L420 # !G1_rWR1_ADDR[19]);


--G1L168 is Sdram_Control_4Port:u6|add~2891 at LCCOMB_X18_Y14_N22
G1L168 = G1_rWR2_ADDR[19] & !G1L167 # !G1_rWR2_ADDR[19] & (G1L167 # GND);

--G1L169 is Sdram_Control_4Port:u6|add~2892 at LCCOMB_X18_Y14_N22
G1L169 = CARRY(!G1L167 # !G1_rWR2_ADDR[19]);


--G1L461 is Sdram_Control_4Port:u6|rWR2_ADDR~1884 at LCCOMB_X18_Y13_N26
G1L461 = C1_oRST_0 & G1L46 & G1L168;


--G1L316 is Sdram_Control_4Port:u6|rRD1_ADDR[19]~1650 at LCCOMB_X21_Y14_N24
G1L316 = G1_rRD1_ADDR[19] & !G1L314 # !G1_rRD1_ADDR[19] & (G1L314 # GND);

--G1L317 is Sdram_Control_4Port:u6|rRD1_ADDR[19]~1651 at LCCOMB_X21_Y14_N24
G1L317 = CARRY(!G1L314 # !G1_rRD1_ADDR[19]);


--G1L425 is Sdram_Control_4Port:u6|rWR1_ADDR[20]~1126 at LCCOMB_X19_Y13_N26
G1L425 = G1_rWR1_ADDR[20] & (G1L423 $ GND) # !G1_rWR1_ADDR[20] & !G1L423 & VCC;

--G1L426 is Sdram_Control_4Port:u6|rWR1_ADDR[20]~1127 at LCCOMB_X19_Y13_N26
G1L426 = CARRY(G1_rWR1_ADDR[20] & !G1L423);


--G1L428 is Sdram_Control_4Port:u6|rWR1_ADDR[21]~1128 at LCCOMB_X19_Y13_N28
G1L428 = G1_rWR1_ADDR[21] & !G1L426 # !G1_rWR1_ADDR[21] & (G1L426 # GND);

--G1L429 is Sdram_Control_4Port:u6|rWR1_ADDR[21]~1129 at LCCOMB_X19_Y13_N28
G1L429 = CARRY(!G1L426 # !G1_rWR1_ADDR[21]);


--G1L431 is Sdram_Control_4Port:u6|rWR1_ADDR[22]~1130 at LCCOMB_X19_Y13_N30
G1L431 = G1L429 $ !G1_rWR1_ADDR[22];


--G1L375 is Sdram_Control_4Port:u6|rRD2_ADDR[20]~1638 at LCCOMB_X19_Y15_N26
G1L375 = G1_rRD2_ADDR[20] & (G1L373 $ GND) # !G1_rRD2_ADDR[20] & !G1L373 & VCC;

--G1L376 is Sdram_Control_4Port:u6|rRD2_ADDR[20]~1639 at LCCOMB_X19_Y15_N26
G1L376 = CARRY(G1_rRD2_ADDR[20] & !G1L373);


--G1L378 is Sdram_Control_4Port:u6|rRD2_ADDR[21]~1640 at LCCOMB_X19_Y15_N28
G1L378 = G1_rRD2_ADDR[21] & !G1L376 # !G1_rRD2_ADDR[21] & (G1L376 # GND);

--G1L379 is Sdram_Control_4Port:u6|rRD2_ADDR[21]~1641 at LCCOMB_X19_Y15_N28
G1L379 = CARRY(!G1L376 # !G1_rRD2_ADDR[21]);


--G1L381 is Sdram_Control_4Port:u6|rRD2_ADDR[22]~1642 at LCCOMB_X19_Y15_N30
G1L381 = G1L379 $ !G1_rRD2_ADDR[22];


--G1L170 is Sdram_Control_4Port:u6|add~2893 at LCCOMB_X18_Y14_N24
G1L170 = G1_rWR2_ADDR[20] & (G1L169 $ GND) # !G1_rWR2_ADDR[20] & !G1L169 & VCC;

--G1L171 is Sdram_Control_4Port:u6|add~2894 at LCCOMB_X18_Y14_N24
G1L171 = CARRY(G1_rWR2_ADDR[20] & !G1L169);


--G1L172 is Sdram_Control_4Port:u6|add~2895 at LCCOMB_X18_Y14_N26
G1L172 = G1_rWR2_ADDR[21] & !G1L171 # !G1_rWR2_ADDR[21] & (G1L171 # GND);

--G1L173 is Sdram_Control_4Port:u6|add~2896 at LCCOMB_X18_Y14_N26
G1L173 = CARRY(!G1L171 # !G1_rWR2_ADDR[21]);


--G1L174 is Sdram_Control_4Port:u6|add~2897 at LCCOMB_X18_Y14_N28
G1L174 = G1_rWR2_ADDR[22] $ !G1L173;


--G1L462 is Sdram_Control_4Port:u6|rWR2_ADDR~1885 at LCCOMB_X18_Y13_N8
G1L462 = C1_oRST_0 & G1L174 & G1L46;


--G1L319 is Sdram_Control_4Port:u6|rRD1_ADDR[20]~1652 at LCCOMB_X21_Y14_N26
G1L319 = G1_rRD1_ADDR[20] & (G1L317 $ GND) # !G1_rRD1_ADDR[20] & !G1L317 & VCC;

--G1L320 is Sdram_Control_4Port:u6|rRD1_ADDR[20]~1653 at LCCOMB_X21_Y14_N26
G1L320 = CARRY(G1_rRD1_ADDR[20] & !G1L317);


--G1L328 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1654 at LCCOMB_X21_Y14_N28
G1L328 = G1_rRD1_ADDR[21] & !G1L320 # !G1_rRD1_ADDR[21] & (G1L320 # GND);

--G1L329 is Sdram_Control_4Port:u6|rRD1_ADDR[21]~1655 at LCCOMB_X21_Y14_N28
G1L329 = CARRY(!G1L320 # !G1_rRD1_ADDR[21]);


--G1L331 is Sdram_Control_4Port:u6|rRD1_ADDR[22]~1656 at LCCOMB_X21_Y14_N30
G1L331 = G1L329 $ !G1_rRD1_ADDR[22];


--G1L463 is Sdram_Control_4Port:u6|rWR2_ADDR~1886 at LCCOMB_X22_Y13_N10
G1L463 = G1_WR_MASK[1] & G1_mWR_DONE;


--G1L464 is Sdram_Control_4Port:u6|rWR2_ADDR~1887 at LCCOMB_X18_Y14_N30
G1L464 = G1L463 & (G1L170 # !G1L46) # !G1L463 & (G1_rWR2_ADDR[20]);


--G1L465 is Sdram_Control_4Port:u6|rWR2_ADDR~1888 at LCCOMB_X18_Y13_N24
G1L465 = C1_oRST_0 & G1L46 & G1L172;


--E1L139 is RAW2RGB:u4|mDVAL~25 at LCCOMB_X57_Y1_N4
E1L139 = !D1_Y_Cont[0] & !D1_X_Cont[0] & D1_mCCD_LVAL & D1_mCCD_FVAL;


--E1_mDATAd_1[0] is RAW2RGB:u4|mDATAd_1[0] at LCFF_X22_Y10_N21
E1_mDATAd_1[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[0],  ,  , VCC);


--N1_q_b[0] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[0] at M4K_X26_Y9
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[0]_PORT_A_data_in = BUS(D1_mCCD_DATA[0], N1_q_b[0]);
N1_q_b[0]_PORT_A_data_in_reg = DFFE(N1_q_b[0]_PORT_A_data_in, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[0]_PORT_A_address_reg = DFFE(N1_q_b[0]_PORT_A_address, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[0]_PORT_B_address_reg = DFFE(N1_q_b[0]_PORT_B_address, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_A_write_enable = VCC;
N1_q_b[0]_PORT_A_write_enable_reg = DFFE(N1_q_b[0]_PORT_A_write_enable, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_B_read_enable = VCC;
N1_q_b[0]_PORT_B_read_enable_reg = DFFE(N1_q_b[0]_PORT_B_read_enable, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_clock_0 = GLOBAL(A1L11);
N1_q_b[0]_clock_enable_0 = D1_oDVAL;
N1_q_b[0]_PORT_B_data_out = MEMORY(N1_q_b[0]_PORT_A_data_in_reg, , N1_q_b[0]_PORT_A_address_reg, N1_q_b[0]_PORT_B_address_reg, N1_q_b[0]_PORT_A_write_enable_reg, N1_q_b[0]_PORT_B_read_enable_reg, , , N1_q_b[0]_clock_0, , N1_q_b[0]_clock_enable_0, , , );
N1_q_b[0]_PORT_B_data_out_reg = DFFE(N1_q_b[0]_PORT_B_data_out, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0] = N1_q_b[0]_PORT_B_data_out_reg[0];

--N1_q_b[10] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[10] at M4K_X26_Y9
N1_q_b[0]_PORT_A_data_in = BUS(D1_mCCD_DATA[0], N1_q_b[0]);
N1_q_b[0]_PORT_A_data_in_reg = DFFE(N1_q_b[0]_PORT_A_data_in, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[0]_PORT_A_address_reg = DFFE(N1_q_b[0]_PORT_A_address, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[0]_PORT_B_address_reg = DFFE(N1_q_b[0]_PORT_B_address, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_A_write_enable = VCC;
N1_q_b[0]_PORT_A_write_enable_reg = DFFE(N1_q_b[0]_PORT_A_write_enable, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_PORT_B_read_enable = VCC;
N1_q_b[0]_PORT_B_read_enable_reg = DFFE(N1_q_b[0]_PORT_B_read_enable, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[0]_clock_0 = GLOBAL(A1L11);
N1_q_b[0]_clock_enable_0 = D1_oDVAL;
N1_q_b[0]_PORT_B_data_out = MEMORY(N1_q_b[0]_PORT_A_data_in_reg, , N1_q_b[0]_PORT_A_address_reg, N1_q_b[0]_PORT_B_address_reg, N1_q_b[0]_PORT_A_write_enable_reg, N1_q_b[0]_PORT_B_read_enable_reg, , , N1_q_b[0]_clock_0, , N1_q_b[0]_clock_enable_0, , , );
N1_q_b[0]_PORT_B_data_out_reg = DFFE(N1_q_b[0]_PORT_B_data_out, N1_q_b[0]_clock_0, , , N1_q_b[0]_clock_enable_0);
N1_q_b[10] = N1_q_b[0]_PORT_B_data_out_reg[1];


--E1L32 is RAW2RGB:u4|mCCD_B~150 at LCCOMB_X22_Y10_N28
E1L32 = D1_X_Cont[0] & (E1_mDATAd_1[0] # D1_Y_Cont[0]) # !D1_X_Cont[0] & (N1_q_b[0] & !D1_Y_Cont[0]);


--E1_mDATAd_0[0] is RAW2RGB:u4|mDATAd_0[0] at LCFF_X22_Y10_N25
E1_mDATAd_0[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[10],  ,  , VCC);


--E1L33 is RAW2RGB:u4|mCCD_B~151 at LCCOMB_X22_Y10_N16
E1L33 = E1L32 & (E1_mDATAd_0[0] # !D1_Y_Cont[0]) # !E1L32 & (N1_q_b[10] & D1_Y_Cont[0]);


--J1L4 is Mirror_Col:u8|Z_Cont[0]~163 at LCCOMB_X14_Y11_N12
J1L4 = J1_Z_Cont[0] & (E1_mDVAL $ VCC) # !J1_Z_Cont[0] & E1_mDVAL & VCC;

--J1L5 is Mirror_Col:u8|Z_Cont[0]~164 at LCCOMB_X14_Y11_N12
J1L5 = CARRY(J1_Z_Cont[0] & E1_mDVAL);


--J1L1 is Mirror_Col:u8|LessThan~84 at LCCOMB_X14_Y11_N0
J1L1 = J1_Z_Cont[9] & (J1_Z_Cont[7] # J1_Z_Cont[8]);


--J1L8 is Mirror_Col:u8|Z_Cont[1]~165 at LCCOMB_X14_Y11_N14
J1L8 = J1_Z_Cont[1] & !J1L5 # !J1_Z_Cont[1] & (J1L5 # GND);

--J1L9 is Mirror_Col:u8|Z_Cont[1]~166 at LCCOMB_X14_Y11_N14
J1L9 = CARRY(!J1L5 # !J1_Z_Cont[1]);


--J1L12 is Mirror_Col:u8|Z_Cont[2]~167 at LCCOMB_X14_Y11_N16
J1L12 = J1_Z_Cont[2] & (J1L9 $ GND) # !J1_Z_Cont[2] & !J1L9 & VCC;

--J1L13 is Mirror_Col:u8|Z_Cont[2]~168 at LCCOMB_X14_Y11_N16
J1L13 = CARRY(J1_Z_Cont[2] & !J1L9);


--J1L16 is Mirror_Col:u8|Z_Cont[3]~169 at LCCOMB_X14_Y11_N18
J1L16 = J1_Z_Cont[3] & !J1L13 # !J1_Z_Cont[3] & (J1L13 # GND);

--J1L17 is Mirror_Col:u8|Z_Cont[3]~170 at LCCOMB_X14_Y11_N18
J1L17 = CARRY(!J1L13 # !J1_Z_Cont[3]);


--J1L20 is Mirror_Col:u8|Z_Cont[4]~171 at LCCOMB_X14_Y11_N20
J1L20 = J1_Z_Cont[4] & (J1L17 $ GND) # !J1_Z_Cont[4] & !J1L17 & VCC;

--J1L21 is Mirror_Col:u8|Z_Cont[4]~172 at LCCOMB_X14_Y11_N20
J1L21 = CARRY(J1_Z_Cont[4] & !J1L17);


--J1L24 is Mirror_Col:u8|Z_Cont[5]~173 at LCCOMB_X14_Y11_N22
J1L24 = J1_Z_Cont[5] & !J1L21 # !J1_Z_Cont[5] & (J1L21 # GND);

--J1L25 is Mirror_Col:u8|Z_Cont[5]~174 at LCCOMB_X14_Y11_N22
J1L25 = CARRY(!J1L21 # !J1_Z_Cont[5]);


--J1L28 is Mirror_Col:u8|Z_Cont[6]~175 at LCCOMB_X14_Y11_N24
J1L28 = J1_Z_Cont[6] & (J1L25 $ GND) # !J1_Z_Cont[6] & !J1L25 & VCC;

--J1L29 is Mirror_Col:u8|Z_Cont[6]~176 at LCCOMB_X14_Y11_N24
J1L29 = CARRY(J1_Z_Cont[6] & !J1L25);


--J1L32 is Mirror_Col:u8|Z_Cont[7]~177 at LCCOMB_X14_Y11_N26
J1L32 = J1_Z_Cont[7] & !J1L29 # !J1_Z_Cont[7] & (J1L29 # GND);

--J1L33 is Mirror_Col:u8|Z_Cont[7]~178 at LCCOMB_X14_Y11_N26
J1L33 = CARRY(!J1L29 # !J1_Z_Cont[7]);


--J1L35 is Mirror_Col:u8|Z_Cont[8]~179 at LCCOMB_X14_Y11_N28
J1L35 = J1_Z_Cont[8] & (J1L33 $ GND) # !J1_Z_Cont[8] & !J1L33 & VCC;

--J1L36 is Mirror_Col:u8|Z_Cont[8]~180 at LCCOMB_X14_Y11_N28
J1L36 = CARRY(J1_Z_Cont[8] & !J1L33);


--J1L38 is Mirror_Col:u8|Z_Cont[9]~181 at LCCOMB_X14_Y11_N30
J1L38 = J1L36 $ J1_Z_Cont[9];


--E1L96 is RAW2RGB:u4|mCCD_R~941 at LCCOMB_X22_Y10_N24
E1L96 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[0] # !D1_Y_Cont[0] & (E1_mDATAd_0[0]));


--E1L97 is RAW2RGB:u4|mCCD_R~942 at LCCOMB_X22_Y10_N22
E1L97 = D1_X_Cont[0] & (E1L96 & N1_q_b[0] # !E1L96 & (N1_q_b[10])) # !D1_X_Cont[0] & (E1L96);


--E1_mDATAd_1[1] is RAW2RGB:u4|mDATAd_1[1] at LCFF_X23_Y11_N15
E1_mDATAd_1[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[1],  ,  , VCC);


--N1_q_b[1] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[1] at M4K_X26_Y12
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[1]_PORT_A_data_in = BUS(D1_mCCD_DATA[1], N1_q_b[1]);
N1_q_b[1]_PORT_A_data_in_reg = DFFE(N1_q_b[1]_PORT_A_data_in, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[1]_PORT_A_address_reg = DFFE(N1_q_b[1]_PORT_A_address, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[1]_PORT_B_address_reg = DFFE(N1_q_b[1]_PORT_B_address, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_A_write_enable = VCC;
N1_q_b[1]_PORT_A_write_enable_reg = DFFE(N1_q_b[1]_PORT_A_write_enable, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_B_read_enable = VCC;
N1_q_b[1]_PORT_B_read_enable_reg = DFFE(N1_q_b[1]_PORT_B_read_enable, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_clock_0 = GLOBAL(A1L11);
N1_q_b[1]_clock_enable_0 = D1_oDVAL;
N1_q_b[1]_PORT_B_data_out = MEMORY(N1_q_b[1]_PORT_A_data_in_reg, , N1_q_b[1]_PORT_A_address_reg, N1_q_b[1]_PORT_B_address_reg, N1_q_b[1]_PORT_A_write_enable_reg, N1_q_b[1]_PORT_B_read_enable_reg, , , N1_q_b[1]_clock_0, , N1_q_b[1]_clock_enable_0, , , );
N1_q_b[1]_PORT_B_data_out_reg = DFFE(N1_q_b[1]_PORT_B_data_out, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1] = N1_q_b[1]_PORT_B_data_out_reg[0];

--N1_q_b[11] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[11] at M4K_X26_Y12
N1_q_b[1]_PORT_A_data_in = BUS(D1_mCCD_DATA[1], N1_q_b[1]);
N1_q_b[1]_PORT_A_data_in_reg = DFFE(N1_q_b[1]_PORT_A_data_in, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[1]_PORT_A_address_reg = DFFE(N1_q_b[1]_PORT_A_address, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[1]_PORT_B_address_reg = DFFE(N1_q_b[1]_PORT_B_address, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_A_write_enable = VCC;
N1_q_b[1]_PORT_A_write_enable_reg = DFFE(N1_q_b[1]_PORT_A_write_enable, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_PORT_B_read_enable = VCC;
N1_q_b[1]_PORT_B_read_enable_reg = DFFE(N1_q_b[1]_PORT_B_read_enable, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[1]_clock_0 = GLOBAL(A1L11);
N1_q_b[1]_clock_enable_0 = D1_oDVAL;
N1_q_b[1]_PORT_B_data_out = MEMORY(N1_q_b[1]_PORT_A_data_in_reg, , N1_q_b[1]_PORT_A_address_reg, N1_q_b[1]_PORT_B_address_reg, N1_q_b[1]_PORT_A_write_enable_reg, N1_q_b[1]_PORT_B_read_enable_reg, , , N1_q_b[1]_clock_0, , N1_q_b[1]_clock_enable_0, , , );
N1_q_b[1]_PORT_B_data_out_reg = DFFE(N1_q_b[1]_PORT_B_data_out, N1_q_b[1]_clock_0, , , N1_q_b[1]_clock_enable_0);
N1_q_b[11] = N1_q_b[1]_PORT_B_data_out_reg[1];


--E1L34 is RAW2RGB:u4|mCCD_B~152 at LCCOMB_X23_Y11_N14
E1L34 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & (E1_mDATAd_1[1]) # !D1_X_Cont[0] & N1_q_b[1]);


--E1_mDATAd_0[1] is RAW2RGB:u4|mDATAd_0[1] at LCFF_X23_Y10_N1
E1_mDATAd_0[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[11],  ,  , VCC);


--E1L35 is RAW2RGB:u4|mCCD_B~153 at LCCOMB_X23_Y11_N26
E1L35 = D1_Y_Cont[0] & (E1L34 & (E1_mDATAd_0[1]) # !E1L34 & N1_q_b[11]) # !D1_Y_Cont[0] & (E1L34);


--E1L98 is RAW2RGB:u4|mCCD_R~943 at LCCOMB_X23_Y11_N22
E1L98 = D1_X_Cont[0] & D1_Y_Cont[0] # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[1] # !D1_Y_Cont[0] & (E1_mDATAd_0[1]));


--E1L99 is RAW2RGB:u4|mCCD_R~944 at LCCOMB_X23_Y11_N28
E1L99 = D1_X_Cont[0] & (E1L98 & N1_q_b[1] # !E1L98 & (N1_q_b[11])) # !D1_X_Cont[0] & E1L98;


--E1_mDATAd_1[2] is RAW2RGB:u4|mDATAd_1[2] at LCFF_X22_Y10_N19
E1_mDATAd_1[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[2],  ,  , VCC);


--N1_q_b[2] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[2] at M4K_X26_Y10
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[2]_PORT_A_data_in = BUS(D1_mCCD_DATA[2], N1_q_b[2]);
N1_q_b[2]_PORT_A_data_in_reg = DFFE(N1_q_b[2]_PORT_A_data_in, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[2]_PORT_A_address_reg = DFFE(N1_q_b[2]_PORT_A_address, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[2]_PORT_B_address_reg = DFFE(N1_q_b[2]_PORT_B_address, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_A_write_enable = VCC;
N1_q_b[2]_PORT_A_write_enable_reg = DFFE(N1_q_b[2]_PORT_A_write_enable, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_B_read_enable = VCC;
N1_q_b[2]_PORT_B_read_enable_reg = DFFE(N1_q_b[2]_PORT_B_read_enable, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_clock_0 = GLOBAL(A1L11);
N1_q_b[2]_clock_enable_0 = D1_oDVAL;
N1_q_b[2]_PORT_B_data_out = MEMORY(N1_q_b[2]_PORT_A_data_in_reg, , N1_q_b[2]_PORT_A_address_reg, N1_q_b[2]_PORT_B_address_reg, N1_q_b[2]_PORT_A_write_enable_reg, N1_q_b[2]_PORT_B_read_enable_reg, , , N1_q_b[2]_clock_0, , N1_q_b[2]_clock_enable_0, , , );
N1_q_b[2]_PORT_B_data_out_reg = DFFE(N1_q_b[2]_PORT_B_data_out, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2] = N1_q_b[2]_PORT_B_data_out_reg[0];

--N1_q_b[12] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[12] at M4K_X26_Y10
N1_q_b[2]_PORT_A_data_in = BUS(D1_mCCD_DATA[2], N1_q_b[2]);
N1_q_b[2]_PORT_A_data_in_reg = DFFE(N1_q_b[2]_PORT_A_data_in, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[2]_PORT_A_address_reg = DFFE(N1_q_b[2]_PORT_A_address, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[2]_PORT_B_address_reg = DFFE(N1_q_b[2]_PORT_B_address, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_A_write_enable = VCC;
N1_q_b[2]_PORT_A_write_enable_reg = DFFE(N1_q_b[2]_PORT_A_write_enable, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_PORT_B_read_enable = VCC;
N1_q_b[2]_PORT_B_read_enable_reg = DFFE(N1_q_b[2]_PORT_B_read_enable, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[2]_clock_0 = GLOBAL(A1L11);
N1_q_b[2]_clock_enable_0 = D1_oDVAL;
N1_q_b[2]_PORT_B_data_out = MEMORY(N1_q_b[2]_PORT_A_data_in_reg, , N1_q_b[2]_PORT_A_address_reg, N1_q_b[2]_PORT_B_address_reg, N1_q_b[2]_PORT_A_write_enable_reg, N1_q_b[2]_PORT_B_read_enable_reg, , , N1_q_b[2]_clock_0, , N1_q_b[2]_clock_enable_0, , , );
N1_q_b[2]_PORT_B_data_out_reg = DFFE(N1_q_b[2]_PORT_B_data_out, N1_q_b[2]_clock_0, , , N1_q_b[2]_clock_enable_0);
N1_q_b[12] = N1_q_b[2]_PORT_B_data_out_reg[1];


--E1L36 is RAW2RGB:u4|mCCD_B~154 at LCCOMB_X22_Y10_N26
E1L36 = D1_Y_Cont[0] & D1_X_Cont[0] # !D1_Y_Cont[0] & (D1_X_Cont[0] & (E1_mDATAd_1[2]) # !D1_X_Cont[0] & N1_q_b[2]);


--E1_mDATAd_0[2] is RAW2RGB:u4|mDATAd_0[2] at LCFF_X22_Y10_N11
E1_mDATAd_0[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[12],  ,  , VCC);


--E1L37 is RAW2RGB:u4|mCCD_B~155 at LCCOMB_X22_Y10_N30
E1L37 = D1_Y_Cont[0] & (E1L36 & (E1_mDATAd_0[2]) # !E1L36 & N1_q_b[12]) # !D1_Y_Cont[0] & E1L36;


--E1L100 is RAW2RGB:u4|mCCD_R~945 at LCCOMB_X22_Y10_N10
E1L100 = D1_Y_Cont[0] & (D1_X_Cont[0] # E1_mDATAd_1[2]) # !D1_Y_Cont[0] & !D1_X_Cont[0] & E1_mDATAd_0[2];


--E1L101 is RAW2RGB:u4|mCCD_R~946 at LCCOMB_X22_Y10_N0
E1L101 = D1_X_Cont[0] & (E1L100 & (N1_q_b[2]) # !E1L100 & N1_q_b[12]) # !D1_X_Cont[0] & (E1L100);


--E1_mDATAd_1[3] is RAW2RGB:u4|mDATAd_1[3] at LCFF_X22_Y10_N15
E1_mDATAd_1[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[3],  ,  , VCC);


--N1_q_b[3] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[3] at M4K_X52_Y10
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[3]_PORT_A_data_in = BUS(D1_mCCD_DATA[3], N1_q_b[3]);
N1_q_b[3]_PORT_A_data_in_reg = DFFE(N1_q_b[3]_PORT_A_data_in, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[3]_PORT_A_address_reg = DFFE(N1_q_b[3]_PORT_A_address, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[3]_PORT_B_address_reg = DFFE(N1_q_b[3]_PORT_B_address, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_A_write_enable = VCC;
N1_q_b[3]_PORT_A_write_enable_reg = DFFE(N1_q_b[3]_PORT_A_write_enable, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_B_read_enable = VCC;
N1_q_b[3]_PORT_B_read_enable_reg = DFFE(N1_q_b[3]_PORT_B_read_enable, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_clock_0 = GLOBAL(A1L11);
N1_q_b[3]_clock_enable_0 = D1_oDVAL;
N1_q_b[3]_PORT_B_data_out = MEMORY(N1_q_b[3]_PORT_A_data_in_reg, , N1_q_b[3]_PORT_A_address_reg, N1_q_b[3]_PORT_B_address_reg, N1_q_b[3]_PORT_A_write_enable_reg, N1_q_b[3]_PORT_B_read_enable_reg, , , N1_q_b[3]_clock_0, , N1_q_b[3]_clock_enable_0, , , );
N1_q_b[3]_PORT_B_data_out_reg = DFFE(N1_q_b[3]_PORT_B_data_out, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3] = N1_q_b[3]_PORT_B_data_out_reg[0];

--N1_q_b[13] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[13] at M4K_X52_Y10
N1_q_b[3]_PORT_A_data_in = BUS(D1_mCCD_DATA[3], N1_q_b[3]);
N1_q_b[3]_PORT_A_data_in_reg = DFFE(N1_q_b[3]_PORT_A_data_in, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[3]_PORT_A_address_reg = DFFE(N1_q_b[3]_PORT_A_address, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[3]_PORT_B_address_reg = DFFE(N1_q_b[3]_PORT_B_address, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_A_write_enable = VCC;
N1_q_b[3]_PORT_A_write_enable_reg = DFFE(N1_q_b[3]_PORT_A_write_enable, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_PORT_B_read_enable = VCC;
N1_q_b[3]_PORT_B_read_enable_reg = DFFE(N1_q_b[3]_PORT_B_read_enable, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[3]_clock_0 = GLOBAL(A1L11);
N1_q_b[3]_clock_enable_0 = D1_oDVAL;
N1_q_b[3]_PORT_B_data_out = MEMORY(N1_q_b[3]_PORT_A_data_in_reg, , N1_q_b[3]_PORT_A_address_reg, N1_q_b[3]_PORT_B_address_reg, N1_q_b[3]_PORT_A_write_enable_reg, N1_q_b[3]_PORT_B_read_enable_reg, , , N1_q_b[3]_clock_0, , N1_q_b[3]_clock_enable_0, , , );
N1_q_b[3]_PORT_B_data_out_reg = DFFE(N1_q_b[3]_PORT_B_data_out, N1_q_b[3]_clock_0, , , N1_q_b[3]_clock_enable_0);
N1_q_b[13] = N1_q_b[3]_PORT_B_data_out_reg[1];


--E1L38 is RAW2RGB:u4|mCCD_B~156 at LCCOMB_X22_Y10_N4
E1L38 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & (E1_mDATAd_1[3]) # !D1_X_Cont[0] & N1_q_b[3]);


--E1_mDATAd_0[3] is RAW2RGB:u4|mDATAd_0[3] at LCFF_X22_Y10_N3
E1_mDATAd_0[3] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[13],  ,  , VCC);


--E1L39 is RAW2RGB:u4|mCCD_B~157 at LCCOMB_X22_Y10_N8
E1L39 = D1_Y_Cont[0] & (E1L38 & (E1_mDATAd_0[3]) # !E1L38 & N1_q_b[13]) # !D1_Y_Cont[0] & (E1L38);


--E1L102 is RAW2RGB:u4|mCCD_R~947 at LCCOMB_X22_Y10_N2
E1L102 = D1_Y_Cont[0] & (D1_X_Cont[0] # E1_mDATAd_1[3]) # !D1_Y_Cont[0] & !D1_X_Cont[0] & E1_mDATAd_0[3];


--E1L103 is RAW2RGB:u4|mCCD_R~948 at LCCOMB_X22_Y10_N12
E1L103 = D1_X_Cont[0] & (E1L102 & N1_q_b[3] # !E1L102 & (N1_q_b[13])) # !D1_X_Cont[0] & (E1L102);


--E1_mDATAd_1[4] is RAW2RGB:u4|mDATAd_1[4] at LCFF_X23_Y9_N3
E1_mDATAd_1[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[4],  ,  , VCC);


--N1_q_b[4] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[4] at M4K_X26_Y8
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[4]_PORT_A_data_in = BUS(D1_mCCD_DATA[4], N1_q_b[4]);
N1_q_b[4]_PORT_A_data_in_reg = DFFE(N1_q_b[4]_PORT_A_data_in, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[4]_PORT_A_address_reg = DFFE(N1_q_b[4]_PORT_A_address, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[4]_PORT_B_address_reg = DFFE(N1_q_b[4]_PORT_B_address, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_A_write_enable = VCC;
N1_q_b[4]_PORT_A_write_enable_reg = DFFE(N1_q_b[4]_PORT_A_write_enable, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_B_read_enable = VCC;
N1_q_b[4]_PORT_B_read_enable_reg = DFFE(N1_q_b[4]_PORT_B_read_enable, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_clock_0 = GLOBAL(A1L11);
N1_q_b[4]_clock_enable_0 = D1_oDVAL;
N1_q_b[4]_PORT_B_data_out = MEMORY(N1_q_b[4]_PORT_A_data_in_reg, , N1_q_b[4]_PORT_A_address_reg, N1_q_b[4]_PORT_B_address_reg, N1_q_b[4]_PORT_A_write_enable_reg, N1_q_b[4]_PORT_B_read_enable_reg, , , N1_q_b[4]_clock_0, , N1_q_b[4]_clock_enable_0, , , );
N1_q_b[4]_PORT_B_data_out_reg = DFFE(N1_q_b[4]_PORT_B_data_out, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4] = N1_q_b[4]_PORT_B_data_out_reg[0];

--N1_q_b[14] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[14] at M4K_X26_Y8
N1_q_b[4]_PORT_A_data_in = BUS(D1_mCCD_DATA[4], N1_q_b[4]);
N1_q_b[4]_PORT_A_data_in_reg = DFFE(N1_q_b[4]_PORT_A_data_in, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[4]_PORT_A_address_reg = DFFE(N1_q_b[4]_PORT_A_address, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[4]_PORT_B_address_reg = DFFE(N1_q_b[4]_PORT_B_address, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_A_write_enable = VCC;
N1_q_b[4]_PORT_A_write_enable_reg = DFFE(N1_q_b[4]_PORT_A_write_enable, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_PORT_B_read_enable = VCC;
N1_q_b[4]_PORT_B_read_enable_reg = DFFE(N1_q_b[4]_PORT_B_read_enable, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[4]_clock_0 = GLOBAL(A1L11);
N1_q_b[4]_clock_enable_0 = D1_oDVAL;
N1_q_b[4]_PORT_B_data_out = MEMORY(N1_q_b[4]_PORT_A_data_in_reg, , N1_q_b[4]_PORT_A_address_reg, N1_q_b[4]_PORT_B_address_reg, N1_q_b[4]_PORT_A_write_enable_reg, N1_q_b[4]_PORT_B_read_enable_reg, , , N1_q_b[4]_clock_0, , N1_q_b[4]_clock_enable_0, , , );
N1_q_b[4]_PORT_B_data_out_reg = DFFE(N1_q_b[4]_PORT_B_data_out, N1_q_b[4]_clock_0, , , N1_q_b[4]_clock_enable_0);
N1_q_b[14] = N1_q_b[4]_PORT_B_data_out_reg[1];


--E1L40 is RAW2RGB:u4|mCCD_B~158 at LCCOMB_X23_Y9_N10
E1L40 = D1_X_Cont[0] & (D1_Y_Cont[0] # E1_mDATAd_1[4]) # !D1_X_Cont[0] & !D1_Y_Cont[0] & N1_q_b[4];


--E1_mDATAd_0[4] is RAW2RGB:u4|mDATAd_0[4] at LCFF_X23_Y9_N21
E1_mDATAd_0[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[14],  ,  , VCC);


--E1L41 is RAW2RGB:u4|mCCD_B~159 at LCCOMB_X23_Y9_N8
E1L41 = D1_Y_Cont[0] & (E1L40 & E1_mDATAd_0[4] # !E1L40 & (N1_q_b[14])) # !D1_Y_Cont[0] & (E1L40);


--E1L104 is RAW2RGB:u4|mCCD_R~949 at LCCOMB_X23_Y9_N2
E1L104 = D1_Y_Cont[0] & (E1_mDATAd_1[4] # D1_X_Cont[0]) # !D1_Y_Cont[0] & E1_mDATAd_0[4] & (!D1_X_Cont[0]);


--E1L105 is RAW2RGB:u4|mCCD_R~950 at LCCOMB_X23_Y9_N28
E1L105 = D1_X_Cont[0] & (E1L104 & (N1_q_b[4]) # !E1L104 & N1_q_b[14]) # !D1_X_Cont[0] & (E1L104);


--E1_mDATAd_1[5] is RAW2RGB:u4|mDATAd_1[5] at LCFF_X23_Y11_N5
E1_mDATAd_1[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[5],  ,  , VCC);


--N1_q_b[5] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[5] at M4K_X52_Y13
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[5]_PORT_A_data_in = BUS(D1_mCCD_DATA[5], N1_q_b[5]);
N1_q_b[5]_PORT_A_data_in_reg = DFFE(N1_q_b[5]_PORT_A_data_in, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[5]_PORT_A_address_reg = DFFE(N1_q_b[5]_PORT_A_address, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[5]_PORT_B_address_reg = DFFE(N1_q_b[5]_PORT_B_address, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_A_write_enable = VCC;
N1_q_b[5]_PORT_A_write_enable_reg = DFFE(N1_q_b[5]_PORT_A_write_enable, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_B_read_enable = VCC;
N1_q_b[5]_PORT_B_read_enable_reg = DFFE(N1_q_b[5]_PORT_B_read_enable, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_clock_0 = GLOBAL(A1L11);
N1_q_b[5]_clock_enable_0 = D1_oDVAL;
N1_q_b[5]_PORT_B_data_out = MEMORY(N1_q_b[5]_PORT_A_data_in_reg, , N1_q_b[5]_PORT_A_address_reg, N1_q_b[5]_PORT_B_address_reg, N1_q_b[5]_PORT_A_write_enable_reg, N1_q_b[5]_PORT_B_read_enable_reg, , , N1_q_b[5]_clock_0, , N1_q_b[5]_clock_enable_0, , , );
N1_q_b[5]_PORT_B_data_out_reg = DFFE(N1_q_b[5]_PORT_B_data_out, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5] = N1_q_b[5]_PORT_B_data_out_reg[0];

--N1_q_b[15] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[15] at M4K_X52_Y13
N1_q_b[5]_PORT_A_data_in = BUS(D1_mCCD_DATA[5], N1_q_b[5]);
N1_q_b[5]_PORT_A_data_in_reg = DFFE(N1_q_b[5]_PORT_A_data_in, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[5]_PORT_A_address_reg = DFFE(N1_q_b[5]_PORT_A_address, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[5]_PORT_B_address_reg = DFFE(N1_q_b[5]_PORT_B_address, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_A_write_enable = VCC;
N1_q_b[5]_PORT_A_write_enable_reg = DFFE(N1_q_b[5]_PORT_A_write_enable, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_PORT_B_read_enable = VCC;
N1_q_b[5]_PORT_B_read_enable_reg = DFFE(N1_q_b[5]_PORT_B_read_enable, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[5]_clock_0 = GLOBAL(A1L11);
N1_q_b[5]_clock_enable_0 = D1_oDVAL;
N1_q_b[5]_PORT_B_data_out = MEMORY(N1_q_b[5]_PORT_A_data_in_reg, , N1_q_b[5]_PORT_A_address_reg, N1_q_b[5]_PORT_B_address_reg, N1_q_b[5]_PORT_A_write_enable_reg, N1_q_b[5]_PORT_B_read_enable_reg, , , N1_q_b[5]_clock_0, , N1_q_b[5]_clock_enable_0, , , );
N1_q_b[5]_PORT_B_data_out_reg = DFFE(N1_q_b[5]_PORT_B_data_out, N1_q_b[5]_clock_0, , , N1_q_b[5]_clock_enable_0);
N1_q_b[15] = N1_q_b[5]_PORT_B_data_out_reg[1];


--E1L42 is RAW2RGB:u4|mCCD_B~160 at LCCOMB_X23_Y11_N6
E1L42 = D1_X_Cont[0] & (D1_Y_Cont[0] # E1_mDATAd_1[5]) # !D1_X_Cont[0] & !D1_Y_Cont[0] & (N1_q_b[5]);


--E1_mDATAd_0[5] is RAW2RGB:u4|mDATAd_0[5] at LCFF_X23_Y11_N31
E1_mDATAd_0[5] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[15],  ,  , VCC);


--E1L43 is RAW2RGB:u4|mCCD_B~161 at LCCOMB_X23_Y11_N2
E1L43 = E1L42 & (E1_mDATAd_0[5] # !D1_Y_Cont[0]) # !E1L42 & D1_Y_Cont[0] & N1_q_b[15];


--E1L106 is RAW2RGB:u4|mCCD_R~951 at LCCOMB_X23_Y11_N30
E1L106 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[5] # !D1_Y_Cont[0] & (E1_mDATAd_0[5]));


--E1L107 is RAW2RGB:u4|mCCD_R~952 at LCCOMB_X23_Y11_N8
E1L107 = D1_X_Cont[0] & (E1L106 & (N1_q_b[5]) # !E1L106 & N1_q_b[15]) # !D1_X_Cont[0] & (E1L106);


--E1_mDATAd_1[6] is RAW2RGB:u4|mDATAd_1[6] at LCFF_X23_Y11_N13
E1_mDATAd_1[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[6],  ,  , VCC);


--N1_q_b[6] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[6] at M4K_X52_Y12
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[6]_PORT_A_data_in = BUS(D1_mCCD_DATA[6], N1_q_b[6]);
N1_q_b[6]_PORT_A_data_in_reg = DFFE(N1_q_b[6]_PORT_A_data_in, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[6]_PORT_A_address_reg = DFFE(N1_q_b[6]_PORT_A_address, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[6]_PORT_B_address_reg = DFFE(N1_q_b[6]_PORT_B_address, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_A_write_enable = VCC;
N1_q_b[6]_PORT_A_write_enable_reg = DFFE(N1_q_b[6]_PORT_A_write_enable, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_B_read_enable = VCC;
N1_q_b[6]_PORT_B_read_enable_reg = DFFE(N1_q_b[6]_PORT_B_read_enable, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_clock_0 = GLOBAL(A1L11);
N1_q_b[6]_clock_enable_0 = D1_oDVAL;
N1_q_b[6]_PORT_B_data_out = MEMORY(N1_q_b[6]_PORT_A_data_in_reg, , N1_q_b[6]_PORT_A_address_reg, N1_q_b[6]_PORT_B_address_reg, N1_q_b[6]_PORT_A_write_enable_reg, N1_q_b[6]_PORT_B_read_enable_reg, , , N1_q_b[6]_clock_0, , N1_q_b[6]_clock_enable_0, , , );
N1_q_b[6]_PORT_B_data_out_reg = DFFE(N1_q_b[6]_PORT_B_data_out, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6] = N1_q_b[6]_PORT_B_data_out_reg[0];

--N1_q_b[16] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[16] at M4K_X52_Y12
N1_q_b[6]_PORT_A_data_in = BUS(D1_mCCD_DATA[6], N1_q_b[6]);
N1_q_b[6]_PORT_A_data_in_reg = DFFE(N1_q_b[6]_PORT_A_data_in, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[6]_PORT_A_address_reg = DFFE(N1_q_b[6]_PORT_A_address, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[6]_PORT_B_address_reg = DFFE(N1_q_b[6]_PORT_B_address, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_A_write_enable = VCC;
N1_q_b[6]_PORT_A_write_enable_reg = DFFE(N1_q_b[6]_PORT_A_write_enable, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_PORT_B_read_enable = VCC;
N1_q_b[6]_PORT_B_read_enable_reg = DFFE(N1_q_b[6]_PORT_B_read_enable, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[6]_clock_0 = GLOBAL(A1L11);
N1_q_b[6]_clock_enable_0 = D1_oDVAL;
N1_q_b[6]_PORT_B_data_out = MEMORY(N1_q_b[6]_PORT_A_data_in_reg, , N1_q_b[6]_PORT_A_address_reg, N1_q_b[6]_PORT_B_address_reg, N1_q_b[6]_PORT_A_write_enable_reg, N1_q_b[6]_PORT_B_read_enable_reg, , , N1_q_b[6]_clock_0, , N1_q_b[6]_clock_enable_0, , , );
N1_q_b[6]_PORT_B_data_out_reg = DFFE(N1_q_b[6]_PORT_B_data_out, N1_q_b[6]_clock_0, , , N1_q_b[6]_clock_enable_0);
N1_q_b[16] = N1_q_b[6]_PORT_B_data_out_reg[1];


--E1L44 is RAW2RGB:u4|mCCD_B~162 at LCCOMB_X23_Y11_N12
E1L44 = D1_X_Cont[0] & (D1_Y_Cont[0] # E1_mDATAd_1[6]) # !D1_X_Cont[0] & !D1_Y_Cont[0] & (N1_q_b[6]);


--E1_mDATAd_0[6] is RAW2RGB:u4|mDATAd_0[6] at LCFF_X23_Y11_N25
E1_mDATAd_0[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[16],  ,  , VCC);


--E1L45 is RAW2RGB:u4|mCCD_B~163 at LCCOMB_X23_Y11_N18
E1L45 = D1_Y_Cont[0] & (E1L44 & (E1_mDATAd_0[6]) # !E1L44 & N1_q_b[16]) # !D1_Y_Cont[0] & (E1L44);


--E1L108 is RAW2RGB:u4|mCCD_R~953 at LCCOMB_X23_Y11_N10
E1L108 = D1_X_Cont[0] & D1_Y_Cont[0] # !D1_X_Cont[0] & (D1_Y_Cont[0] & (E1_mDATAd_1[6]) # !D1_Y_Cont[0] & E1_mDATAd_0[6]);


--E1L109 is RAW2RGB:u4|mCCD_R~954 at LCCOMB_X23_Y11_N0
E1L109 = D1_X_Cont[0] & (E1L108 & N1_q_b[6] # !E1L108 & (N1_q_b[16])) # !D1_X_Cont[0] & (E1L108);


--E1_mDATAd_1[7] is RAW2RGB:u4|mDATAd_1[7] at LCFF_X22_Y11_N13
E1_mDATAd_1[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[7],  ,  , VCC);


--N1_q_b[7] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[7] at M4K_X26_Y11
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[7]_PORT_A_data_in = BUS(D1_mCCD_DATA[7], N1_q_b[7]);
N1_q_b[7]_PORT_A_data_in_reg = DFFE(N1_q_b[7]_PORT_A_data_in, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[7]_PORT_A_address_reg = DFFE(N1_q_b[7]_PORT_A_address, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[7]_PORT_B_address_reg = DFFE(N1_q_b[7]_PORT_B_address, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_A_write_enable = VCC;
N1_q_b[7]_PORT_A_write_enable_reg = DFFE(N1_q_b[7]_PORT_A_write_enable, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_B_read_enable = VCC;
N1_q_b[7]_PORT_B_read_enable_reg = DFFE(N1_q_b[7]_PORT_B_read_enable, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_clock_0 = GLOBAL(A1L11);
N1_q_b[7]_clock_enable_0 = D1_oDVAL;
N1_q_b[7]_PORT_B_data_out = MEMORY(N1_q_b[7]_PORT_A_data_in_reg, , N1_q_b[7]_PORT_A_address_reg, N1_q_b[7]_PORT_B_address_reg, N1_q_b[7]_PORT_A_write_enable_reg, N1_q_b[7]_PORT_B_read_enable_reg, , , N1_q_b[7]_clock_0, , N1_q_b[7]_clock_enable_0, , , );
N1_q_b[7]_PORT_B_data_out_reg = DFFE(N1_q_b[7]_PORT_B_data_out, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7] = N1_q_b[7]_PORT_B_data_out_reg[0];

--N1_q_b[17] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[17] at M4K_X26_Y11
N1_q_b[7]_PORT_A_data_in = BUS(D1_mCCD_DATA[7], N1_q_b[7]);
N1_q_b[7]_PORT_A_data_in_reg = DFFE(N1_q_b[7]_PORT_A_data_in, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[7]_PORT_A_address_reg = DFFE(N1_q_b[7]_PORT_A_address, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[7]_PORT_B_address_reg = DFFE(N1_q_b[7]_PORT_B_address, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_A_write_enable = VCC;
N1_q_b[7]_PORT_A_write_enable_reg = DFFE(N1_q_b[7]_PORT_A_write_enable, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_PORT_B_read_enable = VCC;
N1_q_b[7]_PORT_B_read_enable_reg = DFFE(N1_q_b[7]_PORT_B_read_enable, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[7]_clock_0 = GLOBAL(A1L11);
N1_q_b[7]_clock_enable_0 = D1_oDVAL;
N1_q_b[7]_PORT_B_data_out = MEMORY(N1_q_b[7]_PORT_A_data_in_reg, , N1_q_b[7]_PORT_A_address_reg, N1_q_b[7]_PORT_B_address_reg, N1_q_b[7]_PORT_A_write_enable_reg, N1_q_b[7]_PORT_B_read_enable_reg, , , N1_q_b[7]_clock_0, , N1_q_b[7]_clock_enable_0, , , );
N1_q_b[7]_PORT_B_data_out_reg = DFFE(N1_q_b[7]_PORT_B_data_out, N1_q_b[7]_clock_0, , , N1_q_b[7]_clock_enable_0);
N1_q_b[17] = N1_q_b[7]_PORT_B_data_out_reg[1];


--E1L46 is RAW2RGB:u4|mCCD_B~164 at LCCOMB_X22_Y11_N12
E1L46 = D1_Y_Cont[0] & (D1_X_Cont[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & (E1_mDATAd_1[7]) # !D1_X_Cont[0] & N1_q_b[7]);


--E1_mDATAd_0[7] is RAW2RGB:u4|mDATAd_0[7] at LCFF_X22_Y11_N11
E1_mDATAd_0[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[17],  ,  , VCC);


--E1L47 is RAW2RGB:u4|mCCD_B~165 at LCCOMB_X22_Y11_N24
E1L47 = E1L46 & (E1_mDATAd_0[7] # !D1_Y_Cont[0]) # !E1L46 & N1_q_b[17] & D1_Y_Cont[0];


--E1L110 is RAW2RGB:u4|mCCD_R~955 at LCCOMB_X22_Y11_N26
E1L110 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[7] # !D1_Y_Cont[0] & (E1_mDATAd_0[7]));


--E1L111 is RAW2RGB:u4|mCCD_R~956 at LCCOMB_X22_Y11_N28
E1L111 = D1_X_Cont[0] & (E1L110 & (N1_q_b[7]) # !E1L110 & N1_q_b[17]) # !D1_X_Cont[0] & (E1L110);


--E1_mDATAd_1[8] is RAW2RGB:u4|mDATAd_1[8] at LCFF_X23_Y9_N27
E1_mDATAd_1[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[8],  ,  , VCC);


--N1_q_b[8] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[8] at M4K_X52_Y9
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[8]_PORT_A_data_in = BUS(D1_mCCD_DATA[8], N1_q_b[8]);
N1_q_b[8]_PORT_A_data_in_reg = DFFE(N1_q_b[8]_PORT_A_data_in, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[8]_PORT_A_address_reg = DFFE(N1_q_b[8]_PORT_A_address, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[8]_PORT_B_address_reg = DFFE(N1_q_b[8]_PORT_B_address, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_A_write_enable = VCC;
N1_q_b[8]_PORT_A_write_enable_reg = DFFE(N1_q_b[8]_PORT_A_write_enable, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_B_read_enable = VCC;
N1_q_b[8]_PORT_B_read_enable_reg = DFFE(N1_q_b[8]_PORT_B_read_enable, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_clock_0 = GLOBAL(A1L11);
N1_q_b[8]_clock_enable_0 = D1_oDVAL;
N1_q_b[8]_PORT_B_data_out = MEMORY(N1_q_b[8]_PORT_A_data_in_reg, , N1_q_b[8]_PORT_A_address_reg, N1_q_b[8]_PORT_B_address_reg, N1_q_b[8]_PORT_A_write_enable_reg, N1_q_b[8]_PORT_B_read_enable_reg, , , N1_q_b[8]_clock_0, , N1_q_b[8]_clock_enable_0, , , );
N1_q_b[8]_PORT_B_data_out_reg = DFFE(N1_q_b[8]_PORT_B_data_out, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8] = N1_q_b[8]_PORT_B_data_out_reg[0];

--N1_q_b[18] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[18] at M4K_X52_Y9
N1_q_b[8]_PORT_A_data_in = BUS(D1_mCCD_DATA[8], N1_q_b[8]);
N1_q_b[8]_PORT_A_data_in_reg = DFFE(N1_q_b[8]_PORT_A_data_in, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[8]_PORT_A_address_reg = DFFE(N1_q_b[8]_PORT_A_address, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[8]_PORT_B_address_reg = DFFE(N1_q_b[8]_PORT_B_address, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_A_write_enable = VCC;
N1_q_b[8]_PORT_A_write_enable_reg = DFFE(N1_q_b[8]_PORT_A_write_enable, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_PORT_B_read_enable = VCC;
N1_q_b[8]_PORT_B_read_enable_reg = DFFE(N1_q_b[8]_PORT_B_read_enable, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[8]_clock_0 = GLOBAL(A1L11);
N1_q_b[8]_clock_enable_0 = D1_oDVAL;
N1_q_b[8]_PORT_B_data_out = MEMORY(N1_q_b[8]_PORT_A_data_in_reg, , N1_q_b[8]_PORT_A_address_reg, N1_q_b[8]_PORT_B_address_reg, N1_q_b[8]_PORT_A_write_enable_reg, N1_q_b[8]_PORT_B_read_enable_reg, , , N1_q_b[8]_clock_0, , N1_q_b[8]_clock_enable_0, , , );
N1_q_b[8]_PORT_B_data_out_reg = DFFE(N1_q_b[8]_PORT_B_data_out, N1_q_b[8]_clock_0, , , N1_q_b[8]_clock_enable_0);
N1_q_b[18] = N1_q_b[8]_PORT_B_data_out_reg[1];


--E1L48 is RAW2RGB:u4|mCCD_B~166 at LCCOMB_X23_Y9_N12
E1L48 = D1_X_Cont[0] & (D1_Y_Cont[0] # E1_mDATAd_1[8]) # !D1_X_Cont[0] & !D1_Y_Cont[0] & N1_q_b[8];


--E1_mDATAd_0[8] is RAW2RGB:u4|mDATAd_0[8] at LCFF_X23_Y9_N7
E1_mDATAd_0[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[18],  ,  , VCC);


--E1L49 is RAW2RGB:u4|mCCD_B~167 at LCCOMB_X23_Y9_N0
E1L49 = D1_Y_Cont[0] & (E1L48 & E1_mDATAd_0[8] # !E1L48 & (N1_q_b[18])) # !D1_Y_Cont[0] & (E1L48);


--E1L112 is RAW2RGB:u4|mCCD_R~957 at LCCOMB_X23_Y9_N6
E1L112 = D1_X_Cont[0] & D1_Y_Cont[0] # !D1_X_Cont[0] & (D1_Y_Cont[0] & (E1_mDATAd_1[8]) # !D1_Y_Cont[0] & E1_mDATAd_0[8]);


--E1L113 is RAW2RGB:u4|mCCD_R~958 at LCCOMB_X23_Y9_N18
E1L113 = D1_X_Cont[0] & (E1L112 & N1_q_b[8] # !E1L112 & (N1_q_b[18])) # !D1_X_Cont[0] & E1L112;


--E1_mDATAd_1[9] is RAW2RGB:u4|mDATAd_1[9] at LCFF_X22_Y11_N23
E1_mDATAd_1[9] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[9],  ,  , VCC);


--N1_q_b[9] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[9] at M4K_X52_Y11
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 1278, Port A Logical Width: 20, Port B Logical Depth: 1278, Port B Logical Width: 20
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
N1_q_b[9]_PORT_A_data_in = BUS(D1_mCCD_DATA[9], N1_q_b[9]);
N1_q_b[9]_PORT_A_data_in_reg = DFFE(N1_q_b[9]_PORT_A_data_in, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[9]_PORT_A_address_reg = DFFE(N1_q_b[9]_PORT_A_address, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[9]_PORT_B_address_reg = DFFE(N1_q_b[9]_PORT_B_address, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_A_write_enable = VCC;
N1_q_b[9]_PORT_A_write_enable_reg = DFFE(N1_q_b[9]_PORT_A_write_enable, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_B_read_enable = VCC;
N1_q_b[9]_PORT_B_read_enable_reg = DFFE(N1_q_b[9]_PORT_B_read_enable, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_clock_0 = GLOBAL(A1L11);
N1_q_b[9]_clock_enable_0 = D1_oDVAL;
N1_q_b[9]_PORT_B_data_out = MEMORY(N1_q_b[9]_PORT_A_data_in_reg, , N1_q_b[9]_PORT_A_address_reg, N1_q_b[9]_PORT_B_address_reg, N1_q_b[9]_PORT_A_write_enable_reg, N1_q_b[9]_PORT_B_read_enable_reg, , , N1_q_b[9]_clock_0, , N1_q_b[9]_clock_enable_0, , , );
N1_q_b[9]_PORT_B_data_out_reg = DFFE(N1_q_b[9]_PORT_B_data_out, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9] = N1_q_b[9]_PORT_B_data_out_reg[0];

--N1_q_b[19] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|altsyncram_ohv:altsyncram2|q_b[19] at M4K_X52_Y11
N1_q_b[9]_PORT_A_data_in = BUS(D1_mCCD_DATA[9], N1_q_b[9]);
N1_q_b[9]_PORT_A_data_in_reg = DFFE(N1_q_b[9]_PORT_A_data_in, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[9]_PORT_A_address_reg = DFFE(N1_q_b[9]_PORT_A_address, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8], P1_safe_q[9], P1_safe_q[10]);
N1_q_b[9]_PORT_B_address_reg = DFFE(N1_q_b[9]_PORT_B_address, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_A_write_enable = VCC;
N1_q_b[9]_PORT_A_write_enable_reg = DFFE(N1_q_b[9]_PORT_A_write_enable, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_PORT_B_read_enable = VCC;
N1_q_b[9]_PORT_B_read_enable_reg = DFFE(N1_q_b[9]_PORT_B_read_enable, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[9]_clock_0 = GLOBAL(A1L11);
N1_q_b[9]_clock_enable_0 = D1_oDVAL;
N1_q_b[9]_PORT_B_data_out = MEMORY(N1_q_b[9]_PORT_A_data_in_reg, , N1_q_b[9]_PORT_A_address_reg, N1_q_b[9]_PORT_B_address_reg, N1_q_b[9]_PORT_A_write_enable_reg, N1_q_b[9]_PORT_B_read_enable_reg, , , N1_q_b[9]_clock_0, , N1_q_b[9]_clock_enable_0, , , );
N1_q_b[9]_PORT_B_data_out_reg = DFFE(N1_q_b[9]_PORT_B_data_out, N1_q_b[9]_clock_0, , , N1_q_b[9]_clock_enable_0);
N1_q_b[19] = N1_q_b[9]_PORT_B_data_out_reg[1];


--E1L50 is RAW2RGB:u4|mCCD_B~168 at LCCOMB_X22_Y11_N22
E1L50 = D1_Y_Cont[0] & D1_X_Cont[0] # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[9] # !D1_X_Cont[0] & (N1_q_b[9]));


--E1_mDATAd_0[9] is RAW2RGB:u4|mDATAd_0[9] at LCFF_X22_Y11_N17
E1_mDATAd_0[9] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , N1_q_b[19],  ,  , VCC);


--E1L51 is RAW2RGB:u4|mCCD_B~169 at LCCOMB_X22_Y11_N20
E1L51 = E1L50 & (E1_mDATAd_0[9] # !D1_Y_Cont[0]) # !E1L50 & (D1_Y_Cont[0] & N1_q_b[19]);


--E1L114 is RAW2RGB:u4|mCCD_R~959 at LCCOMB_X22_Y11_N4
E1L114 = D1_X_Cont[0] & (D1_Y_Cont[0]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & (E1_mDATAd_1[9]) # !D1_Y_Cont[0] & E1_mDATAd_0[9]);


--E1L115 is RAW2RGB:u4|mCCD_R~960 at LCCOMB_X22_Y11_N8
E1L115 = E1L114 & (N1_q_b[9] # !D1_X_Cont[0]) # !E1L114 & (N1_q_b[19] & D1_X_Cont[0]);


--E1L1 is RAW2RGB:u4|add~1591 at LCCOMB_X23_Y11_N16
E1L1 = D1_X_Cont[0] & (D1_Y_Cont[0] & (N1_q_b[16]) # !D1_Y_Cont[0] & N1_q_b[6]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & N1_q_b[6] # !D1_Y_Cont[0] & (N1_q_b[16]));


--E1L2 is RAW2RGB:u4|add~1592 at LCCOMB_X23_Y11_N24
E1L2 = D1_X_Cont[0] & (D1_Y_Cont[0] & (E1_mDATAd_1[6]) # !D1_Y_Cont[0] & E1_mDATAd_0[6]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_0[6] # !D1_Y_Cont[0] & (E1_mDATAd_1[6]));


--E1L3 is RAW2RGB:u4|add~1593 at LCCOMB_X23_Y11_N20
E1L3 = D1_X_Cont[0] & (D1_Y_Cont[0] & (N1_q_b[15]) # !D1_Y_Cont[0] & N1_q_b[5]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & N1_q_b[5] # !D1_Y_Cont[0] & (N1_q_b[15]));


--E1L4 is RAW2RGB:u4|add~1594 at LCCOMB_X23_Y11_N4
E1L4 = D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[5] # !D1_Y_Cont[0] & (E1_mDATAd_0[5])) # !D1_X_Cont[0] & (D1_Y_Cont[0] & (E1_mDATAd_0[5]) # !D1_Y_Cont[0] & E1_mDATAd_1[5]);


--E1L5 is RAW2RGB:u4|add~1595 at LCCOMB_X23_Y9_N24
E1L5 = D1_X_Cont[0] & (D1_Y_Cont[0] & N1_q_b[14] # !D1_Y_Cont[0] & (N1_q_b[4])) # !D1_X_Cont[0] & (D1_Y_Cont[0] & (N1_q_b[4]) # !D1_Y_Cont[0] & N1_q_b[14]);


--E1L6 is RAW2RGB:u4|add~1596 at LCCOMB_X23_Y9_N20
E1L6 = D1_X_Cont[0] & (D1_Y_Cont[0] & (E1_mDATAd_1[4]) # !D1_Y_Cont[0] & E1_mDATAd_0[4]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_0[4] # !D1_Y_Cont[0] & (E1_mDATAd_1[4]));


--E1L7 is RAW2RGB:u4|add~1597 at LCCOMB_X22_Y10_N6
E1L7 = D1_Y_Cont[0] & (D1_X_Cont[0] & N1_q_b[13] # !D1_X_Cont[0] & (N1_q_b[3])) # !D1_Y_Cont[0] & (D1_X_Cont[0] & (N1_q_b[3]) # !D1_X_Cont[0] & N1_q_b[13]);


--E1L8 is RAW2RGB:u4|add~1598 at LCCOMB_X22_Y10_N14
E1L8 = D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[3] # !D1_X_Cont[0] & (E1_mDATAd_0[3])) # !D1_Y_Cont[0] & (D1_X_Cont[0] & (E1_mDATAd_0[3]) # !D1_X_Cont[0] & E1_mDATAd_1[3]);


--E1L9 is RAW2RGB:u4|add~1599 at LCCOMB_X23_Y10_N4
E1L9 = D1_Y_Cont[0] & (D1_X_Cont[0] & N1_q_b[12] # !D1_X_Cont[0] & (N1_q_b[2])) # !D1_Y_Cont[0] & (D1_X_Cont[0] & (N1_q_b[2]) # !D1_X_Cont[0] & N1_q_b[12]);


--E1L10 is RAW2RGB:u4|add~1600 at LCCOMB_X22_Y10_N18
E1L10 = D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_1[2] # !D1_X_Cont[0] & (E1_mDATAd_0[2])) # !D1_Y_Cont[0] & (D1_X_Cont[0] & (E1_mDATAd_0[2]) # !D1_X_Cont[0] & E1_mDATAd_1[2]);


--E1L11 is RAW2RGB:u4|add~1601 at LCCOMB_X23_Y10_N6
E1L11 = D1_Y_Cont[0] & (D1_X_Cont[0] & (N1_q_b[11]) # !D1_X_Cont[0] & N1_q_b[1]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & N1_q_b[1] # !D1_X_Cont[0] & (N1_q_b[11]));


--E1L12 is RAW2RGB:u4|add~1602 at LCCOMB_X23_Y10_N0
E1L12 = E1_mDATAd_1[1] & (E1_mDATAd_0[1] # D1_X_Cont[0] $ !D1_Y_Cont[0]) # !E1_mDATAd_1[1] & E1_mDATAd_0[1] & (D1_X_Cont[0] $ D1_Y_Cont[0]);


--E1L13 is RAW2RGB:u4|add~1603 at LCCOMB_X23_Y10_N30
E1L13 = D1_Y_Cont[0] & (D1_X_Cont[0] & (N1_q_b[10]) # !D1_X_Cont[0] & N1_q_b[0]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & N1_q_b[0] # !D1_X_Cont[0] & (N1_q_b[10]));


--E1L14 is RAW2RGB:u4|add~1604 at LCCOMB_X22_Y10_N20
E1L14 = E1_mDATAd_0[0] & (E1_mDATAd_1[0] # D1_X_Cont[0] $ D1_Y_Cont[0]) # !E1_mDATAd_0[0] & E1_mDATAd_1[0] & (D1_X_Cont[0] $ !D1_Y_Cont[0]);


--E1L55 is RAW2RGB:u4|mCCD_G[1]~868 at LCCOMB_X23_Y10_N8
E1L55 = CARRY(E1L14 & E1L13);


--E1L56 is RAW2RGB:u4|mCCD_G[1]~869 at LCCOMB_X23_Y10_N10
E1L56 = E1L11 & (E1L12 & E1L55 & VCC # !E1L12 & !E1L55) # !E1L11 & (E1L12 & !E1L55 # !E1L12 & (E1L55 # GND));

--E1L57 is RAW2RGB:u4|mCCD_G[1]~870 at LCCOMB_X23_Y10_N10
E1L57 = CARRY(E1L11 & !E1L12 & !E1L55 # !E1L11 & (!E1L55 # !E1L12));


--E1L59 is RAW2RGB:u4|mCCD_G[2]~871 at LCCOMB_X23_Y10_N12
E1L59 = (E1L10 $ E1L9 $ !E1L57) # GND;

--E1L60 is RAW2RGB:u4|mCCD_G[2]~872 at LCCOMB_X23_Y10_N12
E1L60 = CARRY(E1L10 & (E1L9 # !E1L57) # !E1L10 & E1L9 & !E1L57);


--E1L62 is RAW2RGB:u4|mCCD_G[3]~873 at LCCOMB_X23_Y10_N14
E1L62 = E1L8 & (E1L7 & E1L60 & VCC # !E1L7 & !E1L60) # !E1L8 & (E1L7 & !E1L60 # !E1L7 & (E1L60 # GND));

--E1L63 is RAW2RGB:u4|mCCD_G[3]~874 at LCCOMB_X23_Y10_N14
E1L63 = CARRY(E1L8 & !E1L7 & !E1L60 # !E1L8 & (!E1L60 # !E1L7));


--E1L65 is RAW2RGB:u4|mCCD_G[4]~875 at LCCOMB_X23_Y10_N16
E1L65 = (E1L5 $ E1L6 $ !E1L63) # GND;

--E1L66 is RAW2RGB:u4|mCCD_G[4]~876 at LCCOMB_X23_Y10_N16
E1L66 = CARRY(E1L5 & (E1L6 # !E1L63) # !E1L5 & E1L6 & !E1L63);


--E1L68 is RAW2RGB:u4|mCCD_G[5]~877 at LCCOMB_X23_Y10_N18
E1L68 = E1L4 & (E1L3 & E1L66 & VCC # !E1L3 & !E1L66) # !E1L4 & (E1L3 & !E1L66 # !E1L3 & (E1L66 # GND));

--E1L69 is RAW2RGB:u4|mCCD_G[5]~878 at LCCOMB_X23_Y10_N18
E1L69 = CARRY(E1L4 & !E1L3 & !E1L66 # !E1L4 & (!E1L66 # !E1L3));


--E1L71 is RAW2RGB:u4|mCCD_G[6]~879 at LCCOMB_X23_Y10_N20
E1L71 = (E1L1 $ E1L2 $ !E1L69) # GND;

--E1L72 is RAW2RGB:u4|mCCD_G[6]~880 at LCCOMB_X23_Y10_N20
E1L72 = CARRY(E1L1 & (E1L2 # !E1L69) # !E1L1 & E1L2 & !E1L69);


--E1L15 is RAW2RGB:u4|add~1605 at LCCOMB_X23_Y10_N2
E1L15 = D1_Y_Cont[0] & (D1_X_Cont[0] & (N1_q_b[17]) # !D1_X_Cont[0] & N1_q_b[7]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & N1_q_b[7] # !D1_X_Cont[0] & (N1_q_b[17]));


--E1L16 is RAW2RGB:u4|add~1606 at LCCOMB_X22_Y11_N10
E1L16 = D1_Y_Cont[0] & (D1_X_Cont[0] & (E1_mDATAd_1[7]) # !D1_X_Cont[0] & E1_mDATAd_0[7]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_0[7] # !D1_X_Cont[0] & (E1_mDATAd_1[7]));


--E1L74 is RAW2RGB:u4|mCCD_G[7]~881 at LCCOMB_X23_Y10_N22
E1L74 = E1L16 & (E1L15 & E1L72 & VCC # !E1L15 & !E1L72) # !E1L16 & (E1L15 & !E1L72 # !E1L15 & (E1L72 # GND));

--E1L75 is RAW2RGB:u4|mCCD_G[7]~882 at LCCOMB_X23_Y10_N22
E1L75 = CARRY(E1L16 & !E1L15 & !E1L72 # !E1L16 & (!E1L72 # !E1L15));


--E1L17 is RAW2RGB:u4|add~1607 at LCCOMB_X23_Y9_N22
E1L17 = D1_X_Cont[0] & (D1_Y_Cont[0] & (N1_q_b[18]) # !D1_Y_Cont[0] & N1_q_b[8]) # !D1_X_Cont[0] & (D1_Y_Cont[0] & N1_q_b[8] # !D1_Y_Cont[0] & (N1_q_b[18]));


--E1L18 is RAW2RGB:u4|add~1608 at LCCOMB_X23_Y9_N26
E1L18 = D1_X_Cont[0] & (D1_Y_Cont[0] & E1_mDATAd_1[8] # !D1_Y_Cont[0] & (E1_mDATAd_0[8])) # !D1_X_Cont[0] & (D1_Y_Cont[0] & (E1_mDATAd_0[8]) # !D1_Y_Cont[0] & E1_mDATAd_1[8]);


--E1L77 is RAW2RGB:u4|mCCD_G[8]~883 at LCCOMB_X23_Y10_N24
E1L77 = (E1L17 $ E1L18 $ !E1L75) # GND;

--E1L78 is RAW2RGB:u4|mCCD_G[8]~884 at LCCOMB_X23_Y10_N24
E1L78 = CARRY(E1L17 & (E1L18 # !E1L75) # !E1L17 & E1L18 & !E1L75);


--E1L19 is RAW2RGB:u4|add~1609 at LCCOMB_X22_Y11_N18
E1L19 = N1_q_b[9] & (N1_q_b[19] # D1_X_Cont[0] $ D1_Y_Cont[0]) # !N1_q_b[9] & N1_q_b[19] & (D1_X_Cont[0] $ !D1_Y_Cont[0]);


--E1L20 is RAW2RGB:u4|add~1610 at LCCOMB_X22_Y11_N16
E1L20 = D1_Y_Cont[0] & (D1_X_Cont[0] & (E1_mDATAd_1[9]) # !D1_X_Cont[0] & E1_mDATAd_0[9]) # !D1_Y_Cont[0] & (D1_X_Cont[0] & E1_mDATAd_0[9] # !D1_X_Cont[0] & (E1_mDATAd_1[9]));


--E1L80 is RAW2RGB:u4|mCCD_G[9]~885 at LCCOMB_X23_Y10_N26
E1L80 = E1L19 & (E1L20 & E1L78 & VCC # !E1L20 & !E1L78) # !E1L19 & (E1L20 & !E1L78 # !E1L20 & (E1L78 # GND));

--E1L81 is RAW2RGB:u4|mCCD_G[9]~886 at LCCOMB_X23_Y10_N26
E1L81 = CARRY(E1L19 & !E1L20 & !E1L78 # !E1L19 & (!E1L78 # !E1L20));


--E1L83 is RAW2RGB:u4|mCCD_G[10]~887 at LCCOMB_X23_Y10_N28
E1L83 = !E1L81;


--LB1L13 is I2C_CCD_Config:u7|I2C_Controller:u0|END~124 at LCCOMB_X44_Y17_N6
LB1L13 = LB1L60Q & LB1L63Q & LB1L57Q & LB1L51Q;


--LB1L14 is I2C_CCD_Config:u7|I2C_Controller:u0|END~125 at LCCOMB_X44_Y17_N16
LB1L14 = LB1L13 & (LB1L54Q & (LB1L66Q) # !LB1L54Q & LB1_END) # !LB1L13 & (LB1_END);


--LB1_ACK3 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK3 at LCFF_X44_Y17_N11
LB1_ACK3 = DFFEAS(LB1L11, GLOBAL(H1L93), GLOBAL(A1L291),  ,  ,  ,  ,  ,  );


--LB1_ACK1 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK1 at LCFF_X44_Y17_N19
LB1_ACK1 = DFFEAS(LB1L3, GLOBAL(H1L93), GLOBAL(A1L291),  ,  ,  ,  ,  ,  );


--LB1_ACK2 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK2 at LCFF_X44_Y17_N23
LB1_ACK2 = DFFEAS(LB1L8, GLOBAL(H1L93), GLOBAL(A1L291),  ,  ,  ,  ,  ,  );


--H1L129 is I2C_CCD_Config:u7|mSetup_ST~124 at LCCOMB_X44_Y17_N8
H1L129 = !LB1_ACK3 & !LB1_ACK2 & !LB1_ACK1;


--H1L130 is I2C_CCD_Config:u7|mSetup_ST~125 at LCCOMB_X44_Y16_N2
H1L130 = H1L129 & !LB1_END & H1_mSetup_ST.0001;


--H1_mSetup_ST.0000 is I2C_CCD_Config:u7|mSetup_ST.0000 at LCFF_X44_Y16_N25
H1_mSetup_ST.0000 = DFFEAS(H1L41, GLOBAL(H1L93), GLOBAL(A1L291),  , H1L38,  ,  ,  ,  );


--H1L40 is I2C_CCD_Config:u7|Select~136 at LCCOMB_X44_Y16_N6
H1L40 = LB1_END & H1_mSetup_ST.0001 # !H1_mSetup_ST.0000;


--H1L14 is I2C_CCD_Config:u7|LUT_INDEX[0]~821 at LCCOMB_X42_Y16_N8
H1L14 = H1_LUT_INDEX[0] $ VCC;

--H1L15 is I2C_CCD_Config:u7|LUT_INDEX[0]~822 at LCCOMB_X42_Y16_N8
H1L15 = CARRY(H1_LUT_INDEX[0]);


--H1L17 is I2C_CCD_Config:u7|LUT_INDEX[1]~823 at LCCOMB_X42_Y16_N10
H1L17 = H1_LUT_INDEX[1] & !H1L15 # !H1_LUT_INDEX[1] & (H1L15 # GND);

--H1L18 is I2C_CCD_Config:u7|LUT_INDEX[1]~824 at LCCOMB_X42_Y16_N10
H1L18 = CARRY(!H1L15 # !H1_LUT_INDEX[1]);


--H1L20 is I2C_CCD_Config:u7|LUT_INDEX[2]~825 at LCCOMB_X42_Y16_N12
H1L20 = H1_LUT_INDEX[2] & (H1L18 $ GND) # !H1_LUT_INDEX[2] & !H1L18 & VCC;

--H1L21 is I2C_CCD_Config:u7|LUT_INDEX[2]~826 at LCCOMB_X42_Y16_N12
H1L21 = CARRY(H1_LUT_INDEX[2] & !H1L18);


--H1L29 is I2C_CCD_Config:u7|LUT_INDEX[5]~0 at LCCOMB_X42_Y16_N30
H1L29 = H1L38 & H1_mSetup_ST.0010;


--H1L23 is I2C_CCD_Config:u7|LUT_INDEX[3]~827 at LCCOMB_X42_Y16_N14
H1L23 = H1_LUT_INDEX[3] & !H1L21 # !H1_LUT_INDEX[3] & (H1L21 # GND);

--H1L24 is I2C_CCD_Config:u7|LUT_INDEX[3]~828 at LCCOMB_X42_Y16_N14
H1L24 = CARRY(!H1L21 # !H1_LUT_INDEX[3]);


--H1L26 is I2C_CCD_Config:u7|LUT_INDEX[4]~829 at LCCOMB_X42_Y16_N16
H1L26 = H1_LUT_INDEX[4] & (H1L24 $ GND) # !H1_LUT_INDEX[4] & !H1L24 & VCC;

--H1L27 is I2C_CCD_Config:u7|LUT_INDEX[4]~830 at LCCOMB_X42_Y16_N16
H1L27 = CARRY(H1_LUT_INDEX[4] & !H1L24);


--H1L30 is I2C_CCD_Config:u7|LUT_INDEX[5]~831 at LCCOMB_X42_Y16_N18
H1L30 = H1L27 $ H1_LUT_INDEX[5];


--H1L8 is I2C_CCD_Config:u7|LUT_DATA[6]~1513 at LCCOMB_X43_Y16_N28
H1L8 = H1_LUT_INDEX[3] & !H1_LUT_INDEX[4] & !H1_LUT_INDEX[2];


--H1L110 is I2C_CCD_Config:u7|mI2C_DATA[4]~969 at LCCOMB_X43_Y16_N8
H1L110 = H1_LUT_INDEX[3] # H1_LUT_INDEX[4] # H1_LUT_INDEX[1] # !H1_LUT_INDEX[2];


--H1L102 is I2C_CCD_Config:u7|mI2C_DATA[2]~906 at LCCOMB_X43_Y16_N16
H1L102 = H1L110 & (H1L8) # !H1L110 & SW[2];


--H1L111 is I2C_CCD_Config:u7|mI2C_DATA[4]~970 at LCCOMB_X42_Y16_N2
H1L111 = H1_LUT_INDEX[3] # H1_LUT_INDEX[4] # H1_LUT_INDEX[2] # !H1_LUT_INDEX[1];


--H1L112 is I2C_CCD_Config:u7|mI2C_DATA[4]~971 at LCCOMB_X42_Y16_N24
H1L112 = H1_LUT_INDEX[5] # H1_LUT_INDEX[0] & H1L111;


--H1L124 is I2C_CCD_Config:u7|mI2C_DATA[15]~972 at LCCOMB_X42_Y16_N4
H1L124 = H1L38 & !H1_mSetup_ST.0000 & KEY[1];


--H1L131 is I2C_CCD_Config:u7|reduce_or~162 at LCCOMB_X42_Y17_N4
H1L131 = H1_LUT_INDEX[1] & (!H1_LUT_INDEX[2] & !H1_LUT_INDEX[3] # !H1_LUT_INDEX[0]) # !H1_LUT_INDEX[1] & (H1_LUT_INDEX[2] # H1_LUT_INDEX[3]);


--H1L132 is I2C_CCD_Config:u7|reduce_or~163 at LCCOMB_X42_Y17_N30
H1L132 = H1_LUT_INDEX[4] & H1L37 & (!H1_LUT_INDEX[0]) # !H1_LUT_INDEX[4] & (H1L131);


--H1L133 is I2C_CCD_Config:u7|reduce_or~164 at LCCOMB_X42_Y17_N2
H1L133 = H1_LUT_INDEX[0] & (H1_LUT_INDEX[3] & (H1_LUT_INDEX[1]) # !H1_LUT_INDEX[3] & H1_LUT_INDEX[2] & !H1_LUT_INDEX[1]);


--H1L99 is I2C_CCD_Config:u7|mI2C_DATA[1]~907 at LCCOMB_X43_Y16_N12
H1L99 = H1L110 & (H1L8) # !H1L110 & SW[1];


--H1L9 is I2C_CCD_Config:u7|LUT_DATA[7]~1514 at LCCOMB_X42_Y16_N28
H1L9 = H1_LUT_INDEX[3] # H1_LUT_INDEX[2] & (H1_LUT_INDEX[1] # SW[7]);


--H1L10 is I2C_CCD_Config:u7|LUT_DATA[7]~1515 at LCCOMB_X42_Y16_N6
H1L10 = H1_LUT_INDEX[0] & (SW[15]) # !H1_LUT_INDEX[0] & !H1_LUT_INDEX[4] & (H1L9);


--H1L1 is I2C_CCD_Config:u7|LUT_DATA[0]~1516 at LCCOMB_X43_Y16_N26
H1L1 = !H1_LUT_INDEX[2] & (H1_LUT_INDEX[4] $ (H1_LUT_INDEX[3] # H1_LUT_INDEX[1]));


--H1L96 is I2C_CCD_Config:u7|mI2C_DATA[0]~908 at LCCOMB_X43_Y16_N4
H1L96 = H1L110 & (H1L1) # !H1L110 & SW[0];


--H1L4 is I2C_CCD_Config:u7|LUT_DATA[4]~1517 at LCCOMB_X43_Y16_N20
H1L4 = H1_LUT_INDEX[4] & !H1_LUT_INDEX[3] & !H1_LUT_INDEX[1] & !H1_LUT_INDEX[2] # !H1_LUT_INDEX[4] & H1_LUT_INDEX[2] & (!H1_LUT_INDEX[1] # !H1_LUT_INDEX[3]);


--H1L108 is I2C_CCD_Config:u7|mI2C_DATA[4]~909 at LCCOMB_X43_Y16_N30
H1L108 = H1L110 & H1L4 # !H1L110 & (SW[4]);


--H1L134 is I2C_CCD_Config:u7|reduce_or~165 at LCCOMB_X42_Y17_N14
H1L134 = H1_LUT_INDEX[0] & (H1_LUT_INDEX[3] # H1_LUT_INDEX[2] & H1_LUT_INDEX[1]);


--H1L135 is I2C_CCD_Config:u7|reduce_or~166 at LCCOMB_X42_Y17_N0
H1L135 = H1_LUT_INDEX[0] & (H1_LUT_INDEX[2] & !H1_LUT_INDEX[3] # !H1_LUT_INDEX[2] & (H1_LUT_INDEX[3] # H1_LUT_INDEX[1]));


--H1L2 is I2C_CCD_Config:u7|LUT_DATA[3]~1518 at LCCOMB_X43_Y16_N18
H1L2 = !H1_LUT_INDEX[1] & (H1_LUT_INDEX[2] & !H1_LUT_INDEX[4] & SW[3] # !H1_LUT_INDEX[2] & H1_LUT_INDEX[4]);


--H1L3 is I2C_CCD_Config:u7|LUT_DATA[3]~1519 at LCCOMB_X43_Y16_N22
H1L3 = !H1_LUT_INDEX[4] & (H1_LUT_INDEX[1] # !H1_LUT_INDEX[2]);


--H1L105 is I2C_CCD_Config:u7|mI2C_DATA[3]~910 at LCCOMB_X43_Y16_N10
H1L105 = H1_LUT_INDEX[3] & H1L3 # !H1_LUT_INDEX[3] & (H1L2);


--H1L115 is I2C_CCD_Config:u7|mI2C_DATA[6]~911 at LCCOMB_X43_Y16_N14
H1L115 = H1L110 & (H1L8) # !H1L110 & SW[6];


--H1L5 is I2C_CCD_Config:u7|LUT_DATA[5]~1520 at LCCOMB_X42_Y17_N10
H1L5 = H1_LUT_INDEX[1] & !H1_LUT_INDEX[3] # !H1_LUT_INDEX[1] & (H1_LUT_INDEX[3] # SW[5]);


--H1L6 is I2C_CCD_Config:u7|LUT_DATA[5]~1521 at LCCOMB_X43_Y16_N6
H1L6 = H1_LUT_INDEX[2] & !H1_LUT_INDEX[4] & H1L5 & !H1_LUT_INDEX[0];


--H1L7 is I2C_CCD_Config:u7|LUT_DATA[5]~1522 at LCCOMB_X43_Y16_N2
H1L7 = !H1L112 & (H1L6 # SW[13] & H1_LUT_INDEX[0]);


--H1L136 is I2C_CCD_Config:u7|reduce_or~167 at LCCOMB_X42_Y16_N20
H1L136 = H1_LUT_INDEX[4] $ (H1_LUT_INDEX[1] # H1_LUT_INDEX[3] # H1_LUT_INDEX[2]);


--H1L137 is I2C_CCD_Config:u7|reduce_or~168 at LCCOMB_X42_Y17_N26
H1L137 = H1_LUT_INDEX[2] & (!H1_LUT_INDEX[0] # !H1_LUT_INDEX[3]) # !H1_LUT_INDEX[2] & (H1_LUT_INDEX[3] # H1_LUT_INDEX[0] $ H1_LUT_INDEX[1]);


--H1L138 is I2C_CCD_Config:u7|reduce_or~169 at LCCOMB_X42_Y17_N20
H1L138 = H1_LUT_INDEX[4] & H1L37 & !H1_LUT_INDEX[0] # !H1_LUT_INDEX[4] & (H1L137);


--R1_command_delay[2] is Sdram_Control_4Port:u6|command:command1|command_delay[2] at LCFF_X20_Y10_N31
R1_command_delay[2] = DFFEAS(R1L70, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L69 is Sdram_Control_4Port:u6|command:command1|command_delay~332 at LCCOMB_X20_Y10_N18
R1L69 = !S1_INIT_REQ & (R1L57 # R1_command_delay[2]);


--R1_rp_shift[2] is Sdram_Control_4Port:u6|command:command1|rp_shift[2] at LCFF_X20_Y10_N7
R1_rp_shift[2] = DFFEAS(R1L106, GLOBAL(KB1L2),  ,  , R1L100,  ,  ,  ,  );


--R1L105 is Sdram_Control_4Port:u6|command:command1|rp_shift~807 at LCCOMB_X20_Y10_N2
R1L105 = !S1_INIT_REQ & (R1_rp_shift[2] # R1_command_done & !R1_command_delay[0]);


--D1_oDVAL is CCD_Capture:u3|oDVAL at LCCOMB_X57_Y10_N8
D1_oDVAL = D1_mCCD_LVAL & D1_mCCD_FVAL;


--P1_safe_q[0] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[0] at LCFF_X27_Y12_N3
P1_safe_q[0] = DFFEAS(P1_counter_comb_bita0, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[1] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[1] at LCFF_X27_Y12_N5
P1_safe_q[1] = DFFEAS(P1_counter_comb_bita1, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[2] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[2] at LCFF_X27_Y12_N7
P1_safe_q[2] = DFFEAS(P1_counter_comb_bita2, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[3] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[3] at LCFF_X27_Y12_N9
P1_safe_q[3] = DFFEAS(P1_counter_comb_bita3, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[4] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[4] at LCFF_X27_Y12_N11
P1_safe_q[4] = DFFEAS(P1_counter_comb_bita4, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[5] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[5] at LCFF_X27_Y12_N13
P1_safe_q[5] = DFFEAS(P1_counter_comb_bita5, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[6] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[6] at LCFF_X27_Y12_N15
P1_safe_q[6] = DFFEAS(P1_counter_comb_bita6, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[7] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[7] at LCFF_X27_Y12_N17
P1_safe_q[7] = DFFEAS(P1_counter_comb_bita7, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[8] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[8] at LCFF_X27_Y12_N19
P1_safe_q[8] = DFFEAS(P1_counter_comb_bita8, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[9] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[9] at LCFF_X27_Y12_N21
P1_safe_q[9] = DFFEAS(P1_counter_comb_bita9, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--P1_safe_q[10] is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|safe_q[10] at LCFF_X27_Y12_N23
P1_safe_q[10] = DFFEAS(P1_counter_comb_bita10, GLOBAL(A1L11),  ,  , D1_oDVAL, ~GND,  ,  , P1_cout_actual);


--D1_mCCD_DATA[0] is CCD_Capture:u3|mCCD_DATA[0] at LCFF_X47_Y22_N17
D1_mCCD_DATA[0] = DFFEAS(D1L170, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[1] is CCD_Capture:u3|mCCD_DATA[1] at LCFF_X45_Y21_N17
D1_mCCD_DATA[1] = DFFEAS(D1L172, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[2] is CCD_Capture:u3|mCCD_DATA[2] at LCFF_X28_Y15_N17
D1_mCCD_DATA[2] = DFFEAS(D1L174, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[3] is CCD_Capture:u3|mCCD_DATA[3] at LCFF_X53_Y20_N29
D1_mCCD_DATA[3] = DFFEAS(D1L176, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[4] is CCD_Capture:u3|mCCD_DATA[4] at LCFF_X57_Y19_N17
D1_mCCD_DATA[4] = DFFEAS(D1L178, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[5] is CCD_Capture:u3|mCCD_DATA[5] at LCFF_X59_Y15_N7
D1_mCCD_DATA[5] = DFFEAS(D1L180, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[6] is CCD_Capture:u3|mCCD_DATA[6] at LCFF_X57_Y20_N31
D1_mCCD_DATA[6] = DFFEAS(D1L182, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--D1_mCCD_DATA[7] is CCD_Capture:u3|mCCD_DATA[7] at LCFF_X53_Y15_N13
D1_mCCD_DATA[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , rCCD_DATA[7],  ,  , VCC);


--D1_mCCD_DATA[8] is CCD_Capture:u3|mCCD_DATA[8] at LCFF_X61_Y17_N7
D1_mCCD_DATA[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11), GLOBAL(C1L81),  ,  , rCCD_DATA[8],  ,  , VCC);


--D1_mCCD_DATA[9] is CCD_Capture:u3|mCCD_DATA[9] at LCFF_X56_Y18_N17
D1_mCCD_DATA[9] = DFFEAS(D1L186, GLOBAL(A1L11), GLOBAL(C1L81),  ,  ,  ,  ,  ,  );


--LB1L10 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK3~215 at LCCOMB_X45_Y17_N30
LB1L10 = LB1L51Q & LB1L66Q & (LB1L67 # LB1L47);


--LB1L85 is I2C_CCD_Config:u7|I2C_Controller:u0|Select~1099 at LCCOMB_X44_Y17_N2
LB1L85 = LB1L51Q & (!LB1L57Q & CCD_SDAT) # !LB1L51Q & LB1_ACK1;


--LB1L2 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK1~170 at LCCOMB_X44_Y17_N26
LB1L2 = LB1L63Q & LB1L66Q & (LB1L60Q $ !LB1L57Q);


--LB1L3 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK1~171 at LCCOMB_X44_Y17_N18
LB1L3 = LB1L54Q & (LB1L2 & (LB1L85) # !LB1L2 & LB1_ACK1) # !LB1L54Q & (LB1_ACK1);


--LB1L6 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK2~251 at LCCOMB_X44_Y17_N20
LB1L6 = LB1L51Q & (!LB1L57Q # !LB1L63Q) # !LB1L51Q & (LB1L63Q # LB1L57Q) # !LB1L66Q;


--H1L41 is I2C_CCD_Config:u7|Select~137 at LCCOMB_X44_Y16_N24
H1L41 = !H1_mSetup_ST.0010 & (H1L129 # LB1_END # !H1_mSetup_ST.0001);


--R1_command_delay[3] is Sdram_Control_4Port:u6|command:command1|command_delay[3] at LCFF_X20_Y11_N17
R1_command_delay[3] = DFFEAS(R1L71, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L70 is Sdram_Control_4Port:u6|command:command1|command_delay~333 at LCCOMB_X20_Y10_N30
R1L70 = !S1_INIT_REQ & (R1_command_delay[3] # R1L57);


--R1_rp_shift[3] is Sdram_Control_4Port:u6|command:command1|rp_shift[3] at LCFF_X20_Y10_N29
R1_rp_shift[3] = DFFEAS(R1L108, GLOBAL(KB1L2),  ,  ,  ,  ,  , S1_INIT_REQ,  );


--R1L106 is Sdram_Control_4Port:u6|command:command1|rp_shift~808 at LCCOMB_X20_Y10_N6
R1L106 = !S1_INIT_REQ & (R1_rp_shift[3] # !R1_command_delay[0] & R1_command_done);


--P1_counter_comb_bita0 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita0 at LCCOMB_X27_Y12_N2
P1_counter_comb_bita0 = P1_safe_q[0] $ VCC;

--P1L5 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita0~COUT at LCCOMB_X27_Y12_N2
P1L5 = CARRY(P1_safe_q[0]);


--P1_counter_comb_bita1 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita1 at LCCOMB_X27_Y12_N4
P1_counter_comb_bita1 = P1_safe_q[1] & !P1L5 # !P1_safe_q[1] & (P1L5 # GND);

--P1L7 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita1~COUT at LCCOMB_X27_Y12_N4
P1L7 = CARRY(!P1L5 # !P1_safe_q[1]);


--P1_counter_comb_bita2 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita2 at LCCOMB_X27_Y12_N6
P1_counter_comb_bita2 = P1_safe_q[2] & (P1L7 $ GND) # !P1_safe_q[2] & !P1L7 & VCC;

--P1L9 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita2~COUT at LCCOMB_X27_Y12_N6
P1L9 = CARRY(P1_safe_q[2] & !P1L7);


--P1_counter_comb_bita3 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita3 at LCCOMB_X27_Y12_N8
P1_counter_comb_bita3 = P1_safe_q[3] & !P1L9 # !P1_safe_q[3] & (P1L9 # GND);

--P1L11 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita3~COUT at LCCOMB_X27_Y12_N8
P1L11 = CARRY(!P1L9 # !P1_safe_q[3]);


--P1_counter_comb_bita4 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita4 at LCCOMB_X27_Y12_N10
P1_counter_comb_bita4 = P1_safe_q[4] & (P1L11 $ GND) # !P1_safe_q[4] & !P1L11 & VCC;

--P1L13 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita4~COUT at LCCOMB_X27_Y12_N10
P1L13 = CARRY(P1_safe_q[4] & !P1L11);


--P1_counter_comb_bita5 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita5 at LCCOMB_X27_Y12_N12
P1_counter_comb_bita5 = P1_safe_q[5] & !P1L13 # !P1_safe_q[5] & (P1L13 # GND);

--P1L15 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita5~COUT at LCCOMB_X27_Y12_N12
P1L15 = CARRY(!P1L13 # !P1_safe_q[5]);


--P1_counter_comb_bita6 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita6 at LCCOMB_X27_Y12_N14
P1_counter_comb_bita6 = P1_safe_q[6] & (P1L15 $ GND) # !P1_safe_q[6] & !P1L15 & VCC;

--P1L17 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita6~COUT at LCCOMB_X27_Y12_N14
P1L17 = CARRY(P1_safe_q[6] & !P1L15);


--P1_counter_comb_bita7 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita7 at LCCOMB_X27_Y12_N16
P1_counter_comb_bita7 = P1_safe_q[7] & !P1L17 # !P1_safe_q[7] & (P1L17 # GND);

--P1L19 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita7~COUT at LCCOMB_X27_Y12_N16
P1L19 = CARRY(!P1L17 # !P1_safe_q[7]);


--P1_counter_comb_bita8 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita8 at LCCOMB_X27_Y12_N18
P1_counter_comb_bita8 = P1_safe_q[8] & (P1L19 $ GND) # !P1_safe_q[8] & !P1L19 & VCC;

--P1L21 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita8~COUT at LCCOMB_X27_Y12_N18
P1L21 = CARRY(P1_safe_q[8] & !P1L19);


--P1_counter_comb_bita9 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita9 at LCCOMB_X27_Y12_N20
P1_counter_comb_bita9 = P1_safe_q[9] & !P1L21 # !P1_safe_q[9] & (P1L21 # GND);

--P1L23 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita9~COUT at LCCOMB_X27_Y12_N20
P1L23 = CARRY(!P1L21 # !P1_safe_q[9]);


--P1_counter_comb_bita10 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita10 at LCCOMB_X27_Y12_N22
P1_counter_comb_bita10 = P1_safe_q[10] & (P1L23 $ GND) # !P1_safe_q[10] & !P1L23 & VCC;

--P1L27 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita10~COUT at LCCOMB_X27_Y12_N22
P1L27 = CARRY(P1_safe_q[10] & !P1L23);


--P1L25 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|counter_comb_bita10~9 at LCCOMB_X27_Y12_N24
P1L25 = P1L27;


--P1L1 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|cmpr5_aeb_int~68 at LCCOMB_X27_Y12_N28
P1L1 = !P1_safe_q[1] & P1_safe_q[0] & P1_safe_q[3] & P1_safe_q[2];


--P1L2 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|cmpr5_aeb_int~69 at LCCOMB_X27_Y12_N30
P1L2 = P1_safe_q[7] & P1_safe_q[4] & P1_safe_q[6] & P1_safe_q[5];


--P1L3 is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|cmpr5_aeb_int~70 at LCCOMB_X27_Y12_N0
P1L3 = P1_safe_q[10] & !P1_safe_q[9] & !P1_safe_q[8];


--P1_cout_actual is RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_jei:auto_generated|cntr_1tc:cntr1|cout_actual at LCCOMB_X27_Y12_N26
P1_cout_actual = P1L25 # P1L3 & P1L1 & P1L2;


--R1_command_delay[4] is Sdram_Control_4Port:u6|command:command1|command_delay[4] at LCFF_X20_Y11_N19
R1_command_delay[4] = DFFEAS(R1L72, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L71 is Sdram_Control_4Port:u6|command:command1|command_delay~334 at LCCOMB_X20_Y11_N16
R1L71 = !S1_INIT_REQ & (R1L57 # R1_command_delay[4]);


--R1L107 is Sdram_Control_4Port:u6|command:command1|rp_shift~809 at LCCOMB_X20_Y10_N26
R1L107 = R1_rp_shift[3] & (R1_ex_read # R1_ex_write);


--R1L108 is Sdram_Control_4Port:u6|command:command1|rp_shift~810 at LCCOMB_X20_Y10_N28
R1L108 = G1_PM_STOP & !R1_command_delay[0] & R1_command_done # !G1_PM_STOP & (R1L107 # !R1_command_delay[0] & R1_command_done);


--R1_command_delay[5] is Sdram_Control_4Port:u6|command:command1|command_delay[5] at LCFF_X20_Y11_N31
R1_command_delay[5] = DFFEAS(R1L73, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L72 is Sdram_Control_4Port:u6|command:command1|command_delay~335 at LCCOMB_X20_Y11_N18
R1L72 = !S1_INIT_REQ & (R1L57 # R1_command_delay[5]);


--R1_command_delay[6] is Sdram_Control_4Port:u6|command:command1|command_delay[6] at LCFF_X20_Y11_N27
R1_command_delay[6] = DFFEAS(R1L74, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L73 is Sdram_Control_4Port:u6|command:command1|command_delay~336 at LCCOMB_X20_Y11_N30
R1L73 = !S1_INIT_REQ & (R1L57 # R1_command_delay[6]);


--R1_command_delay[7] is Sdram_Control_4Port:u6|command:command1|command_delay[7] at LCFF_X20_Y11_N7
R1_command_delay[7] = DFFEAS(R1L75, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--R1L74 is Sdram_Control_4Port:u6|command:command1|command_delay~337 at LCCOMB_X20_Y11_N26
R1L74 = !S1_INIT_REQ & (R1L57 # R1_command_delay[7]);


--R1L75 is Sdram_Control_4Port:u6|command:command1|command_delay~338 at LCCOMB_X20_Y11_N6
R1L75 = !S1_INIT_REQ & (R1_do_reada # !R1L55 # !R1L110);


--LB1L46 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[15]~8 at LCCOMB_X45_Y17_N24
LB1L46 = !LB1L51Q & LB1L47 & LB1L66Q & KEY[1];


--H1L11 is I2C_CCD_Config:u7|LUT_DATA[7]~1523 at LCCOMB_X42_Y16_N0
H1L11 = H1L10 & !H1_LUT_INDEX[5] & (!H1L111 # !H1_LUT_INDEX[0]);


--LB1L11 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK3~216 at LCCOMB_X44_Y17_N10
LB1L11 = LB1L10 & CCD_SDAT & !LB1L63Q # !LB1L10 & (LB1_ACK3);


--LB1L5 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK2~237 at LCCOMB_X44_Y17_N28
LB1L5 = !LB1L51Q & !LB1L63Q & !LB1L57Q & CCD_SDAT;


--LB1L7 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK2~252 at LCCOMB_X44_Y17_N12
LB1L7 = LB1L66Q & (LB1L5 # LB1L6 & LB1_ACK2) # !LB1L66Q & (LB1L6 & LB1_ACK2);


--LB1L8 is I2C_CCD_Config:u7|I2C_Controller:u0|ACK2~253 at LCCOMB_X44_Y17_N22
LB1L8 = LB1L60Q & (LB1L54Q & (LB1L7) # !LB1L54Q & LB1_ACK2) # !LB1L60Q & (LB1_ACK2);


--A1L8 is CCD_MCLK~2 at LCCOMB_X58_Y32_N14
A1L8 = !CCD_MCLK;


--X4L52 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]~19 at LCCOMB_X24_Y17_N16
X4L52 = !EB4_counter_ffa[0];


--X3L47 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]~19 at LCCOMB_X28_Y18_N30
X3L47 = !EB3_counter_ffa[0];


--X1L47 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]~19 at LCCOMB_X14_Y13_N6
X1L47 = !EB1_counter_ffa[0];


--X2L51 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[0]~19 at LCCOMB_X27_Y13_N4
X2L51 = !EB2_counter_ffa[0];


--~GND is ~GND at LCCOMB_X16_Y15_N16
~GND = GND;


--CLOCK_27 is CLOCK_27 at PIN_D13
--operation mode is input

CLOCK_27 = INPUT();


--EXT_CLOCK is EXT_CLOCK at PIN_P26
--operation mode is input

EXT_CLOCK = INPUT();


--UART_RXD is UART_RXD at PIN_C25
--operation mode is input

UART_RXD = INPUT();


--IRDA_RXD is IRDA_RXD at PIN_AE25
--operation mode is input

IRDA_RXD = INPUT();


--OTG_INT0 is OTG_INT0 at PIN_B3
--operation mode is input

OTG_INT0 = INPUT();


--OTG_INT1 is OTG_INT1 at PIN_C3
--operation mode is input

OTG_INT1 = INPUT();


--OTG_DREQ0 is OTG_DREQ0 at PIN_F6
--operation mode is input

OTG_DREQ0 = INPUT();


--OTG_DREQ1 is OTG_DREQ1 at PIN_E5
--operation mode is input

OTG_DREQ1 = INPUT();


--TDI is TDI at PIN_B14
--operation mode is input

TDI = INPUT();


--TCK is TCK at PIN_D14
--operation mode is input

TCK = INPUT();


--TCS is TCS at PIN_A14
--operation mode is input

TCS = INPUT();


--PS2_DAT is PS2_DAT at PIN_C24
--operation mode is input

PS2_DAT = INPUT();


--PS2_CLK is PS2_CLK at PIN_D26
--operation mode is input

PS2_CLK = INPUT();


--ENET_INT is ENET_INT at PIN_B21
--operation mode is input

ENET_INT = INPUT();


--AUD_ADCDAT is AUD_ADCDAT at PIN_B5
--operation mode is input

AUD_ADCDAT = INPUT();


--TD_DATA[0] is TD_DATA[0] at PIN_J9
--operation mode is input

TD_DATA[0] = INPUT();


--TD_DATA[1] is TD_DATA[1] at PIN_E8
--operation mode is input

TD_DATA[1] = INPUT();


--TD_DATA[2] is TD_DATA[2] at PIN_H8
--operation mode is input

TD_DATA[2] = INPUT();


--TD_DATA[3] is TD_DATA[3] at PIN_H10
--operation mode is input

TD_DATA[3] = INPUT();


--TD_DATA[4] is TD_DATA[4] at PIN_G9
--operation mode is input

TD_DATA[4] = INPUT();


--TD_DATA[5] is TD_DATA[5] at PIN_F9
--operation mode is input

TD_DATA[5] = INPUT();


--TD_DATA[6] is TD_DATA[6] at PIN_D7
--operation mode is input

TD_DATA[6] = INPUT();


--TD_DATA[7] is TD_DATA[7] at PIN_C7
--operation mode is input

TD_DATA[7] = INPUT();


--TD_HS is TD_HS at PIN_D5
--operation mode is input

TD_HS = INPUT();


--TD_VS is TD_VS at PIN_K9
--operation mode is input

TD_VS = INPUT();


--SW[0] is SW[0] at PIN_N25
--operation mode is input

SW[0] = INPUT();


--SW[1] is SW[1] at PIN_N26
--operation mode is input

SW[1] = INPUT();


--SW[2] is SW[2] at PIN_P25
--operation mode is input

SW[2] = INPUT();


--SW[3] is SW[3] at PIN_AE14
--operation mode is input

SW[3] = INPUT();


--SW[4] is SW[4] at PIN_AF14
--operation mode is input

SW[4] = INPUT();


--SW[5] is SW[5] at PIN_AD13
--operation mode is input

SW[5] = INPUT();


--SW[6] is SW[6] at PIN_AC13
--operation mode is input

SW[6] = INPUT();


--SW[7] is SW[7] at PIN_C13
--operation mode is input

SW[7] = INPUT();


--SW[8] is SW[8] at PIN_B13
--operation mode is input

SW[8] = INPUT();


--SW[9] is SW[9] at PIN_A13
--operation mode is input

SW[9] = INPUT();


--SW[10] is SW[10] at PIN_N1
--operation mode is input

SW[10] = INPUT();


--SW[11] is SW[11] at PIN_P1
--operation mode is input

SW[11] = INPUT();


--SW[12] is SW[12] at PIN_P2
--operation mode is input

SW[12] = INPUT();


--SW[13] is SW[13] at PIN_T7
--operation mode is input

SW[13] = INPUT();


--SW[14] is SW[14] at PIN_U3
--operation mode is input

SW[14] = INPUT();


--SW[15] is SW[15] at PIN_U4
--operation mode is input

SW[15] = INPUT();


--SW[16] is SW[16] at PIN_V1
--operation mode is input

SW[16] = INPUT();


--SW[17] is SW[17] at PIN_V2
--operation mode is input

SW[17] = INPUT();


--CLOCK_50 is CLOCK_50 at PIN_N2
--operation mode is input

CLOCK_50 = INPUT();


--KEY[0] is KEY[0] at PIN_G26
--operation mode is input

KEY[0] = INPUT();


--KEY[2] is KEY[2] at PIN_P23
--operation mode is input

KEY[2] = INPUT();


--KEY[3] is KEY[3] at PIN_W26
--operation mode is input

KEY[3] = INPUT();


--KEY[1] is KEY[1] at PIN_N23
--operation mode is input

KEY[1] = INPUT();


--HEX0[0] is HEX0[0] at PIN_AF10
--operation mode is output

HEX0[0] = OUTPUT(Q1L1);


--HEX0[1] is HEX0[1] at PIN_AB12
--operation mode is output

HEX0[1] = OUTPUT(Q1L2);


--HEX0[2] is HEX0[2] at PIN_AC12
--operation mode is output

HEX0[2] = OUTPUT(Q1L3);


--HEX0[3] is HEX0[3] at PIN_AD11
--operation mode is output

HEX0[3] = OUTPUT(Q1L4);


--HEX0[4] is HEX0[4] at PIN_AE11
--operation mode is output

HEX0[4] = OUTPUT(Q1L5);


--HEX0[5] is HEX0[5] at PIN_V14
--operation mode is output

HEX0[5] = OUTPUT(Q1L6);


--HEX0[6] is HEX0[6] at PIN_V13
--operation mode is output

HEX0[6] = OUTPUT(!Q1L7);


--HEX1[0] is HEX1[0] at PIN_V20
--operation mode is output

HEX1[0] = OUTPUT(Q2L1);


--HEX1[1] is HEX1[1] at PIN_V21
--operation mode is output

HEX1[1] = OUTPUT(Q2L2);


--HEX1[2] is HEX1[2] at PIN_W21
--operation mode is output

HEX1[2] = OUTPUT(Q2L3);


--HEX1[3] is HEX1[3] at PIN_Y22
--operation mode is output

HEX1[3] = OUTPUT(Q2L4);


--HEX1[4] is HEX1[4] at PIN_AA24
--operation mode is output

HEX1[4] = OUTPUT(Q2L5);


--HEX1[5] is HEX1[5] at PIN_AA23
--operation mode is output

HEX1[5] = OUTPUT(Q2L6);


--HEX1[6] is HEX1[6] at PIN_AB24
--operation mode is output

HEX1[6] = OUTPUT(!Q2L7);


--HEX2[0] is HEX2[0] at PIN_AB23
--operation mode is output

HEX2[0] = OUTPUT(Q3L1);


--HEX2[1] is HEX2[1] at PIN_V22
--operation mode is output

HEX2[1] = OUTPUT(Q3L2);


--HEX2[2] is HEX2[2] at PIN_AC25
--operation mode is output

HEX2[2] = OUTPUT(Q3L3);


--HEX2[3] is HEX2[3] at PIN_AC26
--operation mode is output

HEX2[3] = OUTPUT(Q3L4);


--HEX2[4] is HEX2[4] at PIN_AB26
--operation mode is output

HEX2[4] = OUTPUT(Q3L5);


--HEX2[5] is HEX2[5] at PIN_AB25
--operation mode is output

HEX2[5] = OUTPUT(Q3L6);


--HEX2[6] is HEX2[6] at PIN_Y24
--operation mode is output

HEX2[6] = OUTPUT(!Q3L7);


--HEX3[0] is HEX3[0] at PIN_Y23
--operation mode is output

HEX3[0] = OUTPUT(Q4L1);


--HEX3[1] is HEX3[1] at PIN_AA25
--operation mode is output

HEX3[1] = OUTPUT(Q4L2);


--HEX3[2] is HEX3[2] at PIN_AA26
--operation mode is output

HEX3[2] = OUTPUT(Q4L3);


--HEX3[3] is HEX3[3] at PIN_Y26
--operation mode is output

HEX3[3] = OUTPUT(Q4L4);


--HEX3[4] is HEX3[4] at PIN_Y25
--operation mode is output

HEX3[4] = OUTPUT(Q4L5);


--HEX3[5] is HEX3[5] at PIN_U22
--operation mode is output

HEX3[5] = OUTPUT(Q4L6);


--HEX3[6] is HEX3[6] at PIN_W24
--operation mode is output

HEX3[6] = OUTPUT(!Q4L7);


--HEX4[0] is HEX4[0] at PIN_U9
--operation mode is output

HEX4[0] = OUTPUT(Q5L1);


--HEX4[1] is HEX4[1] at PIN_U1
--operation mode is output

HEX4[1] = OUTPUT(Q5L2);


--HEX4[2] is HEX4[2] at PIN_U2
--operation mode is output

HEX4[2] = OUTPUT(Q5L3);


--HEX4[3] is HEX4[3] at PIN_T4
--operation mode is output

HEX4[3] = OUTPUT(Q5L4);


--HEX4[4] is HEX4[4] at PIN_R7
--operation mode is output

HEX4[4] = OUTPUT(Q5L5);


--HEX4[5] is HEX4[5] at PIN_R6
--operation mode is output

HEX4[5] = OUTPUT(Q5L6);


--HEX4[6] is HEX4[6] at PIN_T3
--operation mode is output

HEX4[6] = OUTPUT(!Q5L7);


--HEX5[0] is HEX5[0] at PIN_T2
--operation mode is output

HEX5[0] = OUTPUT(Q6L1);


--HEX5[1] is HEX5[1] at PIN_P6
--operation mode is output

HEX5[1] = OUTPUT(Q6L2);


--HEX5[2] is HEX5[2] at PIN_P7
--operation mode is output

HEX5[2] = OUTPUT(Q6L3);


--HEX5[3] is HEX5[3] at PIN_T9
--operation mode is output

HEX5[3] = OUTPUT(Q6L4);


--HEX5[4] is HEX5[4] at PIN_R5
--operation mode is output

HEX5[4] = OUTPUT(Q6L5);


--HEX5[5] is HEX5[5] at PIN_R4
--operation mode is output

HEX5[5] = OUTPUT(Q6L6);


--HEX5[6] is HEX5[6] at PIN_R3
--operation mode is output

HEX5[6] = OUTPUT(!Q6L7);


--HEX6[0] is HEX6[0] at PIN_R2
--operation mode is output

HEX6[0] = OUTPUT(Q7L1);


--HEX6[1] is HEX6[1] at PIN_P4
--operation mode is output

HEX6[1] = OUTPUT(Q7L2);


--HEX6[2] is HEX6[2] at PIN_P3
--operation mode is output

HEX6[2] = OUTPUT(Q7L3);


--HEX6[3] is HEX6[3] at PIN_M2
--operation mode is output

HEX6[3] = OUTPUT(Q7L4);


--HEX6[4] is HEX6[4] at PIN_M3
--operation mode is output

HEX6[4] = OUTPUT(Q7L5);


--HEX6[5] is HEX6[5] at PIN_M5
--operation mode is output

HEX6[5] = OUTPUT(Q7L6);


--HEX6[6] is HEX6[6] at PIN_M4
--operation mode is output

HEX6[6] = OUTPUT(!Q7L7);


--HEX7[0] is HEX7[0] at PIN_L3
--operation mode is output

HEX7[0] = OUTPUT(Q8L1);


--HEX7[1] is HEX7[1] at PIN_L2
--operation mode is output

HEX7[1] = OUTPUT(Q8L2);


--HEX7[2] is HEX7[2] at PIN_L9
--operation mode is output

HEX7[2] = OUTPUT(Q8L3);


--HEX7[3] is HEX7[3] at PIN_L6
--operation mode is output

HEX7[3] = OUTPUT(Q8L4);


--HEX7[4] is HEX7[4] at PIN_L7
--operation mode is output

HEX7[4] = OUTPUT(Q8L5);


--HEX7[5] is HEX7[5] at PIN_P9
--operation mode is output

HEX7[5] = OUTPUT(Q8L6);


--HEX7[6] is HEX7[6] at PIN_N9
--operation mode is output

HEX7[6] = OUTPUT(!Q8L7);


--LEDG[0] is LEDG[0] at PIN_AE22
--operation mode is output

LEDG[0] = OUTPUT(D1_Y_Cont[0]);


--LEDG[1] is LEDG[1] at PIN_AF22
--operation mode is output

LEDG[1] = OUTPUT(D1_Y_Cont[1]);


--LEDG[2] is LEDG[2] at PIN_W19
--operation mode is output

LEDG[2] = OUTPUT(D1_Y_Cont[2]);


--LEDG[3] is LEDG[3] at PIN_V18
--operation mode is output

LEDG[3] = OUTPUT(D1_Y_Cont[3]);


--LEDG[4] is LEDG[4] at PIN_U18
--operation mode is output

LEDG[4] = OUTPUT(D1_Y_Cont[4]);


--LEDG[5] is LEDG[5] at PIN_U17
--operation mode is output

LEDG[5] = OUTPUT(D1_Y_Cont[5]);


--LEDG[6] is LEDG[6] at PIN_AA20
--operation mode is output

LEDG[6] = OUTPUT(D1_Y_Cont[6]);


--LEDG[7] is LEDG[7] at PIN_Y18
--operation mode is output

LEDG[7] = OUTPUT(D1_Y_Cont[7]);


--LEDG[8] is LEDG[8] at PIN_Y12
--operation mode is output

LEDG[8] = OUTPUT(D1_Y_Cont[8]);


--LEDR[0] is LEDR[0] at PIN_AE23
--operation mode is output

LEDR[0] = OUTPUT(SW[0]);


--LEDR[1] is LEDR[1] at PIN_AF23
--operation mode is output

LEDR[1] = OUTPUT(SW[1]);


--LEDR[2] is LEDR[2] at PIN_AB21
--operation mode is output

LEDR[2] = OUTPUT(SW[2]);


--LEDR[3] is LEDR[3] at PIN_AC22
--operation mode is output

LEDR[3] = OUTPUT(SW[3]);


--LEDR[4] is LEDR[4] at PIN_AD22
--operation mode is output

LEDR[4] = OUTPUT(SW[4]);


--LEDR[5] is LEDR[5] at PIN_AD23
--operation mode is output

LEDR[5] = OUTPUT(SW[5]);


--LEDR[6] is LEDR[6] at PIN_AD21
--operation mode is output

LEDR[6] = OUTPUT(SW[6]);


--LEDR[7] is LEDR[7] at PIN_AC21
--operation mode is output

LEDR[7] = OUTPUT(SW[7]);


--LEDR[8] is LEDR[8] at PIN_AA14
--operation mode is output

LEDR[8] = OUTPUT(SW[8]);


--LEDR[9] is LEDR[9] at PIN_Y13
--operation mode is output

LEDR[9] = OUTPUT(SW[9]);


--LEDR[10] is LEDR[10] at PIN_AA13
--operation mode is output

LEDR[10] = OUTPUT(SW[10]);


--LEDR[11] is LEDR[11] at PIN_AC14
--operation mode is output

LEDR[11] = OUTPUT(SW[11]);


--LEDR[12] is LEDR[12] at PIN_AD15
--operation mode is output

LEDR[12] = OUTPUT(SW[12]);


--LEDR[13] is LEDR[13] at PIN_AE15
--operation mode is output

LEDR[13] = OUTPUT(SW[13]);


--LEDR[14] is LEDR[14] at PIN_AF13
--operation mode is output

LEDR[14] = OUTPUT(SW[14]);


--LEDR[15] is LEDR[15] at PIN_AE13
--operation mode is output

LEDR[15] = OUTPUT(SW[15]);


--LEDR[16] is LEDR[16] at PIN_AE12
--operation mode is output

LEDR[16] = OUTPUT(SW[16]);


--LEDR[17] is LEDR[17] at PIN_AD12
--operation mode is output

LEDR[17] = OUTPUT(SW[17]);


--UART_TXD is UART_TXD at PIN_B25
--operation mode is output

UART_TXD = OUTPUT(GND);


--IRDA_TXD is IRDA_TXD at PIN_AE24
--operation mode is output

IRDA_TXD = OUTPUT(GND);


--DRAM_ADDR[0] is DRAM_ADDR[0] at PIN_T6
--operation mode is output

DRAM_ADDR[0] = OUTPUT(G1_SA[0]);


--DRAM_ADDR[1] is DRAM_ADDR[1] at PIN_V4
--operation mode is output

DRAM_ADDR[1] = OUTPUT(G1_SA[1]);


--DRAM_ADDR[2] is DRAM_ADDR[2] at PIN_V3
--operation mode is output

DRAM_ADDR[2] = OUTPUT(G1_SA[2]);


--DRAM_ADDR[3] is DRAM_ADDR[3] at PIN_W2
--operation mode is output

DRAM_ADDR[3] = OUTPUT(G1_SA[3]);


--DRAM_ADDR[4] is DRAM_ADDR[4] at PIN_W1
--operation mode is output

DRAM_ADDR[4] = OUTPUT(G1_SA[4]);


--DRAM_ADDR[5] is DRAM_ADDR[5] at PIN_U6
--operation mode is output

DRAM_ADDR[5] = OUTPUT(G1_SA[5]);


--DRAM_ADDR[6] is DRAM_ADDR[6] at PIN_U7
--operation mode is output

DRAM_ADDR[6] = OUTPUT(G1_SA[6]);


--DRAM_ADDR[7] is DRAM_ADDR[7] at PIN_U5
--operation mode is output

DRAM_ADDR[7] = OUTPUT(G1_SA[7]);


--DRAM_ADDR[8] is DRAM_ADDR[8] at PIN_W4
--operation mode is output

DRAM_ADDR[8] = OUTPUT(G1_SA[8]);


--DRAM_ADDR[9] is DRAM_ADDR[9] at PIN_W3
--operation mode is output

DRAM_ADDR[9] = OUTPUT(G1_SA[9]);


--DRAM_ADDR[10] is DRAM_ADDR[10] at PIN_Y1
--operation mode is output

DRAM_ADDR[10] = OUTPUT(G1_SA[10]);


--DRAM_ADDR[11] is DRAM_ADDR[11] at PIN_V5
--operation mode is output

DRAM_ADDR[11] = OUTPUT(G1_SA[11]);


--DRAM_LDQM is DRAM_LDQM at PIN_AD2
--operation mode is output

DRAM_LDQM = OUTPUT(G1_DQM[1]);


--DRAM_UDQM is DRAM_UDQM at PIN_Y5
--operation mode is output

DRAM_UDQM = OUTPUT(G1_DQM[1]);


--DRAM_WE_N is DRAM_WE_N at PIN_AD3
--operation mode is output

DRAM_WE_N = OUTPUT(G1_WE_N);


--DRAM_CAS_N is DRAM_CAS_N at PIN_AB3
--operation mode is output

DRAM_CAS_N = OUTPUT(G1_CAS_N);


--DRAM_RAS_N is DRAM_RAS_N at PIN_AB4
--operation mode is output

DRAM_RAS_N = OUTPUT(G1_RAS_N);


--DRAM_CS_N is DRAM_CS_N at PIN_AC3
--operation mode is output

DRAM_CS_N = OUTPUT(G1_CS_N[0]);


--DRAM_BA_0 is DRAM_BA_0 at PIN_AE2
--operation mode is output

DRAM_BA_0 = OUTPUT(G1_BA[0]);


--DRAM_BA_1 is DRAM_BA_1 at PIN_AE3
--operation mode is output

DRAM_BA_1 = OUTPUT(G1_BA[1]);


--DRAM_CLK is DRAM_CLK at PIN_AA7
--operation mode is output

DRAM_CLK = OUTPUT(A1L34);


--DRAM_CKE is DRAM_CKE at PIN_AA6
--operation mode is output

DRAM_CKE = OUTPUT(VCC);


--FL_ADDR[0] is FL_ADDR[0] at PIN_AC18
--operation mode is output

FL_ADDR[0] = OUTPUT(GND);


--FL_ADDR[1] is FL_ADDR[1] at PIN_AB18
--operation mode is output

FL_ADDR[1] = OUTPUT(GND);


--FL_ADDR[2] is FL_ADDR[2] at PIN_AE19
--operation mode is output

FL_ADDR[2] = OUTPUT(GND);


--FL_ADDR[3] is FL_ADDR[3] at PIN_AF19
--operation mode is output

FL_ADDR[3] = OUTPUT(GND);


--FL_ADDR[4] is FL_ADDR[4] at PIN_AE18
--operation mode is output

FL_ADDR[4] = OUTPUT(GND);


--FL_ADDR[5] is FL_ADDR[5] at PIN_AF18
--operation mode is output

FL_ADDR[5] = OUTPUT(GND);


--FL_ADDR[6] is FL_ADDR[6] at PIN_Y16
--operation mode is output

FL_ADDR[6] = OUTPUT(GND);


--FL_ADDR[7] is FL_ADDR[7] at PIN_AA16
--operation mode is output

FL_ADDR[7] = OUTPUT(GND);


--FL_ADDR[8] is FL_ADDR[8] at PIN_AD17
--operation mode is output

FL_ADDR[8] = OUTPUT(GND);


--FL_ADDR[9] is FL_ADDR[9] at PIN_AC17
--operation mode is output

FL_ADDR[9] = OUTPUT(GND);


--FL_ADDR[10] is FL_ADDR[10] at PIN_AE17
--operation mode is output

FL_ADDR[10] = OUTPUT(GND);


--FL_ADDR[11] is FL_ADDR[11] at PIN_AF17
--operation mode is output

FL_ADDR[11] = OUTPUT(GND);


--FL_ADDR[12] is FL_ADDR[12] at PIN_W16
--operation mode is output

FL_ADDR[12] = OUTPUT(GND);


--FL_ADDR[13] is FL_ADDR[13] at PIN_W15
--operation mode is output

FL_ADDR[13] = OUTPUT(GND);


--FL_ADDR[14] is FL_ADDR[14] at PIN_AC16
--operation mode is output

FL_ADDR[14] = OUTPUT(GND);


--FL_ADDR[15] is FL_ADDR[15] at PIN_AD16
--operation mode is output

FL_ADDR[15] = OUTPUT(GND);


--FL_ADDR[16] is FL_ADDR[16] at PIN_AE16
--operation mode is output

FL_ADDR[16] = OUTPUT(GND);


--FL_ADDR[17] is FL_ADDR[17] at PIN_AC15
--operation mode is output

FL_ADDR[17] = OUTPUT(GND);


--FL_ADDR[18] is FL_ADDR[18] at PIN_AB15
--operation mode is output

FL_ADDR[18] = OUTPUT(GND);


--FL_ADDR[19] is FL_ADDR[19] at PIN_AA15
--operation mode is output

FL_ADDR[19] = OUTPUT(GND);


--FL_ADDR[20] is FL_ADDR[20] at PIN_Y15
--operation mode is output

FL_ADDR[20] = OUTPUT(GND);


--FL_ADDR[21] is FL_ADDR[21] at PIN_Y14
--operation mode is output

FL_ADDR[21] = OUTPUT(GND);


--FL_WE_N is FL_WE_N at PIN_AA17
--operation mode is output

FL_WE_N = OUTPUT(GND);


--FL_RST_N is FL_RST_N at PIN_AA18
--operation mode is output

FL_RST_N = OUTPUT(GND);


--FL_OE_N is FL_OE_N at PIN_W17
--operation mode is output

FL_OE_N = OUTPUT(GND);


--FL_CE_N is FL_CE_N at PIN_V17
--operation mode is output

FL_CE_N = OUTPUT(GND);


--SRAM_ADDR[0] is SRAM_ADDR[0] at PIN_AE4
--operation mode is output

SRAM_ADDR[0] = OUTPUT(GND);


--SRAM_ADDR[1] is SRAM_ADDR[1] at PIN_AF4
--operation mode is output

SRAM_ADDR[1] = OUTPUT(GND);


--SRAM_ADDR[2] is SRAM_ADDR[2] at PIN_AC5
--operation mode is output

SRAM_ADDR[2] = OUTPUT(GND);


--SRAM_ADDR[3] is SRAM_ADDR[3] at PIN_AC6
--operation mode is output

SRAM_ADDR[3] = OUTPUT(GND);


--SRAM_ADDR[4] is SRAM_ADDR[4] at PIN_AD4
--operation mode is output

SRAM_ADDR[4] = OUTPUT(GND);


--SRAM_ADDR[5] is SRAM_ADDR[5] at PIN_AD5
--operation mode is output

SRAM_ADDR[5] = OUTPUT(GND);


--SRAM_ADDR[6] is SRAM_ADDR[6] at PIN_AE5
--operation mode is output

SRAM_ADDR[6] = OUTPUT(GND);


--SRAM_ADDR[7] is SRAM_ADDR[7] at PIN_AF5
--operation mode is output

SRAM_ADDR[7] = OUTPUT(GND);


--SRAM_ADDR[8] is SRAM_ADDR[8] at PIN_AD6
--operation mode is output

SRAM_ADDR[8] = OUTPUT(GND);


--SRAM_ADDR[9] is SRAM_ADDR[9] at PIN_AD7
--operation mode is output

SRAM_ADDR[9] = OUTPUT(GND);


--SRAM_ADDR[10] is SRAM_ADDR[10] at PIN_V10
--operation mode is output

SRAM_ADDR[10] = OUTPUT(GND);


--SRAM_ADDR[11] is SRAM_ADDR[11] at PIN_V9
--operation mode is output

SRAM_ADDR[11] = OUTPUT(GND);


--SRAM_ADDR[12] is SRAM_ADDR[12] at PIN_AC7
--operation mode is output

SRAM_ADDR[12] = OUTPUT(GND);


--SRAM_ADDR[13] is SRAM_ADDR[13] at PIN_W8
--operation mode is output

SRAM_ADDR[13] = OUTPUT(GND);


--SRAM_ADDR[14] is SRAM_ADDR[14] at PIN_W10
--operation mode is output

SRAM_ADDR[14] = OUTPUT(GND);


--SRAM_ADDR[15] is SRAM_ADDR[15] at PIN_Y10
--operation mode is output

SRAM_ADDR[15] = OUTPUT(GND);


--SRAM_ADDR[16] is SRAM_ADDR[16] at PIN_AB8
--operation mode is output

SRAM_ADDR[16] = OUTPUT(GND);


--SRAM_ADDR[17] is SRAM_ADDR[17] at PIN_AC8
--operation mode is output

SRAM_ADDR[17] = OUTPUT(GND);


--SRAM_UB_N is SRAM_UB_N at PIN_AF9
--operation mode is output

SRAM_UB_N = OUTPUT(GND);


--SRAM_LB_N is SRAM_LB_N at PIN_AE9
--operation mode is output

SRAM_LB_N = OUTPUT(GND);


--SRAM_WE_N is SRAM_WE_N at PIN_AE10
--operation mode is output

SRAM_WE_N = OUTPUT(GND);


--SRAM_CE_N is SRAM_CE_N at PIN_AC11
--operation mode is output

SRAM_CE_N = OUTPUT(GND);


--SRAM_OE_N is SRAM_OE_N at PIN_AD10
--operation mode is output

SRAM_OE_N = OUTPUT(GND);


--OTG_ADDR[0] is OTG_ADDR[0] at PIN_K7
--operation mode is output

OTG_ADDR[0] = OUTPUT(GND);


--OTG_ADDR[1] is OTG_ADDR[1] at PIN_F2
--operation mode is output

OTG_ADDR[1] = OUTPUT(GND);


--OTG_CS_N is OTG_CS_N at PIN_F1
--operation mode is output

OTG_CS_N = OUTPUT(GND);


--OTG_RD_N is OTG_RD_N at PIN_G2
--operation mode is output

OTG_RD_N = OUTPUT(GND);


--OTG_WR_N is OTG_WR_N at PIN_G1
--operation mode is output

OTG_WR_N = OUTPUT(GND);


--OTG_RST_N is OTG_RST_N at PIN_G5
--operation mode is output

OTG_RST_N = OUTPUT(GND);


--OTG_FSPEED is OTG_FSPEED at PIN_F3
--operation mode is output

OTG_FSPEED = OUTPUT(GND);


--OTG_LSPEED is OTG_LSPEED at PIN_G6
--operation mode is output

OTG_LSPEED = OUTPUT(GND);


--OTG_DACK0_N is OTG_DACK0_N at PIN_C2
--operation mode is output

OTG_DACK0_N = OUTPUT(GND);


--OTG_DACK1_N is OTG_DACK1_N at PIN_B2
--operation mode is output

OTG_DACK1_N = OUTPUT(GND);


--LCD_ON is LCD_ON at PIN_L4
--operation mode is output

LCD_ON = OUTPUT(VCC);


--LCD_BLON is LCD_BLON at PIN_K2
--operation mode is output

LCD_BLON = OUTPUT(VCC);


--LCD_RW is LCD_RW at PIN_K4
--operation mode is output

LCD_RW = OUTPUT(GND);


--LCD_EN is LCD_EN at PIN_K3
--operation mode is output

LCD_EN = OUTPUT(GND);


--LCD_RS is LCD_RS at PIN_K1
--operation mode is output

LCD_RS = OUTPUT(GND);


--SD_CLK is SD_CLK at PIN_AD25
--operation mode is output

SD_CLK = OUTPUT(GND);


--TDO is TDO at PIN_F14
--operation mode is output

TDO = OUTPUT(GND);


--I2C_SCLK is I2C_SCLK at PIN_A6
--operation mode is output

I2C_SCLK = OUTPUT(GND);


--VGA_CLK is VGA_CLK at PIN_B8
--operation mode is output

VGA_CLK = OUTPUT(!CCD_MCLK);


--VGA_HS is VGA_HS at PIN_A7
--operation mode is output

VGA_HS = OUTPUT(B1_oVGA_H_SYNC);


--VGA_VS is VGA_VS at PIN_D8
--operation mode is output

VGA_VS = OUTPUT(B1_oVGA_V_SYNC);


--VGA_BLANK is VGA_BLANK at PIN_D6
--operation mode is output

VGA_BLANK = OUTPUT(B1_oVGA_BLANK);


--VGA_SYNC is VGA_SYNC at PIN_B7
--operation mode is output

VGA_SYNC = OUTPUT(GND);


--VGA_R[0] is VGA_R[0] at PIN_C8
--operation mode is output

VGA_R[0] = OUTPUT(B1L104);


--VGA_R[1] is VGA_R[1] at PIN_F10
--operation mode is output

VGA_R[1] = OUTPUT(B1L105);


--VGA_R[2] is VGA_R[2] at PIN_G10
--operation mode is output

VGA_R[2] = OUTPUT(B1L106);


--VGA_R[3] is VGA_R[3] at PIN_D9
--operation mode is output

VGA_R[3] = OUTPUT(B1L107);


--VGA_R[4] is VGA_R[4] at PIN_C9
--operation mode is output

VGA_R[4] = OUTPUT(B1L108);


--VGA_R[5] is VGA_R[5] at PIN_A8
--operation mode is output

VGA_R[5] = OUTPUT(B1L109);


--VGA_R[6] is VGA_R[6] at PIN_H11
--operation mode is output

VGA_R[6] = OUTPUT(B1L110);


--VGA_R[7] is VGA_R[7] at PIN_H12
--operation mode is output

VGA_R[7] = OUTPUT(B1L111);


--VGA_R[8] is VGA_R[8] at PIN_F11
--operation mode is output

VGA_R[8] = OUTPUT(B1L112);


--VGA_R[9] is VGA_R[9] at PIN_E10
--operation mode is output

VGA_R[9] = OUTPUT(B1L113);


--VGA_G[0] is VGA_G[0] at PIN_B9
--operation mode is output

VGA_G[0] = OUTPUT(B1L93);


--VGA_G[1] is VGA_G[1] at PIN_A9
--operation mode is output

VGA_G[1] = OUTPUT(B1L94);


--VGA_G[2] is VGA_G[2] at PIN_C10
--operation mode is output

VGA_G[2] = OUTPUT(B1L95);


--VGA_G[3] is VGA_G[3] at PIN_D10
--operation mode is output

VGA_G[3] = OUTPUT(B1L96);


--VGA_G[4] is VGA_G[4] at PIN_B10
--operation mode is output

VGA_G[4] = OUTPUT(B1L97);


--VGA_G[5] is VGA_G[5] at PIN_A10
--operation mode is output

VGA_G[5] = OUTPUT(B1L98);


--VGA_G[6] is VGA_G[6] at PIN_G11
--operation mode is output

VGA_G[6] = OUTPUT(B1L99);


--VGA_G[7] is VGA_G[7] at PIN_D11
--operation mode is output

VGA_G[7] = OUTPUT(B1L100);


--VGA_G[8] is VGA_G[8] at PIN_E12
--operation mode is output

VGA_G[8] = OUTPUT(B1L101);


--VGA_G[9] is VGA_G[9] at PIN_D12
--operation mode is output

VGA_G[9] = OUTPUT(B1L102);


--VGA_B[0] is VGA_B[0] at PIN_J13
--operation mode is output

VGA_B[0] = OUTPUT(B1L83);


--VGA_B[1] is VGA_B[1] at PIN_J14
--operation mode is output

VGA_B[1] = OUTPUT(B1L84);


--VGA_B[2] is VGA_B[2] at PIN_F12
--operation mode is output

VGA_B[2] = OUTPUT(B1L85);


--VGA_B[3] is VGA_B[3] at PIN_G12
--operation mode is output

VGA_B[3] = OUTPUT(B1L86);


--VGA_B[4] is VGA_B[4] at PIN_J10
--operation mode is output

VGA_B[4] = OUTPUT(B1L87);


--VGA_B[5] is VGA_B[5] at PIN_J11
--operation mode is output

VGA_B[5] = OUTPUT(B1L88);


--VGA_B[6] is VGA_B[6] at PIN_C11
--operation mode is output

VGA_B[6] = OUTPUT(B1L89);


--VGA_B[7] is VGA_B[7] at PIN_B11
--operation mode is output

VGA_B[7] = OUTPUT(B1L90);


--VGA_B[8] is VGA_B[8] at PIN_C12
--operation mode is output

VGA_B[8] = OUTPUT(B1L91);


--VGA_B[9] is VGA_B[9] at PIN_B12
--operation mode is output

VGA_B[9] = OUTPUT(B1L92);


--ENET_CMD is ENET_CMD at PIN_A21
--operation mode is output

ENET_CMD = OUTPUT(GND);


--ENET_CS_N is ENET_CS_N at PIN_A23
--operation mode is output

ENET_CS_N = OUTPUT(GND);


--ENET_WR_N is ENET_WR_N at PIN_B22
--operation mode is output

ENET_WR_N = OUTPUT(GND);


--ENET_RD_N is ENET_RD_N at PIN_A22
--operation mode is output

ENET_RD_N = OUTPUT(GND);


--ENET_RST_N is ENET_RST_N at PIN_B23
--operation mode is output

ENET_RST_N = OUTPUT(GND);


--ENET_CLK is ENET_CLK at PIN_B24
--operation mode is output

ENET_CLK = OUTPUT(GND);


--AUD_DACDAT is AUD_DACDAT at PIN_A4
--operation mode is output

AUD_DACDAT = OUTPUT(GND);


--AUD_XCK is AUD_XCK at PIN_A5
--operation mode is output

AUD_XCK = OUTPUT(GND);


--TD_RESET is TD_RESET at PIN_C4
--operation mode is output

TD_RESET = OUTPUT(VCC);


--SD_DAT3 is SD_DAT3 at PIN_AC23
--operation mode is bidir

SD_DAT3 = BIDIR(OPNDRN(VCC));


--SD_CMD is SD_CMD at PIN_Y21
--operation mode is bidir

SD_CMD = BIDIR(OPNDRN(VCC));


--GPIO_0[0] is GPIO_0[0] at PIN_D25
--operation mode is bidir

GPIO_0[0] = BIDIR(OPNDRN(VCC));


--GPIO_0[1] is GPIO_0[1] at PIN_J22
--operation mode is bidir

GPIO_0[1] = BIDIR(OPNDRN(VCC));


--GPIO_0[2] is GPIO_0[2] at PIN_E26
--operation mode is bidir

GPIO_0[2] = BIDIR(OPNDRN(VCC));


--GPIO_0[3] is GPIO_0[3] at PIN_E25
--operation mode is bidir

GPIO_0[3] = BIDIR(OPNDRN(VCC));


--GPIO_0[4] is GPIO_0[4] at PIN_F24
--operation mode is bidir

GPIO_0[4] = BIDIR(OPNDRN(VCC));


--GPIO_0[5] is GPIO_0[5] at PIN_F23
--operation mode is bidir

GPIO_0[5] = BIDIR(OPNDRN(VCC));


--GPIO_0[6] is GPIO_0[6] at PIN_J21
--operation mode is bidir

GPIO_0[6] = BIDIR(OPNDRN(VCC));


--GPIO_0[7] is GPIO_0[7] at PIN_J20
--operation mode is bidir

GPIO_0[7] = BIDIR(OPNDRN(VCC));


--GPIO_0[8] is GPIO_0[8] at PIN_F25
--operation mode is bidir

GPIO_0[8] = BIDIR(OPNDRN(VCC));


--GPIO_0[9] is GPIO_0[9] at PIN_F26
--operation mode is bidir

GPIO_0[9] = BIDIR(OPNDRN(VCC));


--GPIO_0[10] is GPIO_0[10] at PIN_N18
--operation mode is bidir

GPIO_0[10] = BIDIR(OPNDRN(VCC));


--GPIO_0[11] is GPIO_0[11] at PIN_P18
--operation mode is bidir

GPIO_0[11] = BIDIR(OPNDRN(VCC));


--GPIO_0[12] is GPIO_0[12] at PIN_G23
--operation mode is bidir

GPIO_0[12] = BIDIR(OPNDRN(VCC));


--GPIO_0[13] is GPIO_0[13] at PIN_G24
--operation mode is bidir

GPIO_0[13] = BIDIR(OPNDRN(VCC));


--GPIO_0[14] is GPIO_0[14] at PIN_K22
--operation mode is bidir

GPIO_0[14] = BIDIR(OPNDRN(VCC));


--GPIO_0[15] is GPIO_0[15] at PIN_G25
--operation mode is bidir

GPIO_0[15] = BIDIR(OPNDRN(VCC));


--GPIO_0[16] is GPIO_0[16] at PIN_H23
--operation mode is bidir

GPIO_0[16] = BIDIR(OPNDRN(VCC));


--GPIO_0[17] is GPIO_0[17] at PIN_H24
--operation mode is bidir

GPIO_0[17] = BIDIR(OPNDRN(VCC));


--GPIO_0[18] is GPIO_0[18] at PIN_J23
--operation mode is bidir

GPIO_0[18] = BIDIR(OPNDRN(VCC));


--GPIO_0[19] is GPIO_0[19] at PIN_J24
--operation mode is bidir

GPIO_0[19] = BIDIR(OPNDRN(VCC));


--GPIO_0[20] is GPIO_0[20] at PIN_H25
--operation mode is bidir

GPIO_0[20] = BIDIR(OPNDRN(VCC));


--GPIO_0[21] is GPIO_0[21] at PIN_H26
--operation mode is bidir

GPIO_0[21] = BIDIR(OPNDRN(VCC));


--GPIO_0[22] is GPIO_0[22] at PIN_H19
--operation mode is bidir

GPIO_0[22] = BIDIR(OPNDRN(VCC));


--GPIO_0[23] is GPIO_0[23] at PIN_K18
--operation mode is bidir

GPIO_0[23] = BIDIR(OPNDRN(VCC));


--GPIO_0[24] is GPIO_0[24] at PIN_K19
--operation mode is bidir

GPIO_0[24] = BIDIR(OPNDRN(VCC));


--GPIO_0[25] is GPIO_0[25] at PIN_K21
--operation mode is bidir

GPIO_0[25] = BIDIR(OPNDRN(VCC));


--GPIO_0[26] is GPIO_0[26] at PIN_K23
--operation mode is bidir

GPIO_0[26] = BIDIR(OPNDRN(VCC));


--GPIO_0[27] is GPIO_0[27] at PIN_K24
--operation mode is bidir

GPIO_0[27] = BIDIR(OPNDRN(VCC));


--GPIO_0[28] is GPIO_0[28] at PIN_L21
--operation mode is bidir

GPIO_0[28] = BIDIR(OPNDRN(VCC));


--GPIO_0[29] is GPIO_0[29] at PIN_L20
--operation mode is bidir

GPIO_0[29] = BIDIR(OPNDRN(VCC));


--GPIO_0[30] is GPIO_0[30] at PIN_J25
--operation mode is bidir

GPIO_0[30] = BIDIR(OPNDRN(VCC));


--GPIO_0[31] is GPIO_0[31] at PIN_J26
--operation mode is bidir

GPIO_0[31] = BIDIR(OPNDRN(VCC));


--GPIO_0[32] is GPIO_0[32] at PIN_L23
--operation mode is bidir

GPIO_0[32] = BIDIR(OPNDRN(VCC));


--GPIO_0[33] is GPIO_0[33] at PIN_L24
--operation mode is bidir

GPIO_0[33] = BIDIR(OPNDRN(VCC));


--GPIO_0[34] is GPIO_0[34] at PIN_L25
--operation mode is bidir

GPIO_0[34] = BIDIR(OPNDRN(VCC));


--GPIO_0[35] is GPIO_0[35] at PIN_L19
--operation mode is bidir

GPIO_0[35] = BIDIR(OPNDRN(VCC));


--GPIO_1[16] is GPIO_1[16] at PIN_T23
--operation mode is bidir

GPIO_1[16] = BIDIR(OPNDRN(VCC));


--GPIO_1[17] is GPIO_1[17] at PIN_T24
--operation mode is bidir

GPIO_1[17] = BIDIR(OPNDRN(VCC));


--GPIO_1[18] is GPIO_1[18] at PIN_T25
--operation mode is bidir

GPIO_1[18] = BIDIR(OPNDRN(VCC));


--GPIO_1[19] is GPIO_1[19] at PIN_T18
--operation mode is bidir

GPIO_1[19] = BIDIR(OPNDRN(VCC));


--GPIO_1[20] is GPIO_1[20] at PIN_T21
--operation mode is bidir

GPIO_1[20] = BIDIR(OPNDRN(VCC));


--GPIO_1[21] is GPIO_1[21] at PIN_T20
--operation mode is bidir

GPIO_1[21] = BIDIR(OPNDRN(VCC));


--GPIO_1[22] is GPIO_1[22] at PIN_U26
--operation mode is bidir

GPIO_1[22] = BIDIR(OPNDRN(VCC));


--GPIO_1[23] is GPIO_1[23] at PIN_U25
--operation mode is bidir

GPIO_1[23] = BIDIR(OPNDRN(VCC));


--GPIO_1[24] is GPIO_1[24] at PIN_U23
--operation mode is bidir

GPIO_1[24] = BIDIR(OPNDRN(VCC));


--GPIO_1[25] is GPIO_1[25] at PIN_U24
--operation mode is bidir

GPIO_1[25] = BIDIR(OPNDRN(VCC));


--GPIO_1[26] is GPIO_1[26] at PIN_R19
--operation mode is bidir

GPIO_1[26] = BIDIR(OPNDRN(VCC));


--GPIO_1[27] is GPIO_1[27] at PIN_T19
--operation mode is bidir

GPIO_1[27] = BIDIR(OPNDRN(VCC));


--GPIO_1[28] is GPIO_1[28] at PIN_U20
--operation mode is bidir

GPIO_1[28] = BIDIR(OPNDRN(VCC));


--GPIO_1[29] is GPIO_1[29] at PIN_U21
--operation mode is bidir

GPIO_1[29] = BIDIR(OPNDRN(VCC));


--GPIO_1[30] is GPIO_1[30] at PIN_V26
--operation mode is bidir

GPIO_1[30] = BIDIR(OPNDRN(VCC));


--GPIO_1[31] is GPIO_1[31] at PIN_V25
--operation mode is bidir

GPIO_1[31] = BIDIR(OPNDRN(VCC));


--GPIO_1[32] is GPIO_1[32] at PIN_V24
--operation mode is bidir

GPIO_1[32] = BIDIR(OPNDRN(VCC));


--GPIO_1[33] is GPIO_1[33] at PIN_V23
--operation mode is bidir

GPIO_1[33] = BIDIR(OPNDRN(VCC));


--GPIO_1[34] is GPIO_1[34] at PIN_W25
--operation mode is bidir

GPIO_1[34] = BIDIR(OPNDRN(VCC));


--GPIO_1[35] is GPIO_1[35] at PIN_W23
--operation mode is bidir

GPIO_1[35] = BIDIR(OPNDRN(VCC));


--A1L38 is DRAM_DQ[0]~15 at PIN_V6
--operation mode is bidir

A1L38 = DRAM_DQ[0];

--DRAM_DQ[0] is DRAM_DQ[0] at PIN_V6
--operation mode is bidir

DRAM_DQ[0]_tri_out = TRI(G1L223, R1_OE);
DRAM_DQ[0] = BIDIR(DRAM_DQ[0]_tri_out);


--A1L40 is DRAM_DQ[1]~14 at PIN_AA2
--operation mode is bidir

A1L40 = DRAM_DQ[1];

--DRAM_DQ[1] is DRAM_DQ[1] at PIN_AA2
--operation mode is bidir

DRAM_DQ[1]_tri_out = TRI(G1L224, R1_OE);
DRAM_DQ[1] = BIDIR(DRAM_DQ[1]_tri_out);


--A1L42 is DRAM_DQ[2]~13 at PIN_AA1
--operation mode is bidir

A1L42 = DRAM_DQ[2];

--DRAM_DQ[2] is DRAM_DQ[2] at PIN_AA1
--operation mode is bidir

DRAM_DQ[2]_tri_out = TRI(G1L225, R1_OE);
DRAM_DQ[2] = BIDIR(DRAM_DQ[2]_tri_out);


--A1L44 is DRAM_DQ[3]~12 at PIN_Y3
--operation mode is bidir

A1L44 = DRAM_DQ[3];

--DRAM_DQ[3] is DRAM_DQ[3] at PIN_Y3
--operation mode is bidir

DRAM_DQ[3]_tri_out = TRI(G1L226, R1_OE);
DRAM_DQ[3] = BIDIR(DRAM_DQ[3]_tri_out);


--A1L46 is DRAM_DQ[4]~11 at PIN_Y4
--operation mode is bidir

A1L46 = DRAM_DQ[4];

--DRAM_DQ[4] is DRAM_DQ[4] at PIN_Y4
--operation mode is bidir

DRAM_DQ[4]_tri_out = TRI(G1L227, R1_OE);
DRAM_DQ[4] = BIDIR(DRAM_DQ[4]_tri_out);


--A1L48 is DRAM_DQ[5]~10 at PIN_R8
--operation mode is bidir

A1L48 = DRAM_DQ[5];

--DRAM_DQ[5] is DRAM_DQ[5] at PIN_R8
--operation mode is bidir

DRAM_DQ[5]_tri_out = TRI(G1L228, R1_OE);
DRAM_DQ[5] = BIDIR(DRAM_DQ[5]_tri_out);


--A1L50 is DRAM_DQ[6]~9 at PIN_T8
--operation mode is bidir

A1L50 = DRAM_DQ[6];

--DRAM_DQ[6] is DRAM_DQ[6] at PIN_T8
--operation mode is bidir

DRAM_DQ[6]_tri_out = TRI(G1L229, R1_OE);
DRAM_DQ[6] = BIDIR(DRAM_DQ[6]_tri_out);


--A1L52 is DRAM_DQ[7]~8 at PIN_V7
--operation mode is bidir

A1L52 = DRAM_DQ[7];

--DRAM_DQ[7] is DRAM_DQ[7] at PIN_V7
--operation mode is bidir

DRAM_DQ[7]_tri_out = TRI(G1L230, R1_OE);
DRAM_DQ[7] = BIDIR(DRAM_DQ[7]_tri_out);


--A1L54 is DRAM_DQ[8]~7 at PIN_W6
--operation mode is bidir

A1L54 = DRAM_DQ[8];

--DRAM_DQ[8] is DRAM_DQ[8] at PIN_W6
--operation mode is bidir

DRAM_DQ[8]_tri_out = TRI(G1L231, R1_OE);
DRAM_DQ[8] = BIDIR(DRAM_DQ[8]_tri_out);


--A1L56 is DRAM_DQ[9]~6 at PIN_AB2
--operation mode is bidir

A1L56 = DRAM_DQ[9];

--DRAM_DQ[9] is DRAM_DQ[9] at PIN_AB2
--operation mode is bidir

DRAM_DQ[9]_tri_out = TRI(G1L232, R1_OE);
DRAM_DQ[9] = BIDIR(DRAM_DQ[9]_tri_out);


--A1L58 is DRAM_DQ[10]~5 at PIN_AB1
--operation mode is bidir

A1L58 = DRAM_DQ[10];

--DRAM_DQ[10] is DRAM_DQ[10] at PIN_AB1
--operation mode is bidir

DRAM_DQ[10]_tri_out = TRI(G1L233, R1_OE);
DRAM_DQ[10] = BIDIR(DRAM_DQ[10]_tri_out);


--A1L60 is DRAM_DQ[11]~4 at PIN_AA4
--operation mode is bidir

A1L60 = DRAM_DQ[11];

--DRAM_DQ[11] is DRAM_DQ[11] at PIN_AA4
--operation mode is bidir

DRAM_DQ[11]_tri_out = TRI(G1L234, R1_OE);
DRAM_DQ[11] = BIDIR(DRAM_DQ[11]_tri_out);


--A1L62 is DRAM_DQ[12]~3 at PIN_AA3
--operation mode is bidir

A1L62 = DRAM_DQ[12];

--DRAM_DQ[12] is DRAM_DQ[12] at PIN_AA3
--operation mode is bidir

DRAM_DQ[12]_tri_out = TRI(G1L235, R1_OE);
DRAM_DQ[12] = BIDIR(DRAM_DQ[12]_tri_out);


--A1L64 is DRAM_DQ[13]~2 at PIN_AC2
--operation mode is bidir

A1L64 = DRAM_DQ[13];

--DRAM_DQ[13] is DRAM_DQ[13] at PIN_AC2
--operation mode is bidir

DRAM_DQ[13]_tri_out = TRI(G1L236, R1_OE);
DRAM_DQ[13] = BIDIR(DRAM_DQ[13]_tri_out);


--A1L66 is DRAM_DQ[14]~1 at PIN_AC1
--operation mode is bidir

A1L66 = DRAM_DQ[14];

--DRAM_DQ[14] is DRAM_DQ[14] at PIN_AC1
--operation mode is bidir

DRAM_DQ[14]_tri_out = TRI(G1L237, R1_OE);
DRAM_DQ[14] = BIDIR(DRAM_DQ[14]_tri_out);


--DRAM_DQ[15] is DRAM_DQ[15] at PIN_AA5
--operation mode is bidir

DRAM_DQ[15]_tri_out = TRI(G1L238, R1_OE);
DRAM_DQ[15] = BIDIR(DRAM_DQ[15]_tri_out);


--FL_DQ[0] is FL_DQ[0] at PIN_AD19
--operation mode is bidir

FL_DQ[0] = BIDIR(OPNDRN(VCC));


--FL_DQ[1] is FL_DQ[1] at PIN_AC19
--operation mode is bidir

FL_DQ[1] = BIDIR(OPNDRN(VCC));


--FL_DQ[2] is FL_DQ[2] at PIN_AF20
--operation mode is bidir

FL_DQ[2] = BIDIR(OPNDRN(VCC));


--FL_DQ[3] is FL_DQ[3] at PIN_AE20
--operation mode is bidir

FL_DQ[3] = BIDIR(OPNDRN(VCC));


--FL_DQ[4] is FL_DQ[4] at PIN_AB20
--operation mode is bidir

FL_DQ[4] = BIDIR(OPNDRN(VCC));


--FL_DQ[5] is FL_DQ[5] at PIN_AC20
--operation mode is bidir

FL_DQ[5] = BIDIR(OPNDRN(VCC));


--FL_DQ[6] is FL_DQ[6] at PIN_AF21
--operation mode is bidir

FL_DQ[6] = BIDIR(OPNDRN(VCC));


--FL_DQ[7] is FL_DQ[7] at PIN_AE21
--operation mode is bidir

FL_DQ[7] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[0] is SRAM_DQ[0] at PIN_AD8
--operation mode is bidir

SRAM_DQ[0] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[1] is SRAM_DQ[1] at PIN_AE6
--operation mode is bidir

SRAM_DQ[1] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[2] is SRAM_DQ[2] at PIN_AF6
--operation mode is bidir

SRAM_DQ[2] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[3] is SRAM_DQ[3] at PIN_AA9
--operation mode is bidir

SRAM_DQ[3] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[4] is SRAM_DQ[4] at PIN_AA10
--operation mode is bidir

SRAM_DQ[4] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[5] is SRAM_DQ[5] at PIN_AB10
--operation mode is bidir

SRAM_DQ[5] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[6] is SRAM_DQ[6] at PIN_AA11
--operation mode is bidir

SRAM_DQ[6] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[7] is SRAM_DQ[7] at PIN_Y11
--operation mode is bidir

SRAM_DQ[7] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[8] is SRAM_DQ[8] at PIN_AE7
--operation mode is bidir

SRAM_DQ[8] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[9] is SRAM_DQ[9] at PIN_AF7
--operation mode is bidir

SRAM_DQ[9] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[10] is SRAM_DQ[10] at PIN_AE8
--operation mode is bidir

SRAM_DQ[10] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[11] is SRAM_DQ[11] at PIN_AF8
--operation mode is bidir

SRAM_DQ[11] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[12] is SRAM_DQ[12] at PIN_W11
--operation mode is bidir

SRAM_DQ[12] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[13] is SRAM_DQ[13] at PIN_W12
--operation mode is bidir

SRAM_DQ[13] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[14] is SRAM_DQ[14] at PIN_AC9
--operation mode is bidir

SRAM_DQ[14] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[15] is SRAM_DQ[15] at PIN_AC10
--operation mode is bidir

SRAM_DQ[15] = BIDIR(OPNDRN(VCC));


--OTG_DATA[0] is OTG_DATA[0] at PIN_F4
--operation mode is bidir

OTG_DATA[0] = BIDIR(OPNDRN(VCC));


--OTG_DATA[1] is OTG_DATA[1] at PIN_D2
--operation mode is bidir

OTG_DATA[1] = BIDIR(OPNDRN(VCC));


--OTG_DATA[2] is OTG_DATA[2] at PIN_D1
--operation mode is bidir

OTG_DATA[2] = BIDIR(OPNDRN(VCC));


--OTG_DATA[3] is OTG_DATA[3] at PIN_F7
--operation mode is bidir

OTG_DATA[3] = BIDIR(OPNDRN(VCC));


--OTG_DATA[4] is OTG_DATA[4] at PIN_J5
--operation mode is bidir

OTG_DATA[4] = BIDIR(OPNDRN(VCC));


--OTG_DATA[5] is OTG_DATA[5] at PIN_J8
--operation mode is bidir

OTG_DATA[5] = BIDIR(OPNDRN(VCC));


--OTG_DATA[6] is OTG_DATA[6] at PIN_J7
--operation mode is bidir

OTG_DATA[6] = BIDIR(OPNDRN(VCC));


--OTG_DATA[7] is OTG_DATA[7] at PIN_H6
--operation mode is bidir

OTG_DATA[7] = BIDIR(OPNDRN(VCC));


--OTG_DATA[8] is OTG_DATA[8] at PIN_E2
--operation mode is bidir

OTG_DATA[8] = BIDIR(OPNDRN(VCC));


--OTG_DATA[9] is OTG_DATA[9] at PIN_E1
--operation mode is bidir

OTG_DATA[9] = BIDIR(OPNDRN(VCC));


--OTG_DATA[10] is OTG_DATA[10] at PIN_K6
--operation mode is bidir

OTG_DATA[10] = BIDIR(OPNDRN(VCC));


--OTG_DATA[11] is OTG_DATA[11] at PIN_K5
--operation mode is bidir

OTG_DATA[11] = BIDIR(OPNDRN(VCC));


--OTG_DATA[12] is OTG_DATA[12] at PIN_G4
--operation mode is bidir

OTG_DATA[12] = BIDIR(OPNDRN(VCC));


--OTG_DATA[13] is OTG_DATA[13] at PIN_G3
--operation mode is bidir

OTG_DATA[13] = BIDIR(OPNDRN(VCC));


--OTG_DATA[14] is OTG_DATA[14] at PIN_J6
--operation mode is bidir

OTG_DATA[14] = BIDIR(OPNDRN(VCC));


--OTG_DATA[15] is OTG_DATA[15] at PIN_K8
--operation mode is bidir

OTG_DATA[15] = BIDIR(OPNDRN(VCC));


--LCD_DATA[0] is LCD_DATA[0] at PIN_J1
--operation mode is bidir

LCD_DATA[0] = BIDIR(OPNDRN(VCC));


--LCD_DATA[1] is LCD_DATA[1] at PIN_J2
--operation mode is bidir

LCD_DATA[1] = BIDIR(OPNDRN(VCC));


--LCD_DATA[2] is LCD_DATA[2] at PIN_H1
--operation mode is bidir

LCD_DATA[2] = BIDIR(OPNDRN(VCC));


--LCD_DATA[3] is LCD_DATA[3] at PIN_H2
--operation mode is bidir

LCD_DATA[3] = BIDIR(OPNDRN(VCC));


--LCD_DATA[4] is LCD_DATA[4] at PIN_J4
--operation mode is bidir

LCD_DATA[4] = BIDIR(OPNDRN(VCC));


--LCD_DATA[5] is LCD_DATA[5] at PIN_J3
--operation mode is bidir

LCD_DATA[5] = BIDIR(OPNDRN(VCC));


--LCD_DATA[6] is LCD_DATA[6] at PIN_H4
--operation mode is bidir

LCD_DATA[6] = BIDIR(OPNDRN(VCC));


--LCD_DATA[7] is LCD_DATA[7] at PIN_H3
--operation mode is bidir

LCD_DATA[7] = BIDIR(OPNDRN(VCC));


--SD_DAT is SD_DAT at PIN_AD24
--operation mode is bidir

SD_DAT = BIDIR(OPNDRN(VCC));


--I2C_SDAT is I2C_SDAT at PIN_B6
--operation mode is bidir

I2C_SDAT = BIDIR(OPNDRN(VCC));


--ENET_DATA[0] is ENET_DATA[0] at PIN_D17
--operation mode is bidir

ENET_DATA[0] = BIDIR(OPNDRN(VCC));


--ENET_DATA[1] is ENET_DATA[1] at PIN_C17
--operation mode is bidir

ENET_DATA[1] = BIDIR(OPNDRN(VCC));


--ENET_DATA[2] is ENET_DATA[2] at PIN_B18
--operation mode is bidir

ENET_DATA[2] = BIDIR(OPNDRN(VCC));


--ENET_DATA[3] is ENET_DATA[3] at PIN_A18
--operation mode is bidir

ENET_DATA[3] = BIDIR(OPNDRN(VCC));


--ENET_DATA[4] is ENET_DATA[4] at PIN_B17
--operation mode is bidir

ENET_DATA[4] = BIDIR(OPNDRN(VCC));


--ENET_DATA[5] is ENET_DATA[5] at PIN_A17
--operation mode is bidir

ENET_DATA[5] = BIDIR(OPNDRN(VCC));


--ENET_DATA[6] is ENET_DATA[6] at PIN_B16
--operation mode is bidir

ENET_DATA[6] = BIDIR(OPNDRN(VCC));


--ENET_DATA[7] is ENET_DATA[7] at PIN_B15
--operation mode is bidir

ENET_DATA[7] = BIDIR(OPNDRN(VCC));


--ENET_DATA[8] is ENET_DATA[8] at PIN_B20
--operation mode is bidir

ENET_DATA[8] = BIDIR(OPNDRN(VCC));


--ENET_DATA[9] is ENET_DATA[9] at PIN_A20
--operation mode is bidir

ENET_DATA[9] = BIDIR(OPNDRN(VCC));


--ENET_DATA[10] is ENET_DATA[10] at PIN_C19
--operation mode is bidir

ENET_DATA[10] = BIDIR(OPNDRN(VCC));


--ENET_DATA[11] is ENET_DATA[11] at PIN_D19
--operation mode is bidir

ENET_DATA[11] = BIDIR(OPNDRN(VCC));


--ENET_DATA[12] is ENET_DATA[12] at PIN_B19
--operation mode is bidir

ENET_DATA[12] = BIDIR(OPNDRN(VCC));


--ENET_DATA[13] is ENET_DATA[13] at PIN_A19
--operation mode is bidir

ENET_DATA[13] = BIDIR(OPNDRN(VCC));


--ENET_DATA[14] is ENET_DATA[14] at PIN_E18
--operation mode is bidir

ENET_DATA[14] = BIDIR(OPNDRN(VCC));


--ENET_DATA[15] is ENET_DATA[15] at PIN_D18
--operation mode is bidir

ENET_DATA[15] = BIDIR(OPNDRN(VCC));


--AUD_ADCLRCK is AUD_ADCLRCK at PIN_C5
--operation mode is bidir

AUD_ADCLRCK = BIDIR(OPNDRN(VCC));


--AUD_DACLRCK is AUD_DACLRCK at PIN_C6
--operation mode is bidir

AUD_DACLRCK = BIDIR(OPNDRN(VCC));


--AUD_BCLK is AUD_BCLK at PIN_B4
--operation mode is bidir

AUD_BCLK = BIDIR(OPNDRN(VCC));


--rCCD_DATA[0] is rCCD_DATA[0] at PIN_K25
--operation mode is bidir

rCCD_DATA[0] = DFFE(GPIO_1[0], GLOBAL(A1L11), , , );

--GPIO_1[0] is GPIO_1[0] at PIN_K25
--operation mode is bidir

GPIO_1[0] = BIDIR(OPNDRN(VCC));


--rCCD_DATA[1] is rCCD_DATA[1] at PIN_K26
--operation mode is bidir

rCCD_DATA[1] = DFFE(GPIO_1[1], GLOBAL(A1L11), , , );

--GPIO_1[1] is GPIO_1[1] at PIN_K26
--operation mode is bidir

GPIO_1[1] = BIDIR(OPNDRN(VCC));


--rCCD_DATA[4] is rCCD_DATA[4] at PIN_M22
--operation mode is bidir

rCCD_DATA[4] = DFFE(GPIO_1[2], GLOBAL(A1L11), , , );

--GPIO_1[2] is GPIO_1[2] at PIN_M22
--operation mode is bidir

GPIO_1[2] = BIDIR(OPNDRN(VCC));


--rCCD_DATA[3] is rCCD_DATA[3] at PIN_M23
--operation mode is bidir

rCCD_DATA[3] = DFFE(GPIO_1[3], GLOBAL(A1L11), , , );

--GPIO_1[3] is GPIO_1[3] at PIN_M23
--operation mode is bidir

GPIO_1[3] = BIDIR(OPNDRN(VCC));


--rCCD_DATA[5] is rCCD_DATA[5] at PIN_M19
--operation mode is bidir

rCCD_DATA[5] = DFFE(GPIO_1[4], GLOBAL(A1L11), , , );

--GPIO_1[4] is GPIO_1[4] at PIN_M19
--operation mode is bidir

GPIO_1[4] = BIDIR(OPNDRN(VCC));


--rCCD_DATA[2] is rCCD_DATA[2] at PIN_M20
--operation mode is bidir

rCCD_DATA[2] = DFFE(GPIO_1[5], GLOBAL(A1L11), , , );

--GPIO_1[5] is GPIO_1[5] at PIN_M20
--operation mode is bidir

GPIO_1[5] = BIDIR(OPNDRN(VCC));


--rCCD_DATA[6] is rCCD_DATA[6] at PIN_N20
--operation mode is bidir

rCCD_DATA[6] = DFFE(GPIO_1[6], GLOBAL(A1L11), , , );

--GPIO_1[6] is GPIO_1[6] at PIN_N20
--operation mode is bidir

GPIO_1[6] = BIDIR(OPNDRN(VCC));


--rCCD_DATA[7] is rCCD_DATA[7] at PIN_M21
--operation mode is bidir

rCCD_DATA[7] = DFFE(GPIO_1[7], GLOBAL(A1L11), , , );

--GPIO_1[7] is GPIO_1[7] at PIN_M21
--operation mode is bidir

GPIO_1[7] = BIDIR(OPNDRN(VCC));


--rCCD_DATA[8] is rCCD_DATA[8] at PIN_M24
--operation mode is bidir

rCCD_DATA[8] = DFFE(GPIO_1[8], GLOBAL(A1L11), , , );

--GPIO_1[8] is GPIO_1[8] at PIN_M24
--operation mode is bidir

GPIO_1[8] = BIDIR(OPNDRN(VCC));


--rCCD_DATA[9] is rCCD_DATA[9] at PIN_M25
--operation mode is bidir

rCCD_DATA[9] = DFFE(GPIO_1[9], GLOBAL(A1L11), , , );

--GPIO_1[9] is GPIO_1[9] at PIN_M25
--operation mode is bidir

GPIO_1[9] = BIDIR(OPNDRN(VCC));


--CCD_PIXCLK is CCD_PIXCLK at PIN_N24
--operation mode is bidir

CCD_PIXCLK = GPIO_1[10];

--GPIO_1[10] is GPIO_1[10] at PIN_N24
--operation mode is bidir

GPIO_1[10] = BIDIR(OPNDRN(VCC));


--GPIO_1[11] is GPIO_1[11] at PIN_P24
--operation mode is bidir

GPIO_1[11]_tri_out = TRI(CCD_MCLK, VCC);
GPIO_1[11] = BIDIR(GPIO_1[11]_tri_out);


--rCCD_LVAL is rCCD_LVAL at PIN_R25
--operation mode is bidir

rCCD_LVAL = DFFE(GPIO_1[12], GLOBAL(A1L11), , , );

--GPIO_1[12] is GPIO_1[12] at PIN_R25
--operation mode is bidir

GPIO_1[12] = BIDIR(OPNDRN(VCC));


--rCCD_FVAL is rCCD_FVAL at PIN_R24
--operation mode is bidir

rCCD_FVAL = DFFE(GPIO_1[13], GLOBAL(A1L11), , , );

--GPIO_1[13] is GPIO_1[13] at PIN_R24
--operation mode is bidir

GPIO_1[13] = BIDIR(OPNDRN(VCC));


--GPIO_1[14] is GPIO_1[14] at PIN_R20
--operation mode is bidir

GPIO_1[14]_tri_out = TRI(LB1L17, VCC);
GPIO_1[14] = BIDIR(GPIO_1[14]_tri_out);


--CCD_SDAT is CCD_SDAT at PIN_T22
--operation mode is bidir

CCD_SDAT = GPIO_1[15];

--GPIO_1[15] is GPIO_1[15] at PIN_T22
--operation mode is bidir

GPIO_1[15] = BIDIR(OPNDRN(!LB1L25Q));


--J1L6 is Mirror_Col:u8|Z_Cont[0]~183 at LCCOMB_X14_Y15_N16
J1L6 = !J1_Z_Cont[0];


--J1L10 is Mirror_Col:u8|Z_Cont[1]~184 at LCCOMB_X14_Y8_N2
J1L10 = !J1_Z_Cont[1];


--J1L14 is Mirror_Col:u8|Z_Cont[2]~185 at LCCOMB_X14_Y10_N16
J1L14 = !J1_Z_Cont[2];


--J1L18 is Mirror_Col:u8|Z_Cont[3]~186 at LCCOMB_X14_Y11_N8
J1L18 = !J1_Z_Cont[3];


--J1L22 is Mirror_Col:u8|Z_Cont[4]~187 at LCCOMB_X14_Y11_N4
J1L22 = !J1_Z_Cont[4];


--J1L26 is Mirror_Col:u8|Z_Cont[5]~188 at LCCOMB_X14_Y11_N2
J1L26 = !J1_Z_Cont[5];


--J1L30 is Mirror_Col:u8|Z_Cont[6]~189 at LCCOMB_X14_Y9_N28
J1L30 = !J1_Z_Cont[6];


--R1L20 is Sdram_Control_4Port:u6|command:command1|REF_ACK~56 at LCCOMB_X20_Y11_N0
R1L20 = !R1_REF_ACK;




--A1L290 is KEY[1]~clk_delay_ctrl at CLKDELAYCTRL_G4
A1L290 = CLK_DELAY_CTRL.CLKOUT(.CLK(KEY[1]));


--KB1L2 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl at CLKCTRL_G3
KB1L2 = cycloneii_clkctrl(.INCLK[0] = KB1__clk0) WITH (clock_type = "Global Clock");


--A1L9 is CCD_MCLK~clkctrl at CLKCTRL_G6
A1L9 = cycloneii_clkctrl(.INCLK[0] = CCD_MCLK) WITH (clock_type = "Global Clock");


--A1L11 is CCD_PIXCLK~clkctrl at CLKCTRL_G7
A1L11 = cycloneii_clkctrl(.INCLK[0] = CCD_PIXCLK) WITH (clock_type = "Global Clock");


--A1L15 is CLOCK_50~clkctrl at CLKCTRL_G2
A1L15 = cycloneii_clkctrl(.INCLK[0] = CLOCK_50) WITH (clock_type = "Global Clock");


--A1L34 is DRAM_CLK~clkctrl_e at CLKCTRL_X0_Y1_N1
A1L34 = cycloneii_clkctrl(.INCLK[0] = KB1__clk1) WITH (clock_type = "External Clock Output");


--H1L93 is I2C_CCD_Config:u7|mI2C_CTRL_CLK~clkctrl at CLKCTRL_G5
H1L93 = cycloneii_clkctrl(.INCLK[0] = H1_mI2C_CTRL_CLK) WITH (clock_type = "Global Clock");


--X4L19 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdaclr~clkctrl at CLKCTRL_G11
X4L19 = cycloneii_clkctrl(.INCLK[0] = X4_rdaclr) WITH (clock_type = "Global Clock");


--C1L81 is Reset_Delay:u2|oRST_1~clkctrl at CLKCTRL_G15
C1L81 = cycloneii_clkctrl(.INCLK[0] = C1_oRST_1) WITH (clock_type = "Global Clock");


--C1L84 is Reset_Delay:u2|oRST_2~clkctrl at CLKCTRL_G1
C1L84 = cycloneii_clkctrl(.INCLK[0] = C1_oRST_2) WITH (clock_type = "Global Clock");


--C1L78 is Reset_Delay:u2|oRST_0~clkctrl at CLKCTRL_G0
C1L78 = cycloneii_clkctrl(.INCLK[0] = C1_oRST_0) WITH (clock_type = "Global Clock");


--X2L22 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdaclr~clkctrl at CLKCTRL_G12
X2L22 = cycloneii_clkctrl(.INCLK[0] = X2_rdaclr) WITH (clock_type = "Global Clock");


--A1L291 is KEY[1]~clkctrl at CLKCTRL_G4
A1L291 = cycloneii_clkctrl(.INCLK[0] = A1L290) WITH (clock_type = "Global Clock");


--G1L241 is Sdram_Control_4Port:u6|mDATAOUT[0]~feeder at LCCOMB_X22_Y16_N10
G1L241 = A1L38;


--G1L244 is Sdram_Control_4Port:u6|mDATAOUT[2]~feeder at LCCOMB_X6_Y17_N4
G1L244 = A1L42;


--G1L247 is Sdram_Control_4Port:u6|mDATAOUT[4]~feeder at LCCOMB_X21_Y17_N2
G1L247 = A1L46;


--G1L249 is Sdram_Control_4Port:u6|mDATAOUT[5]~feeder at LCCOMB_X22_Y9_N22
G1L249 = A1L48;


--G1L251 is Sdram_Control_4Port:u6|mDATAOUT[6]~feeder at LCCOMB_X20_Y17_N10
G1L251 = A1L50;


--G1L253 is Sdram_Control_4Port:u6|mDATAOUT[7]~feeder at LCCOMB_X18_Y17_N2
G1L253 = A1L52;


--G1L255 is Sdram_Control_4Port:u6|mDATAOUT[8]~feeder at LCCOMB_X7_Y16_N24
G1L255 = A1L54;


--G1L257 is Sdram_Control_4Port:u6|mDATAOUT[9]~feeder at LCCOMB_X27_Y19_N22
G1L257 = A1L56;


--G1L259 is Sdram_Control_4Port:u6|mDATAOUT[10]~feeder at LCCOMB_X18_Y16_N0
G1L259 = A1L58;


--G1L263 is Sdram_Control_4Port:u6|mDATAOUT[13]~feeder at LCCOMB_X10_Y8_N20
G1L263 = A1L64;


--G1L265 is Sdram_Control_4Port:u6|mDATAOUT[14]~feeder at LCCOMB_X25_Y17_N10
G1L265 = A1L66;


--D1L170 is CCD_Capture:u3|mCCD_DATA[0]~feeder at LCCOMB_X47_Y22_N16
D1L170 = rCCD_DATA[0];


--D1L172 is CCD_Capture:u3|mCCD_DATA[1]~feeder at LCCOMB_X45_Y21_N16
D1L172 = rCCD_DATA[1];


--D1L178 is CCD_Capture:u3|mCCD_DATA[4]~feeder at LCCOMB_X57_Y19_N16
D1L178 = rCCD_DATA[4];


--D1L176 is CCD_Capture:u3|mCCD_DATA[3]~feeder at LCCOMB_X53_Y20_N28
D1L176 = rCCD_DATA[3];


--D1L180 is CCD_Capture:u3|mCCD_DATA[5]~feeder at LCCOMB_X59_Y15_N6
D1L180 = rCCD_DATA[5];


--D1L174 is CCD_Capture:u3|mCCD_DATA[2]~feeder at LCCOMB_X28_Y15_N16
D1L174 = rCCD_DATA[2];


--D1L182 is CCD_Capture:u3|mCCD_DATA[6]~feeder at LCCOMB_X57_Y20_N30
D1L182 = rCCD_DATA[6];


--D1L186 is CCD_Capture:u3|mCCD_DATA[9]~feeder at LCCOMB_X56_Y18_N16
D1L186 = rCCD_DATA[9];


--G1L14 is Sdram_Control_4Port:u6|CS_N[0]~feeder at LCCOMB_X19_Y10_N4
G1L14 = R1_CS_N[0];


--G1L3 is Sdram_Control_4Port:u6|BA[0]~feeder at LCCOMB_X20_Y12_N6
G1L3 = R1_BA[0];


--G1L5 is Sdram_Control_4Port:u6|BA[1]~feeder at LCCOMB_X19_Y12_N22
G1L5 = R1_BA[1];


--JB4L5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[2]~feeder at LCCOMB_X23_Y16_N4
JB4L5 = X4_rdptr_g[2];


--JB4L7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[3]~feeder at LCCOMB_X23_Y16_N24
JB4L7 = X4_rdptr_g[3];


--JB4L10 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5]~feeder at LCCOMB_X23_Y16_N10
JB4L10 = X4_rdptr_g[5];


--X4L62 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[7]~feeder at LCCOMB_X23_Y15_N10
X4L62 = EB4_power_modified_counter_values[7];


--X4L60 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6]~feeder at LCCOMB_X23_Y15_N2
X4L60 = EB4_power_modified_counter_values[6];


--X4L58 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5]~feeder at LCCOMB_X23_Y15_N22
X4L58 = EB4_power_modified_counter_values[5];


--X4L29 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0]~feeder at LCCOMB_X25_Y16_N2
X4L29 = Z4_power_modified_counter_values[0];


--X4L32 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2]~feeder at LCCOMB_X23_Y16_N22
X4L32 = Z4_power_modified_counter_values[2];


--X4L34 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[3]~feeder at LCCOMB_X23_Y16_N12
X4L34 = Z4_power_modified_counter_values[3];


--X4L38 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[6]~feeder at LCCOMB_X23_Y16_N14
X4L38 = Z4_power_modified_counter_values[6];


--X4L40 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[7]~feeder at LCCOMB_X25_Y16_N4
X4L40 = Z4_power_modified_counter_values[7];


--X4L42 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8]~feeder at LCCOMB_X25_Y16_N6
X4L42 = Z4_power_modified_counter_values[8];


--X4L7 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3]~feeder at LCCOMB_X23_Y15_N24
X4L7 = X4_wrptr_g[3];


--X4L10 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5]~feeder at LCCOMB_X23_Y17_N16
X4L10 = X4_wrptr_g[5];


--X4L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6]~feeder at LCCOMB_X23_Y15_N12
X4L12 = X4_wrptr_g[6];


--X4L14 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7]~feeder at LCCOMB_X24_Y16_N20
X4L14 = X4_wrptr_g[7];


--X3L50 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2]~feeder at LCCOMB_X28_Y18_N6
X3L50 = EB3_power_modified_counter_values[2];


--X3L58 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8]~feeder at LCCOMB_X28_Y18_N18
X3L58 = EB3_power_modified_counter_values[8];


--X3L54 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5]~feeder at LCCOMB_X28_Y18_N20
X3L54 = EB3_power_modified_counter_values[5];


--X3L25 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0]~feeder at LCCOMB_X27_Y20_N30
X3L25 = Z3_power_modified_counter_values[0];


--X3L27 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[1]~feeder at LCCOMB_X27_Y20_N4
X3L27 = Z3_power_modified_counter_values[1];


--X3L29 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2]~feeder at LCCOMB_X27_Y19_N24
X3L29 = Z3_power_modified_counter_values[2];


--X3L32 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4]~feeder at LCCOMB_X27_Y20_N6
X3L32 = Z3_power_modified_counter_values[4];


--X3L34 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[5]~feeder at LCCOMB_X27_Y19_N4
X3L34 = Z3_power_modified_counter_values[5];


--X3L4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0]~feeder at LCCOMB_X28_Y18_N0
X3L4 = X3_wrptr_g[0];


--X3L6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[1]~feeder at LCCOMB_X28_Y20_N26
X3L6 = X3_wrptr_g[1];


--X3L9 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3]~feeder at LCCOMB_X28_Y20_N4
X3L9 = X3_wrptr_g[3];


--X3L12 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5]~feeder at LCCOMB_X28_Y20_N2
X3L12 = X3_wrptr_g[5];


--X3L16 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[8]~feeder at LCCOMB_X27_Y21_N16
X3L16 = X3_wrptr_g[8];


--R1L14 is Sdram_Control_4Port:u6|command:command1|OE~feeder at LCCOMB_X19_Y10_N28
R1L14 = R1_oe4;


--HB4L6 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[2]~feeder at LCCOMB_X24_Y16_N6
HB4L6 = X4_delayed_wrptr_g[2];


--HB4L4 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1]~feeder at LCCOMB_X24_Y16_N30
HB4L4 = X4_delayed_wrptr_g[1];


--HB4L9 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4]~feeder at LCCOMB_X24_Y16_N24
HB4L9 = X4_delayed_wrptr_g[4];


--HB3L3 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0]~feeder at LCCOMB_X28_Y20_N30
HB3L3 = X3_delayed_wrptr_g[0];


--HB3L5 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1]~feeder at LCCOMB_X28_Y20_N18
HB3L5 = X3_delayed_wrptr_g[1];


--HB3L10 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[5]~feeder at LCCOMB_X28_Y20_N14
HB3L10 = X3_delayed_wrptr_g[5];


--S1L36 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[8]~feeder at LCCOMB_X20_Y12_N30
S1L36 = G1_mADDR[8];


--S1L38 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[9]~feeder at LCCOMB_X20_Y14_N8
S1L38 = G1_mADDR[9];


--S1L41 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[11]~feeder at LCCOMB_X20_Y14_N22
S1L41 = G1_mADDR[11];


--S1L43 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[12]~feeder at LCCOMB_X19_Y14_N28
S1L43 = G1_mADDR[12];


--S1L45 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[13]~feeder at LCCOMB_X20_Y14_N26
S1L45 = G1_mADDR[13];


--S1L47 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[14]~feeder at LCCOMB_X20_Y12_N18
S1L47 = G1_mADDR[14];


--S1L49 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[15]~feeder at LCCOMB_X19_Y14_N22
S1L49 = G1_mADDR[15];


--S1L51 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[16]~feeder at LCCOMB_X20_Y12_N14
S1L51 = G1_mADDR[16];


--S1L53 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[17]~feeder at LCCOMB_X19_Y14_N0
S1L53 = G1_mADDR[17];


--S1L55 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[18]~feeder at LCCOMB_X20_Y15_N6
S1L55 = G1_mADDR[18];


--S1L57 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[19]~feeder at LCCOMB_X20_Y15_N10
S1L57 = G1_mADDR[19];


--S1L63 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[22]~feeder at LCCOMB_X20_Y15_N16
S1L63 = G1_mADDR[22];


--S1L59 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[20]~feeder at LCCOMB_X20_Y12_N10
S1L59 = G1_mADDR[20];


--S1L61 is Sdram_Control_4Port:u6|control_interface:control1|SADDR[21]~feeder at LCCOMB_X19_Y12_N0
S1L61 = G1_mADDR[21];


--JB1L9 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5]~feeder at LCCOMB_X15_Y12_N26
JB1L9 = X1_rdptr_g[5];


--JB1L6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[3]~feeder at LCCOMB_X17_Y12_N16
JB1L6 = X1_rdptr_g[3];


--JB2L11 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[6]~feeder at LCCOMB_X25_Y13_N10
JB2L11 = X2_rdptr_g[6];


--JB2L9 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[5]~feeder at LCCOMB_X25_Y13_N28
JB2L9 = X2_rdptr_g[5];


--JB2L5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe8|dffe9a[2]~feeder at LCCOMB_X25_Y13_N18
JB2L5 = X2_rdptr_g[2];


--X1L58 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[7]~feeder at LCCOMB_X15_Y12_N0
X1L58 = EB1_power_modified_counter_values[7];


--X1L50 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2]~feeder at LCCOMB_X14_Y13_N24
X1L50 = EB1_power_modified_counter_values[2];


--X1L56 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6]~feeder at LCCOMB_X14_Y13_N8
X1L56 = EB1_power_modified_counter_values[6];


--X1L60 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8]~feeder at LCCOMB_X15_Y12_N20
X1L60 = EB1_power_modified_counter_values[8];


--X1L54 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[5]~feeder at LCCOMB_X15_Y12_N8
X1L54 = EB1_power_modified_counter_values[5];


--X1L26 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[0]~feeder at LCCOMB_X16_Y13_N6
X1L26 = Z1_power_modified_counter_values[0];


--X1L30 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[3]~feeder at LCCOMB_X16_Y12_N26
X1L30 = Z1_power_modified_counter_values[3];


--X1L32 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4]~feeder at LCCOMB_X16_Y12_N8
X1L32 = Z1_power_modified_counter_values[4];


--X1L35 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[6]~feeder at LCCOMB_X16_Y13_N20
X1L35 = Z1_power_modified_counter_values[6];


--X1L4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0]~feeder at LCCOMB_X14_Y13_N26
X1L4 = X1_wrptr_g[0];


--X1L6 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[1]~feeder at LCCOMB_X15_Y14_N0
X1L6 = X1_wrptr_g[1];


--X1L9 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3]~feeder at LCCOMB_X14_Y13_N2
X1L9 = X1_wrptr_g[3];


--X1L11 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[4]~feeder at LCCOMB_X25_Y13_N2
X1L11 = X1_wrptr_g[4];


--X1L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6]~feeder at LCCOMB_X14_Y14_N16
X1L14 = X1_wrptr_g[6];


--X1L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7]~feeder at LCCOMB_X15_Y12_N18
X1L16 = X1_wrptr_g[7];


--X2L54 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[2]~feeder at LCCOMB_X27_Y13_N2
X2L54 = EB2_power_modified_counter_values[2];


--X2L60 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[6]~feeder at LCCOMB_X27_Y13_N6
X2L60 = EB2_power_modified_counter_values[6];


--X2L63 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[8]~feeder at LCCOMB_X27_Y13_N8
X2L63 = EB2_power_modified_counter_values[8];


--X2L57 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|wrptr_g[4]~feeder at LCCOMB_X27_Y14_N16
X2L57 = EB2_power_modified_counter_values[4];


--X2L34 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[2]~feeder at LCCOMB_X24_Y13_N10
X2L34 = Z2_power_modified_counter_values[2];


--X2L38 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[5]~feeder at LCCOMB_X24_Y13_N12
X2L38 = Z2_power_modified_counter_values[5];


--X2L4 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[0]~feeder at LCCOMB_X24_Y12_N6
X2L4 = X2_wrptr_g[0];


--X2L7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[2]~feeder at LCCOMB_X23_Y14_N4
X2L7 = X2_wrptr_g[2];


--X2L9 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[3]~feeder at LCCOMB_X23_Y14_N22
X2L9 = X2_wrptr_g[3];


--X2L11 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[4]~feeder at LCCOMB_X23_Y14_N18
X2L11 = X2_wrptr_g[4];


--X2L13 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[5]~feeder at LCCOMB_X24_Y14_N26
X2L13 = X2_wrptr_g[5];


--X2L15 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[6]~feeder at LCCOMB_X24_Y14_N28
X2L15 = X2_wrptr_g[6];


--X2L17 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|delayed_wrptr_g[7]~feeder at LCCOMB_X24_Y14_N12
X2L17 = X2_wrptr_g[7];


--HB1L15 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[7]~feeder at LCCOMB_X16_Y13_N28
HB1L15 = X1_delayed_wrptr_g[7];


--HB1L13 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[6]~feeder at LCCOMB_X16_Y13_N30
HB1L13 = X1_delayed_wrptr_g[6];


--HB1L10 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4]~feeder at LCCOMB_X25_Y13_N4
HB1L10 = X1_delayed_wrptr_g[4];


--HB1L7 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[2]~feeder at LCCOMB_X16_Y13_N10
HB1L7 = X1_delayed_wrptr_g[2];


--HB1L5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1]~feeder at LCCOMB_X15_Y14_N16
HB1L5 = X1_delayed_wrptr_g[1];


--HB1L3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0]~feeder at LCCOMB_X16_Y13_N18
HB1L3 = X1_delayed_wrptr_g[0];


--HB2L16 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[7]~feeder at LCCOMB_X24_Y14_N10
HB2L16 = X2_delayed_wrptr_g[7];


--HB2L14 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[6]~feeder at LCCOMB_X24_Y14_N8
HB2L14 = X2_delayed_wrptr_g[6];


--HB2L12 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[5]~feeder at LCCOMB_X24_Y14_N20
HB2L12 = X2_delayed_wrptr_g[5];


--HB2L10 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[4]~feeder at LCCOMB_X23_Y14_N8
HB2L10 = X2_delayed_wrptr_g[4];


--HB2L8 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[3]~feeder at LCCOMB_X23_Y14_N20
HB2L8 = X2_delayed_wrptr_g[3];


--HB2L5 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[1]~feeder at LCCOMB_X25_Y12_N0
HB2L5 = X2_delayed_wrptr_g[1];


--HB2L3 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|alt_synch_pipe_mc8:rs_dgwp|dffpipe_hd9:dffpipe6|dffe7a[0]~feeder at LCCOMB_X24_Y12_N0
HB2L3 = X2_delayed_wrptr_g[0];


--J1L43 is Mirror_Col:u8|mCCD_DVAL~feeder at LCCOMB_X25_Y13_N16
J1L43 = E1_mDVAL;


--LB1L29 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[2]~feeder at LCCOMB_X43_Y16_N24
LB1L29 = H1_mI2C_DATA[2];


--LB1L40 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[9]~feeder at LCCOMB_X42_Y17_N24
LB1L40 = H1_mI2C_DATA[9];


--LB1L37 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[7]~feeder at LCCOMB_X42_Y17_N22
LB1L37 = H1_mI2C_DATA[7];


--LB1L42 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[10]~feeder at LCCOMB_X43_Y17_N26
LB1L42 = H1_mI2C_DATA[10];


--LB1L31 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[3]~feeder at LCCOMB_X43_Y16_N0
LB1L31 = H1_mI2C_DATA[3];


--LB1L35 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[6]~feeder at LCCOMB_X44_Y17_N4
LB1L35 = H1_mI2C_DATA[6];


--LB1L48 is I2C_CCD_Config:u7|I2C_Controller:u0|SD[15]~feeder at LCCOMB_X42_Y17_N28
LB1L48 = H1_mI2C_DATA[15];


--X4L17 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|p0addr~feeder at LCCOMB_X28_Y20_N10
X4L17 = VCC;


--X4L20 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdaclr~feeder at LCCOMB_X31_Y35_N0
X4L20 = VCC;


--X2L20 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|p0addr~feeder at LCCOMB_X24_Y13_N20
X2L20 = VCC;


--X2L23 is Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdaclr~feeder at LCCOMB_X33_Y1_N16
X2L23 = VCC;


