Analysis & Synthesis report for DE2_D5M
Tue Aug 19 10:23:06 2008
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |DE2_D5M|I2C_CCD_Config:u8|mSetup_ST
  9. Registers Removed During Synthesis
 10. Removed Registers Triggering Further Register Optimizations
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Source assignments for RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_ikn:auto_generated|altsyncram_cm81:altsyncram2
 15. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
 16. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated
 17. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p
 18. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp
 19. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram
 20. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3
 21. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr
 22. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp
 23. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp
 24. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp
 25. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7
 26. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp
 27. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp
 28. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp
 29. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9
 30. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
 31. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated
 32. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p
 33. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp
 34. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram
 35. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3
 36. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr
 37. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp
 38. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp
 39. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp
 40. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7
 41. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp
 42. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp
 43. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp
 44. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9
 45. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
 46. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated
 47. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p
 48. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp
 49. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram
 50. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3
 51. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr
 52. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp
 53. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp
 54. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp
 55. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7
 56. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp
 57. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp
 58. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp
 59. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9
 60. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
 61. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated
 62. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p
 63. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp
 64. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram
 65. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3
 66. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr
 67. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp
 68. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp
 69. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp
 70. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7
 71. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp
 72. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp
 73. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp
 74. Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9
 75. Parameter Settings for User Entity Instance: VGA_Controller:u1
 76. Parameter Settings for User Entity Instance: CCD_Capture:u3
 77. Parameter Settings for User Entity Instance: RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
 78. Parameter Settings for User Entity Instance: sdram_pll:u6|altpll:altpll_component
 79. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7
 80. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|control_interface:control1
 81. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|command:command1
 82. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|sdr_data_path:data_path1
 83. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
 84. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
 85. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
 86. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
 87. Parameter Settings for User Entity Instance: I2C_CCD_Config:u8
 88. altshift_taps Parameter Settings by Entity Instance
 89. dcfifo Parameter Settings by Entity Instance
 90. Analysis & Synthesis Messages



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+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Aug 19 10:23:05 2008         ;
; Quartus II Version                 ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
; Revision Name                      ; DE2_D5M                                       ;
; Top-level Entity Name              ; DE2_D5M                                       ;
; Family                             ; Cyclone II                                    ;
; Total logic elements               ; 1,197                                         ;
;     Total combinational functions  ; 1,197                                         ;
;     Dedicated logic registers      ; 971                                           ;
; Total registers                    ; 971                                           ;
; Total pins                         ; 425                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 62,416                                        ;
; Embedded Multiplier 9-bit elements ; 0                                             ;
; Total PLLs                         ; 1                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                          ; DE2_D5M            ; DE2_D5M            ;
; Family name                                                                    ; Cyclone II         ; Stratix II         ;
; Use smart compilation                                                          ; On                 ; Off                ;
; Use Generated Physical Constraints File                                        ; Off                ;                    ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone II/Cyclone III                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                    ;
+-------------------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------+
; File Name with User-Entered Path          ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                 ;
+-------------------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------+
; Sdram_Control_4Port/Sdram_Params.h        ; yes             ; User File                    ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/Sdram_Control_4Port/Sdram_Params.h        ;
; Sdram_Control_4Port/command.v             ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/Sdram_Control_4Port/command.v             ;
; Sdram_Control_4Port/control_interface.v   ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/Sdram_Control_4Port/control_interface.v   ;
; Sdram_Control_4Port/sdr_data_path.v       ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/Sdram_Control_4Port/sdr_data_path.v       ;
; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/Sdram_Control_4Port/Sdram_Control_4Port.v ;
; Sdram_Control_4Port/Sdram_FIFO.v          ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/Sdram_Control_4Port/Sdram_FIFO.v          ;
; V/VGA_Param.h                             ; yes             ; User File                    ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/VGA_Param.h                             ;
; V/CCD_Capture.v                           ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/CCD_Capture.v                           ;
; V/I2C_CCD_Config.v                        ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/I2C_CCD_Config.v                        ;
; V/I2C_Controller.v                        ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/I2C_Controller.v                        ;
; V/Line_Buffer.v                           ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/Line_Buffer.v                           ;
; V/RAW2RGB.v                               ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/RAW2RGB.v                               ;
; V/Reset_Delay.v                           ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/Reset_Delay.v                           ;
; V/sdram_pll.v                             ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/sdram_pll.v                             ;
; V/SEG7_LUT.v                              ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/SEG7_LUT.v                              ;
; V/SEG7_LUT_8.v                            ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/SEG7_LUT_8.v                            ;
; V/VGA_Controller.v                        ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/VGA_Controller.v                        ;
; DE2_D5M.v                                 ; yes             ; User Verilog HDL File        ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/DE2_D5M.v                                 ;
; altshift_taps.tdf                         ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf               ;
; altdpram.inc                              ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altdpram.inc                    ;
; lpm_counter.inc                           ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/lpm_counter.inc                 ;
; lpm_compare.inc                           ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/lpm_compare.inc                 ;
; lpm_constant.inc                          ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/lpm_constant.inc                ;
; db/shift_taps_ikn.tdf                     ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/shift_taps_ikn.tdf                     ;
; db/altsyncram_cm81.tdf                    ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/altsyncram_cm81.tdf                    ;
; db/cntr_3rf.tdf                           ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/cntr_3rf.tdf                           ;
; altpll.tdf                                ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altpll.tdf                      ;
; aglobal72.inc                             ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/aglobal72.inc                   ;
; stratix_pll.inc                           ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/stratix_pll.inc                 ;
; stratixii_pll.inc                         ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/stratixii_pll.inc               ;
; cycloneii_pll.inc                         ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/cycloneii_pll.inc               ;
; dcfifo.tdf                                ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/dcfifo.tdf                      ;
; lpm_add_sub.inc                           ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.inc                 ;
; a_graycounter.inc                         ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/a_graycounter.inc               ;
; a_fefifo.inc                              ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/a_fefifo.inc                    ;
; a_gray2bin.inc                            ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/a_gray2bin.inc                  ;
; dffpipe.inc                               ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/dffpipe.inc                     ;
; alt_sync_fifo.inc                         ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/alt_sync_fifo.inc               ;
; altsyncram_fifo.inc                       ; yes             ; Megafunction                 ; c:/altera/72/quartus/libraries/megafunctions/altsyncram_fifo.inc             ;
; db/dcfifo_enm1.tdf                        ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/dcfifo_enm1.tdf                        ;
; db/a_gray2bin_kdb.tdf                     ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/a_gray2bin_kdb.tdf                     ;
; db/a_graycounter_o96.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/a_graycounter_o96.tdf                  ;
; db/a_graycounter_fgc.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/a_graycounter_fgc.tdf                  ;
; db/a_graycounter_egc.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/a_graycounter_egc.tdf                  ;
; db/altsyncram_3731.tdf                    ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/altsyncram_3731.tdf                    ;
; db/altsyncram_drg1.tdf                    ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/altsyncram_drg1.tdf                    ;
; db/dffpipe_mcc.tdf                        ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/dffpipe_mcc.tdf                        ;
; db/dffpipe_oe9.tdf                        ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/dffpipe_oe9.tdf                        ;
; db/alt_synch_pipe_ud8.tdf                 ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/alt_synch_pipe_ud8.tdf                 ;
; db/dffpipe_pe9.tdf                        ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/dffpipe_pe9.tdf                        ;
; db/alt_synch_pipe_vd8.tdf                 ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/alt_synch_pipe_vd8.tdf                 ;
; db/dffpipe_qe9.tdf                        ; yes             ; Auto-Generated Megafunction  ; D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/db/dffpipe_qe9.tdf                        ;
+-------------------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                              ;
+---------------------------------------------+--------------------------------------------+
; Resource                                    ; Usage                                      ;
+---------------------------------------------+--------------------------------------------+
; Estimated Total logic elements              ; 1,197                                      ;
;                                             ;                                            ;
; Total combinational functions               ; 1197                                       ;
; Logic element usage by number of LUT inputs ;                                            ;
;     -- 4 input functions                    ; 500                                        ;
;     -- 3 input functions                    ; 309                                        ;
;     -- <=2 input functions                  ; 388                                        ;
;                                             ;                                            ;
; Logic elements by mode                      ;                                            ;
;     -- normal mode                          ; 796                                        ;
;     -- arithmetic mode                      ; 401                                        ;
;                                             ;                                            ;
; Total registers                             ; 971                                        ;
;     -- Dedicated logic registers            ; 971                                        ;
;     -- I/O registers                        ; 0                                          ;
;                                             ;                                            ;
; I/O pins                                    ; 425                                        ;
; Total memory bits                           ; 62416                                      ;
; Total PLLs                                  ; 1                                          ;
; Maximum fan-out node                        ; sdram_pll:u6|altpll:altpll_component|_clk0 ;
; Maximum fan-out                             ; 517                                        ;
; Total fan-out                               ; 8921                                       ;
; Average fan-out                             ; 3.33                                       ;
+---------------------------------------------+--------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                          ;
+--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                       ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                            ; Library Name ;
+--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |DE2_D5M                                         ; 1197 (3)          ; 971 (30)     ; 62416       ; 0            ; 0       ; 0         ; 425  ; 0            ; |DE2_D5M                                                                                                                                                       ; work         ;
;    |CCD_Capture:u3|                              ; 82 (82)           ; 75 (75)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|CCD_Capture:u3                                                                                                                                        ; work         ;
;    |I2C_CCD_Config:u8|                           ; 230 (171)         ; 134 (96)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|I2C_CCD_Config:u8                                                                                                                                     ; work         ;
;       |I2C_Controller:u0|                        ; 59 (59)           ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                                   ; work         ;
;    |RAW2RGB:u4|                                  ; 97 (81)           ; 68 (57)      ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|RAW2RGB:u4                                                                                                                                            ; work         ;
;       |Line_Buffer:u0|                           ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|RAW2RGB:u4|Line_Buffer:u0                                                                                                                             ; work         ;
;          |altshift_taps:altshift_taps_component| ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                       ; work         ;
;             |shift_taps_ikn:auto_generated|      ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_ikn:auto_generated                                                         ; work         ;
;                |altsyncram_cm81:altsyncram2|     ; 0 (0)             ; 0 (0)        ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_ikn:auto_generated|altsyncram_cm81:altsyncram2                             ; work         ;
;                |cntr_3rf:cntr1|                  ; 16 (16)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_ikn:auto_generated|cntr_3rf:cntr1                                          ; work         ;
;    |Reset_Delay:u2|                              ; 49 (49)           ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Reset_Delay:u2                                                                                                                                        ; work         ;
;    |SEG7_LUT_8:u5|                               ; 56 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|SEG7_LUT_8:u5                                                                                                                                         ; work         ;
;       |SEG7_LUT:u0|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|SEG7_LUT_8:u5|SEG7_LUT:u0                                                                                                                             ; work         ;
;       |SEG7_LUT:u1|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|SEG7_LUT_8:u5|SEG7_LUT:u1                                                                                                                             ; work         ;
;       |SEG7_LUT:u2|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|SEG7_LUT_8:u5|SEG7_LUT:u2                                                                                                                             ; work         ;
;       |SEG7_LUT:u3|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|SEG7_LUT_8:u5|SEG7_LUT:u3                                                                                                                             ; work         ;
;       |SEG7_LUT:u4|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|SEG7_LUT_8:u5|SEG7_LUT:u4                                                                                                                             ; work         ;
;       |SEG7_LUT:u5|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|SEG7_LUT_8:u5|SEG7_LUT:u5                                                                                                                             ; work         ;
;       |SEG7_LUT:u6|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|SEG7_LUT_8:u5|SEG7_LUT:u6                                                                                                                             ; work         ;
;       |SEG7_LUT:u7|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|SEG7_LUT_8:u5|SEG7_LUT:u7                                                                                                                             ; work         ;
;    |Sdram_Control_4Port:u7|                      ; 598 (208)         ; 567 (136)    ; 31744       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7                                                                                                                                ; work         ;
;       |Sdram_FIFO:read_fifo1|                    ; 65 (0)            ; 82 (0)       ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                          ; work         ;
;          |dcfifo:dcfifo_component|               ; 65 (0)            ; 82 (0)       ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                                  ; work         ;
;             |dcfifo_enm1:auto_generated|         ; 65 (26)           ; 82 (21)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated                                                       ; work         ;
;                |a_gray2bin_kdb:wrptr_g_gray2bin| ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin                       ; work         ;
;                |a_gray2bin_kdb:ws_dgrp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin                       ; work         ;
;                |a_graycounter_egc:wrptr_gp|      ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp                            ; work         ;
;                |a_graycounter_o96:rdptr_g1p|     ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_o96:rdptr_g1p                           ; work         ;
;                |alt_synch_pipe_ud8:rs_dgwp|      ; 0 (0)             ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp                            ; work         ;
;                   |dffpipe_pe9:dffpipe7|         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7       ; work         ;
;                |alt_synch_pipe_vd8:ws_dgrp|      ; 0 (0)             ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp                            ; work         ;
;                   |dffpipe_qe9:dffpipe9|         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9       ; work         ;
;                |altsyncram_3731:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram                              ; work         ;
;                   |altsyncram_drg1:altsyncram3|  ; 0 (0)             ; 0 (0)        ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3  ; work         ;
;                |dffpipe_mcc:rdaclr|              ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr                                    ; work         ;
;                |dffpipe_oe9:ws_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp                                    ; work         ;
;                |dffpipe_oe9:ws_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp                                    ; work         ;
;       |Sdram_FIFO:read_fifo2|                    ; 67 (0)            ; 82 (0)       ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                          ; work         ;
;          |dcfifo:dcfifo_component|               ; 67 (0)            ; 82 (0)       ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                                  ; work         ;
;             |dcfifo_enm1:auto_generated|         ; 67 (28)           ; 82 (21)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated                                                       ; work         ;
;                |a_gray2bin_kdb:wrptr_g_gray2bin| ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin                       ; work         ;
;                |a_gray2bin_kdb:ws_dgrp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin                       ; work         ;
;                |a_graycounter_egc:wrptr_gp|      ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp                            ; work         ;
;                |a_graycounter_o96:rdptr_g1p|     ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_o96:rdptr_g1p                           ; work         ;
;                |alt_synch_pipe_ud8:rs_dgwp|      ; 0 (0)             ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp                            ; work         ;
;                   |dffpipe_pe9:dffpipe7|         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7       ; work         ;
;                |alt_synch_pipe_vd8:ws_dgrp|      ; 0 (0)             ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp                            ; work         ;
;                   |dffpipe_qe9:dffpipe9|         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9       ; work         ;
;                |altsyncram_3731:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram                              ; work         ;
;                   |altsyncram_drg1:altsyncram3|  ; 0 (0)             ; 0 (0)        ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3  ; work         ;
;                |dffpipe_mcc:rdaclr|              ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr                                    ; work         ;
;                |dffpipe_oe9:ws_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp                                    ; work         ;
;                |dffpipe_oe9:ws_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp                                    ; work         ;
;       |Sdram_FIFO:write_fifo1|                   ; 67 (0)            ; 82 (0)       ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                         ; work         ;
;          |dcfifo:dcfifo_component|               ; 67 (0)            ; 82 (0)       ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                                 ; work         ;
;             |dcfifo_enm1:auto_generated|         ; 67 (27)           ; 82 (21)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated                                                      ; work         ;
;                |a_gray2bin_kdb:rdptr_g_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin                      ; work         ;
;                |a_gray2bin_kdb:rs_dgwp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_gray2bin_kdb:rs_dgwp_gray2bin                      ; work         ;
;                |a_graycounter_egc:wrptr_gp|      ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp                           ; work         ;
;                |a_graycounter_o96:rdptr_g1p|     ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_o96:rdptr_g1p                          ; work         ;
;                |alt_synch_pipe_ud8:rs_dgwp|      ; 0 (0)             ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp                           ; work         ;
;                   |dffpipe_pe9:dffpipe7|         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7      ; work         ;
;                |alt_synch_pipe_vd8:ws_dgrp|      ; 0 (0)             ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp                           ; work         ;
;                   |dffpipe_qe9:dffpipe9|         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9      ; work         ;
;                |altsyncram_3731:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram                             ; work         ;
;                   |altsyncram_drg1:altsyncram3|  ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3 ; work         ;
;                |dffpipe_mcc:rdaclr|              ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr                                   ; work         ;
;                |dffpipe_oe9:rs_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp                                   ; work         ;
;                |dffpipe_oe9:rs_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp                                   ; work         ;
;       |Sdram_FIFO:write_fifo2|                   ; 67 (0)            ; 82 (0)       ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                         ; work         ;
;          |dcfifo:dcfifo_component|               ; 67 (0)            ; 82 (0)       ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                                 ; work         ;
;             |dcfifo_enm1:auto_generated|         ; 67 (27)           ; 82 (21)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated                                                      ; work         ;
;                |a_gray2bin_kdb:rdptr_g_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin                      ; work         ;
;                |a_gray2bin_kdb:rs_dgwp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_gray2bin_kdb:rs_dgwp_gray2bin                      ; work         ;
;                |a_graycounter_egc:wrptr_gp|      ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp                           ; work         ;
;                |a_graycounter_o96:rdptr_g1p|     ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_o96:rdptr_g1p                          ; work         ;
;                |alt_synch_pipe_ud8:rs_dgwp|      ; 0 (0)             ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp                           ; work         ;
;                   |dffpipe_pe9:dffpipe7|         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7      ; work         ;
;                |alt_synch_pipe_vd8:ws_dgrp|      ; 0 (0)             ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp                           ; work         ;
;                   |dffpipe_qe9:dffpipe9|         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9      ; work         ;
;                |altsyncram_3731:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram                             ; work         ;
;                   |altsyncram_drg1:altsyncram3|  ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3 ; work         ;
;                |dffpipe_mcc:rdaclr|              ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr                                   ; work         ;
;                |dffpipe_oe9:rs_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp                                   ; work         ;
;                |dffpipe_oe9:rs_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp                                   ; work         ;
;       |command:command1|                         ; 61 (61)           ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|command:command1                                                                                                               ; work         ;
;       |control_interface:control1|               ; 63 (63)           ; 55 (55)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|Sdram_Control_4Port:u7|control_interface:control1                                                                                                     ; work         ;
;    |VGA_Controller:u1|                           ; 82 (82)           ; 62 (62)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|VGA_Controller:u1                                                                                                                                     ; work         ;
;    |sdram_pll:u6|                                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|sdram_pll:u6                                                                                                                                          ; work         ;
;       |altpll:altpll_component|                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_D5M|sdram_pll:u6|altpll:altpll_component                                                                                                                  ; work         ;
+--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                      ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; Name                                                                                                                                                             ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_ikn:auto_generated|altsyncram_cm81:altsyncram2|ALTSYNCRAM                             ; AUTO ; Simple Dual Port ; 1278         ; 24           ; 1278         ; 24           ; 30672 ; None ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3|ALTSYNCRAM  ; M4K  ; True Dual Port   ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3|ALTSYNCRAM  ; M4K  ; True Dual Port   ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3|ALTSYNCRAM ; M4K  ; True Dual Port   ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3|ALTSYNCRAM ; M4K  ; True Dual Port   ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------+
; State Machine - |DE2_D5M|I2C_CCD_Config:u8|mSetup_ST              ;
+----------------+----------------+----------------+----------------+
; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001 ;
+----------------+----------------+----------------+----------------+
; mSetup_ST.0000 ; 0              ; 0              ; 0              ;
; mSetup_ST.0001 ; 1              ; 0              ; 1              ;
; mSetup_ST.0010 ; 1              ; 1              ; 0              ;
+----------------+----------------+----------------+----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                 ;
+-------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
; Register name                                                                                                                             ; Reason for Removal                                                     ;
+-------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
; Sdram_Control_4Port:u7|mDATAOUT[15]                                                                                                       ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|rWR1_LENGTH[8]                                                                                                     ; Stuck at VCC due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|rWR1_LENGTH[0..7]                                                                                                  ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|rWR2_LENGTH[8]                                                                                                     ; Stuck at VCC due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|rWR2_LENGTH[0..7]                                                                                                  ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|rRD1_LENGTH[8]                                                                                                     ; Stuck at VCC due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|rRD1_LENGTH[0..7]                                                                                                  ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|rRD2_LENGTH[8]                                                                                                     ; Stuck at VCC due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|rRD2_LENGTH[0..7]                                                                                                  ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|command:command1|CKE                                                                                               ; Stuck at VCC due to stuck port data_in                                 ;
; VGA_Controller:u1|oVGA_SYNC                                                                                                               ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|CKE                                                                                                                ; Stuck at VCC due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa0  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa1  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa2  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa3  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa4  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa5  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa6  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa7  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa8  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa9  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|parity_ff     ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa0  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa1  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa2  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa3  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa4  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa5  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa6  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa7  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa8  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa9  ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|parity_ff     ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa0 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa1 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa2 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa3 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa4 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa5 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa6 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa7 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa8 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa9 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|parity_ff    ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa0 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa1 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa2 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa3 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa4 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa5 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa6 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa7 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa8 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa9 ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|parity_ff    ; Lost fanout                                                            ;
; I2C_CCD_Config:u8|mI2C_DATA[31]                                                                                                           ; Stuck at VCC due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|mI2C_DATA[30]                                                                                                           ; Stuck at GND due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|mI2C_DATA[27..29]                                                                                                       ; Stuck at VCC due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|mI2C_DATA[26]                                                                                                           ; Stuck at GND due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|mI2C_DATA[25]                                                                                                           ; Stuck at VCC due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|mI2C_DATA[24]                                                                                                           ; Stuck at GND due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                                                                                                ; Stuck at VCC due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                                                                                                ; Stuck at GND due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD[27..29]                                                                                            ; Stuck at VCC due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                                                                                                ; Stuck at GND due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                                                                                                ; Stuck at VCC due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                                                                                                ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp|dffe6a[9]              ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp|dffe6a[9]              ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp|dffe6a[9]              ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp|dffe6a[9]              ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp|dffe6a[9]             ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp|dffe6a[9]             ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp|dffe6a[9]             ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp|dffe6a[9]             ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|rWR1_ADDR[0..6]                                                                                                    ; Merged with Sdram_Control_4Port:u7|rWR1_ADDR[7]                        ;
; Sdram_Control_4Port:u7|rWR2_ADDR[0..6]                                                                                                    ; Merged with Sdram_Control_4Port:u7|rWR2_ADDR[7]                        ;
; Sdram_Control_4Port:u7|rRD1_ADDR[0..6]                                                                                                    ; Merged with Sdram_Control_4Port:u7|rRD1_ADDR[7]                        ;
; Sdram_Control_4Port:u7|rRD2_ADDR[0..6]                                                                                                    ; Merged with Sdram_Control_4Port:u7|rRD2_ADDR[7]                        ;
; Sdram_Control_4Port:u7|mLENGTH[0..6]                                                                                                      ; Merged with Sdram_Control_4Port:u7|mLENGTH[7]                          ;
; Sdram_Control_4Port:u7|DQM[1]                                                                                                             ; Merged with Sdram_Control_4Port:u7|DQM[0]                              ;
; Sdram_Control_4Port:u7|mADDR[0..6]                                                                                                        ; Merged with Sdram_Control_4Port:u7|mADDR[7]                            ;
; Sdram_Control_4Port:u7|control_interface:control1|SADDR[0..6]                                                                             ; Merged with Sdram_Control_4Port:u7|control_interface:control1|SADDR[7] ;
; Sdram_Control_4Port:u7|rWR1_ADDR[7]                                                                                                       ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|rWR2_ADDR[7]                                                                                                       ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|rRD1_ADDR[7]                                                                                                       ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|rRD2_ADDR[7]                                                                                                       ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|mLENGTH[7]                                                                                                         ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|mADDR[7]                                                                                                           ; Stuck at GND due to stuck port data_in                                 ;
; Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]                                                                                ; Stuck at GND due to stuck port data_in                                 ;
; rClk[1]                                                                                                                                   ; Lost fanout                                                            ;
; Sdram_Control_4Port:u7|mLENGTH[8]                                                                                                         ; Stuck at VCC due to stuck port data_in                                 ;
; I2C_CCD_Config:u8|mSetup_ST~93                                                                                                            ; Lost fanout                                                            ;
; I2C_CCD_Config:u8|mSetup_ST~94                                                                                                            ; Lost fanout                                                            ;
; CCD_Capture:u3|Y_Cont[11..15]                                                                                                             ; Lost fanout                                                            ;
; Total Number of Removed Registers = 174                                                                                                   ;                                                                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                          ;
+---------------------------------------------+---------------------------+------------------------------------------------------------+
; Register name                               ; Reason for Removal        ; Registers Removed due to This Register                     ;
+---------------------------------------------+---------------------------+------------------------------------------------------------+
; Sdram_Control_4Port:u7|rWR1_ADDR[7]         ; Stuck at GND              ; Sdram_Control_4Port:u7|mADDR[7],                           ;
;                                             ; due to stuck port data_in ; Sdram_Control_4Port:u7|control_interface:control1|SADDR[7] ;
; Sdram_Control_4Port:u7|rWR1_LENGTH[8]       ; Stuck at VCC              ; Sdram_Control_4Port:u7|mLENGTH[8]                          ;
;                                             ; due to stuck port data_in ;                                                            ;
; Sdram_Control_4Port:u7|rWR1_LENGTH[7]       ; Stuck at GND              ; Sdram_Control_4Port:u7|mLENGTH[7]                          ;
;                                             ; due to stuck port data_in ;                                                            ;
; Sdram_Control_4Port:u7|command:command1|CKE ; Stuck at VCC              ; Sdram_Control_4Port:u7|CKE                                 ;
;                                             ; due to stuck port data_in ;                                                            ;
; I2C_CCD_Config:u8|mI2C_DATA[31]             ; Stuck at VCC              ; I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                 ;
;                                             ; due to stuck port data_in ;                                                            ;
; I2C_CCD_Config:u8|mI2C_DATA[30]             ; Stuck at GND              ; I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                 ;
;                                             ; due to stuck port data_in ;                                                            ;
; I2C_CCD_Config:u8|mI2C_DATA[29]             ; Stuck at VCC              ; I2C_CCD_Config:u8|I2C_Controller:u0|SD[29]                 ;
;                                             ; due to stuck port data_in ;                                                            ;
; I2C_CCD_Config:u8|mI2C_DATA[28]             ; Stuck at VCC              ; I2C_CCD_Config:u8|I2C_Controller:u0|SD[28]                 ;
;                                             ; due to stuck port data_in ;                                                            ;
; I2C_CCD_Config:u8|mI2C_DATA[27]             ; Stuck at VCC              ; I2C_CCD_Config:u8|I2C_Controller:u0|SD[27]                 ;
;                                             ; due to stuck port data_in ;                                                            ;
; I2C_CCD_Config:u8|mI2C_DATA[26]             ; Stuck at GND              ; I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                 ;
;                                             ; due to stuck port data_in ;                                                            ;
; I2C_CCD_Config:u8|mI2C_DATA[25]             ; Stuck at VCC              ; I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                 ;
;                                             ; due to stuck port data_in ;                                                            ;
; I2C_CCD_Config:u8|mI2C_DATA[24]             ; Stuck at GND              ; I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                 ;
;                                             ; due to stuck port data_in ;                                                            ;
+---------------------------------------------+---------------------------+------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 971   ;
; Number of registers using Synchronous Clear  ; 132   ;
; Number of registers using Synchronous Load   ; 82    ;
; Number of registers using Asynchronous Clear ; 643   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 327   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------+
; Inverted Register Statistics                                ;
+---------------------------------------------------+---------+
; Inverted Register                                 ; Fan out ;
+---------------------------------------------------+---------+
; I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5] ; 12      ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3] ; 21      ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4] ; 13      ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2] ; 19      ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0] ; 18      ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1] ; 19      ;
; I2C_CCD_Config:u8|senosr_exposure[10]             ; 4       ;
; I2C_CCD_Config:u8|senosr_exposure[3]              ; 4       ;
; I2C_CCD_Config:u8|senosr_exposure[4]              ; 4       ;
; I2C_CCD_Config:u8|senosr_exposure[5]              ; 3       ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SDO           ; 6       ;
; I2C_CCD_Config:u8|I2C_Controller:u0|SCLK          ; 3       ;
; I2C_CCD_Config:u8|I2C_Controller:u0|END           ; 5       ;
; Total number of inverted registers = 13           ;         ;
+---------------------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------+
; 4:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |DE2_D5M|RAW2RGB:u4|mCCD_B[7]                                        ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |DE2_D5M|CCD_Capture:u3|Y_Cont[0]                                    ;
; 3:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|command:command1|SA[8]               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|control_interface:control1|timer[13] ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|command:command1|command_done        ;
; 4:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |DE2_D5M|I2C_CCD_Config:u8|senosr_exposure[6]                        ;
; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |DE2_D5M|CCD_Capture:u3|X_Cont[15]                                   ;
; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|rRD2_ADDR[22]                        ;
; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|rRD1_ADDR[8]                         ;
; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|rWR2_ADDR[14]                        ;
; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|rWR1_ADDR[10]                        ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|command:command1|rp_shift[1]         ;
; 5:1                ; 15 bits   ; 45 LEs        ; 30 LEs               ; 15 LEs                 ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|mADDR[22]                            ;
; 64:1               ; 5 bits    ; 210 LEs       ; 60 LEs               ; 150 LEs                ; Yes        ; |DE2_D5M|I2C_CCD_Config:u8|mI2C_DATA[12]                             ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|CMD[1]                               ;
; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|mWR                                  ;
; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|mRD                                  ;
; 7:1                ; 10 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |DE2_D5M|Sdram_Control_4Port:u7|ST[0]                                ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |DE2_D5M|I2C_CCD_Config:u8|senosr_exposure[3]                        ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |DE2_D5M|I2C_CCD_Config:u8|Mux12                                     ;
; 4:1                ; 24 bits   ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; No         ; |DE2_D5M|RAW2RGB:u4|Add0                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_ikn:auto_generated|altsyncram_cm81:altsyncram2 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                  ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+---------------------------------------------+
; Assignment                      ; Value ; From ; To                                          ;
+---------------------------------+-------+------+---------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                           ;
+---------------------------------+-------+------+---------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated ;
+---------------------------------+-------+-----------------+-------------------------------------------------------------+
; Assignment                      ; Value ; From            ; To                                                          ;
+---------------------------------+-------+-----------------+-------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -               ; -                                                           ;
; REMOVE_DUPLICATE_REGISTERS      ; OFF   ; -               ; -                                                           ;
; SUPPRESS_DA_RULE_INTERNAL       ; d101  ; -               ; -                                                           ;
; SUPPRESS_DA_RULE_INTERNAL       ; d102  ; -               ; -                                                           ;
; SUPPRESS_DA_RULE_INTERNAL       ; s102  ; -               ; -                                                           ;
; POWER_UP_LEVEL                  ; LOW   ; -               ; p0addr                                                      ;
; CUT                             ; ON    ; rdptr_g         ; ws_dgrp|dffpipe9|dffe10a                                    ;
; CUT                             ; ON    ; delayed_wrptr_g ; rs_dgwp|dffpipe7|dffe8a                                     ;
+---------------------------------+-------+-----------------+-------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p ;
+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                       ;
+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                        ;
; POWER_UP_LEVEL            ; HIGH  ; -    ; counter_ffa0                                                                                             ;
; POWER_UP_LEVEL            ; HIGH  ; -    ; parity_ff                                                                                                ;
+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                      ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                       ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                  ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                             ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                              ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                        ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                         ;
; SUPPRESS_DA_RULE_INTERNAL       ; c106  ; -    ; -                                                                                         ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                        ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                         ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                        ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                         ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                          ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                           ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                        ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                         ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                        ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                         ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                          ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                           ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+---------------------------------------------+
; Assignment                      ; Value ; From ; To                                          ;
+---------------------------------+-------+------+---------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                           ;
+---------------------------------+-------+------+---------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated ;
+---------------------------------+-------+-----------------+-------------------------------------------------------------+
; Assignment                      ; Value ; From            ; To                                                          ;
+---------------------------------+-------+-----------------+-------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -               ; -                                                           ;
; REMOVE_DUPLICATE_REGISTERS      ; OFF   ; -               ; -                                                           ;
; SUPPRESS_DA_RULE_INTERNAL       ; d101  ; -               ; -                                                           ;
; SUPPRESS_DA_RULE_INTERNAL       ; d102  ; -               ; -                                                           ;
; SUPPRESS_DA_RULE_INTERNAL       ; s102  ; -               ; -                                                           ;
; POWER_UP_LEVEL                  ; LOW   ; -               ; p0addr                                                      ;
; CUT                             ; ON    ; rdptr_g         ; ws_dgrp|dffpipe9|dffe10a                                    ;
; CUT                             ; ON    ; delayed_wrptr_g ; rs_dgwp|dffpipe7|dffe8a                                     ;
+---------------------------------+-------+-----------------+-------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p ;
+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                       ;
+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                        ;
; POWER_UP_LEVEL            ; HIGH  ; -    ; counter_ffa0                                                                                             ;
; POWER_UP_LEVEL            ; HIGH  ; -    ; parity_ff                                                                                                ;
+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                      ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                       ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                  ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                             ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                              ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                        ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                         ;
; SUPPRESS_DA_RULE_INTERNAL       ; c106  ; -    ; -                                                                                         ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                        ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                         ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                        ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                         ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                          ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                           ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                        ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                         ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                        ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                         ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                          ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                           ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+--------------------------------------------+
; Assignment                      ; Value ; From ; To                                         ;
+---------------------------------+-------+------+--------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                          ;
+---------------------------------+-------+------+--------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated ;
+---------------------------------+-------+-----------------+------------------------------------------------------------+
; Assignment                      ; Value ; From            ; To                                                         ;
+---------------------------------+-------+-----------------+------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -               ; -                                                          ;
; REMOVE_DUPLICATE_REGISTERS      ; OFF   ; -               ; -                                                          ;
; SUPPRESS_DA_RULE_INTERNAL       ; d101  ; -               ; -                                                          ;
; SUPPRESS_DA_RULE_INTERNAL       ; d102  ; -               ; -                                                          ;
; SUPPRESS_DA_RULE_INTERNAL       ; s102  ; -               ; -                                                          ;
; POWER_UP_LEVEL                  ; LOW   ; -               ; p0addr                                                     ;
; CUT                             ; ON    ; rdptr_g         ; ws_dgrp|dffpipe9|dffe10a                                   ;
; CUT                             ; ON    ; delayed_wrptr_g ; rs_dgwp|dffpipe7|dffe8a                                    ;
+---------------------------------+-------+-----------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                      ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                       ;
; POWER_UP_LEVEL            ; HIGH  ; -    ; counter_ffa0                                                                                            ;
; POWER_UP_LEVEL            ; HIGH  ; -    ; parity_ff                                                                                               ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                     ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                      ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                 ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                            ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                             ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                        ;
; SUPPRESS_DA_RULE_INTERNAL       ; c106  ; -    ; -                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                         ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                          ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                    ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                     ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                         ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                          ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                    ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                     ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+--------------------------------------------+
; Assignment                      ; Value ; From ; To                                         ;
+---------------------------------+-------+------+--------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                          ;
+---------------------------------+-------+------+--------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated ;
+---------------------------------+-------+-----------------+------------------------------------------------------------+
; Assignment                      ; Value ; From            ; To                                                         ;
+---------------------------------+-------+-----------------+------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -               ; -                                                          ;
; REMOVE_DUPLICATE_REGISTERS      ; OFF   ; -               ; -                                                          ;
; SUPPRESS_DA_RULE_INTERNAL       ; d101  ; -               ; -                                                          ;
; SUPPRESS_DA_RULE_INTERNAL       ; d102  ; -               ; -                                                          ;
; SUPPRESS_DA_RULE_INTERNAL       ; s102  ; -               ; -                                                          ;
; POWER_UP_LEVEL                  ; LOW   ; -               ; p0addr                                                     ;
; CUT                             ; ON    ; rdptr_g         ; ws_dgrp|dffpipe9|dffe10a                                   ;
; CUT                             ; ON    ; delayed_wrptr_g ; rs_dgwp|dffpipe7|dffe8a                                    ;
+---------------------------------+-------+-----------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                      ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                       ;
; POWER_UP_LEVEL            ; HIGH  ; -    ; counter_ffa0                                                                                            ;
; POWER_UP_LEVEL            ; HIGH  ; -    ; parity_ff                                                                                               ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                     ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                      ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                 ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                            ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                             ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                        ;
; SUPPRESS_DA_RULE_INTERNAL       ; c106  ; -    ; -                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                         ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                          ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                    ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                     ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                         ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                          ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                    ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                     ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VGA_Controller:u1 ;
+----------------+-------+---------------------------------------+
; Parameter Name ; Value ; Type                                  ;
+----------------+-------+---------------------------------------+
; H_SYNC_CYC     ; 96    ; Signed Integer                        ;
; H_SYNC_BACK    ; 48    ; Signed Integer                        ;
; H_SYNC_ACT     ; 640   ; Signed Integer                        ;
; H_SYNC_FRONT   ; 16    ; Signed Integer                        ;
; H_SYNC_TOTAL   ; 800   ; Signed Integer                        ;
; V_SYNC_CYC     ; 2     ; Signed Integer                        ;
; V_SYNC_BACK    ; 33    ; Signed Integer                        ;
; V_SYNC_ACT     ; 480   ; Signed Integer                        ;
; V_SYNC_FRONT   ; 10    ; Signed Integer                        ;
; V_SYNC_TOTAL   ; 525   ; Signed Integer                        ;
; X_START        ; 144   ; Signed Integer                        ;
; Y_START        ; 35    ; Signed Integer                        ;
+----------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CCD_Capture:u3 ;
+----------------+-------+------------------------------------+
; Parameter Name ; Value ; Type                               ;
+----------------+-------+------------------------------------+
; COLUMN_WIDTH   ; 1280  ; Signed Integer                     ;
+----------------+-------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
+----------------+----------------+----------------------------------------------------------------------------+
; Parameter Name ; Value          ; Type                                                                       ;
+----------------+----------------+----------------------------------------------------------------------------+
; WIDTH_BYTEENA  ; 1              ; Untyped                                                                    ;
; NUMBER_OF_TAPS ; 2              ; Signed Integer                                                             ;
; TAP_DISTANCE   ; 1280           ; Signed Integer                                                             ;
; WIDTH          ; 12             ; Signed Integer                                                             ;
; POWER_UP_STATE ; CLEARED        ; Untyped                                                                    ;
; CBXI_PARAMETER ; shift_taps_ikn ; Untyped                                                                    ;
+----------------+----------------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sdram_pll:u6|altpll:altpll_component ;
+-------------------------------+-------------------+-------------------------------+
; Parameter Name                ; Value             ; Type                          ;
+-------------------------------+-------------------+-------------------------------+
; OPERATION_MODE                ; NORMAL            ; Untyped                       ;
; PLL_TYPE                      ; AUTO              ; Untyped                       ;
; QUALIFY_CONF_DONE             ; OFF               ; Untyped                       ;
; COMPENSATE_CLOCK              ; CLK0              ; Untyped                       ;
; SCAN_CHAIN                    ; LONG              ; Untyped                       ;
; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                       ;
; INCLK0_INPUT_FREQUENCY        ; 20000             ; Signed Integer                ;
; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                       ;
; GATE_LOCK_SIGNAL              ; NO                ; Untyped                       ;
; GATE_LOCK_COUNTER             ; 0                 ; Untyped                       ;
; LOCK_HIGH                     ; 1                 ; Untyped                       ;
; LOCK_LOW                      ; 1                 ; Untyped                       ;
; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                       ;
; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                       ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                       ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                       ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                       ;
; SKIP_VCO                      ; OFF               ; Untyped                       ;
; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                       ;
; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                       ;
; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                       ;
; BANDWIDTH                     ; 0                 ; Untyped                       ;
; BANDWIDTH_TYPE                ; AUTO              ; Untyped                       ;
; SPREAD_FREQUENCY              ; 0                 ; Untyped                       ;
; DOWN_SPREAD                   ; 0                 ; Untyped                       ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                       ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                       ;
; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                       ;
; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                       ;
; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                       ;
; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                       ;
; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                       ;
; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                       ;
; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                       ;
; CLK2_MULTIPLY_BY              ; 2                 ; Signed Integer                ;
; CLK1_MULTIPLY_BY              ; 5                 ; Signed Integer                ;
; CLK0_MULTIPLY_BY              ; 5                 ; Signed Integer                ;
; CLK9_DIVIDE_BY                ; 0                 ; Untyped                       ;
; CLK8_DIVIDE_BY                ; 0                 ; Untyped                       ;
; CLK7_DIVIDE_BY                ; 0                 ; Untyped                       ;
; CLK6_DIVIDE_BY                ; 0                 ; Untyped                       ;
; CLK5_DIVIDE_BY                ; 1                 ; Untyped                       ;
; CLK4_DIVIDE_BY                ; 1                 ; Untyped                       ;
; CLK3_DIVIDE_BY                ; 1                 ; Untyped                       ;
; CLK2_DIVIDE_BY                ; 1                 ; Signed Integer                ;
; CLK1_DIVIDE_BY                ; 2                 ; Signed Integer                ;
; CLK0_DIVIDE_BY                ; 2                 ; Signed Integer                ;
; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK1_PHASE_SHIFT              ; -3000             ; Untyped                       ;
; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                       ;
; CLK5_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK4_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK3_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK2_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK1_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK0_TIME_DELAY               ; 0                 ; Untyped                       ;
; CLK9_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK8_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK7_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK6_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK5_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK4_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK3_DUTY_CYCLE               ; 50                ; Untyped                       ;
; CLK2_DUTY_CYCLE               ; 50                ; Signed Integer                ;
; CLK1_DUTY_CYCLE               ; 50                ; Signed Integer                ;
; CLK0_DUTY_CYCLE               ; 50                ; Signed Integer                ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                       ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                       ;
; LOCK_WINDOW_UI                ;  0.05             ; Untyped                       ;
; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                       ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                       ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                       ;
; DPA_MULTIPLY_BY               ; 0                 ; Untyped                       ;
; DPA_DIVIDE_BY                 ; 1                 ; Untyped                       ;
; DPA_DIVIDER                   ; 0                 ; Untyped                       ;
; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                       ;
; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                       ;
; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                       ;
; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                       ;
; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                       ;
; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                       ;
; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                       ;
; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                       ;
; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                       ;
; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                       ;
; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                       ;
; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                       ;
; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                       ;
; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                       ;
; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                       ;
; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                       ;
; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                       ;
; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                       ;
; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                       ;
; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                       ;
; VCO_MULTIPLY_BY               ; 0                 ; Untyped                       ;
; VCO_DIVIDE_BY                 ; 0                 ; Untyped                       ;
; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                       ;
; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                       ;
; VCO_MIN                       ; 0                 ; Untyped                       ;
; VCO_MAX                       ; 0                 ; Untyped                       ;
; VCO_CENTER                    ; 0                 ; Untyped                       ;
; PFD_MIN                       ; 0                 ; Untyped                       ;
; PFD_MAX                       ; 0                 ; Untyped                       ;
; M_INITIAL                     ; 0                 ; Untyped                       ;
; M                             ; 0                 ; Untyped                       ;
; N                             ; 1                 ; Untyped                       ;
; M2                            ; 1                 ; Untyped                       ;
; N2                            ; 1                 ; Untyped                       ;
; SS                            ; 1                 ; Untyped                       ;
; C0_HIGH                       ; 0                 ; Untyped                       ;
; C1_HIGH                       ; 0                 ; Untyped                       ;
; C2_HIGH                       ; 0                 ; Untyped                       ;
; C3_HIGH                       ; 0                 ; Untyped                       ;
; C4_HIGH                       ; 0                 ; Untyped                       ;
; C5_HIGH                       ; 0                 ; Untyped                       ;
; C6_HIGH                       ; 0                 ; Untyped                       ;
; C7_HIGH                       ; 0                 ; Untyped                       ;
; C8_HIGH                       ; 0                 ; Untyped                       ;
; C9_HIGH                       ; 0                 ; Untyped                       ;
; C0_LOW                        ; 0                 ; Untyped                       ;
; C1_LOW                        ; 0                 ; Untyped                       ;
; C2_LOW                        ; 0                 ; Untyped                       ;
; C3_LOW                        ; 0                 ; Untyped                       ;
; C4_LOW                        ; 0                 ; Untyped                       ;
; C5_LOW                        ; 0                 ; Untyped                       ;
; C6_LOW                        ; 0                 ; Untyped                       ;
; C7_LOW                        ; 0                 ; Untyped                       ;
; C8_LOW                        ; 0                 ; Untyped                       ;
; C9_LOW                        ; 0                 ; Untyped                       ;
; C0_INITIAL                    ; 0                 ; Untyped                       ;
; C1_INITIAL                    ; 0                 ; Untyped                       ;
; C2_INITIAL                    ; 0                 ; Untyped                       ;
; C3_INITIAL                    ; 0                 ; Untyped                       ;
; C4_INITIAL                    ; 0                 ; Untyped                       ;
; C5_INITIAL                    ; 0                 ; Untyped                       ;
; C6_INITIAL                    ; 0                 ; Untyped                       ;
; C7_INITIAL                    ; 0                 ; Untyped                       ;
; C8_INITIAL                    ; 0                 ; Untyped                       ;
; C9_INITIAL                    ; 0                 ; Untyped                       ;
; C0_MODE                       ; BYPASS            ; Untyped                       ;
; C1_MODE                       ; BYPASS            ; Untyped                       ;
; C2_MODE                       ; BYPASS            ; Untyped                       ;
; C3_MODE                       ; BYPASS            ; Untyped                       ;
; C4_MODE                       ; BYPASS            ; Untyped                       ;
; C5_MODE                       ; BYPASS            ; Untyped                       ;
; C6_MODE                       ; BYPASS            ; Untyped                       ;
; C7_MODE                       ; BYPASS            ; Untyped                       ;
; C8_MODE                       ; BYPASS            ; Untyped                       ;
; C9_MODE                       ; BYPASS            ; Untyped                       ;
; C0_PH                         ; 0                 ; Untyped                       ;
; C1_PH                         ; 0                 ; Untyped                       ;
; C2_PH                         ; 0                 ; Untyped                       ;
; C3_PH                         ; 0                 ; Untyped                       ;
; C4_PH                         ; 0                 ; Untyped                       ;
; C5_PH                         ; 0                 ; Untyped                       ;
; C6_PH                         ; 0                 ; Untyped                       ;
; C7_PH                         ; 0                 ; Untyped                       ;
; C8_PH                         ; 0                 ; Untyped                       ;
; C9_PH                         ; 0                 ; Untyped                       ;
; L0_HIGH                       ; 1                 ; Untyped                       ;
; L1_HIGH                       ; 1                 ; Untyped                       ;
; G0_HIGH                       ; 1                 ; Untyped                       ;
; G1_HIGH                       ; 1                 ; Untyped                       ;
; G2_HIGH                       ; 1                 ; Untyped                       ;
; G3_HIGH                       ; 1                 ; Untyped                       ;
; E0_HIGH                       ; 1                 ; Untyped                       ;
; E1_HIGH                       ; 1                 ; Untyped                       ;
; E2_HIGH                       ; 1                 ; Untyped                       ;
; E3_HIGH                       ; 1                 ; Untyped                       ;
; L0_LOW                        ; 1                 ; Untyped                       ;
; L1_LOW                        ; 1                 ; Untyped                       ;
; G0_LOW                        ; 1                 ; Untyped                       ;
; G1_LOW                        ; 1                 ; Untyped                       ;
; G2_LOW                        ; 1                 ; Untyped                       ;
; G3_LOW                        ; 1                 ; Untyped                       ;
; E0_LOW                        ; 1                 ; Untyped                       ;
; E1_LOW                        ; 1                 ; Untyped                       ;
; E2_LOW                        ; 1                 ; Untyped                       ;
; E3_LOW                        ; 1                 ; Untyped                       ;
; L0_INITIAL                    ; 1                 ; Untyped                       ;
; L1_INITIAL                    ; 1                 ; Untyped                       ;
; G0_INITIAL                    ; 1                 ; Untyped                       ;
; G1_INITIAL                    ; 1                 ; Untyped                       ;
; G2_INITIAL                    ; 1                 ; Untyped                       ;
; G3_INITIAL                    ; 1                 ; Untyped                       ;
; E0_INITIAL                    ; 1                 ; Untyped                       ;
; E1_INITIAL                    ; 1                 ; Untyped                       ;
; E2_INITIAL                    ; 1                 ; Untyped                       ;
; E3_INITIAL                    ; 1                 ; Untyped                       ;
; L0_MODE                       ; BYPASS            ; Untyped                       ;
; L1_MODE                       ; BYPASS            ; Untyped                       ;
; G0_MODE                       ; BYPASS            ; Untyped                       ;
; G1_MODE                       ; BYPASS            ; Untyped                       ;
; G2_MODE                       ; BYPASS            ; Untyped                       ;
; G3_MODE                       ; BYPASS            ; Untyped                       ;
; E0_MODE                       ; BYPASS            ; Untyped                       ;
; E1_MODE                       ; BYPASS            ; Untyped                       ;
; E2_MODE                       ; BYPASS            ; Untyped                       ;
; E3_MODE                       ; BYPASS            ; Untyped                       ;
; L0_PH                         ; 0                 ; Untyped                       ;
; L1_PH                         ; 0                 ; Untyped                       ;
; G0_PH                         ; 0                 ; Untyped                       ;
; G1_PH                         ; 0                 ; Untyped                       ;
; G2_PH                         ; 0                 ; Untyped                       ;
; G3_PH                         ; 0                 ; Untyped                       ;
; E0_PH                         ; 0                 ; Untyped                       ;
; E1_PH                         ; 0                 ; Untyped                       ;
; E2_PH                         ; 0                 ; Untyped                       ;
; E3_PH                         ; 0                 ; Untyped                       ;
; M_PH                          ; 0                 ; Untyped                       ;
; C1_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C2_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C3_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C4_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C5_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C6_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C7_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C8_USE_CASC_IN                ; OFF               ; Untyped                       ;
; C9_USE_CASC_IN                ; OFF               ; Untyped                       ;
; CLK0_COUNTER                  ; G0                ; Untyped                       ;
; CLK1_COUNTER                  ; G0                ; Untyped                       ;
; CLK2_COUNTER                  ; G0                ; Untyped                       ;
; CLK3_COUNTER                  ; G0                ; Untyped                       ;
; CLK4_COUNTER                  ; G0                ; Untyped                       ;
; CLK5_COUNTER                  ; G0                ; Untyped                       ;
; CLK6_COUNTER                  ; E0                ; Untyped                       ;
; CLK7_COUNTER                  ; E1                ; Untyped                       ;
; CLK8_COUNTER                  ; E2                ; Untyped                       ;
; CLK9_COUNTER                  ; E3                ; Untyped                       ;
; L0_TIME_DELAY                 ; 0                 ; Untyped                       ;
; L1_TIME_DELAY                 ; 0                 ; Untyped                       ;
; G0_TIME_DELAY                 ; 0                 ; Untyped                       ;
; G1_TIME_DELAY                 ; 0                 ; Untyped                       ;
; G2_TIME_DELAY                 ; 0                 ; Untyped                       ;
; G3_TIME_DELAY                 ; 0                 ; Untyped                       ;
; E0_TIME_DELAY                 ; 0                 ; Untyped                       ;
; E1_TIME_DELAY                 ; 0                 ; Untyped                       ;
; E2_TIME_DELAY                 ; 0                 ; Untyped                       ;
; E3_TIME_DELAY                 ; 0                 ; Untyped                       ;
; M_TIME_DELAY                  ; 0                 ; Untyped                       ;
; N_TIME_DELAY                  ; 0                 ; Untyped                       ;
; EXTCLK3_COUNTER               ; E3                ; Untyped                       ;
; EXTCLK2_COUNTER               ; E2                ; Untyped                       ;
; EXTCLK1_COUNTER               ; E1                ; Untyped                       ;
; EXTCLK0_COUNTER               ; E0                ; Untyped                       ;
; ENABLE0_COUNTER               ; L0                ; Untyped                       ;
; ENABLE1_COUNTER               ; L0                ; Untyped                       ;
; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                       ;
; LOOP_FILTER_R                 ;  1.000000         ; Untyped                       ;
; LOOP_FILTER_C                 ; 5                 ; Untyped                       ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                       ;
; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                       ;
; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                       ;
; VCO_POST_SCALE                ; 0                 ; Untyped                       ;
; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                       ;
; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                       ;
; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                       ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II        ; Untyped                       ;
; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLK0                     ; PORT_USED         ; Untyped                       ;
; PORT_CLK1                     ; PORT_USED         ; Untyped                       ;
; PORT_CLK2                     ; PORT_USED         ; Untyped                       ;
; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLK6                     ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_CLK7                     ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_CLK8                     ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_CLK9                     ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                       ;
; PORT_INCLK0                   ; PORT_USED         ; Untyped                       ;
; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                       ;
; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                       ;
; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                       ;
; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                       ;
; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                       ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_LOCKED                   ; PORT_UNUSED       ; Untyped                       ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED       ; Untyped                       ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                       ;
; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                       ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                       ;
; PORT_SCANCLKENA               ; PORT_UNUSED       ; Untyped                       ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                       ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                       ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                       ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                       ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C6_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C7_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C8_TEST_SOURCE                ; 5                 ; Untyped                       ;
; C9_TEST_SOURCE                ; 5                 ; Untyped                       ;
; CBXI_PARAMETER                ; NOTHING           ; Untyped                       ;
; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                       ;
; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                       ;
; WIDTH_CLOCK                   ; 6                 ; Untyped                       ;
; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                       ;
; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                       ;
; DEVICE_FAMILY                 ; Cyclone II        ; Untyped                       ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped                       ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                    ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                  ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                  ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                ;
+-------------------------------+-------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7 ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; INIT_PER       ; 24000 ; Signed Integer                             ;
; REF_PER        ; 1024  ; Signed Integer                             ;
; SC_CL          ; 3     ; Signed Integer                             ;
; SC_RCD         ; 3     ; Signed Integer                             ;
; SC_RRD         ; 7     ; Signed Integer                             ;
; SC_PM          ; 1     ; Signed Integer                             ;
; SC_BL          ; 1     ; Signed Integer                             ;
; SDR_BL         ; 111   ; Unsigned Binary                            ;
; SDR_BT         ; 0     ; Unsigned Binary                            ;
; SDR_CL         ; 011   ; Unsigned Binary                            ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|control_interface:control1 ;
+----------------+-------+-----------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                  ;
+----------------+-------+-----------------------------------------------------------------------+
; INIT_PER       ; 24000 ; Signed Integer                                                        ;
; REF_PER        ; 1024  ; Signed Integer                                                        ;
; SC_CL          ; 3     ; Signed Integer                                                        ;
; SC_RCD         ; 3     ; Signed Integer                                                        ;
; SC_RRD         ; 7     ; Signed Integer                                                        ;
; SC_PM          ; 1     ; Signed Integer                                                        ;
; SC_BL          ; 1     ; Signed Integer                                                        ;
; SDR_BL         ; 111   ; Unsigned Binary                                                       ;
; SDR_BT         ; 0     ; Unsigned Binary                                                       ;
; SDR_CL         ; 011   ; Unsigned Binary                                                       ;
+----------------+-------+-----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|command:command1 ;
+----------------+-------+-------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                        ;
+----------------+-------+-------------------------------------------------------------+
; INIT_PER       ; 24000 ; Signed Integer                                              ;
; REF_PER        ; 1024  ; Signed Integer                                              ;
; SC_CL          ; 3     ; Signed Integer                                              ;
; SC_RCD         ; 3     ; Signed Integer                                              ;
; SC_RRD         ; 7     ; Signed Integer                                              ;
; SC_PM          ; 1     ; Signed Integer                                              ;
; SC_BL          ; 1     ; Signed Integer                                              ;
; SDR_BL         ; 111   ; Unsigned Binary                                             ;
; SDR_BT         ; 0     ; Unsigned Binary                                             ;
; SDR_CL         ; 011   ; Unsigned Binary                                             ;
+----------------+-------+-------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|sdr_data_path:data_path1 ;
+----------------+-------+---------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                ;
+----------------+-------+---------------------------------------------------------------------+
; INIT_PER       ; 24000 ; Signed Integer                                                      ;
; REF_PER        ; 1024  ; Signed Integer                                                      ;
; SC_CL          ; 3     ; Signed Integer                                                      ;
; SC_RCD         ; 3     ; Signed Integer                                                      ;
; SC_RRD         ; 7     ; Signed Integer                                                      ;
; SC_PM          ; 1     ; Signed Integer                                                      ;
; SC_BL          ; 1     ; Signed Integer                                                      ;
; SDR_BL         ; 111   ; Unsigned Binary                                                     ;
; SDR_BT         ; 0     ; Unsigned Binary                                                     ;
; SDR_CL         ; 011   ; Unsigned Binary                                                     ;
+----------------+-------+---------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
+-------------------------+-------------+----------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                       ;
+-------------------------+-------------+----------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                    ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                 ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                               ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                               ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                             ;
; LPM_WIDTH               ; 16          ; Signed Integer                                                             ;
; LPM_NUMWORDS            ; 512         ; Signed Integer                                                             ;
; LPM_WIDTHU              ; 9           ; Signed Integer                                                             ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                    ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                    ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                    ;
; USE_EAB                 ; ON          ; Untyped                                                                    ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                    ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                    ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                    ;
; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                    ;
; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                    ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                    ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                    ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                    ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                    ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                    ;
; CBXI_PARAMETER          ; dcfifo_enm1 ; Untyped                                                                    ;
+-------------------------+-------------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
+-------------------------+-------------+----------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                       ;
+-------------------------+-------------+----------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                    ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                 ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                               ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                               ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                             ;
; LPM_WIDTH               ; 16          ; Signed Integer                                                             ;
; LPM_NUMWORDS            ; 512         ; Signed Integer                                                             ;
; LPM_WIDTHU              ; 9           ; Signed Integer                                                             ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                    ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                    ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                    ;
; USE_EAB                 ; ON          ; Untyped                                                                    ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                    ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                    ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                    ;
; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                    ;
; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                    ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                    ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                    ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                    ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                    ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                    ;
; CBXI_PARAMETER          ; dcfifo_enm1 ; Untyped                                                                    ;
+-------------------------+-------------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
+-------------------------+-------------+---------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                      ;
+-------------------------+-------------+---------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                   ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                              ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                              ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                            ;
; LPM_WIDTH               ; 16          ; Signed Integer                                                            ;
; LPM_NUMWORDS            ; 512         ; Signed Integer                                                            ;
; LPM_WIDTHU              ; 9           ; Signed Integer                                                            ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                   ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                   ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                   ;
; USE_EAB                 ; ON          ; Untyped                                                                   ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                   ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                   ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                   ;
; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                   ;
; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                   ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                   ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                   ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                   ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                   ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                   ;
; CBXI_PARAMETER          ; dcfifo_enm1 ; Untyped                                                                   ;
+-------------------------+-------------+---------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
+-------------------------+-------------+---------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                      ;
+-------------------------+-------------+---------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                   ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                              ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                              ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                            ;
; LPM_WIDTH               ; 16          ; Signed Integer                                                            ;
; LPM_NUMWORDS            ; 512         ; Signed Integer                                                            ;
; LPM_WIDTHU              ; 9           ; Signed Integer                                                            ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                   ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                   ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                   ;
; USE_EAB                 ; ON          ; Untyped                                                                   ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                   ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                   ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                   ;
; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                   ;
; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                   ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                   ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                   ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                   ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                   ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                   ;
; CBXI_PARAMETER          ; dcfifo_enm1 ; Untyped                                                                   ;
+-------------------------+-------------+---------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: I2C_CCD_Config:u8 ;
+-----------------------+------------------+---------------------+
; Parameter Name        ; Value            ; Type                ;
+-----------------------+------------------+---------------------+
; default_exposure      ; 0000010000111000 ; Unsigned Binary     ;
; exposure_change_value ; 0000000000110010 ; Unsigned Binary     ;
; CLK_Freq              ; 50000000         ; Signed Integer      ;
; I2C_Freq              ; 20000            ; Signed Integer      ;
; LUT_SIZE              ; 25               ; Signed Integer      ;
+-----------------------+------------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------+
; altshift_taps Parameter Settings by Entity Instance                                          ;
+----------------------------+-----------------------------------------------------------------+
; Name                       ; Value                                                           ;
+----------------------------+-----------------------------------------------------------------+
; Number of entity instances ; 1                                                               ;
; Entity Instance            ; RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
;     -- NUMBER_OF_TAPS      ; 2                                                               ;
;     -- TAP_DISTANCE        ; 1280                                                            ;
;     -- WIDTH               ; 12                                                              ;
+----------------------------+-----------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance                                                       ;
+----------------------------+-----------------------------------------------------------------------+
; Name                       ; Value                                                                 ;
+----------------------------+-----------------------------------------------------------------------+
; Number of entity instances ; 4                                                                     ;
; Entity Instance            ; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                            ;
;     -- LPM_WIDTH           ; 16                                                                    ;
;     -- LPM_NUMWORDS        ; 512                                                                   ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                   ;
;     -- USE_EAB             ; ON                                                                    ;
; Entity Instance            ; Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                            ;
;     -- LPM_WIDTH           ; 16                                                                    ;
;     -- LPM_NUMWORDS        ; 512                                                                   ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                   ;
;     -- USE_EAB             ; ON                                                                    ;
; Entity Instance            ; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component  ;
;     -- FIFO Type           ; Dual Clock                                                            ;
;     -- LPM_WIDTH           ; 16                                                                    ;
;     -- LPM_NUMWORDS        ; 512                                                                   ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                   ;
;     -- USE_EAB             ; ON                                                                    ;
; Entity Instance            ; Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component  ;
;     -- FIFO Type           ; Dual Clock                                                            ;
;     -- LPM_WIDTH           ; 16                                                                    ;
;     -- LPM_NUMWORDS        ; 512                                                                   ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                   ;
;     -- USE_EAB             ; ON                                                                    ;
+----------------------------+-----------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Tue Aug 19 10:22:54 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_D5M -c DE2_D5M
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/command.v
    Info: Found entity 1: command
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/control_interface.v
    Info: Found entity 1: control_interface
Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/sdr_data_path.v
    Info: Found entity 1: sdr_data_path
Warning (10238): Verilog Module Declaration warning at Sdram_Control_4Port.v(98): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "Sdram_Control_4Port"
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/Sdram_Control_4Port.v
    Info: Found entity 1: Sdram_Control_4Port
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/Sdram_FIFO.v
    Info: Found entity 1: Sdram_FIFO
Warning: Can't analyze file -- file D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/async_receiver.v is missing
Info: Found 1 design units, including 1 entities, in source file V/CCD_Capture.v
    Info: Found entity 1: CCD_Capture
Info: Found 1 design units, including 1 entities, in source file V/I2C_CCD_Config.v
    Info: Found entity 1: I2C_CCD_Config
Info: Found 1 design units, including 1 entities, in source file V/I2C_Controller.v
    Info: Found entity 1: I2C_Controller
Info: Found 1 design units, including 1 entities, in source file V/Line_Buffer.v
    Info: Found entity 1: Line_Buffer
Info: Found 1 design units, including 1 entities, in source file V/RAW2RGB.v
    Info: Found entity 1: RAW2RGB
Info: Found 1 design units, including 1 entities, in source file V/Reset_Delay.v
    Info: Found entity 1: Reset_Delay
Info: Found 1 design units, including 1 entities, in source file V/sdram_pll.v
    Info: Found entity 1: sdram_pll
Info: Found 1 design units, including 1 entities, in source file V/SEG7_LUT.v
    Info: Found entity 1: SEG7_LUT
Info: Found 1 design units, including 1 entities, in source file V/SEG7_LUT_8.v
    Info: Found entity 1: SEG7_LUT_8
Warning: Can't analyze file -- file D:/0Clare/DE2/DE2_CAMERA_D5M_fixed/V/uart_crtl.v is missing
Info: Found 1 design units, including 1 entities, in source file V/VGA_Controller.v
    Info: Found entity 1: VGA_Controller
Info: Found 1 design units, including 1 entities, in source file DE2_D5M.v
    Info: Found entity 1: DE2_D5M
Info: Elaborating entity "DE2_D5M" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at DE2_D5M.v(363): truncated value with size 16 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at DE2_D5M.v(368): truncated value with size 32 to match size of target (2)
Warning (10034): Output port "IRDA_TXD" at DE2_D5M.v(196) has no driver
Warning (10034): Output port "FL_ADDR[21]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[20]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[19]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[18]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[17]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[16]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[15]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[14]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[13]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[12]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[11]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[10]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[9]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[8]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[7]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[6]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[5]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[4]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[3]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[2]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[1]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_ADDR[0]" at DE2_D5M.v(213) has no driver
Warning (10034): Output port "FL_WE_N" at DE2_D5M.v(214) has no driver
Warning (10034): Output port "FL_RST_N" at DE2_D5M.v(215) has no driver
Warning (10034): Output port "FL_OE_N" at DE2_D5M.v(216) has no driver
Warning (10034): Output port "FL_CE_N" at DE2_D5M.v(217) has no driver
Warning (10034): Output port "SRAM_ADDR[17]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[16]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[15]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[14]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[13]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[12]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[11]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[10]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[9]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[8]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[7]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[6]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[5]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[4]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[3]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[2]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[1]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_ADDR[0]" at DE2_D5M.v(220) has no driver
Warning (10034): Output port "SRAM_UB_N" at DE2_D5M.v(221) has no driver
Warning (10034): Output port "SRAM_LB_N" at DE2_D5M.v(222) has no driver
Warning (10034): Output port "SRAM_WE_N" at DE2_D5M.v(223) has no driver
Warning (10034): Output port "SRAM_CE_N" at DE2_D5M.v(224) has no driver
Warning (10034): Output port "SRAM_OE_N" at DE2_D5M.v(225) has no driver
Warning (10034): Output port "OTG_ADDR[1]" at DE2_D5M.v(228) has no driver
Warning (10034): Output port "OTG_ADDR[0]" at DE2_D5M.v(228) has no driver
Warning (10034): Output port "OTG_CS_N" at DE2_D5M.v(229) has no driver
Warning (10034): Output port "OTG_RD_N" at DE2_D5M.v(230) has no driver
Warning (10034): Output port "OTG_WR_N" at DE2_D5M.v(231) has no driver
Warning (10034): Output port "OTG_RST_N" at DE2_D5M.v(232) has no driver
Warning (10034): Output port "OTG_FSPEED" at DE2_D5M.v(233) has no driver
Warning (10034): Output port "OTG_LSPEED" at DE2_D5M.v(234) has no driver
Warning (10034): Output port "OTG_DACK0_N" at DE2_D5M.v(239) has no driver
Warning (10034): Output port "OTG_DACK1_N" at DE2_D5M.v(240) has no driver
Warning (10034): Output port "LCD_ON" at DE2_D5M.v(243) has no driver
Warning (10034): Output port "LCD_BLON" at DE2_D5M.v(244) has no driver
Warning (10034): Output port "LCD_RW" at DE2_D5M.v(245) has no driver
Warning (10034): Output port "LCD_EN" at DE2_D5M.v(246) has no driver
Warning (10034): Output port "LCD_RS" at DE2_D5M.v(247) has no driver
Warning (10034): Output port "SD_CLK" at DE2_D5M.v(252) has no driver
Warning (10034): Output port "I2C_SCLK" at DE2_D5M.v(255) has no driver
Warning (10034): Output port "TDO" at DE2_D5M.v(263) has no driver
Warning (10034): Output port "ENET_CMD" at DE2_D5M.v(275) has no driver
Warning (10034): Output port "ENET_CS_N" at DE2_D5M.v(276) has no driver
Warning (10034): Output port "ENET_WR_N" at DE2_D5M.v(277) has no driver
Warning (10034): Output port "ENET_RD_N" at DE2_D5M.v(278) has no driver
Warning (10034): Output port "ENET_RST_N" at DE2_D5M.v(279) has no driver
Warning (10034): Output port "ENET_CLK" at DE2_D5M.v(281) has no driver
Warning (10034): Output port "AUD_DACDAT" at DE2_D5M.v(286) has no driver
Warning (10034): Output port "AUD_XCK" at DE2_D5M.v(288) has no driver
Warning (10034): Output port "TD_RESET" at DE2_D5M.v(293) has no driver
Info: Elaborating entity "VGA_Controller" for hierarchy "VGA_Controller:u1"
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(104): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(107): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(110): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(167): truncated value with size 32 to match size of target (13)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(193): truncated value with size 32 to match size of target (13)
Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:u2"
Info: Elaborating entity "CCD_Capture" for hierarchy "CCD_Capture:u3"
Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "RAW2RGB" for hierarchy "RAW2RGB:u4"
Info: Elaborating entity "Line_Buffer" for hierarchy "RAW2RGB:u4|Line_Buffer:u0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf
    Info: Found entity 1: altshift_taps
Info: Elaborating entity "altshift_taps" for hierarchy "RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
Info: Elaborated megafunction instantiation "RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
Info: Found 1 design units, including 1 entities, in source file db/shift_taps_ikn.tdf
    Info: Found entity 1: shift_taps_ikn
Info: Elaborating entity "shift_taps_ikn" for hierarchy "RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_ikn:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_cm81.tdf
    Info: Found entity 1: altsyncram_cm81
Info: Elaborating entity "altsyncram_cm81" for hierarchy "RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_ikn:auto_generated|altsyncram_cm81:altsyncram2"
Info: Found 1 design units, including 1 entities, in source file db/cntr_3rf.tdf
    Info: Found entity 1: cntr_3rf
Info: Elaborating entity "cntr_3rf" for hierarchy "RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_ikn:auto_generated|cntr_3rf:cntr1"
Info: Elaborating entity "SEG7_LUT_8" for hierarchy "SEG7_LUT_8:u5"
Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT_8:u5|SEG7_LUT:u0"
Info: Elaborating entity "sdram_pll" for hierarchy "sdram_pll:u6"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "sdram_pll:u6|altpll:altpll_component"
Info: Elaborated megafunction instantiation "sdram_pll:u6|altpll:altpll_component"
Info: Elaborating entity "Sdram_Control_4Port" for hierarchy "Sdram_Control_4Port:u7"
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(405): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(451): truncated value with size 32 to match size of target (23)
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(452): truncated value with size 32 to match size of target (23)
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(453): truncated value with size 32 to match size of target (23)
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(454): truncated value with size 32 to match size of target (23)
Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(443): inferring latch(es) for variable "rWR1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(443): inferring latch(es) for variable "rWR2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(443): inferring latch(es) for variable "rRD1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(443): inferring latch(es) for variable "rRD2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "rRD2_MAX_ADDR[0]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[1]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[2]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[3]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[4]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[5]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[6]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[7]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[8]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[9]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[10]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[11]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[12]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[13]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[14]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[15]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[16]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[17]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[18]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[19]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[20]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[21]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD2_MAX_ADDR[22]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[0]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[1]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[2]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[3]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[4]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[5]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[6]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[7]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[8]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[9]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[10]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[11]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[12]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[13]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[14]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[15]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[16]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[17]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[18]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[19]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[20]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[21]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rRD1_MAX_ADDR[22]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[0]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[1]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[2]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[3]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[4]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[5]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[6]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[7]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[8]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[9]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[10]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[11]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[12]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[13]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[14]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[15]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[16]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[17]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[18]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[19]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[20]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[21]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR2_MAX_ADDR[22]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[0]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[1]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[2]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[3]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[4]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[5]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[6]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[7]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[8]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[9]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[10]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[11]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[12]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[13]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[14]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[15]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[16]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[17]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[18]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[19]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[20]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[21]" at Sdram_Control_4Port.v(443)
Info (10041): Inferred latch for "rWR1_MAX_ADDR[22]" at Sdram_Control_4Port.v(443)
Info: Elaborating entity "control_interface" for hierarchy "Sdram_Control_4Port:u7|control_interface:control1"
Warning (10230): Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "command" for hierarchy "Sdram_Control_4Port:u7|command:command1"
Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always construct
Info: Elaborating entity "sdr_data_path" for hierarchy "Sdram_Control_4Port:u7|sdr_data_path:data_path1"
Warning (10230): Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)
Info: Elaborating entity "Sdram_FIFO" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/dcfifo.tdf
    Info: Found entity 1: dcfifo
Info: Elaborating entity "dcfifo" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
Info: Elaborated megafunction instantiation "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
Info: Found 1 design units, including 1 entities, in source file db/dcfifo_enm1.tdf
    Info: Found entity 1: dcfifo_enm1
Info: Elaborating entity "dcfifo_enm1" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_kdb.tdf
    Info: Found entity 1: a_gray2bin_kdb
Info: Elaborating entity "a_gray2bin_kdb" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_o96.tdf
    Info: Found entity 1: a_graycounter_o96
Info: Elaborating entity "a_graycounter_o96" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_o96:rdptr_g1p"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_fgc.tdf
    Info: Found entity 1: a_graycounter_fgc
Info: Elaborating entity "a_graycounter_fgc" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_egc.tdf
    Info: Found entity 1: a_graycounter_egc
Info: Elaborating entity "a_graycounter_egc" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_egc:wrptr_gp"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3731.tdf
    Info: Found entity 1: altsyncram_3731
Info: Elaborating entity "altsyncram_3731" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_drg1.tdf
    Info: Found entity 1: altsyncram_drg1
Info: Elaborating entity "altsyncram_drg1" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_mcc.tdf
    Info: Found entity 1: dffpipe_mcc
Info: Elaborating entity "dffpipe_mcc" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_mcc:rdaclr"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf
    Info: Found entity 1: dffpipe_oe9
Info: Elaborating entity "dffpipe_oe9" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ud8.tdf
    Info: Found entity 1: alt_synch_pipe_ud8
Info: Elaborating entity "alt_synch_pipe_ud8" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
    Info: Found entity 1: dffpipe_pe9
Info: Elaborating entity "dffpipe_pe9" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_ud8:rs_dgwp|dffpipe_pe9:dffpipe7"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_vd8.tdf
    Info: Found entity 1: alt_synch_pipe_vd8
Info: Elaborating entity "alt_synch_pipe_vd8" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
    Info: Found entity 1: dffpipe_qe9
Info: Elaborating entity "dffpipe_qe9" for hierarchy "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|alt_synch_pipe_vd8:ws_dgrp|dffpipe_qe9:dffpipe9"
Info: Elaborating entity "I2C_CCD_Config" for hierarchy "I2C_CCD_Config:u8"
Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(121): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(122): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(155): truncated value with size 32 to match size of target (25)
Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(185): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(235): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "I2C_Controller" for hierarchy "I2C_CCD_Config:u8|I2C_Controller:u0"
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)
Warning (12010): Port "CMD" on the entity instantiation of "control1" is connected to a signal of width 2. The formal width of the signal in the module is 3.  Extra bits will be driven by GND.
Warning (12030): Port "CS_N" on the entity instantiation of "u7" is connected to a signal of width 1. The formal width of the signal in the module is 2.  Extra bits will be left dangling without any fanout logic.
Warning (12020): Port "RD1_ADDR" on the entity instantiation of "u7" is connected to a signal of width 32. The formal width of the signal in the module is 23.  Extra bits will be ignored.
Warning (12020): Port "RD1_MAX_ADDR" on the entity instantiation of "u7" is connected to a signal of width 32. The formal width of the signal in the module is 23.  Extra bits will be ignored.
Warning (12010): Port "RD2_ADDR" on the entity instantiation of "u7" is connected to a signal of width 22. The formal width of the signal in the module is 23.  Extra bits will be driven by GND.
Warning (12020): Port "RD2_MAX_ADDR" on the entity instantiation of "u7" is connected to a signal of width 32. The formal width of the signal in the module is 23.  Extra bits will be ignored.
Warning (12020): Port "WR1_ADDR" on the entity instantiation of "u7" is connected to a signal of width 32. The formal width of the signal in the module is 23.  Extra bits will be ignored.
Warning (12020): Port "WR1_MAX_ADDR" on the entity instantiation of "u7" is connected to a signal of width 32. The formal width of the signal in the module is 23.  Extra bits will be ignored.
Warning (12010): Port "WR2_ADDR" on the entity instantiation of "u7" is connected to a signal of width 22. The formal width of the signal in the module is 23.  Extra bits will be driven by GND.
Warning (12020): Port "WR2_MAX_ADDR" on the entity instantiation of "u7" is connected to a signal of width 32. The formal width of the signal in the module is 23.  Extra bits will be ignored.
Warning (12020): Port "iX_Cont" on the entity instantiation of "u4" is connected to a signal of width 16. The formal width of the signal in the module is 11.  Extra bits will be ignored.
Warning (12020): Port "iY_Cont" on the entity instantiation of "u4" is connected to a signal of width 16. The formal width of the signal in the module is 11.  Extra bits will be ignored.
Info: Power-up level of register "Sdram_Control_4Port:u7|rWR1_LENGTH[8]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR1_LENGTH[8]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR1_LENGTH[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR1_LENGTH[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR1_LENGTH[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR1_LENGTH[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR1_LENGTH[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR1_LENGTH[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR1_LENGTH[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR1_LENGTH[0]" with stuck data_in port to stuck value GND
Info: Power-up level of register "Sdram_Control_4Port:u7|rWR2_LENGTH[8]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR2_LENGTH[8]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR2_LENGTH[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR2_LENGTH[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR2_LENGTH[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR2_LENGTH[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR2_LENGTH[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR2_LENGTH[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR2_LENGTH[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR2_LENGTH[0]" with stuck data_in port to stuck value GND
Info: Power-up level of register "Sdram_Control_4Port:u7|rRD1_LENGTH[8]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD1_LENGTH[8]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD1_LENGTH[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD1_LENGTH[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD1_LENGTH[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD1_LENGTH[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD1_LENGTH[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD1_LENGTH[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD1_LENGTH[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD1_LENGTH[0]" with stuck data_in port to stuck value GND
Info: Power-up level of register "Sdram_Control_4Port:u7|rRD2_LENGTH[8]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD2_LENGTH[8]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD2_LENGTH[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD2_LENGTH[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD2_LENGTH[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD2_LENGTH[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD2_LENGTH[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD2_LENGTH[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD2_LENGTH[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD2_LENGTH[0]" with stuck data_in port to stuck value GND
Info: Power-up level of register "Sdram_Control_4Port:u7|command:command1|CKE" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "Sdram_Control_4Port:u7|command:command1|CKE" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "VGA_Controller:u1|oVGA_SYNC" with stuck data_in port to stuck value GND
Info: Power-up level of register "Sdram_Control_4Port:u7|CKE" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "Sdram_Control_4Port:u7|CKE" with stuck data_in port to stuck value VCC
Warning: Synthesized away the following node(s):
    Warning: Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3|q_a[15]"
        Warning (14320): Synthesized away node "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3|q_a[15]"
Info: Power-up level of register "I2C_CCD_Config:u8|mI2C_DATA[31]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "I2C_CCD_Config:u8|mI2C_DATA[31]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "I2C_CCD_Config:u8|mI2C_DATA[30]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_CCD_Config:u8|mI2C_DATA[29]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "I2C_CCD_Config:u8|mI2C_DATA[29]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "I2C_CCD_Config:u8|mI2C_DATA[28]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "I2C_CCD_Config:u8|mI2C_DATA[28]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "I2C_CCD_Config:u8|mI2C_DATA[27]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "I2C_CCD_Config:u8|mI2C_DATA[27]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "I2C_CCD_Config:u8|mI2C_DATA[26]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_CCD_Config:u8|mI2C_DATA[25]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "I2C_CCD_Config:u8|mI2C_DATA[25]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "I2C_CCD_Config:u8|mI2C_DATA[24]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[29]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[29]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[28]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[28]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[27]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[27]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR1_ADDR[6]" merged to single register "Sdram_Control_4Port:u7|rWR1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR1_ADDR[1]" merged to single register "Sdram_Control_4Port:u7|rWR1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR1_ADDR[3]" merged to single register "Sdram_Control_4Port:u7|rWR1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR1_ADDR[4]" merged to single register "Sdram_Control_4Port:u7|rWR1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR1_ADDR[2]" merged to single register "Sdram_Control_4Port:u7|rWR1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR1_ADDR[0]" merged to single register "Sdram_Control_4Port:u7|rWR1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR1_ADDR[5]" merged to single register "Sdram_Control_4Port:u7|rWR1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR2_ADDR[4]" merged to single register "Sdram_Control_4Port:u7|rWR2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR2_ADDR[0]" merged to single register "Sdram_Control_4Port:u7|rWR2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR2_ADDR[1]" merged to single register "Sdram_Control_4Port:u7|rWR2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR2_ADDR[5]" merged to single register "Sdram_Control_4Port:u7|rWR2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR2_ADDR[3]" merged to single register "Sdram_Control_4Port:u7|rWR2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR2_ADDR[2]" merged to single register "Sdram_Control_4Port:u7|rWR2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rWR2_ADDR[6]" merged to single register "Sdram_Control_4Port:u7|rWR2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD1_ADDR[3]" merged to single register "Sdram_Control_4Port:u7|rRD1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD1_ADDR[2]" merged to single register "Sdram_Control_4Port:u7|rRD1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD1_ADDR[5]" merged to single register "Sdram_Control_4Port:u7|rRD1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD1_ADDR[1]" merged to single register "Sdram_Control_4Port:u7|rRD1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD1_ADDR[0]" merged to single register "Sdram_Control_4Port:u7|rRD1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD1_ADDR[6]" merged to single register "Sdram_Control_4Port:u7|rRD1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD1_ADDR[4]" merged to single register "Sdram_Control_4Port:u7|rRD1_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD2_ADDR[6]" merged to single register "Sdram_Control_4Port:u7|rRD2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD2_ADDR[2]" merged to single register "Sdram_Control_4Port:u7|rRD2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD2_ADDR[3]" merged to single register "Sdram_Control_4Port:u7|rRD2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD2_ADDR[5]" merged to single register "Sdram_Control_4Port:u7|rRD2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD2_ADDR[0]" merged to single register "Sdram_Control_4Port:u7|rRD2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD2_ADDR[1]" merged to single register "Sdram_Control_4Port:u7|rRD2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|rRD2_ADDR[4]" merged to single register "Sdram_Control_4Port:u7|rRD2_ADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mLENGTH[6]" merged to single register "Sdram_Control_4Port:u7|mLENGTH[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mLENGTH[5]" merged to single register "Sdram_Control_4Port:u7|mLENGTH[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mLENGTH[4]" merged to single register "Sdram_Control_4Port:u7|mLENGTH[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mLENGTH[3]" merged to single register "Sdram_Control_4Port:u7|mLENGTH[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mLENGTH[2]" merged to single register "Sdram_Control_4Port:u7|mLENGTH[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mLENGTH[1]" merged to single register "Sdram_Control_4Port:u7|mLENGTH[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mLENGTH[0]" merged to single register "Sdram_Control_4Port:u7|mLENGTH[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|DQM[1]" merged to single register "Sdram_Control_4Port:u7|DQM[0]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mADDR[6]" merged to single register "Sdram_Control_4Port:u7|mADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mADDR[5]" merged to single register "Sdram_Control_4Port:u7|mADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mADDR[4]" merged to single register "Sdram_Control_4Port:u7|mADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mADDR[3]" merged to single register "Sdram_Control_4Port:u7|mADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mADDR[2]" merged to single register "Sdram_Control_4Port:u7|mADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mADDR[1]" merged to single register "Sdram_Control_4Port:u7|mADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|mADDR[0]" merged to single register "Sdram_Control_4Port:u7|mADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[6]" merged to single register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[5]" merged to single register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[4]" merged to single register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[3]" merged to single register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[2]" merged to single register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[1]" merged to single register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]"
    Info: Duplicate register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[0]" merged to single register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]"
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR1_ADDR[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rWR2_ADDR[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD1_ADDR[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|rRD2_ADDR[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|mLENGTH[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|mADDR[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]" with stuck data_in port to stuck value GND
Info: Power-up level of register "Sdram_Control_4Port:u7|mLENGTH[8]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "Sdram_Control_4Port:u7|mLENGTH[8]" with stuck data_in port to stuck value VCC
Info: State machine "|DE2_D5M|I2C_CCD_Config:u8|mSetup_ST" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|DE2_D5M|I2C_CCD_Config:u8|mSetup_ST"
Info: Encoding result for state machine "|DE2_D5M|I2C_CCD_Config:u8|mSetup_ST"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "I2C_CCD_Config:u8|mSetup_ST.0000"
        Info: Encoded state bit "I2C_CCD_Config:u8|mSetup_ST.0010"
        Info: Encoded state bit "I2C_CCD_Config:u8|mSetup_ST.0001"
    Info: State "|DE2_D5M|I2C_CCD_Config:u8|mSetup_ST.0000" uses code string "000"
    Info: State "|DE2_D5M|I2C_CCD_Config:u8|mSetup_ST.0001" uses code string "101"
    Info: State "|DE2_D5M|I2C_CCD_Config:u8|mSetup_ST.0010" uses code string "110"
Warning: Hierarchy name "Sdram_Control_4Port:u11" does not exist.  It is associated with user assignments.
Warning: The bidir "FL_DQ[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FL_DQ[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FL_DQ[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FL_DQ[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FL_DQ[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FL_DQ[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FL_DQ[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FL_DQ[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[13]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SRAM_DQ[15]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[13]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[15]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SD_DAT" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SD_DAT3" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SD_CMD" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "I2C_SDAT" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[13]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[15]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "AUD_ADCLRCK" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "AUD_DACLRCK" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "AUD_BCLK" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[13]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[15]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[16]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[17]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[18]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[19]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[20]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[21]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[22]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[23]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[24]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[25]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[26]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[27]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[28]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[29]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[30]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[31]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[32]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[33]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[34]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_0[35]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[15]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[18]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[20]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[25]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[26]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[27]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[28]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[29]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[30]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[31]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[32]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[33]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[34]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[35]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[13]" has no source; inserted an always disabled tri-state buffer.
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1[16]~6 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1[17]~5 that it feeds
Warning: Replaced VCC or GND feeding tri-state bus GPIO_1[19]~4 with an always-enabled tri-state buffer
Warning: The bidir "GPIO_1[21]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIO_1[22]" has no source; inserted an always disabled tri-state buffer.
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1[24]~0 that it feeds
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "GPIO_1[16]~67"
    Warning: Node "GPIO_1[17]~68"
    Warning: Node "GPIO_1[19]~69"
    Warning: Node "GPIO_1[24]~72"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "IRDA_TXD" stuck at GND
    Warning (13410): Pin "DRAM_CKE" stuck at VCC
    Warning (13410): Pin "FL_ADDR[0]" stuck at GND
    Warning (13410): Pin "FL_ADDR[1]" stuck at GND
    Warning (13410): Pin "FL_ADDR[2]" stuck at GND
    Warning (13410): Pin "FL_ADDR[3]" stuck at GND
    Warning (13410): Pin "FL_ADDR[4]" stuck at GND
    Warning (13410): Pin "FL_ADDR[5]" stuck at GND
    Warning (13410): Pin "FL_ADDR[6]" stuck at GND
    Warning (13410): Pin "FL_ADDR[7]" stuck at GND
    Warning (13410): Pin "FL_ADDR[8]" stuck at GND
    Warning (13410): Pin "FL_ADDR[9]" stuck at GND
    Warning (13410): Pin "FL_ADDR[10]" stuck at GND
    Warning (13410): Pin "FL_ADDR[11]" stuck at GND
    Warning (13410): Pin "FL_ADDR[12]" stuck at GND
    Warning (13410): Pin "FL_ADDR[13]" stuck at GND
    Warning (13410): Pin "FL_ADDR[14]" stuck at GND
    Warning (13410): Pin "FL_ADDR[15]" stuck at GND
    Warning (13410): Pin "FL_ADDR[16]" stuck at GND
    Warning (13410): Pin "FL_ADDR[17]" stuck at GND
    Warning (13410): Pin "FL_ADDR[18]" stuck at GND
    Warning (13410): Pin "FL_ADDR[19]" stuck at GND
    Warning (13410): Pin "FL_ADDR[20]" stuck at GND
    Warning (13410): Pin "FL_ADDR[21]" stuck at GND
    Warning (13410): Pin "FL_WE_N" stuck at GND
    Warning (13410): Pin "FL_RST_N" stuck at GND
    Warning (13410): Pin "FL_OE_N" stuck at GND
    Warning (13410): Pin "FL_CE_N" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[0]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[1]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[2]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[3]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[4]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[5]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[6]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[7]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[8]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[9]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[10]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[11]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[12]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[13]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[14]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[15]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[16]" stuck at GND
    Warning (13410): Pin "SRAM_ADDR[17]" stuck at GND
    Warning (13410): Pin "SRAM_UB_N" stuck at GND
    Warning (13410): Pin "SRAM_LB_N" stuck at GND
    Warning (13410): Pin "SRAM_WE_N" stuck at GND
    Warning (13410): Pin "SRAM_CE_N" stuck at GND
    Warning (13410): Pin "SRAM_OE_N" stuck at GND
    Warning (13410): Pin "OTG_ADDR[0]" stuck at GND
    Warning (13410): Pin "OTG_ADDR[1]" stuck at GND
    Warning (13410): Pin "OTG_CS_N" stuck at GND
    Warning (13410): Pin "OTG_RD_N" stuck at GND
    Warning (13410): Pin "OTG_WR_N" stuck at GND
    Warning (13410): Pin "OTG_RST_N" stuck at GND
    Warning (13410): Pin "OTG_FSPEED" stuck at GND
    Warning (13410): Pin "OTG_LSPEED" stuck at GND
    Warning (13410): Pin "OTG_DACK0_N" stuck at GND
    Warning (13410): Pin "OTG_DACK1_N" stuck at GND
    Warning (13410): Pin "LCD_ON" stuck at GND
    Warning (13410): Pin "LCD_BLON" stuck at GND
    Warning (13410): Pin "LCD_RW" stuck at GND
    Warning (13410): Pin "LCD_EN" stuck at GND
    Warning (13410): Pin "LCD_RS" stuck at GND
    Warning (13410): Pin "SD_CLK" stuck at GND
    Warning (13410): Pin "TDO" stuck at GND
    Warning (13410): Pin "I2C_SCLK" stuck at GND
    Warning (13410): Pin "VGA_SYNC" stuck at GND
    Warning (13410): Pin "ENET_CMD" stuck at GND
    Warning (13410): Pin "ENET_CS_N" stuck at GND
    Warning (13410): Pin "ENET_WR_N" stuck at GND
    Warning (13410): Pin "ENET_RD_N" stuck at GND
    Warning (13410): Pin "ENET_RST_N" stuck at GND
    Warning (13410): Pin "ENET_CLK" stuck at GND
    Warning (13410): Pin "AUD_DACDAT" stuck at GND
    Warning (13410): Pin "AUD_XCK" stuck at GND
    Warning (13410): Pin "TD_RESET" stuck at GND
Info: 61 registers lost all their fanouts during netlist optimizations. The first 61 are displayed below.
    Info: Register "Sdram_Control_4Port:u7|mDATAOUT[15]" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa0" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa1" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa2" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa3" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa4" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa5" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa6" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa7" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa8" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa9" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|parity_ff" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa0" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa1" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa2" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa3" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa4" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa5" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa6" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa7" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa8" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa9" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|parity_ff" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa0" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa1" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa2" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa3" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa4" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa5" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa6" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa7" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa8" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa9" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|parity_ff" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa0" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa1" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa2" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa3" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa4" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa5" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa6" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa7" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa8" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|counter_ffa9" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|a_graycounter_fgc:wrptr_g1p|parity_ff" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp|dffe6a[9]" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp|dffe6a[9]" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_bwp|dffe6a[9]" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:ws_brp|dffe6a[9]" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp|dffe6a[9]" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp|dffe6a[9]" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_bwp|dffe6a[9]" lost all its fanouts during netlist optimizations.
    Info: Register "Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_enm1:auto_generated|dffpipe_oe9:rs_brp|dffe6a[9]" lost all its fanouts during netlist optimizations.
    Info: Register "rClk[1]" lost all its fanouts during netlist optimizations.
    Info: Register "I2C_CCD_Config:u8|mSetup_ST~93" lost all its fanouts during netlist optimizations.
    Info: Register "I2C_CCD_Config:u8|mSetup_ST~94" lost all its fanouts during netlist optimizations.
    Info: Register "CCD_Capture:u3|Y_Cont[11]" lost all its fanouts during netlist optimizations.
    Info: Register "CCD_Capture:u3|Y_Cont[12]" lost all its fanouts during netlist optimizations.
    Info: Register "CCD_Capture:u3|Y_Cont[13]" lost all its fanouts during netlist optimizations.
    Info: Register "CCD_Capture:u3|Y_Cont[14]" lost all its fanouts during netlist optimizations.
    Info: Register "CCD_Capture:u3|Y_Cont[15]" lost all its fanouts during netlist optimizations.
Warning: Design contains 24 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "CLOCK_27"
    Warning (15610): No output dependent on input pin "EXT_CLOCK"
    Warning (15610): No output dependent on input pin "IRDA_RXD"
    Warning (15610): No output dependent on input pin "OTG_INT0"
    Warning (15610): No output dependent on input pin "OTG_INT1"
    Warning (15610): No output dependent on input pin "OTG_DREQ0"
    Warning (15610): No output dependent on input pin "OTG_DREQ1"
    Warning (15610): No output dependent on input pin "TDI"
    Warning (15610): No output dependent on input pin "TCK"
    Warning (15610): No output dependent on input pin "TCS"
    Warning (15610): No output dependent on input pin "PS2_DAT"
    Warning (15610): No output dependent on input pin "PS2_CLK"
    Warning (15610): No output dependent on input pin "ENET_INT"
    Warning (15610): No output dependent on input pin "AUD_ADCDAT"
    Warning (15610): No output dependent on input pin "TD_DATA[0]"
    Warning (15610): No output dependent on input pin "TD_DATA[1]"
    Warning (15610): No output dependent on input pin "TD_DATA[2]"
    Warning (15610): No output dependent on input pin "TD_DATA[3]"
    Warning (15610): No output dependent on input pin "TD_DATA[4]"
    Warning (15610): No output dependent on input pin "TD_DATA[5]"
    Warning (15610): No output dependent on input pin "TD_DATA[6]"
    Warning (15610): No output dependent on input pin "TD_DATA[7]"
    Warning (15610): No output dependent on input pin "TD_HS"
    Warning (15610): No output dependent on input pin "TD_VS"
Info: Implemented 2022 device resources after synthesis - the final resource count might be different
    Info: Implemented 48 input pins
    Info: Implemented 218 output pins
    Info: Implemented 159 bidirectional pins
    Info: Implemented 1510 logic cells
    Info: Implemented 86 RAM segments
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 447 warnings
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Tue Aug 19 10:23:06 2008
    Info: Elapsed time: 00:00:12


