Classic Timing Analyzer report for DE2_70
Mon Sep 29 16:27:53 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
  6. Clock Setup: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
  7. Clock Setup: 'GPIO_CLKIN_N1'
  8. Clock Setup: 'iCLK_50'
  9. Clock Hold: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
 10. Clock Hold: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
 11. Clock Hold: 'GPIO_CLKIN_N1'
 12. Clock Hold: 'iCLK_50'
 13. tsu
 14. tco
 15. tpd
 16. th
 17. Ignored Timing Assignments
 18. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



 
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
 
; Type                                                              ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                             ; To                                                                                                                               ; From Clock                                         ; To Clock                                           ; Failed Paths ;
 
; Worst-case tsu                                                    ; -0.330 ns ; 1.000 ns                         ; 1.330 ns                         ; DRAM_DQ[30]                                                                                                                                                      ; Sdram_Control_4Port:sdram1|mDATAOUT[14]                                                                                          ; --                                                 ; iCLK_50_3                                          ; 24           ;
; Worst-case tco                                                    ; -4.930 ns ; 1.000 ns                         ; 5.930 ns                         ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3] ; DRAM_DQ[3]                                                                                                                       ; iCLK_50_3                                          ; --                                                 ; 128          ;
; Worst-case tpd                                                    ; N/A       ; None                             ; 10.588 ns                        ; iSW[3]                                                                                                                                                           ; oLEDR[3]                                                                                                                         ; --                                                 ; --                                                 ; 0            ;
; Worst-case th                                                     ; N/A       ; None                             ; 0.553 ns                         ; GPIO_1[19]                                                                                                                                                       ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4                                                                            ; --                                                 ; iCLK_50                                            ; 0            ;
; Clock Setup: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0' ; 1.144 ns  ; 166.67 MHz ( period = 6.000 ns ) ; 205.93 MHz ( period = 4.856 ns ) ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                                ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'GPIO_CLKIN_N1'                                      ; 2.038 ns  ; 110.01 MHz ( period = 9.090 ns ) ; 141.80 MHz ( period = 7.052 ns ) ; CCD_Capture:capture0|Y_Cont[3]                                                                                                                                   ; RAW2RGB:raw0|rGreen[5]                                                                                                           ; GPIO_CLKIN_N1                                      ; GPIO_CLKIN_N1                                      ; 0            ;
; Clock Setup: 'iCLK_50'                                            ; 6.670 ns  ; 50.00 MHz ( period = 20.000 ns ) ; 150.15 MHz ( period = 6.660 ns ) ; lcd_3wire_config:lcd_config0|m3wire_data[14]                                                                                                                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA                                                                            ; iCLK_50                                            ; iCLK_50                                            ; 0            ;
; Clock Setup: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'     ; 10.156 ns ; 33.33 MHz ( period = 30.000 ns ) ; 103.22 MHz ( period = 9.688 ns ) ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; touch_tcon:vga0|oLCD_B[5]                                                                                                        ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; 0            ;
; Clock Hold: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'  ; 0.391 ns  ; 166.67 MHz ( period = 6.000 ns ) ; N/A                              ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                                ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'GPIO_CLKIN_N1'                                       ; 0.391 ns  ; 110.01 MHz ( period = 9.090 ns ) ; N/A                              ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                                   ; CCD_Capture:capture0|mCCD_FVAL                                                                                                   ; GPIO_CLKIN_N1                                      ; GPIO_CLKIN_N1                                      ; 0            ;
; Clock Hold: 'iCLK_50'                                             ; 0.391 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; rClk[0]                                                                                                                                                          ; rClk[0]                                                                                                                          ; iCLK_50                                            ; iCLK_50                                            ; 0            ;
; Clock Hold: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'      ; 0.520 ns  ; 33.33 MHz ( period = 30.000 ns ) ; N/A                              ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[0]                                 ; Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[0] ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; 0            ;
; Total number of failed paths                                      ;           ;                                  ;                                  ;                                                                                                                                                                  ;                                                                                                                                  ;                                                    ;                                                    ; 152          ;
 


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                             ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
; Option                                                              ; Setting            ; From            ; To                        ; Entity Name ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
; Device Name                                                         ; EP2C70F896C6       ;                 ;                           ;             ;
; Timing Models                                                       ; Final              ;                 ;                           ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;                 ;                           ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;                 ;                           ;             ;
; Cut off read during write signal paths                              ; On                 ;                 ;                           ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;                 ;                           ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;                 ;                           ;             ;
; Ignore Clock Settings                                               ; Off                ;                 ;                           ;             ;
; Analyze latches as synchronous elements                             ; On                 ;                 ;                           ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;                 ;                           ;             ;
; Enable Clock Latency                                                ; Off                ;                 ;                           ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;                 ;                           ;             ;
; Number of source nodes to report per destination node               ; 10                 ;                 ;                           ;             ;
; Number of destination nodes to report                               ; 10                 ;                 ;                           ;             ;
; Number of paths to report                                           ; 200                ;                 ;                           ;             ;
; Report Minimum Timing Checks                                        ; Off                ;                 ;                           ;             ;
; Use Fast Timing Models                                              ; Off                ;                 ;                           ;             ;
; Report IO Paths Separately                                          ; Off                ;                 ;                           ;             ;
; Perform Multicorner Analysis                                        ; On                 ;                 ;                           ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;                 ;                           ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;                 ;                           ;             ;
; tsu Requirement                                                     ; 5 ns               ; *               ; rCCD_DATA                 ;             ;
; tsu Requirement                                                     ; 5 ns               ; *               ; rCCD_FVAL                 ;             ;
; tsu Requirement                                                     ; 5 ns               ; *               ; rCCD_LVAL                 ;             ;
; tsu Requirement                                                     ; 1 ns               ; DRAM_DQ         ; *                         ;             ;
; tco Requirement                                                     ; 1 ns               ; *               ; DRAM_DQ                   ;             ;
; Clock Settings                                                      ; CCD_PIXCLK         ;                 ; GPIO_CLKIN_N1             ;             ;
; Clock Settings                                                      ; CCD_MCLK           ;                 ; GPIO_CLKOUT_N1            ;             ;
; Clock Settings                                                      ; CLK50              ;                 ; iCLK_50                   ;             ;
; Clock Settings                                                      ; DRAM0_CLK          ;                 ; oDRAM0_CLK                ;             ;
; Cut Timing Path                                                     ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe9|dffe10a  ; dcfifo_m2o1 ;
; Cut Timing Path                                                     ; On                 ; rdptr_g         ; ws_dgrp|dffpipe11|dffe12a ; dcfifo_m2o1 ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                         ;
+----------------------------------------------------+--------------------+---------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                    ; Clock Setting Name ; Type          ; Fmax Requirement ; Early Latency ; Late Latency ; Based on  ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+----------------------------------------------------+--------------------+---------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+
; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ;                    ; PLL output    ; 166.67 MHz       ; 0.000 ns      ; 0.000 ns     ; iCLK_50_3 ; 10                    ; 3                   ; -2.594 ns ;              ;
; sdram_pll:sdram_pll0|altpll:altpll_component|_clk1 ;                    ; PLL output    ; 166.67 MHz       ; 0.000 ns      ; 0.000 ns     ; iCLK_50_3 ; 10                    ; 3                   ; -4.094 ns ;              ;
; sdram_pll:sdram_pll0|altpll:altpll_component|_clk2 ;                    ; PLL output    ; 166.67 MHz       ; 0.000 ns      ; 0.000 ns     ; iCLK_50_3 ; 10                    ; 3                   ; -4.094 ns ;              ;
; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ;                    ; PLL output    ; 33.33 MHz        ; 0.000 ns      ; 0.000 ns     ; iCLK_50_2 ; 2                     ; 3                   ; -2.608 ns ;              ;
; GPIO_CLKIN_N1                                      ; CCD_PIXCLK         ; User Pin      ; 110.01 MHz       ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; iCLK_50                                            ; CLK50              ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_CLKOUT_N1                                     ; CCD_MCLK           ; User Pin      ; 96.01 MHz        ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; oDRAM0_CLK                                         ; DRAM0_CLK          ; Internal Node ; 150.02 MHz       ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; iCLK_50_3                                          ;                    ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; iCLK_50_2                                          ;                    ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
+----------------------------------------------------+--------------------+---------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+


 
; Clock Setup: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
 
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                            ; To                                                                                                                                                                                       ; From Clock                                         ; To Clock                                           ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
 
; 1.144 ns                                ; 205.93 MHz ( period = 4.856 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.681 ns                ;
; 1.144 ns                                ; 205.93 MHz ( period = 4.856 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.681 ns                ;
; 1.211 ns                                ; 208.81 MHz ( period = 4.789 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.575 ns                ;
; 1.244 ns                                ; 210.26 MHz ( period = 4.756 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.581 ns                ;
; 1.244 ns                                ; 210.26 MHz ( period = 4.756 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.581 ns                ;
; 1.276 ns                                ; 211.69 MHz ( period = 4.724 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.511 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.504 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.304 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.523 ns                ;
; 1.308 ns                                ; 213.13 MHz ( period = 4.692 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.479 ns                ;
; 1.329 ns                                ; 214.09 MHz ( period = 4.671 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.496 ns                ;
; 1.329 ns                                ; 214.09 MHz ( period = 4.671 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.496 ns                ;
; 1.342 ns                                ; 214.68 MHz ( period = 4.658 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.445 ns                ;
; 1.347 ns                                ; 214.92 MHz ( period = 4.653 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.440 ns                ;
; 1.353 ns                                ; 215.19 MHz ( period = 4.647 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.472 ns                ;
; 1.353 ns                                ; 215.19 MHz ( period = 4.647 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.472 ns                ;
; 1.353 ns                                ; 215.19 MHz ( period = 4.647 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.433 ns                ;
; 1.379 ns                                ; 216.40 MHz ( period = 4.621 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.408 ns                ;
; 1.387 ns                                ; 216.78 MHz ( period = 4.613 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.779 ns                  ; 4.392 ns                ;
; 1.387 ns                                ; 216.78 MHz ( period = 4.613 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.779 ns                  ; 4.392 ns                ;
; 1.390 ns                                ; 216.92 MHz ( period = 4.610 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.435 ns                ;
; 1.390 ns                                ; 216.92 MHz ( period = 4.610 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.435 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.404 ns                                ; 217.58 MHz ( period = 4.596 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.423 ns                ;
; 1.406 ns                                ; 217.68 MHz ( period = 4.594 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.380 ns                ;
; 1.413 ns                                ; 218.01 MHz ( period = 4.587 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.374 ns                ;
; 1.418 ns                                ; 218.25 MHz ( period = 4.582 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.369 ns                ;
; 1.424 ns                                ; 218.53 MHz ( period = 4.576 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.362 ns                ;
; 1.427 ns                                ; 218.67 MHz ( period = 4.573 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.359 ns                ;
; 1.450 ns                                ; 219.78 MHz ( period = 4.550 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.337 ns                ;
; 1.457 ns                                ; 220.12 MHz ( period = 4.543 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.330 ns                ;
; 1.470 ns                                ; 220.75 MHz ( period = 4.530 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.355 ns                ;
; 1.470 ns                                ; 220.75 MHz ( period = 4.530 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.355 ns                ;
; 1.471 ns                                ; 220.80 MHz ( period = 4.529 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.315 ns                ;
; 1.473 ns                                ; 220.90 MHz ( period = 4.527 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.313 ns                ;
; 1.477 ns                                ; 221.09 MHz ( period = 4.523 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.309 ns                ;
; 1.479 ns                                ; 221.19 MHz ( period = 4.521 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.307 ns                ;
; 1.479 ns                                ; 221.19 MHz ( period = 4.521 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.307 ns                ;
; 1.484 ns                                ; 221.43 MHz ( period = 4.516 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3]                               ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.774 ns                  ; 4.290 ns                ;
; 1.484 ns                                ; 221.43 MHz ( period = 4.516 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.303 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.338 ns                ;
; 1.489 ns                                ; 221.68 MHz ( period = 4.511 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.298 ns                ;
; 1.490 ns                                ; 221.73 MHz ( period = 4.510 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.296 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.291 ns                ;
; 1.496 ns                                ; 222.02 MHz ( period = 4.504 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.329 ns                ;
; 1.496 ns                                ; 222.02 MHz ( period = 4.504 ns )                    ; Sdram_Control_4Port:sdram1|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.779 ns                  ; 4.283 ns                ;
; 1.496 ns                                ; 222.02 MHz ( period = 4.504 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.329 ns                ;
; 1.496 ns                                ; 222.02 MHz ( period = 4.504 ns )                    ; Sdram_Control_4Port:sdram1|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.779 ns                  ; 4.283 ns                ;
; 1.498 ns                                ; 222.12 MHz ( period = 4.502 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.288 ns                ;
; 1.501 ns                                ; 222.27 MHz ( period = 4.499 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.285 ns                ;
; 1.508 ns                                ; 222.62 MHz ( period = 4.492 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.779 ns                  ; 4.271 ns                ;
; 1.508 ns                                ; 222.62 MHz ( period = 4.492 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.779 ns                  ; 4.271 ns                ;
; 1.511 ns                                ; 222.77 MHz ( period = 4.489 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.275 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.513 ns                                ; 222.87 MHz ( period = 4.487 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.314 ns                ;
; 1.517 ns                                ; 223.06 MHz ( period = 4.483 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.774 ns                  ; 4.257 ns                ;
; 1.521 ns                                ; 223.26 MHz ( period = 4.479 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.265 ns                ;
; 1.521 ns                                ; 223.26 MHz ( period = 4.479 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.266 ns                ;
; 1.526 ns                                ; 223.51 MHz ( period = 4.474 ns )                    ; Sdram_Control_4Port:sdram1|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.779 ns                  ; 4.253 ns                ;
; 1.526 ns                                ; 223.51 MHz ( period = 4.474 ns )                    ; Sdram_Control_4Port:sdram1|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.779 ns                  ; 4.253 ns                ;
; 1.528 ns                                ; 223.61 MHz ( period = 4.472 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.259 ns                ;
; 1.532 ns                                ; 223.81 MHz ( period = 4.468 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.293 ns                ;
; 1.532 ns                                ; 223.81 MHz ( period = 4.468 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.293 ns                ;
; 1.541 ns                                ; 224.27 MHz ( period = 4.459 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.245 ns                ;
; 1.542 ns                                ; 224.32 MHz ( period = 4.458 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.244 ns                ;
; 1.544 ns                                ; 224.42 MHz ( period = 4.456 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.242 ns                ;
; 1.546 ns                                ; 224.52 MHz ( period = 4.454 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.240 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.547 ns                                ; 224.57 MHz ( period = 4.453 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.781 ns                  ; 4.234 ns                ;
; 1.548 ns                                ; 224.62 MHz ( period = 4.452 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.238 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.277 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.236 ns                ;
; 1.550 ns                                ; 224.72 MHz ( period = 4.450 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.236 ns                ;
; 1.555 ns                                ; 224.97 MHz ( period = 4.445 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.232 ns                ;
; 1.560 ns                                ; 225.23 MHz ( period = 4.440 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.227 ns                ;
; 1.561 ns                                ; 225.28 MHz ( period = 4.439 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.225 ns                ;
; 1.561 ns                                ; 225.28 MHz ( period = 4.439 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.225 ns                ;
; 1.566 ns                                ; 225.53 MHz ( period = 4.434 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[4]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.259 ns                ;
; 1.566 ns                                ; 225.53 MHz ( period = 4.434 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[4]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.259 ns                ;
; 1.566 ns                                ; 225.53 MHz ( period = 4.434 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.220 ns                ;
; 1.566 ns                                ; 225.53 MHz ( period = 4.434 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.221 ns                ;
; 1.569 ns                                ; 225.68 MHz ( period = 4.431 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.217 ns                ;
; 1.572 ns                                ; 225.84 MHz ( period = 4.428 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.214 ns                ;
; 1.578 ns                                ; 226.14 MHz ( period = 4.422 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.209 ns                ;
; 1.580 ns                                ; 226.24 MHz ( period = 4.420 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.769 ns                  ; 4.189 ns                ;
; 1.580 ns                                ; 226.24 MHz ( period = 4.420 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.769 ns                  ; 4.189 ns                ;
; 1.580 ns                                ; 226.24 MHz ( period = 4.420 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.206 ns                ;
; 1.582 ns                                ; 226.35 MHz ( period = 4.418 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.204 ns                ;
; 1.586 ns                                ; 226.55 MHz ( period = 4.414 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|RD_MASK[0]                                                                                                                                                    ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.834 ns                  ; 4.248 ns                ;
; 1.589 ns                                ; 226.71 MHz ( period = 4.411 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.773 ns                  ; 4.184 ns                ;
; 1.592 ns                                ; 226.86 MHz ( period = 4.408 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.194 ns                ;
; 1.592 ns                                ; 226.86 MHz ( period = 4.408 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.195 ns                ;
; 1.593 ns                                ; 226.91 MHz ( period = 4.407 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.194 ns                ;
; 1.594 ns                                ; 226.96 MHz ( period = 4.406 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.193 ns                ;
; 1.599 ns                                ; 227.22 MHz ( period = 4.401 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.188 ns                ;
; 1.600 ns                                ; 227.27 MHz ( period = 4.400 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[4]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.225 ns                ;
; 1.600 ns                                ; 227.27 MHz ( period = 4.400 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[4]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.825 ns                  ; 4.225 ns                ;
; 1.612 ns                                ; 227.89 MHz ( period = 4.388 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.785 ns                  ; 4.173 ns                ;
; 1.612 ns                                ; 227.89 MHz ( period = 4.388 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.174 ns                ;
; 1.613 ns                                ; 227.95 MHz ( period = 4.387 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.173 ns                ;
; 1.615 ns                                ; 228.05 MHz ( period = 4.385 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.171 ns                ;
; 1.617 ns                                ; 228.15 MHz ( period = 4.383 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.169 ns                ;
; 1.619 ns                                ; 228.26 MHz ( period = 4.381 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.167 ns                ;
; 1.621 ns                                ; 228.36 MHz ( period = 4.379 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.165 ns                ;
; 1.621 ns                                ; 228.36 MHz ( period = 4.379 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.165 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_datain_reg8  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.768 ns                  ; 4.145 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_datain_reg7  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.768 ns                  ; 4.145 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_datain_reg6  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.768 ns                  ; 4.145 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_datain_reg5  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.768 ns                  ; 4.145 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_datain_reg4  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.768 ns                  ; 4.145 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_datain_reg3  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.768 ns                  ; 4.145 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_datain_reg2  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.768 ns                  ; 4.145 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_datain_reg1  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.768 ns                  ; 4.145 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_address_reg8 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.161 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_address_reg7 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.161 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_address_reg6 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.161 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_address_reg5 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.161 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_address_reg4 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.161 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_address_reg3 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.161 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_address_reg2 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.161 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_address_reg1 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.161 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_address_reg0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.161 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_datain_reg0  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.768 ns                  ; 4.145 ns                ;
; 1.623 ns                                ; Restricted to 210.08 MHz ( period = 4.76 ns )       ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~portb_we_reg       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.161 ns                ;
; 1.626 ns                                ; 228.62 MHz ( period = 4.374 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.161 ns                ;
; 1.629 ns                                ; 228.78 MHz ( period = 4.371 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.785 ns                  ; 4.156 ns                ;
; 1.630 ns                                ; 228.83 MHz ( period = 4.370 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.197 ns                ;
; 1.630 ns                                ; 228.83 MHz ( period = 4.370 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.197 ns                ;
; 1.630 ns                                ; 228.83 MHz ( period = 4.370 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.197 ns                ;
; 1.630 ns                                ; 228.83 MHz ( period = 4.370 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.197 ns                ;
; 1.630 ns                                ; 228.83 MHz ( period = 4.370 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.197 ns                ;
; 1.630 ns                                ; 228.83 MHz ( period = 4.370 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.827 ns                  ; 4.197 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                 ;                                                                                                                                                                                          ;                                                    ;                                                    ;                             ;                           ;                         ;
 


 
; Clock Setup: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
 
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                             ; To                                                                                                                                                                                       ; From Clock                                     ; To Clock                                       ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
 
; 10.156 ns                               ; 103.22 MHz ( period = 9.688 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; touch_tcon:vga0|oLCD_B[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 4.713 ns                ;
; 10.202 ns                               ; 104.21 MHz ( period = 9.596 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; touch_tcon:vga0|oLCD_B[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 4.667 ns                ;
; 10.670 ns                               ; 115.47 MHz ( period = 8.660 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; touch_tcon:vga0|oLCD_B[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.855 ns                 ; 4.185 ns                ;
; 10.706 ns                               ; 116.44 MHz ( period = 8.588 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; touch_tcon:vga0|oLCD_B[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.847 ns                 ; 4.141 ns                ;
; 10.789 ns                               ; 118.74 MHz ( period = 8.422 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; touch_tcon:vga0|oLCD_B[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.847 ns                 ; 4.058 ns                ;
; 10.834 ns                               ; 120.02 MHz ( period = 8.332 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; touch_tcon:vga0|oLCD_B[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.833 ns                 ; 3.999 ns                ;
; 10.869 ns                               ; 121.04 MHz ( period = 8.262 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_R[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 4.000 ns                ;
; 10.910 ns                               ; 122.25 MHz ( period = 8.180 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.834 ns                ;
; 10.981 ns                               ; 124.41 MHz ( period = 8.038 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.763 ns                ;
; 11.052 ns                               ; 126.65 MHz ( period = 7.896 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.692 ns                ;
; 11.056 ns                               ; 126.77 MHz ( period = 7.888 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; touch_tcon:vga0|oLCD_B[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 3.813 ns                ;
; 11.059 ns                               ; 126.87 MHz ( period = 7.882 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_B[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 3.810 ns                ;
; 11.123 ns                               ; 128.97 MHz ( period = 7.754 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.621 ns                ;
; 11.165 ns                               ; 130.38 MHz ( period = 7.670 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.757 ns                 ; 3.592 ns                ;
; 11.165 ns                               ; 130.38 MHz ( period = 7.670 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.757 ns                 ; 3.592 ns                ;
; 11.194 ns                               ; 131.37 MHz ( period = 7.612 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.550 ns                ;
; 11.213 ns                               ; 132.03 MHz ( period = 7.574 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; touch_tcon:vga0|oLCD_R[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.849 ns                 ; 3.636 ns                ;
; 11.242 ns                               ; 133.05 MHz ( period = 7.516 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; touch_tcon:vga0|oLCD_R[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.862 ns                 ; 3.620 ns                ;
; 11.353 ns                               ; 137.10 MHz ( period = 7.294 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.391 ns                ;
; 11.378 ns                               ; 138.05 MHz ( period = 7.244 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; touch_tcon:vga0|oLCD_R[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 3.491 ns                ;
; 11.402 ns                               ; 138.97 MHz ( period = 7.196 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 3.340 ns                ;
; 11.402 ns                               ; 138.97 MHz ( period = 7.196 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 3.340 ns                ;
; 11.402 ns                               ; 138.97 MHz ( period = 7.196 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 3.340 ns                ;
; 11.414 ns                               ; 139.43 MHz ( period = 7.172 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; touch_tcon:vga0|oLCD_R[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.849 ns                 ; 3.435 ns                ;
; 11.424 ns                               ; 139.82 MHz ( period = 7.152 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.320 ns                ;
; 11.475 ns                               ; 141.84 MHz ( period = 7.050 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 3.290 ns                ;
; 11.495 ns                               ; 142.65 MHz ( period = 7.010 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.249 ns                ;
; 11.503 ns                               ; 142.98 MHz ( period = 6.994 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; touch_tcon:vga0|oLCD_R[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.849 ns                 ; 3.346 ns                ;
; 11.525 ns                               ; 143.88 MHz ( period = 6.950 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.716 ns                 ; 3.191 ns                ;
; 11.525 ns                               ; 143.88 MHz ( period = 6.950 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.716 ns                 ; 3.191 ns                ;
; 11.525 ns                               ; 143.88 MHz ( period = 6.950 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.716 ns                 ; 3.191 ns                ;
; 11.525 ns                               ; 143.88 MHz ( period = 6.950 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.716 ns                 ; 3.191 ns                ;
; 11.527 ns                               ; 143.97 MHz ( period = 6.946 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.702 ns                 ; 3.175 ns                ;
; 11.527 ns                               ; 143.97 MHz ( period = 6.946 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.702 ns                 ; 3.175 ns                ;
; 11.527 ns                               ; 143.97 MHz ( period = 6.946 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.702 ns                 ; 3.175 ns                ;
; 11.527 ns                               ; 143.97 MHz ( period = 6.946 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.702 ns                 ; 3.175 ns                ;
; 11.527 ns                               ; 143.97 MHz ( period = 6.946 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.702 ns                 ; 3.175 ns                ;
; 11.527 ns                               ; 143.97 MHz ( period = 6.946 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.702 ns                 ; 3.175 ns                ;
; 11.527 ns                               ; 143.97 MHz ( period = 6.946 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.702 ns                 ; 3.175 ns                ;
; 11.527 ns                               ; 143.97 MHz ( period = 6.946 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.702 ns                 ; 3.175 ns                ;
; 11.527 ns                               ; 143.97 MHz ( period = 6.946 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.702 ns                 ; 3.175 ns                ;
; 11.529 ns                               ; 144.05 MHz ( period = 6.942 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; touch_tcon:vga0|oLCD_R[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.846 ns                 ; 3.317 ns                ;
; 11.542 ns                               ; 144.59 MHz ( period = 6.916 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_B[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.855 ns                 ; 3.313 ns                ;
; 11.546 ns                               ; 144.76 MHz ( period = 6.908 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 3.219 ns                ;
; 11.566 ns                               ; 145.60 MHz ( period = 6.868 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; touch_tcon:vga0|oLCD_B[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 3.303 ns                ;
; 11.566 ns                               ; 145.60 MHz ( period = 6.868 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.178 ns                ;
; 11.617 ns                               ; 147.80 MHz ( period = 6.766 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 3.148 ns                ;
; 11.631 ns                               ; 148.41 MHz ( period = 6.738 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.758 ns                 ; 3.127 ns                ;
; 11.631 ns                               ; 148.41 MHz ( period = 6.738 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.758 ns                 ; 3.127 ns                ;
; 11.637 ns                               ; 148.68 MHz ( period = 6.726 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.107 ns                ;
; 11.637 ns                               ; 148.68 MHz ( period = 6.726 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.107 ns                ;
; 11.637 ns                               ; 148.68 MHz ( period = 6.726 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.107 ns                ;
; 11.637 ns                               ; 148.68 MHz ( period = 6.726 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 3.107 ns                ;
; 11.663 ns                               ; 149.84 MHz ( period = 6.674 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; touch_tcon:vga0|oLCD_B[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.847 ns                 ; 3.184 ns                ;
; 11.677 ns                               ; 150.47 MHz ( period = 6.646 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; touch_tcon:vga0|oLCD_R[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.866 ns                 ; 3.189 ns                ;
; 11.683 ns                               ; 150.74 MHz ( period = 6.634 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_B[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.833 ns                 ; 3.150 ns                ;
; 11.688 ns                               ; 150.97 MHz ( period = 6.624 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 3.077 ns                ;
; 11.713 ns                               ; 152.11 MHz ( period = 6.574 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_R[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.855 ns                 ; 3.142 ns                ;
; 11.755 ns                               ; 154.08 MHz ( period = 6.490 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; touch_tcon:vga0|oLCD_R[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.827 ns                 ; 3.072 ns                ;
; 11.759 ns                               ; 154.27 MHz ( period = 6.482 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_G[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.866 ns                 ; 3.107 ns                ;
; 11.759 ns                               ; 154.27 MHz ( period = 6.482 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 3.006 ns                ;
; 11.798 ns                               ; 156.15 MHz ( period = 6.404 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.944 ns                ;
; 11.798 ns                               ; 156.15 MHz ( period = 6.404 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.944 ns                ;
; 11.798 ns                               ; 156.15 MHz ( period = 6.404 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.944 ns                ;
; 11.798 ns                               ; 156.15 MHz ( period = 6.404 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.944 ns                ;
; 11.798 ns                               ; 156.15 MHz ( period = 6.404 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.944 ns                ;
; 11.798 ns                               ; 156.15 MHz ( period = 6.404 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.944 ns                ;
; 11.798 ns                               ; 156.15 MHz ( period = 6.404 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.944 ns                ;
; 11.798 ns                               ; 156.15 MHz ( period = 6.404 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.944 ns                ;
; 11.798 ns                               ; 156.15 MHz ( period = 6.404 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.944 ns                ;
; 11.807 ns                               ; 156.59 MHz ( period = 6.386 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.728 ns                 ; 2.921 ns                ;
; 11.807 ns                               ; 156.59 MHz ( period = 6.386 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.728 ns                 ; 2.921 ns                ;
; 11.807 ns                               ; 156.59 MHz ( period = 6.386 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.728 ns                 ; 2.921 ns                ;
; 11.807 ns                               ; 156.59 MHz ( period = 6.386 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.728 ns                 ; 2.921 ns                ;
; 11.807 ns                               ; 156.59 MHz ( period = 6.386 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.728 ns                 ; 2.921 ns                ;
; 11.807 ns                               ; 156.59 MHz ( period = 6.386 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.728 ns                 ; 2.921 ns                ;
; 11.807 ns                               ; 156.59 MHz ( period = 6.386 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.728 ns                 ; 2.921 ns                ;
; 11.807 ns                               ; 156.59 MHz ( period = 6.386 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.728 ns                 ; 2.921 ns                ;
; 11.807 ns                               ; 156.59 MHz ( period = 6.386 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.728 ns                 ; 2.921 ns                ;
; 11.827 ns                               ; 157.58 MHz ( period = 6.346 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_R[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.833 ns                 ; 3.006 ns                ;
; 11.830 ns                               ; 157.73 MHz ( period = 6.340 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~porta_datain_reg1                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.821 ns                 ; 2.991 ns                ;
; 11.830 ns                               ; 157.73 MHz ( period = 6.340 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 2.935 ns                ;
; 11.855 ns                               ; 158.98 MHz ( period = 6.290 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.753 ns                 ; 2.898 ns                ;
; 11.855 ns                               ; 158.98 MHz ( period = 6.290 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.753 ns                 ; 2.898 ns                ;
; 11.855 ns                               ; 158.98 MHz ( period = 6.290 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.753 ns                 ; 2.898 ns                ;
; 11.855 ns                               ; 158.98 MHz ( period = 6.290 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.753 ns                 ; 2.898 ns                ;
; 11.855 ns                               ; 158.98 MHz ( period = 6.290 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.753 ns                 ; 2.898 ns                ;
; 11.855 ns                               ; 158.98 MHz ( period = 6.290 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.753 ns                 ; 2.898 ns                ;
; 11.855 ns                               ; 158.98 MHz ( period = 6.290 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.753 ns                 ; 2.898 ns                ;
; 11.855 ns                               ; 158.98 MHz ( period = 6.290 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.753 ns                 ; 2.898 ns                ;
; 11.855 ns                               ; 158.98 MHz ( period = 6.290 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.753 ns                 ; 2.898 ns                ;
; 11.855 ns                               ; 158.98 MHz ( period = 6.290 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.753 ns                 ; 2.898 ns                ;
; 11.890 ns                               ; 160.77 MHz ( period = 6.220 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; touch_tcon:vga0|oLCD_G[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 2.979 ns                ;
; 11.901 ns                               ; 161.34 MHz ( period = 6.198 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 2.864 ns                ;
; 11.985 ns                               ; 165.84 MHz ( period = 6.030 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_R[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.849 ns                 ; 2.864 ns                ;
; 12.000 ns                               ; 166.67 MHz ( period = 6.000 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_B[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.849 ns                 ; 2.849 ns                ;
; 12.024 ns                               ; 168.01 MHz ( period = 5.952 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.744 ns                 ; 2.720 ns                ;
; 12.032 ns                               ; 168.46 MHz ( period = 5.936 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~porta_datain_reg3                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.807 ns                 ; 2.775 ns                ;
; 12.038 ns                               ; 168.80 MHz ( period = 5.924 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; touch_tcon:vga0|oLCD_B[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.847 ns                 ; 2.809 ns                ;
; 12.049 ns                               ; 169.43 MHz ( period = 5.902 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.709 ns                 ; 2.660 ns                ;
; 12.049 ns                               ; 169.43 MHz ( period = 5.902 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.709 ns                 ; 2.660 ns                ;
; 12.060 ns                               ; 170.07 MHz ( period = 5.880 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 2.705 ns                ;
; 12.100 ns                               ; 172.41 MHz ( period = 5.800 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; touch_tcon:vga0|oLCD_R[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.827 ns                 ; 2.727 ns                ;
; 12.131 ns                               ; 174.28 MHz ( period = 5.738 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 2.634 ns                ;
; 12.209 ns                               ; 179.15 MHz ( period = 5.582 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~porta_datain_reg2                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.807 ns                 ; 2.598 ns                ;
; 12.222 ns                               ; 179.99 MHz ( period = 5.556 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_B[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.827 ns                 ; 2.605 ns                ;
; 12.246 ns                               ; 181.55 MHz ( period = 5.508 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; touch_tcon:vga0|oLCD_R[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.840 ns                 ; 2.594 ns                ;
; 12.273 ns                               ; 183.35 MHz ( period = 5.454 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~porta_datain_reg0                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.821 ns                 ; 2.548 ns                ;
; 12.290 ns                               ; 184.50 MHz ( period = 5.420 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 2.475 ns                ;
; 12.331 ns                               ; 187.34 MHz ( period = 5.338 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_R[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.827 ns                 ; 2.496 ns                ;
; 12.336 ns                               ; 187.69 MHz ( period = 5.328 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_G[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.833 ns                 ; 2.497 ns                ;
; 12.347 ns                               ; 188.47 MHz ( period = 5.306 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.722 ns                 ; 2.375 ns                ;
; 12.347 ns                               ; 188.47 MHz ( period = 5.306 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.722 ns                 ; 2.375 ns                ;
; 12.347 ns                               ; 188.47 MHz ( period = 5.306 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.722 ns                 ; 2.375 ns                ;
; 12.347 ns                               ; 188.47 MHz ( period = 5.306 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.722 ns                 ; 2.375 ns                ;
; 12.347 ns                               ; 188.47 MHz ( period = 5.306 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.722 ns                 ; 2.375 ns                ;
; 12.347 ns                               ; 188.47 MHz ( period = 5.306 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.722 ns                 ; 2.375 ns                ;
; 12.347 ns                               ; 188.47 MHz ( period = 5.306 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.722 ns                 ; 2.375 ns                ;
; 12.347 ns                               ; 188.47 MHz ( period = 5.306 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.722 ns                 ; 2.375 ns                ;
; 12.347 ns                               ; 188.47 MHz ( period = 5.306 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.722 ns                 ; 2.375 ns                ;
; 12.380 ns                               ; 190.84 MHz ( period = 5.240 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_G[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.855 ns                 ; 2.475 ns                ;
; 12.480 ns                               ; 198.41 MHz ( period = 5.040 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.735 ns                 ; 2.255 ns                ;
; 12.480 ns                               ; 198.41 MHz ( period = 5.040 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.735 ns                 ; 2.255 ns                ;
; 12.480 ns                               ; 198.41 MHz ( period = 5.040 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.735 ns                 ; 2.255 ns                ;
; 12.480 ns                               ; 198.41 MHz ( period = 5.040 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.735 ns                 ; 2.255 ns                ;
; 12.480 ns                               ; 198.41 MHz ( period = 5.040 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.735 ns                 ; 2.255 ns                ;
; 12.480 ns                               ; 198.41 MHz ( period = 5.040 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.735 ns                 ; 2.255 ns                ;
; 12.480 ns                               ; 198.41 MHz ( period = 5.040 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.735 ns                 ; 2.255 ns                ;
; 12.480 ns                               ; 198.41 MHz ( period = 5.040 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.735 ns                 ; 2.255 ns                ;
; 12.480 ns                               ; 198.41 MHz ( period = 5.040 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.735 ns                 ; 2.255 ns                ;
; 12.481 ns                               ; 198.49 MHz ( period = 5.038 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_R[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.827 ns                 ; 2.346 ns                ;
; 12.510 ns                               ; 200.80 MHz ( period = 4.980 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_B[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.827 ns                 ; 2.317 ns                ;
; 12.660 ns                               ; 213.68 MHz ( period = 4.680 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; touch_tcon:vga0|oLCD_G[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.844 ns                 ; 2.184 ns                ;
; 12.677 ns                               ; 215.24 MHz ( period = 4.646 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.765 ns                 ; 2.088 ns                ;
; 12.784 ns                               ; 225.63 MHz ( period = 4.432 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.748 ns                 ; 1.964 ns                ;
; 12.784 ns                               ; 225.63 MHz ( period = 4.432 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.748 ns                 ; 1.964 ns                ;
; 12.784 ns                               ; 225.63 MHz ( period = 4.432 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.748 ns                 ; 1.964 ns                ;
; 12.784 ns                               ; 225.63 MHz ( period = 4.432 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.748 ns                 ; 1.964 ns                ;
; 12.784 ns                               ; 225.63 MHz ( period = 4.432 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.748 ns                 ; 1.964 ns                ;
; 12.784 ns                               ; 225.63 MHz ( period = 4.432 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.748 ns                 ; 1.964 ns                ;
; 12.784 ns                               ; 225.63 MHz ( period = 4.432 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.748 ns                 ; 1.964 ns                ;
; 12.784 ns                               ; 225.63 MHz ( period = 4.432 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.748 ns                 ; 1.964 ns                ;
; 12.784 ns                               ; 225.63 MHz ( period = 4.432 ns )                    ; Sobel:sobel0|oDVAL                                                                                                                                               ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.748 ns                 ; 1.964 ns                ;
; 12.821 ns                               ; 229.46 MHz ( period = 4.358 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a0~porta_datain_reg3                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.812 ns                 ; 1.991 ns                ;
; 12.845 ns                               ; 232.02 MHz ( period = 4.310 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_G[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.846 ns                 ; 2.001 ns                ;
; 13.147 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_G[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.827 ns                 ; 1.680 ns                ;
; 13.215 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_G[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.824 ns                 ; 1.609 ns                ;
; 13.291 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a0~porta_datain_reg0                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.792 ns                 ; 1.501 ns                ;
; 13.570 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a0~porta_datain_reg2                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.792 ns                 ; 1.222 ns                ;
; 13.660 ns                               ; 61.20 MHz ( period = 16.340 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][0]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 16.140 ns               ;
; 13.706 ns                               ; 61.37 MHz ( period = 16.294 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:b_dffe[11]|sr[0][0]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 16.094 ns               ;
; 13.740 ns                               ; 61.50 MHz ( period = 16.260 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[1][6]                                                                                       ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 16.058 ns               ;
; 13.746 ns                               ; 61.52 MHz ( period = 16.254 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:b_dffe[11]|sr[0][1]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 16.054 ns               ;
; 13.758 ns                               ; 61.57 MHz ( period = 16.242 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][1]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 16.042 ns               ;
; 13.782 ns                               ; 61.66 MHz ( period = 16.218 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][5]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.802 ns                 ; 16.020 ns               ;
; 13.801 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a0~porta_datain_reg1                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.792 ns                 ; 0.991 ns                ;
; 13.806 ns                               ; 61.75 MHz ( period = 16.194 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][2]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 15.994 ns               ;
; 13.819 ns                               ; 61.80 MHz ( period = 16.181 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[1][7]                                                                                       ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 15.979 ns               ;
; 13.873 ns                               ; 62.01 MHz ( period = 16.127 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:b_dffe[11]|sr[0][2]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.796 ns                 ; 15.923 ns               ;
; 13.896 ns                               ; 62.10 MHz ( period = 16.104 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:b_dffe[11]|sr[0][3]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.796 ns                 ; 15.900 ns               ;
; 13.919 ns                               ; 62.19 MHz ( period = 16.081 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][3]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 15.881 ns               ;
; 13.949 ns                               ; 62.30 MHz ( period = 16.051 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][4]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 15.851 ns               ;
; 14.008 ns                               ; 62.53 MHz ( period = 15.992 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:b_dffe[11]|sr[0][4]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.796 ns                 ; 15.788 ns               ;
; 14.048 ns                               ; 62.69 MHz ( period = 15.952 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:b_dffe[11]|sr[0][5]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.796 ns                 ; 15.748 ns               ;
; 14.201 ns                               ; 63.30 MHz ( period = 15.799 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][6]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 15.599 ns               ;
; 14.273 ns                               ; 63.58 MHz ( period = 15.727 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][7]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 15.527 ns               ;
; 14.359 ns                               ; 63.93 MHz ( period = 15.641 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][8]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 15.441 ns               ;
; 14.424 ns                               ; 64.20 MHz ( period = 15.576 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][9]                                                                                    ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 15.376 ns               ;
; 14.457 ns                               ; 64.34 MHz ( period = 15.543 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][10]                                                                                   ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 15.343 ns               ;
; 14.569 ns                               ; 64.80 MHz ( period = 15.431 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][11]                                                                                   ; Sobel:sobel0|oDATA[9]                                                                                                                                                                    ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.800 ns                 ; 15.231 ns               ;
; 14.858 ns                               ; 66.04 MHz ( period = 15.142 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][3]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.940 ns               ;
; 14.858 ns                               ; 66.04 MHz ( period = 15.142 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][4]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.940 ns               ;
; 14.858 ns                               ; 66.04 MHz ( period = 15.142 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][6]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.940 ns               ;
; 14.858 ns                               ; 66.04 MHz ( period = 15.142 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][7]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.940 ns               ;
; 14.858 ns                               ; 66.04 MHz ( period = 15.142 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][8]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.940 ns               ;
; 14.858 ns                               ; 66.04 MHz ( period = 15.142 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][9]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.940 ns               ;
; 14.858 ns                               ; 66.04 MHz ( period = 15.142 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][10]                                                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.940 ns               ;
; 14.858 ns                               ; 66.04 MHz ( period = 15.142 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][11]                                                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.940 ns               ;
; 14.961 ns                               ; 66.49 MHz ( period = 15.039 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][2]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.837 ns               ;
; 14.973 ns                               ; 66.55 MHz ( period = 15.027 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][3]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.825 ns               ;
; 14.973 ns                               ; 66.55 MHz ( period = 15.027 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][4]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.825 ns               ;
; 14.973 ns                               ; 66.55 MHz ( period = 15.027 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][6]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.825 ns               ;
; 14.973 ns                               ; 66.55 MHz ( period = 15.027 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][7]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.825 ns               ;
; 14.973 ns                               ; 66.55 MHz ( period = 15.027 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][8]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.825 ns               ;
; 14.973 ns                               ; 66.55 MHz ( period = 15.027 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][9]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.825 ns               ;
; 14.973 ns                               ; 66.55 MHz ( period = 15.027 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][10]                                                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.825 ns               ;
; 14.973 ns                               ; 66.55 MHz ( period = 15.027 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][11]                                                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.825 ns               ;
; 15.076 ns                               ; 67.01 MHz ( period = 14.924 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][2]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.722 ns               ;
; 15.108 ns                               ; 67.15 MHz ( period = 14.892 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][5]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.796 ns                 ; 14.688 ns               ;
; 15.133 ns                               ; 67.26 MHz ( period = 14.867 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:b_dffe[11]|sr[0][0]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.665 ns               ;
; 15.136 ns                               ; 67.28 MHz ( period = 14.864 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][1]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.662 ns               ;
; 15.137 ns                               ; 67.28 MHz ( period = 14.863 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][19]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][0]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.661 ns               ;
; 15.223 ns                               ; 67.67 MHz ( period = 14.777 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][5]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.796 ns                 ; 14.573 ns               ;
; 15.248 ns                               ; 67.79 MHz ( period = 14.752 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:b_dffe[11]|sr[0][0]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.550 ns               ;
; 15.251 ns                               ; 67.80 MHz ( period = 14.749 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][1]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.547 ns               ;
; 15.252 ns                               ; 67.81 MHz ( period = 14.748 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][18]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][0]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.546 ns               ;
; 15.410 ns                               ; 68.54 MHz ( period = 14.590 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][16]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][3]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.388 ns               ;
; 15.410 ns                               ; 68.54 MHz ( period = 14.590 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][16]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][4]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.388 ns               ;
; 15.410 ns                               ; 68.54 MHz ( period = 14.590 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][16]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][6]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.388 ns               ;
; 15.410 ns                               ; 68.54 MHz ( period = 14.590 ns )                    ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][16]                                                                                      ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:r_dffe[11]|sr[0][7]                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.798 ns                 ; 14.388 ns               ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                  ;                                                                                                                                                                                          ;                                                ;                                                ;                             ;                           ;                         ;
 


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'GPIO_CLKIN_N1'                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------+---------------+---------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                ; To                      ; From Clock    ; To Clock      ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------+---------------+---------------+-----------------------------+---------------------------+-------------------------+
; 2.038 ns                                ; 141.80 MHz ( period = 7.052 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.853 ns                ;
; 2.079 ns                                ; 142.63 MHz ( period = 7.011 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.812 ns                ;
; 2.150 ns                                ; 144.09 MHz ( period = 6.940 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.741 ns                ;
; 2.169 ns                                ; 144.49 MHz ( period = 6.921 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.722 ns                ;
; 2.196 ns                                ; 145.05 MHz ( period = 6.894 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.702 ns                ;
; 2.216 ns                                ; 145.48 MHz ( period = 6.874 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.675 ns                ;
; 2.234 ns                                ; 145.86 MHz ( period = 6.856 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.664 ns                ;
; 2.237 ns                                ; 145.92 MHz ( period = 6.853 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.661 ns                ;
; 2.254 ns                                ; 146.28 MHz ( period = 6.836 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.637 ns                ;
; 2.275 ns                                ; 146.74 MHz ( period = 6.815 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.623 ns                ;
; 2.302 ns                                ; 147.32 MHz ( period = 6.788 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.589 ns                ;
; 2.308 ns                                ; 147.45 MHz ( period = 6.782 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.590 ns                ;
; 2.327 ns                                ; 147.86 MHz ( period = 6.763 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.571 ns                ;
; 2.346 ns                                ; 148.28 MHz ( period = 6.744 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.551 ns                ;
; 2.346 ns                                ; 148.28 MHz ( period = 6.744 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.552 ns                ;
; 2.355 ns                                ; 148.48 MHz ( period = 6.735 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.543 ns                ;
; 2.365 ns                                ; 148.70 MHz ( period = 6.725 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.526 ns                ;
; 2.365 ns                                ; 148.70 MHz ( period = 6.725 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.533 ns                ;
; 2.366 ns                                ; 148.72 MHz ( period = 6.724 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.526 ns                ;
; 2.374 ns                                ; 148.90 MHz ( period = 6.716 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.524 ns                ;
; 2.384 ns                                ; 149.12 MHz ( period = 6.706 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.514 ns                ;
; 2.387 ns                                ; 149.19 MHz ( period = 6.703 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.510 ns                ;
; 2.396 ns                                ; 149.39 MHz ( period = 6.694 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.502 ns                ;
; 2.407 ns                                ; 149.63 MHz ( period = 6.683 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.485 ns                ;
; 2.411 ns                                ; 149.72 MHz ( period = 6.679 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.473 ns                ;
; 2.412 ns                                ; 149.75 MHz ( period = 6.678 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.486 ns                ;
; 2.412 ns                                ; 149.75 MHz ( period = 6.678 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.486 ns                ;
; 2.416 ns                                ; 149.84 MHz ( period = 6.674 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.475 ns                ;
; 2.425 ns                                ; 150.04 MHz ( period = 6.665 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.466 ns                ;
; 2.425 ns                                ; 150.04 MHz ( period = 6.665 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.473 ns                ;
; 2.448 ns                                ; 150.56 MHz ( period = 6.642 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.443 ns                ;
; 2.450 ns                                ; 150.60 MHz ( period = 6.640 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.448 ns                ;
; 2.452 ns                                ; 150.65 MHz ( period = 6.638 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.432 ns                ;
; 2.455 ns                                ; 150.72 MHz ( period = 6.635 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.436 ns                ;
; 2.458 ns                                ; 150.78 MHz ( period = 6.632 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.439 ns                ;
; 2.460 ns                                ; 150.83 MHz ( period = 6.630 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.438 ns                ;
; 2.466 ns                                ; 150.97 MHz ( period = 6.624 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.425 ns                ;
; 2.467 ns                                ; 150.99 MHz ( period = 6.623 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.431 ns                ;
; 2.477 ns                                ; 151.22 MHz ( period = 6.613 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.420 ns                ;
; 2.478 ns                                ; 151.24 MHz ( period = 6.612 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.414 ns                ;
; 2.486 ns                                ; 151.42 MHz ( period = 6.604 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.412 ns                ;
; 2.496 ns                                ; 151.65 MHz ( period = 6.594 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.402 ns                ;
; 2.497 ns                                ; 151.68 MHz ( period = 6.593 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.395 ns                ;
; 2.498 ns                                ; 151.70 MHz ( period = 6.592 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.400 ns                ;
; 2.507 ns                                ; 151.91 MHz ( period = 6.583 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.390 ns                ;
; 2.515 ns                                ; 152.09 MHz ( period = 6.575 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.383 ns                ;
; 2.523 ns                                ; 152.28 MHz ( period = 6.567 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.361 ns                ;
; 2.523 ns                                ; 152.28 MHz ( period = 6.567 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.375 ns                ;
; 2.524 ns                                ; 152.30 MHz ( period = 6.566 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.373 ns                ;
; 2.533 ns                                ; 152.51 MHz ( period = 6.557 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.365 ns                ;
; 2.539 ns                                ; 152.65 MHz ( period = 6.551 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.358 ns                ;
; 2.542 ns                                ; 152.72 MHz ( period = 6.548 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.342 ns                ;
; 2.544 ns                                ; 152.77 MHz ( period = 6.546 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.348 ns                ;
; 2.548 ns                                ; 152.86 MHz ( period = 6.542 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.349 ns                ;
; 2.561 ns                                ; 153.16 MHz ( period = 6.529 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.337 ns                ;
; 2.562 ns                                ; 153.19 MHz ( period = 6.528 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.335 ns                ;
; 2.562 ns                                ; 153.19 MHz ( period = 6.528 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.336 ns                ;
; 2.571 ns                                ; 153.40 MHz ( period = 6.519 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.327 ns                ;
; 2.574 ns                                ; 153.47 MHz ( period = 6.516 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.324 ns                ;
; 2.580 ns                                ; 153.61 MHz ( period = 6.510 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.317 ns                ;
; 2.582 ns                                ; 153.66 MHz ( period = 6.508 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.310 ns                ;
; 2.583 ns                                ; 153.68 MHz ( period = 6.507 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.315 ns                ;
; 2.588 ns                                ; 153.80 MHz ( period = 6.502 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.303 ns                ;
; 2.589 ns                                ; 153.82 MHz ( period = 6.501 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.295 ns                ;
; 2.590 ns                                ; 153.85 MHz ( period = 6.500 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.294 ns                ;
; 2.600 ns                                ; 154.08 MHz ( period = 6.490 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.298 ns                ;
; 2.606 ns                                ; 154.23 MHz ( period = 6.484 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.292 ns                ;
; 2.610 ns                                ; 154.32 MHz ( period = 6.480 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.287 ns                ;
; 2.611 ns                                ; 154.34 MHz ( period = 6.479 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.280 ns                ;
; 2.612 ns                                ; 154.37 MHz ( period = 6.478 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.286 ns                ;
; 2.613 ns                                ; 154.39 MHz ( period = 6.477 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.285 ns                ;
; 2.619 ns                                ; 154.54 MHz ( period = 6.471 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.279 ns                ;
; 2.619 ns                                ; 154.54 MHz ( period = 6.471 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.278 ns                ;
; 2.621 ns                                ; 154.58 MHz ( period = 6.469 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.277 ns                ;
; 2.624 ns                                ; 154.66 MHz ( period = 6.466 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.274 ns                ;
; 2.627 ns                                ; 154.73 MHz ( period = 6.463 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.257 ns                ;
; 2.630 ns                                ; 154.80 MHz ( period = 6.460 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.262 ns                ;
; 2.631 ns                                ; 154.82 MHz ( period = 6.459 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.253 ns                ;
; 2.638 ns                                ; 154.99 MHz ( period = 6.452 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.259 ns                ;
; 2.644 ns                                ; 155.13 MHz ( period = 6.446 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.254 ns                ;
; 2.648 ns                                ; 155.23 MHz ( period = 6.442 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.250 ns                ;
; 2.651 ns                                ; 155.30 MHz ( period = 6.439 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.246 ns                ;
; 2.651 ns                                ; 155.30 MHz ( period = 6.439 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.247 ns                ;
; 2.662 ns                                ; 155.57 MHz ( period = 6.428 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.236 ns                ;
; 2.670 ns                                ; 155.76 MHz ( period = 6.420 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.227 ns                ;
; 2.673 ns                                ; 155.84 MHz ( period = 6.417 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.224 ns                ;
; 2.675 ns                                ; 155.88 MHz ( period = 6.415 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.209 ns                ;
; 2.682 ns                                ; 156.05 MHz ( period = 6.408 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.216 ns                ;
; 2.685 ns                                ; 156.13 MHz ( period = 6.405 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.212 ns                ;
; 2.693 ns                                ; 156.32 MHz ( period = 6.397 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.199 ns                ;
; 2.702 ns                                ; 156.54 MHz ( period = 6.388 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.182 ns                ;
; 2.711 ns                                ; 156.76 MHz ( period = 6.379 ns )                    ; CCD_Capture:capture0|Y_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.180 ns                ;
; 2.711 ns                                ; 156.76 MHz ( period = 6.379 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.187 ns                ;
; 2.717 ns                                ; 156.91 MHz ( period = 6.373 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.180 ns                ;
; 2.721 ns                                ; 157.01 MHz ( period = 6.369 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.163 ns                ;
; 2.723 ns                                ; 157.06 MHz ( period = 6.367 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.174 ns                ;
; 2.724 ns                                ; 157.08 MHz ( period = 6.366 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.173 ns                ;
; 2.733 ns                                ; 157.31 MHz ( period = 6.357 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.164 ns                ;
; 2.733 ns                                ; 157.31 MHz ( period = 6.357 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.165 ns                ;
; 2.735 ns                                ; 157.36 MHz ( period = 6.355 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.149 ns                ;
; 2.738 ns                                ; 157.43 MHz ( period = 6.352 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.146 ns                ;
; 2.742 ns                                ; 157.53 MHz ( period = 6.348 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.156 ns                ;
; 2.744 ns                                ; 157.58 MHz ( period = 6.346 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.148 ns                ;
; 2.746 ns                                ; 157.63 MHz ( period = 6.344 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.152 ns                ;
; 2.749 ns                                ; 157.70 MHz ( period = 6.341 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[10]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.902 ns                  ; 6.153 ns                ;
; 2.753 ns                                ; 157.80 MHz ( period = 6.337 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.139 ns                ;
; 2.755 ns                                ; 157.85 MHz ( period = 6.335 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.142 ns                ;
; 2.756 ns                                ; 157.88 MHz ( period = 6.334 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.141 ns                ;
; 2.759 ns                                ; 157.95 MHz ( period = 6.331 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[5]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.125 ns                ;
; 2.761 ns                                ; 158.00 MHz ( period = 6.329 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[7]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.130 ns                ;
; 2.762 ns                                ; 158.03 MHz ( period = 6.328 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.136 ns                ;
; 2.763 ns                                ; 158.05 MHz ( period = 6.327 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.134 ns                ;
; 2.765 ns                                ; 158.10 MHz ( period = 6.325 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.133 ns                ;
; 2.768 ns                                ; 158.18 MHz ( period = 6.322 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.116 ns                ;
; 2.769 ns                                ; 158.20 MHz ( period = 6.321 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.129 ns                ;
; 2.771 ns                                ; 158.25 MHz ( period = 6.319 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.126 ns                ;
; 2.771 ns                                ; 158.25 MHz ( period = 6.319 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.127 ns                ;
; 2.772 ns                                ; 158.28 MHz ( period = 6.318 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.126 ns                ;
; 2.774 ns                                ; 158.33 MHz ( period = 6.316 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.123 ns                ;
; 2.776 ns                                ; 158.38 MHz ( period = 6.314 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.108 ns                ;
; 2.776 ns                                ; 158.38 MHz ( period = 6.314 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.116 ns                ;
; 2.783 ns                                ; 158.55 MHz ( period = 6.307 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.109 ns                ;
; 2.783 ns                                ; 158.55 MHz ( period = 6.307 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.115 ns                ;
; 2.784 ns                                ; 158.58 MHz ( period = 6.306 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.114 ns                ;
; 2.789 ns                                ; 158.70 MHz ( period = 6.301 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.095 ns                ;
; 2.790 ns                                ; 158.73 MHz ( period = 6.300 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rRed[10]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.902 ns                  ; 6.112 ns                ;
; 2.794 ns                                ; 158.83 MHz ( period = 6.296 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 6.098 ns                ;
; 2.794 ns                                ; 158.83 MHz ( period = 6.296 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.104 ns                ;
; 2.798 ns                                ; 158.93 MHz ( period = 6.292 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.086 ns                ;
; 2.800 ns                                ; 158.98 MHz ( period = 6.290 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rRed[5]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.084 ns                ;
; 2.801 ns                                ; 159.01 MHz ( period = 6.289 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.097 ns                ;
; 2.802 ns                                ; 159.03 MHz ( period = 6.288 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rRed[7]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.089 ns                ;
; 2.803 ns                                ; 159.06 MHz ( period = 6.287 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.094 ns                ;
; 2.806 ns                                ; 159.13 MHz ( period = 6.284 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.078 ns                ;
; 2.806 ns                                ; 159.13 MHz ( period = 6.284 ns )                    ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[26] ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.910 ns                  ; 6.104 ns                ;
; 2.807 ns                                ; 159.16 MHz ( period = 6.283 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.091 ns                ;
; 2.812 ns                                ; 159.29 MHz ( period = 6.278 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[2]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.072 ns                ;
; 2.812 ns                                ; 159.29 MHz ( period = 6.278 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.086 ns                ;
; 2.821 ns                                ; 159.52 MHz ( period = 6.269 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.063 ns                ;
; 2.828 ns                                ; 159.69 MHz ( period = 6.262 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.056 ns                ;
; 2.834 ns                                ; 159.85 MHz ( period = 6.256 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.063 ns                ;
; 2.839 ns                                ; 159.97 MHz ( period = 6.251 ns )                    ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[4]  ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.919 ns                  ; 6.080 ns                ;
; 2.839 ns                                ; 159.97 MHz ( period = 6.251 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.045 ns                ;
; 2.847 ns                                ; 160.18 MHz ( period = 6.243 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.037 ns                ;
; 2.853 ns                                ; 160.33 MHz ( period = 6.237 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rRed[2]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.031 ns                ;
; 2.854 ns                                ; 160.36 MHz ( period = 6.236 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.030 ns                ;
; 2.861 ns                                ; 160.54 MHz ( period = 6.229 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[10]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.902 ns                  ; 6.041 ns                ;
; 2.866 ns                                ; 160.67 MHz ( period = 6.224 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.018 ns                ;
; 2.866 ns                                ; 160.67 MHz ( period = 6.224 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.031 ns                ;
; 2.869 ns                                ; 160.75 MHz ( period = 6.221 ns )                    ; CCD_Capture:capture0|Y_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 6.029 ns                ;
; 2.871 ns                                ; 160.80 MHz ( period = 6.219 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[5]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.013 ns                ;
; 2.873 ns                                ; 160.85 MHz ( period = 6.217 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[7]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 6.018 ns                ;
; 2.880 ns                                ; 161.03 MHz ( period = 6.210 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rRed[10]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.902 ns                  ; 6.022 ns                ;
; 2.885 ns                                ; 161.16 MHz ( period = 6.205 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.012 ns                ;
; 2.890 ns                                ; 161.29 MHz ( period = 6.200 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rRed[5]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.994 ns                ;
; 2.892 ns                                ; 161.34 MHz ( period = 6.198 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rRed[7]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 5.999 ns                ;
; 2.894 ns                                ; 161.39 MHz ( period = 6.196 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.003 ns                ;
; 2.896 ns                                ; 161.45 MHz ( period = 6.194 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 6.001 ns                ;
; 2.899 ns                                ; 161.52 MHz ( period = 6.191 ns )                    ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[28] ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.901 ns                  ; 6.002 ns                ;
; 2.905 ns                                ; 161.68 MHz ( period = 6.185 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 5.993 ns                ;
; 2.913 ns                                ; 161.89 MHz ( period = 6.177 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.971 ns                ;
; 2.916 ns                                ; 161.97 MHz ( period = 6.174 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 5.976 ns                ;
; 2.917 ns                                ; 162.00 MHz ( period = 6.173 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.967 ns                ;
; 2.917 ns                                ; 162.00 MHz ( period = 6.173 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 5.980 ns                ;
; 2.917 ns                                ; 162.00 MHz ( period = 6.173 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 5.980 ns                ;
; 2.919 ns                                ; 162.05 MHz ( period = 6.171 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 5.978 ns                ;
; 2.924 ns                                ; 162.18 MHz ( period = 6.166 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[2]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.960 ns                ;
; 2.924 ns                                ; 162.18 MHz ( period = 6.166 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 5.973 ns                ;
; 2.926 ns                                ; 162.23 MHz ( period = 6.164 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 5.971 ns                ;
; 2.927 ns                                ; 162.26 MHz ( period = 6.163 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[10]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.902 ns                  ; 5.975 ns                ;
; 2.928 ns                                ; 162.28 MHz ( period = 6.162 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 5.970 ns                ;
; 2.930 ns                                ; 162.34 MHz ( period = 6.160 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[4]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 5.961 ns                ;
; 2.934 ns                                ; 162.44 MHz ( period = 6.156 ns )                    ; CCD_Capture:capture0|Y_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 5.964 ns                ;
; 2.934 ns                                ; 162.44 MHz ( period = 6.156 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 5.964 ns                ;
; 2.935 ns                                ; 162.47 MHz ( period = 6.155 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 5.962 ns                ;
; 2.937 ns                                ; 162.52 MHz ( period = 6.153 ns )                    ; CCD_Capture:capture0|X_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 5.954 ns                ;
; 2.937 ns                                ; 162.52 MHz ( period = 6.153 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[5]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.947 ns                ;
; 2.939 ns                                ; 162.58 MHz ( period = 6.151 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.892 ns                  ; 5.953 ns                ;
; 2.939 ns                                ; 162.58 MHz ( period = 6.151 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[7]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 5.952 ns                ;
; 2.943 ns                                ; 162.68 MHz ( period = 6.147 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rRed[2]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.941 ns                ;
; 2.949 ns                                ; 162.84 MHz ( period = 6.141 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 5.948 ns                ;
; 2.951 ns                                ; 162.89 MHz ( period = 6.139 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.933 ns                ;
; 2.956 ns                                ; 163.03 MHz ( period = 6.134 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 5.941 ns                ;
; 2.957 ns                                ; 163.05 MHz ( period = 6.133 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 5.941 ns                ;
; 2.961 ns                                ; 163.16 MHz ( period = 6.129 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.923 ns                ;
; 2.964 ns                                ; 163.24 MHz ( period = 6.126 ns )                    ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[26] ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.917 ns                  ; 5.953 ns                ;
; 2.965 ns                                ; 163.27 MHz ( period = 6.125 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rRed[10]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.902 ns                  ; 5.937 ns                ;
; 2.967 ns                                ; 163.32 MHz ( period = 6.123 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.897 ns                  ; 5.930 ns                ;
; 2.968 ns                                ; 163.35 MHz ( period = 6.122 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.916 ns                ;
; 2.971 ns                                ; 163.43 MHz ( period = 6.119 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rRed[4]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 5.920 ns                ;
; 2.972 ns                                ; 163.45 MHz ( period = 6.118 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[8]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 5.926 ns                ;
; 2.975 ns                                ; 163.53 MHz ( period = 6.115 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rRed[5]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.909 ns                ;
; 2.977 ns                                ; 163.59 MHz ( period = 6.113 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.907 ns                ;
; 2.977 ns                                ; 163.59 MHz ( period = 6.113 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rRed[7]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.891 ns                  ; 5.914 ns                ;
; 2.984 ns                                ; 163.77 MHz ( period = 6.106 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.900 ns                ;
; 2.990 ns                                ; 163.93 MHz ( period = 6.100 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[2]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.894 ns                ;
; 2.997 ns                                ; 164.12 MHz ( period = 6.093 ns )                    ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[4]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.926 ns                  ; 5.929 ns                ;
; 2.999 ns                                ; 164.18 MHz ( period = 6.091 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.885 ns                ;
; 3.000 ns                                ; 164.20 MHz ( period = 6.090 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.884 ns                ;
; 3.007 ns                                ; 164.39 MHz ( period = 6.083 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.877 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                     ;                         ;               ;               ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------+---------------+---------------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'iCLK_50'                                                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                            ; To                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 6.670 ns                                ; 150.15 MHz ( period = 6.660 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[14]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 3.116 ns                ;
; 6.982 ns                                ; 165.67 MHz ( period = 6.036 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[15]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.804 ns                ;
; 7.292 ns                                ; 184.64 MHz ( period = 5.416 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[11]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.787 ns                  ; 2.495 ns                ;
; 7.562 ns                                ; 205.09 MHz ( period = 4.876 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.220 ns                ;
; 7.562 ns                                ; 205.09 MHz ( period = 4.876 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.220 ns                ;
; 7.564 ns                                ; 205.25 MHz ( period = 4.872 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.218 ns                ;
; 7.564 ns                                ; 205.25 MHz ( period = 4.872 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.218 ns                ;
; 7.597 ns                                ; 208.07 MHz ( period = 4.806 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[13]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.189 ns                ;
; 7.643 ns                                ; 212.13 MHz ( period = 4.714 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[3]                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.789 ns                  ; 2.146 ns                ;
; 7.646 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[8]                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.787 ns                  ; 2.141 ns                ;
; 7.660 ns                                ; 213.68 MHz ( period = 4.680 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.788 ns                  ; 2.128 ns                ;
; 7.666 ns                                ; 214.22 MHz ( period = 4.668 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[12]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.787 ns                  ; 2.121 ns                ;
; 7.670 ns                                ; 214.59 MHz ( period = 4.660 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA~en ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.791 ns                  ; 2.121 ns                ;
; 7.699 ns                                ; 217.30 MHz ( period = 4.602 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.083 ns                ;
; 7.699 ns                                ; 217.30 MHz ( period = 4.602 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.083 ns                ;
; 7.701 ns                                ; 217.49 MHz ( period = 4.598 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.081 ns                ;
; 7.701 ns                                ; 217.49 MHz ( period = 4.598 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.081 ns                ;
; 7.710 ns                                ; 218.34 MHz ( period = 4.580 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN      ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 2.080 ns                ;
; 7.710 ns                                ; 218.34 MHz ( period = 4.580 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSCLK     ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 2.080 ns                ;
; 7.745 ns                                ; 221.73 MHz ( period = 4.510 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[10]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.041 ns                ;
; 7.776 ns                                ; 224.82 MHz ( period = 4.448 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[2]                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.789 ns                  ; 2.013 ns                ;
; 7.895 ns                                ; 237.53 MHz ( period = 4.210 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[1]                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.789 ns                  ; 1.894 ns                ;
; 7.953 ns                                ; 244.26 MHz ( period = 4.094 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[7]                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.787 ns                  ; 1.834 ns                ;
; 8.041 ns                                ; 255.23 MHz ( period = 3.918 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[0]                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.789 ns                  ; 1.748 ns                ;
; 8.085 ns                                ; 261.10 MHz ( period = 3.830 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.697 ns                ;
; 8.085 ns                                ; 261.10 MHz ( period = 3.830 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.697 ns                ;
; 8.087 ns                                ; 261.37 MHz ( period = 3.826 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.695 ns                ;
; 8.087 ns                                ; 261.37 MHz ( period = 3.826 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.695 ns                ;
; 8.236 ns                                ; 283.45 MHz ( period = 3.528 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.546 ns                ;
; 8.236 ns                                ; 283.45 MHz ( period = 3.528 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.546 ns                ;
; 8.238 ns                                ; 283.77 MHz ( period = 3.524 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.544 ns                ;
; 8.238 ns                                ; 283.77 MHz ( period = 3.524 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.544 ns                ;
; 8.352 ns                                ; 303.40 MHz ( period = 3.296 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[4]                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.787 ns                  ; 1.435 ns                ;
; 8.359 ns                                ; 304.69 MHz ( period = 3.282 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.423 ns                ;
; 8.359 ns                                ; 304.69 MHz ( period = 3.282 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.423 ns                ;
; 8.361 ns                                ; 305.06 MHz ( period = 3.278 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.421 ns                ;
; 8.361 ns                                ; 305.06 MHz ( period = 3.278 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.421 ns                ;
; 8.453 ns                                ; 323.21 MHz ( period = 3.094 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[5]                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.333 ns                ;
; 8.536 ns                                ; 341.53 MHz ( period = 2.928 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK      ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.254 ns                ;
; 8.536 ns                                ; 341.53 MHz ( period = 2.928 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.254 ns                ;
; 8.536 ns                                ; 341.53 MHz ( period = 2.928 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.254 ns                ;
; 8.536 ns                                ; 341.53 MHz ( period = 2.928 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.254 ns                ;
; 8.536 ns                                ; 341.53 MHz ( period = 2.928 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.254 ns                ;
; 8.536 ns                                ; 341.53 MHz ( period = 2.928 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.254 ns                ;
; 8.562 ns                                ; 347.71 MHz ( period = 2.876 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[6]                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.787 ns                  ; 1.225 ns                ;
; 8.695 ns                                ; 383.14 MHz ( period = 2.610 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.087 ns                ;
; 8.696 ns                                ; 383.44 MHz ( period = 2.608 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.086 ns                ;
; 13.866 ns                               ; 163.03 MHz ( period = 6.134 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.788 ns                 ; 5.922 ns                ;
; 13.902 ns                               ; 163.99 MHz ( period = 6.098 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[0]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.788 ns                 ; 5.886 ns                ;
; 13.918 ns                               ; 164.42 MHz ( period = 6.082 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.869 ns                ;
; 13.959 ns                               ; 165.54 MHz ( period = 6.041 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.828 ns                ;
; 13.961 ns                               ; 165.59 MHz ( period = 6.039 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.825 ns                ;
; 13.966 ns                               ; 165.73 MHz ( period = 6.034 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.820 ns                ;
; 13.973 ns                               ; 165.92 MHz ( period = 6.027 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.813 ns                ;
; 13.976 ns                               ; 166.00 MHz ( period = 6.024 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.811 ns                ;
; 14.029 ns                               ; 167.48 MHz ( period = 5.971 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.757 ns                ;
; 14.042 ns                               ; 167.84 MHz ( period = 5.958 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.745 ns                ;
; 14.058 ns                               ; 168.29 MHz ( period = 5.942 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.728 ns                ;
; 14.068 ns                               ; 168.58 MHz ( period = 5.932 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.718 ns                ;
; 14.096 ns                               ; 169.38 MHz ( period = 5.904 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.691 ns                ;
; 14.106 ns                               ; 169.66 MHz ( period = 5.894 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.680 ns                ;
; 14.108 ns                               ; 169.72 MHz ( period = 5.892 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.678 ns                ;
; 14.121 ns                               ; 170.10 MHz ( period = 5.879 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.665 ns                ;
; 14.127 ns                               ; 170.27 MHz ( period = 5.873 ns )                    ; Reset_Delay:reset0|Cont[10]                                     ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.996 ns                ;
; 14.132 ns                               ; 170.42 MHz ( period = 5.868 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.654 ns                ;
; 14.142 ns                               ; 170.71 MHz ( period = 5.858 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.644 ns                ;
; 14.156 ns                               ; 171.12 MHz ( period = 5.844 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.631 ns                ;
; 14.187 ns                               ; 172.03 MHz ( period = 5.813 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.599 ns                ;
; 14.197 ns                               ; 172.32 MHz ( period = 5.803 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.590 ns                ;
; 14.198 ns                               ; 172.35 MHz ( period = 5.802 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[1]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.788 ns                 ; 5.590 ns                ;
; 14.214 ns                               ; 172.83 MHz ( period = 5.786 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.573 ns                ;
; 14.229 ns                               ; 173.28 MHz ( period = 5.771 ns )                    ; Reset_Delay:reset0|Cont[15]                                     ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.129 ns                 ; 4.900 ns                ;
; 14.240 ns                               ; 173.61 MHz ( period = 5.760 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.547 ns                ;
; 14.260 ns                               ; 174.22 MHz ( period = 5.740 ns )                    ; Reset_Delay:reset0|Cont[13]                                     ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.129 ns                 ; 4.869 ns                ;
; 14.280 ns                               ; 174.83 MHz ( period = 5.720 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.507 ns                ;
; 14.287 ns                               ; 175.04 MHz ( period = 5.713 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.499 ns                ;
; 14.290 ns                               ; 175.13 MHz ( period = 5.710 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.497 ns                ;
; 14.296 ns                               ; 175.32 MHz ( period = 5.704 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.490 ns                ;
; 14.304 ns                               ; 175.56 MHz ( period = 5.696 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.482 ns                ;
; 14.306 ns                               ; 175.62 MHz ( period = 5.694 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.480 ns                ;
; 14.314 ns                               ; 175.87 MHz ( period = 5.686 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.472 ns                ;
; 14.331 ns                               ; 176.40 MHz ( period = 5.669 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.456 ns                ;
; 14.334 ns                               ; 176.49 MHz ( period = 5.666 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.453 ns                ;
; 14.348 ns                               ; 176.93 MHz ( period = 5.652 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.439 ns                ;
; 14.356 ns                               ; 177.18 MHz ( period = 5.644 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[5]          ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.752 ns                 ; 5.396 ns                ;
; 14.375 ns                               ; 177.78 MHz ( period = 5.625 ns )                    ; Reset_Delay:reset0|Cont[14]                                     ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.129 ns                 ; 4.754 ns                ;
; 14.383 ns                               ; 178.03 MHz ( period = 5.617 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.403 ns                ;
; 14.396 ns                               ; 178.44 MHz ( period = 5.604 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.390 ns                ;
; 14.401 ns                               ; 178.60 MHz ( period = 5.599 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.385 ns                ;
; 14.413 ns                               ; 178.99 MHz ( period = 5.587 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.373 ns                ;
; 14.414 ns                               ; 179.02 MHz ( period = 5.586 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.373 ns                ;
; 14.425 ns                               ; 179.37 MHz ( period = 5.575 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.361 ns                ;
; 14.430 ns                               ; 179.53 MHz ( period = 5.570 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.356 ns                ;
; 14.440 ns                               ; 179.86 MHz ( period = 5.560 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.346 ns                ;
; 14.457 ns                               ; 180.41 MHz ( period = 5.543 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.329 ns                ;
; 14.468 ns                               ; 180.77 MHz ( period = 5.532 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.319 ns                ;
; 14.478 ns                               ; 181.09 MHz ( period = 5.522 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.309 ns                ;
; 14.508 ns                               ; 182.08 MHz ( period = 5.492 ns )                    ; Reset_Delay:reset0|Cont[12]                                     ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.129 ns                 ; 4.621 ns                ;
; 14.528 ns                               ; 182.75 MHz ( period = 5.472 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.258 ns                ;
; 14.537 ns                               ; 183.05 MHz ( period = 5.463 ns )                    ; Reset_Delay:reset0|Cont[2]                                      ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.586 ns                ;
; 14.559 ns                               ; 183.79 MHz ( period = 5.441 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.227 ns                ;
; 14.562 ns                               ; 183.89 MHz ( period = 5.438 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.224 ns                ;
; 14.566 ns                               ; 184.03 MHz ( period = 5.434 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.220 ns                ;
; 14.578 ns                               ; 184.43 MHz ( period = 5.422 ns )                    ; Reset_Delay:reset0|Cont[0]                                      ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.545 ns                ;
; 14.602 ns                               ; 185.25 MHz ( period = 5.398 ns )                    ; Reset_Delay:reset0|Cont[11]                                     ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.521 ns                ;
; 14.612 ns                               ; 185.60 MHz ( period = 5.388 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.175 ns                ;
; 14.667 ns                               ; 187.51 MHz ( period = 5.333 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[19]         ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.753 ns                 ; 5.086 ns                ;
; 14.685 ns                               ; 188.15 MHz ( period = 5.315 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.101 ns                ;
; 14.685 ns                               ; 188.15 MHz ( period = 5.315 ns )                    ; Reset_Delay:reset0|Cont[6]                                      ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.438 ns                ;
; 14.688 ns                               ; 188.25 MHz ( period = 5.312 ns )                    ; Reset_Delay:reset0|Cont[3]                                      ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.435 ns                ;
; 14.712 ns                               ; 189.11 MHz ( period = 5.288 ns )                    ; Reset_Delay:reset0|Cont[8]                                      ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.411 ns                ;
; 14.717 ns                               ; 189.29 MHz ( period = 5.283 ns )                    ; Reset_Delay:reset0|Cont[7]                                      ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.406 ns                ;
; 14.757 ns                               ; 190.73 MHz ( period = 5.243 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[4]          ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.752 ns                 ; 4.995 ns                ;
; 14.802 ns                               ; 192.38 MHz ( period = 5.198 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.984 ns                ;
; 14.806 ns                               ; 192.53 MHz ( period = 5.194 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.981 ns                ;
; 14.817 ns                               ; 192.94 MHz ( period = 5.183 ns )                    ; Reset_Delay:reset0|Cont[1]                                      ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.306 ns                ;
; 14.822 ns                               ; 193.12 MHz ( period = 5.178 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[3]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.072 ns                 ; 4.250 ns                ;
; 14.831 ns                               ; 193.46 MHz ( period = 5.169 ns )                    ; Reset_Delay:reset0|Cont[4]                                      ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.292 ns                ;
; 14.847 ns                               ; 194.06 MHz ( period = 5.153 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.940 ns                ;
; 14.850 ns                               ; 194.17 MHz ( period = 5.150 ns )                    ; Reset_Delay:reset0|Cont[9]                                      ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.273 ns                ;
; 14.857 ns                               ; 194.44 MHz ( period = 5.143 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.929 ns                ;
; 14.864 ns                               ; 194.70 MHz ( period = 5.136 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.923 ns                ;
; 14.865 ns                               ; 194.74 MHz ( period = 5.135 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[5]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.072 ns                 ; 4.207 ns                ;
; 14.907 ns                               ; 196.35 MHz ( period = 5.093 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.880 ns                ;
; 14.910 ns                               ; 196.46 MHz ( period = 5.090 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.877 ns                ;
; 14.930 ns                               ; 197.24 MHz ( period = 5.070 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.857 ns                ;
; 14.948 ns                               ; 197.94 MHz ( period = 5.052 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.839 ns                ;
; 14.951 ns                               ; 198.06 MHz ( period = 5.049 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.835 ns                ;
; 14.958 ns                               ; 198.33 MHz ( period = 5.042 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.828 ns                ;
; 14.958 ns                               ; 198.33 MHz ( period = 5.042 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[4]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.072 ns                 ; 4.114 ns                ;
; 14.958 ns                               ; 198.33 MHz ( period = 5.042 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[14] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.072 ns                 ; 4.114 ns                ;
; 14.959 ns                               ; 198.37 MHz ( period = 5.041 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.827 ns                ;
; 14.961 ns                               ; 198.45 MHz ( period = 5.039 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.825 ns                ;
; 14.964 ns                               ; 198.57 MHz ( period = 5.036 ns )                    ; Reset_Delay:reset0|Cont[5]                                      ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.123 ns                 ; 4.159 ns                ;
; 14.965 ns                               ; 198.61 MHz ( period = 5.035 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.822 ns                ;
; 14.969 ns                               ; 198.77 MHz ( period = 5.031 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.818 ns                ;
; 14.984 ns                               ; 199.36 MHz ( period = 5.016 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.803 ns                ;
; 14.999 ns                               ; 199.96 MHz ( period = 5.001 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.788 ns                ;
; 15.016 ns                               ; 200.64 MHz ( period = 4.984 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.770 ns                ;
; 15.031 ns                               ; 201.25 MHz ( period = 4.969 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.756 ns                ;
; 15.056 ns                               ; 202.27 MHz ( period = 4.944 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.730 ns                ;
; 15.068 ns                               ; 202.76 MHz ( period = 4.932 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[18]         ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.753 ns                 ; 4.685 ns                ;
; 15.080 ns                               ; 203.25 MHz ( period = 4.920 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.706 ns                ;
; 15.085 ns                               ; 203.46 MHz ( period = 4.915 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.702 ns                ;
; 15.087 ns                               ; 203.54 MHz ( period = 4.913 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.699 ns                ;
; 15.090 ns                               ; 203.67 MHz ( period = 4.910 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.696 ns                ;
; 15.090 ns                               ; 203.67 MHz ( period = 4.910 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[2]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.072 ns                 ; 3.982 ns                ;
; 15.091 ns                               ; 203.71 MHz ( period = 4.909 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.696 ns                ;
; 15.100 ns                               ; 204.08 MHz ( period = 4.900 ns )                    ; Reset_Delay:reset0|Cont[18]                                     ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.129 ns                 ; 4.029 ns                ;
; 15.129 ns                               ; 205.30 MHz ( period = 4.871 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.658 ns                ;
; 15.133 ns                               ; 205.47 MHz ( period = 4.867 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.654 ns                ;
; 15.144 ns                               ; 205.93 MHz ( period = 4.856 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.643 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.162 ns                               ; 206.70 MHz ( period = 4.838 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.629 ns                ;
; 15.166 ns                               ; 206.87 MHz ( period = 4.834 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[8]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.072 ns                 ; 3.906 ns                ;
; 15.183 ns                               ; 207.60 MHz ( period = 4.817 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.604 ns                ;
; 15.188 ns                               ; 207.81 MHz ( period = 4.812 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.598 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.785 ns                 ; 4.592 ns                ;
; 15.193 ns                               ; 208.03 MHz ( period = 4.807 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[16]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.785 ns                 ; 4.592 ns                ;
; 15.241 ns                               ; 210.13 MHz ( period = 4.759 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[7]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.072 ns                 ; 3.831 ns                ;
; 15.243 ns                               ; 210.22 MHz ( period = 4.757 ns )                    ; Reset_Delay:reset0|Cont[16]                                     ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.129 ns                 ; 3.886 ns                ;
; 15.252 ns                               ; 210.61 MHz ( period = 4.748 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.785 ns                 ; 4.533 ns                ;
; 15.252 ns                               ; 210.61 MHz ( period = 4.748 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[16]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.785 ns                 ; 4.533 ns                ;
; 15.266 ns                               ; 211.24 MHz ( period = 4.734 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.791 ns                 ; 4.525 ns                ;
; 15.268 ns                               ; 211.33 MHz ( period = 4.732 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[13]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.785 ns                 ; 4.517 ns                ;
; 15.269 ns                               ; 211.37 MHz ( period = 4.731 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.518 ns                ;
; 15.269 ns                               ; 211.37 MHz ( period = 4.731 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.518 ns                ;
; 15.269 ns                               ; 211.37 MHz ( period = 4.731 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.518 ns                ;
; 15.269 ns                               ; 211.37 MHz ( period = 4.731 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.518 ns                ;
; 15.269 ns                               ; 211.37 MHz ( period = 4.731 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.518 ns                ;
; 15.269 ns                               ; 211.37 MHz ( period = 4.731 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.518 ns                ;
; 15.269 ns                               ; 211.37 MHz ( period = 4.731 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 4.518 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                 ;                                                          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


 
; Clock Hold: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
 
; Minimum Slack                           ; From                                                                                                                                                            ; To                                                                                                                                                                                        ; From Clock                                         ; To Clock                                           ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
 
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                               ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_rw                                                                                                               ; Sdram_Control_4Port:sdram0|command:command1|do_rw                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rw_flag                                                                                                             ; Sdram_Control_4Port:sdram1|command:command1|rw_flag                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rw_flag                                                                                                             ; Sdram_Control_4Port:sdram0|command:command1|rw_flag                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|OUT_VALID                                                                                                                            ; Sdram_Control_4Port:sdram1|OUT_VALID                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|IN_REQ                                                                                                                               ; Sdram_Control_4Port:sdram1|IN_REQ                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|Write                                                                                                                                ; Sdram_Control_4Port:sdram1|Write                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|Read                                                                                                                                 ; Sdram_Control_4Port:sdram1|Read                                                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|mWR_DONE                                                                                                                             ; Sdram_Control_4Port:sdram1|mWR_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|CM_ACK                                                                                                              ; Sdram_Control_4Port:sdram1|command:command1|CM_ACK                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|mRD_DONE                                                                                                                             ; Sdram_Control_4Port:sdram1|mRD_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|ST[0]                                                                                                                                ; Sdram_Control_4Port:sdram1|ST[0]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|CMD_ACK                                                                                                   ; Sdram_Control_4Port:sdram1|control_interface:control1|CMD_ACK                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|RD_MASK[0]                                                                                                                           ; Sdram_Control_4Port:sdram1|RD_MASK[0]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|ex_read                                                                                                             ; Sdram_Control_4Port:sdram1|command:command1|ex_read                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|ex_write                                                                                                            ; Sdram_Control_4Port:sdram1|command:command1|ex_write                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|REF_ACK                                                                                                             ; Sdram_Control_4Port:sdram1|command:command1|REF_ACK                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|REF_REQ                                                                                                   ; Sdram_Control_4Port:sdram1|control_interface:control1|REF_REQ                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_precharge                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|do_precharge                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|do_load_mode                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|OUT_VALID                                                                                                                            ; Sdram_Control_4Port:sdram0|OUT_VALID                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|IN_REQ                                                                                                                               ; Sdram_Control_4Port:sdram0|IN_REQ                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|Write                                                                                                                                ; Sdram_Control_4Port:sdram0|Write                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|Read                                                                                                                                 ; Sdram_Control_4Port:sdram0|Read                                                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|mWR_DONE                                                                                                                             ; Sdram_Control_4Port:sdram0|mWR_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|CM_ACK                                                                                                              ; Sdram_Control_4Port:sdram0|command:command1|CM_ACK                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|mRD_DONE                                                                                                                             ; Sdram_Control_4Port:sdram0|mRD_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|ST[0]                                                                                                                                ; Sdram_Control_4Port:sdram0|ST[0]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|ex_read                                                                                                             ; Sdram_Control_4Port:sdram0|command:command1|ex_read                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|ex_write                                                                                                            ; Sdram_Control_4Port:sdram0|command:command1|ex_write                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|CMD_ACK                                                                                                   ; Sdram_Control_4Port:sdram0|control_interface:control1|CMD_ACK                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|RD_MASK[0]                                                                                                                           ; Sdram_Control_4Port:sdram0|RD_MASK[0]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|REF_ACK                                                                                                             ; Sdram_Control_4Port:sdram0|command:command1|REF_ACK                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|REF_REQ                                                                                                   ; Sdram_Control_4Port:sdram0|control_interface:control1|REF_REQ                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_precharge                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|do_precharge                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[0]                                                                                             ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[0]                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|do_load_mode                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.516 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[20]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|BA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.532 ns                 ;
; 0.517 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rw_shift[0]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.533 ns                 ;
; 0.518 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[20]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|BA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.534 ns                 ;
; 0.519 ns                                ; Sdram_Control_4Port:sdram0|command:command1|CS_N[0]                                                                                                             ; Sdram_Control_4Port:sdram0|CS_N[0]                                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.535 ns                 ;
; 0.519 ns                                ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                             ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[8]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.535 ns                 ;
; 0.522 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.524 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[3]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|command_delay[2]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.540 ns                 ;
; 0.527 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.543 ns                 ;
; 0.527 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.543 ns                 ;
; 0.528 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[0]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|rp_done                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.544 ns                 ;
; 0.530 ns                                ; Sdram_Control_4Port:sdram0|CMD[0]                                                                                                                               ; Sdram_Control_4Port:sdram0|control_interface:control1|READA                                                                                                                               ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.546 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram0|rRD1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram0|rWR1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[15]                                                                                                 ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[15]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[15]                                                                                                 ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[15]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram0|CMD[0]                                                                                                                               ; Sdram_Control_4Port:sdram0|control_interface:control1|WRITEA                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.533 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.549 ns                 ;
; 0.533 ns                                ; Sdram_Control_4Port:sdram0|command:command1|CM_ACK                                                                                                              ; Sdram_Control_4Port:sdram0|control_interface:control1|CMD_ACK                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.549 ns                 ;
; 0.537 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_done                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|do_load_mode                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.553 ns                 ;
; 0.538 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.554 ns                 ;
; 0.542 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[15]                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[15]                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.558 ns                 ;
; 0.543 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.559 ns                 ;
; 0.545 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.561 ns                 ;
; 0.565 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.581 ns                 ;
; 0.575 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_done                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[3]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.591 ns                 ;
; 0.622 ns                                ; Sdram_Control_4Port:sdram1|command:command1|SA[9]                                                                                                               ; Sdram_Control_4Port:sdram1|SA[9]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.638 ns                 ;
; 0.642 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[9]                                                                                                  ; Sdram_Control_4Port:sdram1|command:command1|SA[1]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.658 ns                 ;
; 0.645 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[9]                                                                                                  ; Sdram_Control_4Port:sdram0|command:command1|SA[1]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.661 ns                 ;
; 0.649 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[12]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[4]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.665 ns                 ;
; 0.649 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[5]                                                                                                               ; Sdram_Control_4Port:sdram0|SA[5]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.665 ns                 ;
; 0.651 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[13]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[5]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.667 ns                 ;
; 0.652 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[6]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|command_delay[5]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.668 ns                 ;
; 0.653 ns                                ; Sdram_Control_4Port:sdram1|command:command1|SA[4]                                                                                                               ; Sdram_Control_4Port:sdram1|SA[4]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.669 ns                 ;
; 0.653 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[1]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|command_delay[0]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.669 ns                 ;
; 0.654 ns                                ; Sdram_Control_4Port:sdram1|command:command1|SA[10]                                                                                                              ; Sdram_Control_4Port:sdram1|SA[10]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.670 ns                 ;
; 0.654 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[13]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[5]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.670 ns                 ;
; 0.654 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[11]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[3]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.670 ns                 ;
; 0.655 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[16]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[8]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.671 ns                 ;
; 0.655 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[4]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|command_delay[3]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.671 ns                 ;
; 0.655 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[2]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|command_delay[1]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.671 ns                 ;
; 0.656 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[4]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[3]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.672 ns                 ;
; 0.660 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg1  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.067 ns                   ; 0.727 ns                 ;
; 0.662 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg0  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.067 ns                   ; 0.729 ns                 ;
; 0.662 ns                                ; Sdram_Control_4Port:sdram0|CMD[1]                                                                                                                               ; Sdram_Control_4Port:sdram0|control_interface:control1|WRITEA                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.678 ns                 ;
; 0.663 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[3]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[2]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.679 ns                 ;
; 0.663 ns                                ; Sdram_Control_4Port:sdram0|CMD[1]                                                                                                                               ; Sdram_Control_4Port:sdram0|control_interface:control1|READA                                                                                                                               ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.679 ns                 ;
; 0.665 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[2]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[1]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.681 ns                 ;
; 0.665 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[1]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.681 ns                 ;
; 0.667 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_rw                                                                                                               ; Sdram_Control_4Port:sdram0|command:command1|SA[10]                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.683 ns                 ;
; 0.667 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[6]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[5]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.683 ns                 ;
; 0.674 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|BA[1]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.690 ns                 ;
; 0.674 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|BA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.690 ns                 ;
; 0.674 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.690 ns                 ;
; 0.674 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.690 ns                 ;
; 0.676 ns                                ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                            ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[17]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.690 ns                 ;
; 0.678 ns                                ; Sdram_Control_4Port:sdram1|command:command1|CS_N[0]                                                                                                             ; Sdram_Control_4Port:sdram1|CS_N[0]                                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.692 ns                 ;
; 0.679 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg0  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.071 ns                   ; 0.750 ns                 ;
; 0.679 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.695 ns                 ;
; 0.685 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.702 ns                 ;
; 0.686 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.702 ns                 ;
; 0.692 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg2 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.723 ns                 ;
; 0.692 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.708 ns                 ;
; 0.693 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg7 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.724 ns                 ;
; 0.693 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[15]                                                                                            ; Sdram_Control_4Port:sdram1|control_interface:control1|INIT_REQ                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.707 ns                 ;
; 0.694 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[2]                                                                    ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.710 ns                 ;
; 0.694 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.710 ns                 ;
; 0.696 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg7 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.727 ns                 ;
; 0.697 ns                                ; Sdram_Control_4Port:sdram1|RD_MASK[0]                                                                                                                           ; Sdram_Control_4Port:sdram1|Pre_RD                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.713 ns                 ;
; 0.698 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg2 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.729 ns                 ;
; 0.703 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg4 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.734 ns                 ;
; 0.704 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg5 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.735 ns                 ;
; 0.704 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg5 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.735 ns                 ;
; 0.705 ns                                ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                            ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[21]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.719 ns                 ;
; 0.705 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg6 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.736 ns                 ;
; 0.706 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg6 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.737 ns                 ;
; 0.711 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg3 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.742 ns                 ;
; 0.714 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.731 ns                 ;
; 0.725 ns                                ; Sdram_Control_4Port:sdram1|PM_STOP                                                                                                                              ; Sdram_Control_4Port:sdram1|command:command1|ex_write                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.018 ns                   ; 0.743 ns                 ;
; 0.737 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[16]                                                                                                                        ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.751 ns                 ;
; 0.738 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_writea                                                                                                           ; Sdram_Control_4Port:sdram0|command:command1|oe4                                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.753 ns                 ;
; 0.738 ns                                ; Sdram_Control_4Port:sdram1|Write                                                                                                                                ; Sdram_Control_4Port:sdram1|mWR_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.754 ns                 ;
; 0.739 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.753 ns                 ;
; 0.740 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_writea                                                                                                           ; Sdram_Control_4Port:sdram0|command:command1|rw_flag                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.755 ns                 ;
; 0.740 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.755 ns                 ;
; 0.741 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_writea                                                                                                           ; Sdram_Control_4Port:sdram0|command:command1|do_rw                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.756 ns                 ;
; 0.742 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_writea                                                                                                           ; Sdram_Control_4Port:sdram0|command:command1|rw_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.757 ns                 ;
; 0.742 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.013 ns                   ; 0.755 ns                 ;
; 0.743 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.758 ns                 ;
; 0.743 ns                                ; Sdram_Control_4Port:sdram0|PM_STOP                                                                                                                              ; Sdram_Control_4Port:sdram0|command:command1|ex_write                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.757 ns                 ;
; 0.744 ns                                ; Sdram_Control_4Port:sdram0|PM_STOP                                                                                                                              ; Sdram_Control_4Port:sdram0|command:command1|ex_read                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.758 ns                 ;
; 0.746 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[2]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.761 ns                 ;
; 0.749 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[2]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.764 ns                 ;
; 0.749 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.764 ns                 ;
; 0.756 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[9]                                                                                             ; Sdram_Control_4Port:sdram1|control_interface:control1|PRECHARGE                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.770 ns                 ;
; 0.758 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg4 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.789 ns                 ;
; 0.759 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.774 ns                 ;
; 0.760 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[2]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.775 ns                 ;
; 0.762 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[22]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|CS_N[0]                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.778 ns                 ;
; 0.765 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[18]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[10]                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.781 ns                 ;
; 0.766 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_done                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|do_precharge                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.782 ns                 ;
; 0.768 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_refresh                                                                                                          ; Sdram_Control_4Port:sdram0|command:command1|RAS_N                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.783 ns                 ;
; 0.768 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_refresh                                                                                                          ; Sdram_Control_4Port:sdram0|command:command1|WE_N                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.783 ns                 ;
; 0.768 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg3 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.799 ns                 ;
; 0.775 ns                                ; Sdram_Control_4Port:sdram1|command:command1|CAS_N                                                                                                               ; Sdram_Control_4Port:sdram1|CAS_N                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.789 ns                 ;
; 0.777 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|WRITEA                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|do_writea                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.793 ns                 ;
; 0.778 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[1]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[1]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.794 ns                 ;
; 0.778 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[1]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[1]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.794 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[11]                                                                                                 ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[11]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[9]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[9]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[13]                                                                                                 ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[13]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[7]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[7]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[11]                                                                                                 ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[11]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[9]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[9]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[7]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[7]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[13]                                                                                                 ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[13]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.786 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.786 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.788 ns                                ; Sdram_Control_4Port:sdram1|command:command1|SA[3]                                                                                                               ; Sdram_Control_4Port:sdram1|SA[3]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.804 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|p0addr                                                     ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.790 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|p0addr                                                     ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.806 ns                 ;
; 0.790 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.806 ns                 ;
; 0.791 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.807 ns                 ;
; 0.791 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.807 ns                 ;
; 0.792 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[21]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|BA[1]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.808 ns                 ;
; 0.792 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[14]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[6]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.808 ns                 ;
; 0.792 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[12]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[4]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.808 ns                 ;
; 0.794 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[7]                                                                                                               ; Sdram_Control_4Port:sdram0|SA[7]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.810 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[0]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[0]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[0]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[0]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.796 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[19]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[11]                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.797 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[11]                                                                                                              ; Sdram_Control_4Port:sdram0|SA[11]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.812 ns                 ;
; 0.798 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[10]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[2]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.799 ns                                ; Sdram_Control_4Port:sdram1|command:command1|SA[11]                                                                                                              ; Sdram_Control_4Port:sdram1|SA[11]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.815 ns                 ;
; 0.799 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                               ; Sdram_Control_4Port:sdram1|command:command1|SA[10]                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.815 ns                 ;
; 0.800 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_initial                                                                                                          ; Sdram_Control_4Port:sdram1|command:command1|CS_N[0]                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.816 ns                 ;
; 0.800 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[11]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[3]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.816 ns                 ;
; 0.800 ns                                ; Sdram_Control_4Port:sdram1|command:command1|SA[1]                                                                                                               ; Sdram_Control_4Port:sdram1|SA[1]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.816 ns                 ;
; 0.800 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[2]                                                                                                         ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[1]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.816 ns                 ;
; 0.801 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rw_flag                                                                                                             ; Sdram_Control_4Port:sdram1|command:command1|WE_N                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.801 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rw_shift[1]                                                                                                         ; Sdram_Control_4Port:sdram0|command:command1|rw_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[17]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[9]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[14]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[6]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[0]                                                                                                               ; Sdram_Control_4Port:sdram0|SA[0]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[21]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[21]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[11]                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[11]                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.803 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff                        ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.819 ns                 ;
; 0.804 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[8]                                                                                                                         ; Sdram_Control_4Port:sdram1|rWR1_ADDR[8]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.820 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_precharge                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|BA[1]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_precharge                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|BA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|REF_REQ                                                                                                   ; Sdram_Control_4Port:sdram1|command:command1|CM_ACK                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[14]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[14]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[9]                                                                                                                         ; Sdram_Control_4Port:sdram1|rRD1_ADDR[9]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[11]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[11]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[21]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[21]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                             ;                                                                                                                                                                                           ;                                                    ;                                                    ;                            ;                            ;                          ;
 


 
; Clock Hold: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
 
; Minimum Slack                           ; From                                                                                                                                              ; To                                                                                                                                                                                       ; From Clock                                     ; To Clock                                       ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
 
; 0.520 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[0]                  ; Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[0]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.536 ns                 ;
; 0.522 ns                                ; Dilation:dilation0|X6[6]                                                                                                                          ; Dilation:dilation0|X5[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Dilation:dilation0|X5[5]                                                                                                                          ; Dilation:dilation0|X4[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Dilation:dilation0|X5[4]                                                                                                                          ; Dilation:dilation0|X4[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Sobel:sobel0|MAC_3:y1|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[4]                  ; Sobel:sobel0|MAC_3:x1|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[4]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Sobel:sobel0|MAC_3:y2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[7]                  ; Sobel:sobel0|MAC_3:x2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[7]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Sobel:sobel0|MAC_3:y2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[3]                  ; Sobel:sobel0|MAC_3:x2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[3]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Sobel:sobel0|MAC_3:y2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[1]                  ; Sobel:sobel0|MAC_3:x2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[1]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[4]                  ; Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[4]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.523 ns                                ; Dilation:dilation0|X3[8]                                                                                                                          ; Dilation:dilation0|X2[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.539 ns                 ;
; 0.523 ns                                ; Dilation:dilation0|X9[8]                                                                                                                          ; Dilation:dilation0|X8[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.539 ns                 ;
; 0.523 ns                                ; Dilation:dilation0|X9[6]                                                                                                                          ; Dilation:dilation0|X8[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.539 ns                 ;
; 0.523 ns                                ; Dilation:dilation0|X9[5]                                                                                                                          ; Dilation:dilation0|X8[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.539 ns                 ;
; 0.523 ns                                ; Sobel:sobel0|MAC_3:y2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[4]                  ; Sobel:sobel0|MAC_3:x2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[4]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.539 ns                 ;
; 0.523 ns                                ; Sobel:sobel0|MAC_3:y2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[2]                  ; Sobel:sobel0|MAC_3:x2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[2]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.539 ns                 ;
; 0.523 ns                                ; Dilation:dilation0|X9[2]                                                                                                                          ; Dilation:dilation0|X8[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.539 ns                 ;
; 0.525 ns                                ; Dilation:dilation0|X5[8]                                                                                                                          ; Dilation:dilation0|X4[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.541 ns                 ;
; 0.525 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[1]                  ; Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[1]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.541 ns                 ;
; 0.526 ns                                ; Dilation:dilation0|X6[9]                                                                                                                          ; Dilation:dilation0|X5[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.542 ns                 ;
; 0.526 ns                                ; Dilation:dilation0|X6[5]                                                                                                                          ; Dilation:dilation0|X5[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.542 ns                 ;
; 0.526 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[3]                  ; Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[3]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.542 ns                 ;
; 0.527 ns                                ; Dilation:dilation0|X6[8]                                                                                                                          ; Dilation:dilation0|X5[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.543 ns                 ;
; 0.527 ns                                ; Dilation:dilation0|X5[2]                                                                                                                          ; Dilation:dilation0|X4[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.543 ns                 ;
; 0.530 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[5]                  ; Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[5]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.546 ns                 ;
; 0.531 ns                                ; Dilation:dilation0|X3[3]                                                                                                                          ; Dilation:dilation0|X2[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Dilation:dilation0|X5[9]                                                                                                                          ; Dilation:dilation0|X4[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Dilation:dilation0|X3[4]                                                                                                                          ; Dilation:dilation0|X2[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.532 ns                                ; Dilation:dilation0|X5[3]                                                                                                                          ; Dilation:dilation0|X4[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.548 ns                 ;
; 0.532 ns                                ; Dilation:dilation0|X5[7]                                                                                                                          ; Dilation:dilation0|X4[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.548 ns                 ;
; 0.533 ns                                ; Dilation:dilation0|X6[3]                                                                                                                          ; Dilation:dilation0|X5[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.549 ns                 ;
; 0.537 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.553 ns                 ;
; 0.541 ns                                ; Dilation:dilation0|X9[4]                                                                                                                          ; Dilation:dilation0|X8[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.557 ns                 ;
; 0.543 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.559 ns                 ;
; 0.646 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[12] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.695 ns                 ;
; 0.647 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[15] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a5~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.696 ns                 ;
; 0.648 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[9]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[5]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a5~porta_datain_reg1                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.649 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[7]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a7~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.698 ns                 ;
; 0.654 ns                                ; touch_tcon:vga0|mvd                                                                                                                               ; touch_tcon:vga0|oVD                                                                                                                                                                      ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.018 ns                   ; 0.672 ns                 ;
; 0.654 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[16] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a6~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.703 ns                 ;
; 0.654 ns                                ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][2]                                                                        ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[1][2]                                                                                                               ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.670 ns                 ;
; 0.657 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[6]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a6~porta_datain_reg1                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.706 ns                 ;
; 0.657 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[2]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_datain_reg1                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.706 ns                 ;
; 0.664 ns                                ; Dilation:dilation0|X8[5]                                                                                                                          ; Dilation:dilation0|X7[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.680 ns                 ;
; 0.664 ns                                ; Sobel:sobel0|MAC_3:y2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[0]                  ; Sobel:sobel0|MAC_3:x2|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[0]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.680 ns                 ;
; 0.664 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[7]                  ; Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[7]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.680 ns                 ;
; 0.664 ns                                ; Dilation:dilation0|X2[2]                                                                                                                          ; Dilation:dilation0|X1[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.680 ns                 ;
; 0.665 ns                                ; Dilation:dilation0|X2[7]                                                                                                                          ; Dilation:dilation0|X1[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.681 ns                 ;
; 0.665 ns                                ; Dilation:dilation0|X8[6]                                                                                                                          ; Dilation:dilation0|X7[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.681 ns                 ;
; 0.665 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[4]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.714 ns                 ;
; 0.665 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[2]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~portb_address_reg2                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.067 ns                   ; 0.732 ns                 ;
; 0.666 ns                                ; Dilation:dilation0|X2[8]                                                                                                                          ; Dilation:dilation0|X1[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.682 ns                 ;
; 0.666 ns                                ; Dilation:dilation0|X2[6]                                                                                                                          ; Dilation:dilation0|X1[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.682 ns                 ;
; 0.667 ns                                ; Dilation:dilation0|X8[8]                                                                                                                          ; Dilation:dilation0|X7[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.683 ns                 ;
; 0.667 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[6]                  ; Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[6]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.683 ns                 ;
; 0.667 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[2]                  ; Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[2]                                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.683 ns                 ;
; 0.668 ns                                ; Dilation:dilation0|X2[9]                                                                                                                          ; Dilation:dilation0|X1[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.684 ns                 ;
; 0.668 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[19] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.717 ns                 ;
; 0.670 ns                                ; Dilation:dilation0|X2[5]                                                                                                                          ; Dilation:dilation0|X1[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.686 ns                 ;
; 0.671 ns                                ; Dilation:dilation0|X9[9]                                                                                                                          ; Dilation:dilation0|X8[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.687 ns                 ;
; 0.671 ns                                ; Dilation:dilation0|X3[5]                                                                                                                          ; Dilation:dilation0|X2[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.687 ns                 ;
; 0.672 ns                                ; Dilation:dilation0|X2[3]                                                                                                                          ; Dilation:dilation0|X1[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.688 ns                 ;
; 0.672 ns                                ; Dilation:dilation0|X3[9]                                                                                                                          ; Dilation:dilation0|X2[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.688 ns                 ;
; 0.673 ns                                ; Dilation:dilation0|X2[4]                                                                                                                          ; Dilation:dilation0|X1[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.689 ns                 ;
; 0.674 ns                                ; Dilation:dilation0|X8[4]                                                                                                                          ; Dilation:dilation0|X7[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.690 ns                 ;
; 0.675 ns                                ; Dilation:dilation0|X8[9]                                                                                                                          ; Dilation:dilation0|X7[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.691 ns                 ;
; 0.676 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[6]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~portb_address_reg6                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.065 ns                   ; 0.741 ns                 ;
; 0.676 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[1]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~portb_address_reg1                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.067 ns                   ; 0.743 ns                 ;
; 0.679 ns                                ; Dilation:dilation0|X6[4]                                                                                                                          ; Dilation:dilation0|X5[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.695 ns                 ;
; 0.687 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.039 ns                   ; 0.726 ns                 ;
; 0.691 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.707 ns                 ;
; 0.695 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.711 ns                 ;
; 0.696 ns                                ; touch_tcon:vga0|mden                                                                                                                              ; touch_tcon:vga0|oDEN                                                                                                                                                                     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.019 ns                   ; 0.715 ns                 ;
; 0.696 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[0]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~porta_address_reg0                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.039 ns                   ; 0.735 ns                 ;
; 0.698 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[22] ; Dilation:dilation0|X3[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.028 ns                   ; 0.726 ns                 ;
; 0.702 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[9]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~portb_address_reg9                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.065 ns                   ; 0.767 ns                 ;
; 0.702 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[8]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~portb_address_reg8                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.065 ns                   ; 0.767 ns                 ;
; 0.702 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[2]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~porta_address_reg2                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.039 ns                   ; 0.741 ns                 ;
; 0.703 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.039 ns                   ; 0.742 ns                 ;
; 0.703 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[2]  ; Dilation:dilation0|X9[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.028 ns                   ; 0.731 ns                 ;
; 0.704 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[6]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~porta_address_reg6                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.037 ns                   ; 0.741 ns                 ;
; 0.704 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[1]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~porta_address_reg1                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.039 ns                   ; 0.743 ns                 ;
; 0.704 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.038 ns                   ; 0.742 ns                 ;
; 0.705 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[27] ; Dilation:dilation0|X3[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.028 ns                   ; 0.733 ns                 ;
; 0.706 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[6]  ; Dilation:dilation0|X9[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.028 ns                   ; 0.734 ns                 ;
; 0.706 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.038 ns                   ; 0.744 ns                 ;
; 0.708 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[28] ; Dilation:dilation0|X3[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.028 ns                   ; 0.736 ns                 ;
; 0.708 ns                                ; Dilation:dilation0|X6[2]                                                                                                                          ; Dilation:dilation0|X5[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.722 ns                 ;
; 0.708 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.038 ns                   ; 0.746 ns                 ;
; 0.708 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.038 ns                   ; 0.746 ns                 ;
; 0.709 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[26] ; Dilation:dilation0|X3[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.028 ns                   ; 0.737 ns                 ;
; 0.709 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[25] ; Dilation:dilation0|X3[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.027 ns                   ; 0.736 ns                 ;
; 0.710 ns                                ; Dilation:dilation0|X6[7]                                                                                                                          ; Dilation:dilation0|X5[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.724 ns                 ;
; 0.710 ns                                ; Dilation:dilation0|X3[2]                                                                                                                          ; Dilation:dilation0|X2[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.724 ns                 ;
; 0.711 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[15] ; Dilation:dilation0|X6[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.027 ns                   ; 0.738 ns                 ;
; 0.712 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[5]  ; Dilation:dilation0|X9[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.027 ns                   ; 0.739 ns                 ;
; 0.712 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.038 ns                   ; 0.750 ns                 ;
; 0.713 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.727 ns                 ;
; 0.714 ns                                ; Dilation:dilation0|X3[7]                                                                                                                          ; Dilation:dilation0|X2[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.728 ns                 ;
; 0.714 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.728 ns                 ;
; 0.718 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[5]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~portb_address_reg5                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.065 ns                   ; 0.783 ns                 ;
; 0.720 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[4]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~portb_address_reg4                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.065 ns                   ; 0.785 ns                 ;
; 0.721 ns                                ; Dilation:dilation0|X9[6]                                                                                                                          ; Dilation:dilation0|oDATA[6]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.735 ns                 ;
; 0.722 ns                                ; Dilation:dilation0|X9[7]                                                                                                                          ; Dilation:dilation0|oDATA[7]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.736 ns                 ;
; 0.722 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.736 ns                 ;
; 0.724 ns                                ; Dilation:dilation0|X9[7]                                                                                                                          ; Dilation:dilation0|X8[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.738 ns                 ;
; 0.724 ns                                ; Dilation:dilation0|X3[6]                                                                                                                          ; Dilation:dilation0|X2[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.738 ns                 ;
; 0.724 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[3]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~portb_address_reg3                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.065 ns                   ; 0.789 ns                 ;
; 0.730 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[9]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~porta_address_reg9                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.037 ns                   ; 0.767 ns                 ;
; 0.730 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[8]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~porta_address_reg8                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.037 ns                   ; 0.767 ns                 ;
; 0.746 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[5]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~porta_address_reg5                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.037 ns                   ; 0.783 ns                 ;
; 0.748 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[4]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~porta_address_reg4                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.037 ns                   ; 0.785 ns                 ;
; 0.752 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[3]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|altsyncram_mj81:altsyncram2|ram_block3a4~porta_address_reg3                             ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.037 ns                   ; 0.789 ns                 ;
; 0.784 ns                                ; Dilation:dilation0|X1[9]                                                                                                                          ; Dilation:dilation0|oDATA[9]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.800 ns                 ;
; 0.785 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.801 ns                 ;
; 0.786 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.790 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe6                                                        ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe5                                                                                               ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.806 ns                 ;
; 0.793 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe35                                                       ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe47                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.809 ns                 ;
; 0.794 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe30                                                       ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe41                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.810 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.796 ns                                ; Sobel:sobel0|PA_3:pa0|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe1~_Duplicate_4                                           ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][0]                                                                                                               ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.796 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe20                                                       ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe26                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.796 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe4                                                        ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe2                                                                                               ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.797 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe22                                                       ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe29                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.813 ns                 ;
; 0.797 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.813 ns                 ;
; 0.799 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff         ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.815 ns                 ;
; 0.801 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe32                                                       ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe44                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.801 ns                                ; touch_tcon:vga0|x_cnt[9]                                                                                                                          ; touch_tcon:vga0|x_cnt[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.808 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[9]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[9]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.824 ns                 ;
; 0.809 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.809 ns                                ; touch_tcon:vga0|x_cnt[7]                                                                                                                          ; touch_tcon:vga0|x_cnt[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.811 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff         ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.827 ns                 ;
; 0.812 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[9]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[9]                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.828 ns                 ;
; 0.812 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.828 ns                 ;
; 0.813 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; touch_tcon:vga0|y_cnt[7]                                                                                                                          ; touch_tcon:vga0|y_cnt[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; touch_tcon:vga0|y_cnt[5]                                                                                                                          ; touch_tcon:vga0|y_cnt[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.816 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[5]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[5]                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.816 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[5]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[5]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.816 ns                                ; Dilation:dilation0|X8[2]                                                                                                                          ; Dilation:dilation0|X7[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.830 ns                 ;
; 0.816 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.816 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.817 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[7]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[7]                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.833 ns                 ;
; 0.817 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[3]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[3]                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.833 ns                 ;
; 0.817 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[0]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[0]                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.833 ns                 ;
; 0.817 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[7]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[7]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.833 ns                 ;
; 0.817 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[3]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[3]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.833 ns                 ;
; 0.817 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[0]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[0]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.833 ns                 ;
; 0.818 ns                                ; touch_tcon:vga0|x_cnt[0]                                                                                                                          ; touch_tcon:vga0|x_cnt[0]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.834 ns                 ;
; 0.819 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.835 ns                 ;
; 0.822 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.822 ns                                ; touch_tcon:vga0|x_cnt[3]                                                                                                                          ; touch_tcon:vga0|x_cnt[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.822 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.822 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.826 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.842 ns                 ;
; 0.827 ns                                ; Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe22                                                       ; Sobel:sobel0|PA_3:pa0|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe29                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.843 ns                 ;
; 0.827 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.843 ns                 ;
; 0.833 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe37                                                       ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe50                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.849 ns                 ;
; 0.834 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe8                                                        ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe8                                                                                               ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.850 ns                 ;
; 0.835 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe28                                                       ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe38                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe14                                                       ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe17                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe10                                                       ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe11                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.836 ns                                ; Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|dffe24                                                       ; Sobel:sobel0|PA_3:pa1|parallel_add:parallel_add_component|par_add_65f:auto_generated|dffe32                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.852 ns                 ;
; 0.838 ns                                ; Dilation:dilation0|X9[9]                                                                                                                          ; Dilation:dilation0|oDATA[9]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; touch_tcon:vga0|x_cnt[8]                                                                                                                          ; touch_tcon:vga0|x_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; touch_tcon:vga0|x_cnt[6]                                                                                                                          ; touch_tcon:vga0|x_cnt[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; touch_tcon:vga0|x_cnt[4]                                                                                                                          ; touch_tcon:vga0|x_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.839 ns                                ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][1]                                                                        ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[1][1]                                                                                                               ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.841 ns                                ; touch_tcon:vga0|y_cnt[6]                                                                                                                          ; touch_tcon:vga0|y_cnt[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.857 ns                 ;
; 0.841 ns                                ; touch_tcon:vga0|y_cnt[8]                                                                                                                          ; touch_tcon:vga0|y_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.857 ns                 ;
; 0.842 ns                                ; touch_tcon:vga0|y_cnt[1]                                                                                                                          ; touch_tcon:vga0|y_cnt[1]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.844 ns                                ; Dilation:dilation0|X8[7]                                                                                                                          ; Dilation:dilation0|X7[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.860 ns                 ;
; 0.844 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[16] ; Dilation:dilation0|X6[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.028 ns                   ; 0.872 ns                 ;
; 0.844 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[12] ; Dilation:dilation0|X6[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.028 ns                   ; 0.872 ns                 ;
; 0.845 ns                                ; Dilation:dilation0|X5[6]                                                                                                                          ; Dilation:dilation0|X4[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.859 ns                 ;
; 0.845 ns                                ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[0][0]                                                                        ; Sobel:sobel0|SQRT:sqrt0|altsqrt:altsqrt_component|dffpipe:a_delay|sr[1][0]                                                                                                               ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; touch_tcon:vga0|y_cnt[4]                                                                                                                          ; touch_tcon:vga0|y_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.846 ns                                ; Dilation:dilation0|X8[3]                                                                                                                          ; Dilation:dilation0|X7[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.019 ns                   ; 0.865 ns                 ;
; 0.846 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.849 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[2]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[2]                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[2]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[2]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[1]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[1]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.850 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[1]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[1]                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.850 ns                                ; touch_tcon:vga0|x_cnt[2]                                                                                                                          ; touch_tcon:vga0|x_cnt[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.850 ns                                ; touch_tcon:vga0|x_cnt[1]                                                                                                                          ; touch_tcon:vga0|x_cnt[1]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.850 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.850 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.851 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[4]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[4]                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.867 ns                 ;
; 0.851 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[4]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[4]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.867 ns                 ;
; 0.851 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.867 ns                 ;
; 0.852 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[6]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[6]                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.868 ns                 ;
; 0.853 ns                                ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[8]                         ; Sobel:sobel0|LineBuffer_3:b0|altshift_taps:altshift_taps_component|shift_taps_lhn:auto_generated|cntr_opf:cntr1|safe_q[8]                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.869 ns                 ;
; 0.853 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[8]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[8]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.869 ns                 ;
; 0.853 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.869 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.855 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.871 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                               ;                                                                                                                                                                                          ;                                                ;                                                ;                            ;                            ;                          ;
 


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'GPIO_CLKIN_N1'                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                           ; From                                                                                                                                           ; To                                                                                                                                                                                        ; From Clock    ; To Clock      ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+-----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+----------------------------+----------------------------+--------------------------+
; 0.391 ns                                ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                 ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; CCD_Capture:capture0|mSTART                                                                                                                    ; CCD_Capture:capture0|mSTART                                                                                                                                                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; CCD_Capture:capture0|Frame_Cont[0]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[0]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.646 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[20]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.695 ns                 ;
; 0.646 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[16]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a3~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.695 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[22]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a10~porta_datain_reg3                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[21]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a8~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[18]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a6~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[17]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a4~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[5]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a4~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.649 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[13]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a11~porta_datain_reg2                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.698 ns                 ;
; 0.652 ns                                ; RAW2RGB:raw0|wData1_d2[2]                                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.668 ns                 ;
; 0.653 ns                                ; RAW2RGB:raw0|wData1_d2[3]                                                                                                                      ; RAW2RGB:raw0|rRed[3]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.669 ns                 ;
; 0.654 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[9]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a8~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.703 ns                 ;
; 0.654 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[14]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a2~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.703 ns                 ;
; 0.660 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[12]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a0~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.709 ns                 ;
; 0.663 ns                                ; RAW2RGB:raw0|wData1_d1[8]                                                                                                                      ; RAW2RGB:raw0|rBlue[8]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.680 ns                 ;
; 0.666 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[0]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a0~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.715 ns                 ;
; 0.675 ns                                ; RAW2RGB:raw0|wData1_d1[8]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[8]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.691 ns                 ;
; 0.677 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[0]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a11~portb_address_reg0                              ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.068 ns                   ; 0.745 ns                 ;
; 0.678 ns                                ; RAW2RGB:raw0|wData0_d1[10]                                                                                                                     ; RAW2RGB:raw0|wData0_d2[10]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.694 ns                 ;
; 0.678 ns                                ; RAW2RGB:raw0|wData0_d1[7]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[7]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.694 ns                 ;
; 0.678 ns                                ; RAW2RGB:raw0|wData0_d1[4]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[4]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.694 ns                 ;
; 0.679 ns                                ; RAW2RGB:raw0|wData2_d1[2]                                                                                                                      ; RAW2RGB:raw0|wData2_d2[2]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.695 ns                 ;
; 0.680 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a11~portb_address_reg1                              ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.068 ns                   ; 0.748 ns                 ;
; 0.681 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg5 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.740 ns                 ;
; 0.682 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg2 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.741 ns                 ;
; 0.685 ns                                ; RAW2RGB:raw0|wData0_d1[6]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[6]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.701 ns                 ;
; 0.691 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg7 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.750 ns                 ;
; 0.691 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg3 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.750 ns                 ;
; 0.693 ns                                ; RAW2RGB:raw0|wData2_d1[6]                                                                                                                      ; RAW2RGB:raw0|wData2_d2[6]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.709 ns                 ;
; 0.697 ns                                ; RAW2RGB:raw0|wData2_d1[3]                                                                                                                      ; RAW2RGB:raw0|wData2_d2[3]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.713 ns                 ;
; 0.699 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[2]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a11~porta_address_reg2                              ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.040 ns                   ; 0.739 ns                 ;
; 0.699 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[1]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.715 ns                 ;
; 0.700 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg4 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.759 ns                 ;
; 0.704 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[1]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.720 ns                 ;
; 0.720 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a11~porta_address_reg1                              ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.040 ns                   ; 0.760 ns                 ;
; 0.722 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[8]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.739 ns                 ;
; 0.727 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[0]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.744 ns                 ;
; 0.729 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[3]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.746 ns                 ;
; 0.729 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[8]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.746 ns                 ;
; 0.733 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[2]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.750 ns                 ;
; 0.739 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[0]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.756 ns                 ;
; 0.755 ns                                ; RAW2RGB:raw0|wData1_d1[2]                                                                                                                      ; RAW2RGB:raw0|rBlue[2]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.771 ns                 ;
; 0.758 ns                                ; RAW2RGB:raw0|wData1_d1[2]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[2]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.774 ns                 ;
; 0.784 ns                                ; RAW2RGB:raw0|wData2_d2[10]                                                                                                                     ; RAW2RGB:raw0|rGreen[11]                                                                                                                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.800 ns                 ;
; 0.786 ns                                ; RAW2RGB:raw0|wData2_d2[8]                                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.787 ns                                ; RAW2RGB:raw0|wData0_d2[2]                                                                                                                      ; RAW2RGB:raw0|rRed[2]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.803 ns                 ;
; 0.788 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff      ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.804 ns                 ;
; 0.789 ns                                ; RAW2RGB:raw0|wData0_d2[5]                                                                                                                      ; RAW2RGB:raw0|rRed[5]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.790 ns                                ; RAW2RGB:raw0|wData0_d2[8]                                                                                                                      ; RAW2RGB:raw0|rRed[8]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.806 ns                 ;
; 0.792 ns                                ; RAW2RGB:raw0|wData0_d2[6]                                                                                                                      ; RAW2RGB:raw0|rRed[6]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.808 ns                 ;
; 0.799 ns                                ; CCD_Capture:capture0|Y_Cont[0]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[0]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.815 ns                 ;
; 0.799 ns                                ; CCD_Capture:capture0|Frame_Cont[16]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[16]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.815 ns                 ;
; 0.802 ns                                ; RAW2RGB:raw0|wData1_d2[7]                                                                                                                      ; RAW2RGB:raw0|rRed[7]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.803 ns                                ; RAW2RGB:raw0|wData1_d2[4]                                                                                                                      ; RAW2RGB:raw0|rGreen[5]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.819 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|X_Cont[1]                                                                                                                 ; CCD_Capture:capture0|X_Cont[1]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|Frame_Cont[31]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[31]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|Frame_Cont[17]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[17]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[9]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[9]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[11]                                                                                                                ; CCD_Capture:capture0|Y_Cont[11]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[14]                                                                                                                ; CCD_Capture:capture0|Y_Cont[14]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[13]                                                                                                                ; CCD_Capture:capture0|Y_Cont[13]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[15]                                                                                                                ; CCD_Capture:capture0|Y_Cont[15]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[11]                                                                                                                ; CCD_Capture:capture0|X_Cont[11]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[13]                                                                                                                ; CCD_Capture:capture0|X_Cont[13]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[7]                                                                                                                 ; CCD_Capture:capture0|X_Cont[7]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[2]                                                                                                                 ; CCD_Capture:capture0|X_Cont[2]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[15]                                                                                                                ; CCD_Capture:capture0|X_Cont[15]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[14]                                                                                                                ; CCD_Capture:capture0|X_Cont[14]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[4]                                                                                                                 ; CCD_Capture:capture0|X_Cont[4]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[9]                                                                                                                 ; CCD_Capture:capture0|X_Cont[9]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[30]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[30]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[29]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[29]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[27]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[27]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[25]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[25]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[23]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[23]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[20]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[20]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[18]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[18]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[15]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[15]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[14]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[14]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[13]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[13]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.808 ns                                ; RAW2RGB:raw0|wData1_d2[5]                                                                                                                      ; RAW2RGB:raw0|rRed[5]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.824 ns                 ;
; 0.808 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.824 ns                 ;
; 0.809 ns                                ; RAW2RGB:raw0|wData1_d2[5]                                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.810 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.812 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.828 ns                 ;
; 0.813 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[9]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[9]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[7]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[7]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; CCD_Capture:capture0|Y_Cont[1]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[1]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.814 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; CCD_Capture:capture0|Y_Cont[7]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[7]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; CCD_Capture:capture0|Y_Cont[4]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[4]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; CCD_Capture:capture0|Y_Cont[2]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[2]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.815 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.831 ns                 ;
; 0.818 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.834 ns                 ;
; 0.820 ns                                ; RAW2RGB:raw0|wData1_d1[10]                                                                                                                     ; RAW2RGB:raw0|wData1_d2[10]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.836 ns                 ;
; 0.820 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[0]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[0]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.836 ns                 ;
; 0.821 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[2]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[2]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.837 ns                 ;
; 0.821 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.837 ns                 ;
; 0.822 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[5]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[5]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.822 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.825 ns                                ; RAW2RGB:raw0|wData1_d1[7]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[7]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.841 ns                 ;
; 0.825 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.841 ns                 ;
; 0.827 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.843 ns                 ;
; 0.829 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.845 ns                 ;
; 0.829 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[9]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.846 ns                 ;
; 0.830 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff      ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.846 ns                 ;
; 0.830 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[5]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.846 ns                 ;
; 0.831 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.847 ns                 ;
; 0.834 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.850 ns                 ;
; 0.835 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.836 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.852 ns                 ;
; 0.838 ns                                ; RAW2RGB:raw0|wData1_d2[9]                                                                                                                      ; RAW2RGB:raw0|rRed[9]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[12]                                                                                                                ; CCD_Capture:capture0|Y_Cont[12]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[10]                                                                                                                ; CCD_Capture:capture0|Y_Cont[10]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[8]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[8]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[3]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[3]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[10]                                                                                                                ; CCD_Capture:capture0|X_Cont[10]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[12]                                                                                                                ; CCD_Capture:capture0|X_Cont[12]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[3]                                                                                                                 ; CCD_Capture:capture0|X_Cont[3]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[8]                                                                                                                 ; CCD_Capture:capture0|X_Cont[8]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[28]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[28]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[26]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[26]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[19]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[19]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[12]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[12]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.839 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Y_Cont[6]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[6]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|X_Cont[6]                                                                                                                 ; CCD_Capture:capture0|X_Cont[6]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|X_Cont[5]                                                                                                                 ; CCD_Capture:capture0|X_Cont[5]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Frame_Cont[22]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[22]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Frame_Cont[21]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[21]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.842 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.845 ns                                ; RAW2RGB:raw0|wData1_d2[11]                                                                                                                     ; RAW2RGB:raw0|rRed[11]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.846 ns                                ; RAW2RGB:raw0|wData1_d1[11]                                                                                                                     ; RAW2RGB:raw0|wData1_d2[11]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.847 ns                                ; CCD_Capture:capture0|Y_Cont[5]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[5]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.863 ns                 ;
; 0.848 ns                                ; RAW2RGB:raw0|wData1_d1[9]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[9]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.864 ns                 ;
; 0.848 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.864 ns                 ;
; 0.848 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.864 ns                 ;
; 0.850 ns                                ; RAW2RGB:raw0|wData0_d1[11]                                                                                                                     ; RAW2RGB:raw0|wData0_d2[11]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.850 ns                                ; RAW2RGB:raw0|wData1_d1[11]                                                                                                                     ; RAW2RGB:raw0|rBlue[11]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.852 ns                                ; RAW2RGB:raw0|wData0_d1[2]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[2]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.868 ns                 ;
; 0.852 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.868 ns                 ;
; 0.853 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[4]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[4]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.869 ns                 ;
; 0.853 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[3]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[3]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.869 ns                 ;
; 0.853 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.869 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.856 ns                                ; RAW2RGB:raw0|wData1_d1[4]                                                                                                                      ; RAW2RGB:raw0|rBlue[4]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.872 ns                 ;
; 0.856 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[9]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.873 ns                 ;
; 0.857 ns                                ; RAW2RGB:raw0|wData0_d1[3]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[3]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.873 ns                 ;
; 0.857 ns                                ; RAW2RGB:raw0|wData1_d1[3]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[3]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.873 ns                 ;
; 0.860 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.876 ns                 ;
; 0.861 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.877 ns                 ;
; 0.862 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.878 ns                 ;
; 0.862 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.878 ns                 ;
; 0.863 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.879 ns                 ;
; 0.865 ns                                ; RAW2RGB:raw0|wData1_d1[4]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[4]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.881 ns                 ;
; 0.865 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.881 ns                 ;
; 0.865 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[4]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.882 ns                 ;
; 0.866 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.882 ns                 ;
; 0.866 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.882 ns                 ;
; 0.868 ns                                ; RAW2RGB:raw0|wData2_d1[8]                                                                                                                      ; RAW2RGB:raw0|wData2_d2[8]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.884 ns                 ;
; 0.868 ns                                ; RAW2RGB:raw0|wData2_d1[7]                                                                                                                      ; RAW2RGB:raw0|wData2_d2[7]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.884 ns                 ;
; 0.868 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[5]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.884 ns                 ;
; 0.872 ns                                ; RAW2RGB:raw0|wData2_d1[4]                                                                                                                      ; RAW2RGB:raw0|wData2_d2[4]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.888 ns                 ;
; 0.872 ns                                ; RAW2RGB:raw0|wData0_d1[9]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[9]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.888 ns                 ;
; 0.872 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[2]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.889 ns                 ;
; 0.877 ns                                ; RAW2RGB:raw0|wData0_d1[5]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[5]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.893 ns                 ;
; 0.889 ns                                ; RAW2RGB:raw0|wData2_d1[11]                                                                                                                     ; RAW2RGB:raw0|wData2_d2[11]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.905 ns                 ;
; 0.897 ns                                ; CCD_Capture:capture0|mCCD_DATA[7]                                                                                                              ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_datain_reg0                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.029 ns                   ; 0.926 ns                 ;
; 0.902 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[10]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a10~porta_datain_reg1                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.951 ns                 ;
; 0.903 ns                                ; CCD_Capture:capture0|mCCD_DATA[9]                                                                                                              ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a8~porta_datain_reg1                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.031 ns                   ; 0.934 ns                 ;
; 0.909 ns                                ; RAW2RGB:raw0|wData0_d2[11]                                                                                                                     ; RAW2RGB:raw0|rRed[11]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.925 ns                 ;
; 0.910 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[2]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a2~porta_datain_reg1                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.959 ns                 ;
; 0.911 ns                                ; CCD_Capture:capture0|mCCD_DATA[8]                                                                                                              ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a8~porta_datain_reg0                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.031 ns                   ; 0.942 ns                 ;
; 0.916 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[6]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a6~porta_datain_reg1                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.965 ns                 ;
; 0.920 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[15]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a3~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.058 ns                   ; 0.978 ns                 ;
; 0.922 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg0 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.981 ns                 ;
; 0.928 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg1 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.987 ns                 ;
; 0.928 ns                                ; RAW2RGB:raw0|wData0_d2[10]                                                                                                                     ; RAW2RGB:raw0|rRed[10]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.944 ns                 ;
; 0.931 ns                                ; RAW2RGB:raw0|wData0_d2[7]                                                                                                                      ; RAW2RGB:raw0|rRed[7]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.947 ns                 ;
; 0.939 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[3]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a2~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.040 ns                   ; 0.979 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                            ;                                                                                                                                                                                           ;               ;               ;                            ;                            ;                          ;
+-----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+----------------------------+----------------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'iCLK_50'                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------------------+-----------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                           ; From                                                            ; To                                                              ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+-----------------------------------------+-----------------------------------------------------------------+-----------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; 0.391 ns                                ; rClk[0]                                                         ; rClk[0]                                                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SCLK           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SCLK           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO            ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|lut_index[0]                       ; lcd_3wire_config:lcd_config0|lut_index[0]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|m3wire_str                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Reset_Delay:reset0|Cont[0]                                      ; Reset_Delay:reset0|Cont[0]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Reset_Delay:reset0|oRST_2                                       ; Reset_Delay:reset0|oRST_2                                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.559 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.575 ns                 ;
; 0.563 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSCLK            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.579 ns                 ;
; 0.836 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.852 ns                 ;
; 0.856 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.872 ns                 ;
; 0.861 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 0.875 ns                 ;
; 0.865 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.881 ns                 ;
; 0.872 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.888 ns                 ;
; 0.976 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.992 ns                 ;
; 0.977 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.993 ns                 ;
; 1.045 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]               ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.246 ns                   ; 5.291 ns                 ;
; 1.049 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[20]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.066 ns                 ;
; 1.055 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]               ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[6]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.247 ns                   ; 5.302 ns                 ;
; 1.058 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.052 ns                   ; 1.110 ns                 ;
; 1.061 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.052 ns                   ; 1.113 ns                 ;
; 1.067 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[3]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.083 ns                 ;
; 1.091 ns                                ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; lcd_3wire_config:lcd_config0|m3wire_data[10]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.018 ns                   ; 1.109 ns                 ;
; 1.096 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[19]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.113 ns                 ;
; 1.098 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[16]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[16]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.115 ns                 ;
; 1.099 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.115 ns                 ;
; 1.100 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.116 ns                 ;
; 1.114 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[20]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.131 ns                 ;
; 1.123 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.139 ns                 ;
; 1.125 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[9]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.140 ns                 ;
; 1.128 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.145 ns                 ;
; 1.132 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[11]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 1.146 ns                 ;
; 1.133 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[6]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[6]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 1.147 ns                 ;
; 1.136 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[18]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[18]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 1.150 ns                 ;
; 1.138 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[23]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.155 ns                 ;
; 1.138 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[21]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.155 ns                 ;
; 1.139 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[22]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[22]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; -0.019 ns                  ; 1.120 ns                 ;
; 1.150 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]              ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.247 ns                   ; 5.397 ns                 ;
; 1.152 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]              ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.246 ns                   ; 5.398 ns                 ;
; 1.162 ns                                ; lcd_3wire_config:lcd_config0|lut_index[2]                       ; lcd_3wire_config:lcd_config0|m3wire_data[2]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.177 ns                 ;
; 1.164 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; -0.020 ns                  ; 1.144 ns                 ;
; 1.164 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[0]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; -0.020 ns                  ; 1.144 ns                 ;
; 1.164 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[1]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; -0.020 ns                  ; 1.144 ns                 ;
; 1.164 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[2]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; -0.020 ns                  ; 1.144 ns                 ;
; 1.164 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; -0.020 ns                  ; 1.144 ns                 ;
; 1.164 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; -0.020 ns                  ; 1.144 ns                 ;
; 1.164 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[5]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; -0.020 ns                  ; 1.144 ns                 ;
; 1.178 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]               ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.246 ns                   ; 5.424 ns                 ;
; 1.192 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|m3wire_str                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.208 ns                 ;
; 1.194 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.210 ns                 ;
; 1.197 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[2]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[2]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.213 ns                 ;
; 1.200 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[5]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[5]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.216 ns                 ;
; 1.200 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[20]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[20]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.216 ns                 ;
; 1.203 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[11] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[11] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.219 ns                 ;
; 1.204 ns                                ; lcd_3wire_config:lcd_config0|lut_index[2]                       ; lcd_3wire_config:lcd_config0|m3wire_data[12]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.221 ns                 ;
; 1.204 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[8]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[8]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.220 ns                 ;
; 1.207 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[14]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[14]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.223 ns                 ;
; 1.207 ns                                ; lcd_3wire_config:lcd_config0|lut_index[1]                       ; lcd_3wire_config:lcd_config0|lut_index[2]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.223 ns                 ;
; 1.208 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[3]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[3]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.224 ns                 ;
; 1.208 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[13] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[13] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.224 ns                 ;
; 1.209 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.225 ns                 ;
; 1.209 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[23]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.226 ns                 ;
; 1.210 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[12] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[12] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.226 ns                 ;
; 1.213 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.229 ns                 ;
; 1.213 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]               ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.246 ns                   ; 5.459 ns                 ;
; 1.213 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.230 ns                 ;
; 1.213 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.229 ns                 ;
; 1.214 ns                                ; lcd_3wire_config:lcd_config0|lut_index[1]                       ; lcd_3wire_config:lcd_config0|m3wire_data[12]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.231 ns                 ;
; 1.215 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[8]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[8]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.231 ns                 ;
; 1.216 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[4]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[4]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.232 ns                 ;
; 1.217 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.233 ns                 ;
; 1.219 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.235 ns                 ;
; 1.219 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[2]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[2]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.235 ns                 ;
; 1.220 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.251 ns                   ; 5.471 ns                 ;
; 1.220 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[20]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.251 ns                   ; 5.471 ns                 ;
; 1.220 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.251 ns                   ; 5.471 ns                 ;
; 1.220 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[18]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.251 ns                   ; 5.471 ns                 ;
; 1.220 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.251 ns                   ; 5.471 ns                 ;
; 1.220 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.251 ns                   ; 5.471 ns                 ;
; 1.220 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[6]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.251 ns                   ; 5.471 ns                 ;
; 1.221 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.237 ns                 ;
; 1.221 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|msetup_st.0100                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.237 ns                 ;
; 1.222 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[21]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[21]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.238 ns                 ;
; 1.224 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.020 ns                   ; 1.244 ns                 ;
; 1.226 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[8]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[8]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.242 ns                 ;
; 1.226 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[22]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[22]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.242 ns                 ;
; 1.226 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.242 ns                 ;
; 1.227 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.243 ns                 ;
; 1.227 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.243 ns                 ;
; 1.228 ns                                ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; lcd_3wire_config:lcd_config0|m3wire_data[14]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.018 ns                   ; 1.246 ns                 ;
; 1.228 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[5]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[5]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.244 ns                 ;
; 1.229 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[3]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[3]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.245 ns                 ;
; 1.229 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[6]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[6]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.245 ns                 ;
; 1.230 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[9]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[9]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.246 ns                 ;
; 1.230 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[1]           ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.246 ns                 ;
; 1.230 ns                                ; Reset_Delay:reset0|Cont[0]                                      ; Reset_Delay:reset0|Cont[1]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.246 ns                 ;
; 1.231 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.247 ns                 ;
; 1.231 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.247 ns                 ;
; 1.232 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[0]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[0]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.248 ns                 ;
; 1.233 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[0]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.249 ns                 ;
; 1.234 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.052 ns                   ; 1.286 ns                 ;
; 1.234 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.052 ns                   ; 1.286 ns                 ;
; 1.234 ns                                ; lcd_3wire_config:lcd_config0|lut_index[1]                       ; lcd_3wire_config:lcd_config0|lut_index[1]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.250 ns                 ;
; 1.235 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.251 ns                 ;
; 1.235 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.250 ns                 ;
; 1.235 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[9]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[9]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.251 ns                 ;
; 1.235 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[6]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[6]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.250 ns                   ; 5.486 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.250 ns                   ; 5.486 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.250 ns                   ; 5.486 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.250 ns                   ; 5.486 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.250 ns                   ; 5.486 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.250 ns                   ; 5.486 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[21]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[20]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[23]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[22]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[16]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[19]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[18]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[24]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[1]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[1]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.252 ns                 ;
; 1.237 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[16]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.252 ns                 ;
; 1.237 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[13]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.249 ns                   ; 5.486 ns                 ;
; 1.237 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[10] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[10] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.253 ns                 ;
; 1.238 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.254 ns                 ;
; 1.238 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[4]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[4]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.254 ns                 ;
; 1.238 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[1]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[1]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.254 ns                 ;
; 1.239 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.254 ns                 ;
; 1.239 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[14] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[14] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.255 ns                 ;
; 1.239 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0001                     ; lcd_3wire_config:lcd_config0|msetup_st.0010                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.255 ns                 ;
; 1.240 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[17]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.257 ns                 ;
; 1.240 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[0]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[0]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.256 ns                 ;
; 1.240 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[4]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[4]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.256 ns                 ;
; 1.241 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[19]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[19]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.257 ns                 ;
; 1.241 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.257 ns                 ;
; 1.242 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[20]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[20]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.258 ns                 ;
; 1.242 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.258 ns                 ;
; 1.243 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.259 ns                 ;
; 1.243 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[0]           ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[1]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.259 ns                 ;
; 1.243 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[5]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[5]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.259 ns                 ;
; 1.243 ns                                ; Reset_Delay:reset0|Cont[4]                                      ; Reset_Delay:reset0|Cont[4]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.259 ns                 ;
; 1.245 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.261 ns                 ;
; 1.245 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[16]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[16]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.261 ns                 ;
; 1.245 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.261 ns                 ;
; 1.246 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1           ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.048 ns                   ; 1.294 ns                 ;
; 1.246 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1           ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.048 ns                   ; 1.294 ns                 ;
; 1.246 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.262 ns                 ;
; 1.247 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[0]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[0]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.263 ns                 ;
; 1.248 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[2]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[2]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.264 ns                 ;
; 1.248 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.264 ns                 ;
; 1.248 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[12]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[12]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.264 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[5]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[4]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[1]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[0]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[3]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[2]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[9]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[8]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 1.268 ns                 ;
; 1.249 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.265 ns                 ;
; 1.250 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.266 ns                 ;
; 1.250 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[7]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[7]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.266 ns                 ;
; 1.251 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.267 ns                 ;
; 1.251 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]               ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.247 ns                   ; 5.498 ns                 ;
; 1.251 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.267 ns                 ;
; 1.251 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[11]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[11]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.267 ns                 ;
; 1.251 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.267 ns                 ;
; 1.252 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[5]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.268 ns                 ;
; 1.253 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]               ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.246 ns                   ; 5.499 ns                 ;
; 1.253 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[20]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.270 ns                 ;
; 1.253 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[24]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[24]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.269 ns                 ;
; 1.254 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[1]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[1]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.270 ns                 ;
; 1.255 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.271 ns                 ;
; 1.256 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[10]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[10]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.272 ns                 ;
; 1.257 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[19]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.251 ns                   ; 5.508 ns                 ;
; 1.257 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.251 ns                   ; 5.508 ns                 ;
; 1.257 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 4.251 ns                   ; 5.508 ns                 ;
; 1.257 ns                                ; Reset_Delay:reset0|Cont[21]                                     ; Reset_Delay:reset0|Cont[21]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.273 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)             ;                                                                 ;            ;          ;                            ;                            ;                          ;
+-----------------------------------------+-----------------------------------------------------------------+-----------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                         ;
+-----------+--------------+------------+-------------+-------------------------------------------------------+---------------+
; Slack     ; Required tsu ; Actual tsu ; From        ; To                                                    ; To Clock      ;
+-----------+--------------+------------+-------------+-------------------------------------------------------+---------------+
; -0.330 ns ; 1.000 ns     ; 1.330 ns   ; DRAM_DQ[30] ; Sdram_Control_4Port:sdram1|mDATAOUT[14]               ; iCLK_50_3     ;
; -0.317 ns ; 1.000 ns     ; 1.317 ns   ; DRAM_DQ[28] ; Sdram_Control_4Port:sdram1|mDATAOUT[12]               ; iCLK_50_3     ;
; -0.310 ns ; 1.000 ns     ; 1.310 ns   ; DRAM_DQ[29] ; Sdram_Control_4Port:sdram1|mDATAOUT[13]               ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[3]  ; Sdram_Control_4Port:sdram0|mDATAOUT[3]                ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[4]  ; Sdram_Control_4Port:sdram0|mDATAOUT[4]                ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[25] ; Sdram_Control_4Port:sdram1|mDATAOUT[9]                ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[24] ; Sdram_Control_4Port:sdram1|mDATAOUT[8]                ; iCLK_50_3     ;
; -0.286 ns ; 1.000 ns     ; 1.286 ns   ; DRAM_DQ[2]  ; Sdram_Control_4Port:sdram0|mDATAOUT[2]                ; iCLK_50_3     ;
; -0.276 ns ; 1.000 ns     ; 1.276 ns   ; DRAM_DQ[5]  ; Sdram_Control_4Port:sdram0|mDATAOUT[5]                ; iCLK_50_3     ;
; -0.270 ns ; 1.000 ns     ; 1.270 ns   ; DRAM_DQ[22] ; Sdram_Control_4Port:sdram1|mDATAOUT[6]                ; iCLK_50_3     ;
; -0.270 ns ; 1.000 ns     ; 1.270 ns   ; DRAM_DQ[21] ; Sdram_Control_4Port:sdram1|mDATAOUT[5]                ; iCLK_50_3     ;
; -0.270 ns ; 1.000 ns     ; 1.270 ns   ; DRAM_DQ[19] ; Sdram_Control_4Port:sdram1|mDATAOUT[3]                ; iCLK_50_3     ;
; -0.268 ns ; 1.000 ns     ; 1.268 ns   ; DRAM_DQ[23] ; Sdram_Control_4Port:sdram1|mDATAOUT[7]                ; iCLK_50_3     ;
; -0.267 ns ; 1.000 ns     ; 1.267 ns   ; DRAM_DQ[6]  ; Sdram_Control_4Port:sdram0|mDATAOUT[6]                ; iCLK_50_3     ;
; -0.267 ns ; 1.000 ns     ; 1.267 ns   ; DRAM_DQ[7]  ; Sdram_Control_4Port:sdram0|mDATAOUT[7]                ; iCLK_50_3     ;
; -0.262 ns ; 1.000 ns     ; 1.262 ns   ; DRAM_DQ[10] ; Sdram_Control_4Port:sdram0|mDATAOUT[10]               ; iCLK_50_3     ;
; -0.262 ns ; 1.000 ns     ; 1.262 ns   ; DRAM_DQ[9]  ; Sdram_Control_4Port:sdram0|mDATAOUT[9]                ; iCLK_50_3     ;
; -0.260 ns ; 1.000 ns     ; 1.260 ns   ; DRAM_DQ[20] ; Sdram_Control_4Port:sdram1|mDATAOUT[4]                ; iCLK_50_3     ;
; -0.256 ns ; 1.000 ns     ; 1.256 ns   ; DRAM_DQ[14] ; Sdram_Control_4Port:sdram0|mDATAOUT[14]               ; iCLK_50_3     ;
; -0.256 ns ; 1.000 ns     ; 1.256 ns   ; DRAM_DQ[13] ; Sdram_Control_4Port:sdram0|mDATAOUT[13]               ; iCLK_50_3     ;
; -0.254 ns ; 1.000 ns     ; 1.254 ns   ; DRAM_DQ[18] ; Sdram_Control_4Port:sdram1|mDATAOUT[2]                ; iCLK_50_3     ;
; -0.246 ns ; 1.000 ns     ; 1.246 ns   ; DRAM_DQ[12] ; Sdram_Control_4Port:sdram0|mDATAOUT[12]               ; iCLK_50_3     ;
; -0.229 ns ; 1.000 ns     ; 1.229 ns   ; DRAM_DQ[11] ; Sdram_Control_4Port:sdram0|mDATAOUT[11]               ; iCLK_50_3     ;
; -0.222 ns ; 1.000 ns     ; 1.222 ns   ; DRAM_DQ[8]  ; Sdram_Control_4Port:sdram0|mDATAOUT[8]                ; iCLK_50_3     ;
; 2.509 ns  ; 5.000 ns     ; 2.491 ns   ; GPIO_1[10]  ; rCCD_DATA[1]                                          ; GPIO_CLKIN_N1 ;
; 2.520 ns  ; 5.000 ns     ; 2.480 ns   ; GPIO_1[8]   ; rCCD_DATA[3]                                          ; GPIO_CLKIN_N1 ;
; 2.520 ns  ; 5.000 ns     ; 2.480 ns   ; GPIO_1[6]   ; rCCD_DATA[5]                                          ; GPIO_CLKIN_N1 ;
; 2.529 ns  ; 5.000 ns     ; 2.471 ns   ; GPIO_1[9]   ; rCCD_DATA[2]                                          ; GPIO_CLKIN_N1 ;
; 2.529 ns  ; 5.000 ns     ; 2.471 ns   ; GPIO_1[7]   ; rCCD_DATA[4]                                          ; GPIO_CLKIN_N1 ;
; 2.554 ns  ; 5.000 ns     ; 2.446 ns   ; GPIO_1[11]  ; rCCD_DATA[0]                                          ; GPIO_CLKIN_N1 ;
; 2.566 ns  ; 5.000 ns     ; 2.434 ns   ; GPIO_1[17]  ; rCCD_LVAL                                             ; GPIO_CLKIN_N1 ;
; 2.575 ns  ; 5.000 ns     ; 2.425 ns   ; GPIO_1[1]   ; rCCD_DATA[10]                                         ; GPIO_CLKIN_N1 ;
; 2.575 ns  ; 5.000 ns     ; 2.425 ns   ; GPIO_1[0]   ; rCCD_DATA[11]                                         ; GPIO_CLKIN_N1 ;
; 2.578 ns  ; 5.000 ns     ; 2.422 ns   ; GPIO_1[5]   ; rCCD_DATA[6]                                          ; GPIO_CLKIN_N1 ;
; 2.578 ns  ; 5.000 ns     ; 2.422 ns   ; GPIO_1[3]   ; rCCD_DATA[8]                                          ; GPIO_CLKIN_N1 ;
; 2.585 ns  ; 5.000 ns     ; 2.415 ns   ; GPIO_1[4]   ; rCCD_DATA[7]                                          ; GPIO_CLKIN_N1 ;
; 2.585 ns  ; 5.000 ns     ; 2.415 ns   ; GPIO_1[2]   ; rCCD_DATA[9]                                          ; GPIO_CLKIN_N1 ;
; 2.586 ns  ; 5.000 ns     ; 2.414 ns   ; GPIO_1[18]  ; rCCD_FVAL                                             ; GPIO_CLKIN_N1 ;
; N/A       ; None         ; 10.474 ns  ; iSW[14]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 10.275 ns  ; iSW[14]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 10.231 ns  ; iSW[15]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 10.164 ns  ; iSW[14]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 10.058 ns  ; iSW[14]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 10.030 ns  ; iSW[15]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.919 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.876 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.846 ns   ; iSW[6]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A       ; None         ; 9.846 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.824 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.818 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.807 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.796 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.787 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.777 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.765 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.664 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.642 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.633 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.631 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.631 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.607 ns   ; iSW[2]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A       ; None         ; 9.594 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.583 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.579 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.574 ns   ; iSW[4]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A       ; None         ; 9.574 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.566 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.564 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.507 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.506 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.485 ns   ; iSW[3]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A       ; None         ; 9.455 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.451 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.429 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.418 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.407 ns   ; iSW[5]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A       ; None         ; 9.349 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.335 ns   ; iSW[7]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A       ; None         ; 9.262 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.261 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.250 ns   ; iSW[8]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A       ; None         ; 9.167 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.120 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.115 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.086 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.860 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.860 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.839 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.839 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.820 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.802 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.802 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.798 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.797 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.678 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.658 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.646 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.613 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.613 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.598 ns   ; iSW[9]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A       ; None         ; 8.592 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.592 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.501 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.498 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.314 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.314 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.235 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.235 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.148 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.148 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.127 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.127 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.067 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.067 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.770 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.770 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.602 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.602 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A       ; None         ; 6.263 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A       ; None         ; 6.132 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A       ; None         ; 5.094 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A       ; None         ; 4.990 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A       ; None         ; 3.998 ns   ; iSW[17]     ; RAW2RGB:raw0|mirror_sw                                ; iCLK_50       ;
; N/A       ; None         ; 3.815 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[0] ; iCLK_50       ;
; N/A       ; None         ; 3.730 ns   ; iSW[17]     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]          ; iCLK_50       ;
; N/A       ; None         ; 2.906 ns   ; iKEY[2]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A       ; None         ; 2.639 ns   ; iKEY[3]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A       ; None         ; 0.754 ns   ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1 ; iCLK_50       ;
; N/A       ; None         ; 0.505 ns   ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2 ; iCLK_50       ;
; N/A       ; None         ; -0.319 ns  ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3 ; iCLK_50       ;
; N/A       ; None         ; -0.323 ns  ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4 ; iCLK_50       ;
+-----------+--------------+------------+-------------+-------------------------------------------------------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------+
; Slack                                   ; Required tco                                        ; Actual tco ; From                                                                                                                                                              ; To          ; From Clock    ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------+
; -4.930 ns                               ; 1.000 ns                                            ; 5.930 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[3]  ; iCLK_50_3     ;
; -4.922 ns                               ; 1.000 ns                                            ; 5.922 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[3]  ; iCLK_50_3     ;
; -4.858 ns                               ; 1.000 ns                                            ; 5.858 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[8]  ; iCLK_50_3     ;
; -4.818 ns                               ; 1.000 ns                                            ; 5.818 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[8]  ; iCLK_50_3     ;
; -4.817 ns                               ; 1.000 ns                                            ; 5.817 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[17] ; iCLK_50_3     ;
; -4.793 ns                               ; 1.000 ns                                            ; 5.793 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[4]  ; iCLK_50_3     ;
; -4.788 ns                               ; 1.000 ns                                            ; 5.788 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[21] ; iCLK_50_3     ;
; -4.781 ns                               ; 1.000 ns                                            ; 5.781 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[1]  ; iCLK_50_3     ;
; -4.778 ns                               ; 1.000 ns                                            ; 5.778 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[22] ; iCLK_50_3     ;
; -4.777 ns                               ; 1.000 ns                                            ; 5.777 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[5]  ; iCLK_50_3     ;
; -4.775 ns                               ; 1.000 ns                                            ; 5.775 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[24] ; iCLK_50_3     ;
; -4.774 ns                               ; 1.000 ns                                            ; 5.774 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[19] ; iCLK_50_3     ;
; -4.750 ns                               ; 1.000 ns                                            ; 5.750 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[11] ; iCLK_50_3     ;
; -4.742 ns                               ; 1.000 ns                                            ; 5.742 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[16] ; iCLK_50_3     ;
; -4.736 ns                               ; 1.000 ns                                            ; 5.736 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[12] ; iCLK_50_3     ;
; -4.726 ns                               ; 1.000 ns                                            ; 5.726 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[4]  ; iCLK_50_3     ;
; -4.723 ns                               ; 1.000 ns                                            ; 5.723 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[14] ; iCLK_50_3     ;
; -4.720 ns                               ; 1.000 ns                                            ; 5.720 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[1]  ; iCLK_50_3     ;
; -4.718 ns                               ; 1.000 ns                                            ; 5.718 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[10] ; iCLK_50_3     ;
; -4.715 ns                               ; 1.000 ns                                            ; 5.715 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[11] ; iCLK_50_3     ;
; -4.714 ns                               ; 1.000 ns                                            ; 5.714 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[24] ; iCLK_50_3     ;
; -4.712 ns                               ; 1.000 ns                                            ; 5.712 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[28] ; iCLK_50_3     ;
; -4.710 ns                               ; 1.000 ns                                            ; 5.710 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[18] ; iCLK_50_3     ;
; -4.710 ns                               ; 1.000 ns                                            ; 5.710 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[5]  ; iCLK_50_3     ;
; -4.707 ns                               ; 1.000 ns                                            ; 5.707 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[27] ; iCLK_50_3     ;
; -4.674 ns                               ; 1.000 ns                                            ; 5.674 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[10] ; iCLK_50_3     ;
; -4.670 ns                               ; 1.000 ns                                            ; 5.670 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[16] ; iCLK_50_3     ;
; -4.666 ns                               ; 1.000 ns                                            ; 5.666 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[20] ; iCLK_50_3     ;
; -4.660 ns                               ; 1.000 ns                                            ; 5.660 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[10] ; iCLK_50_3     ;
; -4.637 ns                               ; 1.000 ns                                            ; 5.637 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[14] ; iCLK_50_3     ;
; -4.636 ns                               ; 1.000 ns                                            ; 5.636 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[20] ; iCLK_50_3     ;
; -4.626 ns                               ; 1.000 ns                                            ; 5.626 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[2]  ; iCLK_50_3     ;
; -4.626 ns                               ; 1.000 ns                                            ; 5.626 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[7]  ; iCLK_50_3     ;
; -4.620 ns                               ; 1.000 ns                                            ; 5.620 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[31] ; iCLK_50_3     ;
; -4.601 ns                               ; 1.000 ns                                            ; 5.601 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[4]  ; iCLK_50_3     ;
; -4.599 ns                               ; 1.000 ns                                            ; 5.599 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[22] ; iCLK_50_3     ;
; -4.589 ns                               ; 1.000 ns                                            ; 5.589 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[5]  ; iCLK_50_3     ;
; -4.586 ns                               ; 1.000 ns                                            ; 5.586 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[30] ; iCLK_50_3     ;
; -4.585 ns                               ; 1.000 ns                                            ; 5.585 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[1]  ; iCLK_50_3     ;
; -4.575 ns                               ; 1.000 ns                                            ; 5.575 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[23] ; iCLK_50_3     ;
; -4.574 ns                               ; 1.000 ns                                            ; 5.574 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[3]  ; iCLK_50_3     ;
; -4.570 ns                               ; 1.000 ns                                            ; 5.570 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[12] ; iCLK_50_3     ;
; -4.567 ns                               ; 1.000 ns                                            ; 5.567 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[11] ; iCLK_50_3     ;
; -4.566 ns                               ; 1.000 ns                                            ; 5.566 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[21] ; iCLK_50_3     ;
; -4.565 ns                               ; 1.000 ns                                            ; 5.565 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[13] ; iCLK_50_3     ;
; -4.560 ns                               ; 1.000 ns                                            ; 5.560 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[29] ; iCLK_50_3     ;
; -4.559 ns                               ; 1.000 ns                                            ; 5.559 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[17] ; iCLK_50_3     ;
; -4.557 ns                               ; 1.000 ns                                            ; 5.557 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[31] ; iCLK_50_3     ;
; -4.551 ns                               ; 1.000 ns                                            ; 5.551 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[29] ; iCLK_50_3     ;
; -4.551 ns                               ; 1.000 ns                                            ; 5.551 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[26] ; iCLK_50_3     ;
; -4.543 ns                               ; 1.000 ns                                            ; 5.543 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[25] ; iCLK_50_3     ;
; -4.531 ns                               ; 1.000 ns                                            ; 5.531 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[18] ; iCLK_50_3     ;
; -4.524 ns                               ; 1.000 ns                                            ; 5.524 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[16] ; iCLK_50_3     ;
; -4.520 ns                               ; 1.000 ns                                            ; 5.520 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[6]  ; iCLK_50_3     ;
; -4.500 ns                               ; 1.000 ns                                            ; 5.500 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[12] ; iCLK_50_3     ;
; -4.492 ns                               ; 1.000 ns                                            ; 5.492 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[15] ; iCLK_50_3     ;
; -4.469 ns                               ; 1.000 ns                                            ; 5.469 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[7]  ; iCLK_50_3     ;
; -4.462 ns                               ; 1.000 ns                                            ; 5.462 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[18] ; iCLK_50_3     ;
; -4.459 ns                               ; 1.000 ns                                            ; 5.459 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[26] ; iCLK_50_3     ;
; -4.451 ns                               ; 1.000 ns                                            ; 5.451 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[2]  ; iCLK_50_3     ;
; -4.446 ns                               ; 1.000 ns                                            ; 5.446 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[9]  ; iCLK_50_3     ;
; -4.442 ns                               ; 1.000 ns                                            ; 5.442 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[13] ; iCLK_50_3     ;
; -4.441 ns                               ; 1.000 ns                                            ; 5.441 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[8]  ; iCLK_50_3     ;
; -4.440 ns                               ; 1.000 ns                                            ; 5.440 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[19] ; iCLK_50_3     ;
; -4.426 ns                               ; 1.000 ns                                            ; 5.426 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[28] ; iCLK_50_3     ;
; -4.419 ns                               ; 1.000 ns                                            ; 5.419 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[17] ; iCLK_50_3     ;
; -4.409 ns                               ; 1.000 ns                                            ; 5.409 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[31] ; iCLK_50_3     ;
; -4.402 ns                               ; 1.000 ns                                            ; 5.402 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[2]  ; iCLK_50_3     ;
; -4.399 ns                               ; 1.000 ns                                            ; 5.399 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[26] ; iCLK_50_3     ;
; -4.398 ns                               ; 1.000 ns                                            ; 5.398 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[22] ; iCLK_50_3     ;
; -4.375 ns                               ; 1.000 ns                                            ; 5.375 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[25] ; iCLK_50_3     ;
; -4.364 ns                               ; 1.000 ns                                            ; 5.364 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[6]  ; iCLK_50_3     ;
; -4.362 ns                               ; 1.000 ns                                            ; 5.362 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[20] ; iCLK_50_3     ;
; -4.361 ns                               ; 1.000 ns                                            ; 5.361 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[9]  ; iCLK_50_3     ;
; -4.357 ns                               ; 1.000 ns                                            ; 5.357 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[30] ; iCLK_50_3     ;
; -4.349 ns                               ; 1.000 ns                                            ; 5.349 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[29] ; iCLK_50_3     ;
; -4.339 ns                               ; 1.000 ns                                            ; 5.339 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[30] ; iCLK_50_3     ;
; -4.338 ns                               ; 1.000 ns                                            ; 5.338 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[25] ; iCLK_50_3     ;
; -4.333 ns                               ; 1.000 ns                                            ; 5.333 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[27] ; iCLK_50_3     ;
; -4.328 ns                               ; 1.000 ns                                            ; 5.328 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[28] ; iCLK_50_3     ;
; -4.317 ns                               ; 1.000 ns                                            ; 5.317 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[6]  ; iCLK_50_3     ;
; -4.311 ns                               ; 1.000 ns                                            ; 5.311 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[15] ; iCLK_50_3     ;
; -4.310 ns                               ; 1.000 ns                                            ; 5.310 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[13] ; iCLK_50_3     ;
; -4.310 ns                               ; 1.000 ns                                            ; 5.310 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[0]  ; iCLK_50_3     ;
; -4.301 ns                               ; 1.000 ns                                            ; 5.301 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[21] ; iCLK_50_3     ;
; -4.284 ns                               ; 1.000 ns                                            ; 5.284 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[14] ; iCLK_50_3     ;
; -4.282 ns                               ; 1.000 ns                                            ; 5.282 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[7]  ; iCLK_50_3     ;
; -4.250 ns                               ; 1.000 ns                                            ; 5.250 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[0]  ; iCLK_50_3     ;
; -4.232 ns                               ; 1.000 ns                                            ; 5.232 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[19] ; iCLK_50_3     ;
; -4.217 ns                               ; 1.000 ns                                            ; 5.217 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[27] ; iCLK_50_3     ;
; -4.199 ns                               ; 1.000 ns                                            ; 5.199 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[24] ; iCLK_50_3     ;
; -4.193 ns                               ; 1.000 ns                                            ; 5.193 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[23] ; iCLK_50_3     ;
; -4.189 ns                               ; 1.000 ns                                            ; 5.189 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[23] ; iCLK_50_3     ;
; -4.132 ns                               ; 1.000 ns                                            ; 5.132 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[9]  ; iCLK_50_3     ;
; -4.120 ns                               ; 1.000 ns                                            ; 5.120 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[0]  ; iCLK_50_3     ;
; -4.096 ns                               ; 1.000 ns                                            ; 5.096 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[15] ; iCLK_50_3     ;
; -3.413 ns                               ; 1.000 ns                                            ; 4.413 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[11] ; iCLK_50_3     ;
; -3.158 ns                               ; 1.000 ns                                            ; 4.158 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[16] ; iCLK_50_3     ;
; -3.158 ns                               ; 1.000 ns                                            ; 4.158 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[17] ; iCLK_50_3     ;
; -3.135 ns                               ; 1.000 ns                                            ; 4.135 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[13] ; iCLK_50_3     ;
; -3.135 ns                               ; 1.000 ns                                            ; 4.135 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[14] ; iCLK_50_3     ;
; -3.135 ns                               ; 1.000 ns                                            ; 4.135 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[15] ; iCLK_50_3     ;
; -3.125 ns                               ; 1.000 ns                                            ; 4.125 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[12] ; iCLK_50_3     ;
; -3.123 ns                               ; 1.000 ns                                            ; 4.123 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[10] ; iCLK_50_3     ;
; -3.123 ns                               ; 1.000 ns                                            ; 4.123 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[9]  ; iCLK_50_3     ;
; -3.111 ns                               ; 1.000 ns                                            ; 4.111 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[8]  ; iCLK_50_3     ;
; -2.911 ns                               ; 1.000 ns                                            ; 3.911 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[3]  ; iCLK_50_3     ;
; -2.911 ns                               ; 1.000 ns                                            ; 3.911 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[4]  ; iCLK_50_3     ;
; -2.907 ns                               ; 1.000 ns                                            ; 3.907 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[0]  ; iCLK_50_3     ;
; -2.907 ns                               ; 1.000 ns                                            ; 3.907 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[1]  ; iCLK_50_3     ;
; -2.901 ns                               ; 1.000 ns                                            ; 3.901 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[2]  ; iCLK_50_3     ;
; -2.890 ns                               ; 1.000 ns                                            ; 3.890 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[5]  ; iCLK_50_3     ;
; -2.856 ns                               ; 1.000 ns                                            ; 3.856 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[30] ; iCLK_50_3     ;
; -2.856 ns                               ; 1.000 ns                                            ; 3.856 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[31] ; iCLK_50_3     ;
; -2.849 ns                               ; 1.000 ns                                            ; 3.849 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[18] ; iCLK_50_3     ;
; -2.848 ns                               ; 1.000 ns                                            ; 3.848 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[19] ; iCLK_50_3     ;
; -2.848 ns                               ; 1.000 ns                                            ; 3.848 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[21] ; iCLK_50_3     ;
; -2.848 ns                               ; 1.000 ns                                            ; 3.848 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[22] ; iCLK_50_3     ;
; -2.846 ns                               ; 1.000 ns                                            ; 3.846 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[28] ; iCLK_50_3     ;
; -2.846 ns                               ; 1.000 ns                                            ; 3.846 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[27] ; iCLK_50_3     ;
; -2.838 ns                               ; 1.000 ns                                            ; 3.838 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[20] ; iCLK_50_3     ;
; -2.836 ns                               ; 1.000 ns                                            ; 3.836 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[29] ; iCLK_50_3     ;
; -2.822 ns                               ; 1.000 ns                                            ; 3.822 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[23] ; iCLK_50_3     ;
; -2.595 ns                               ; 1.000 ns                                            ; 3.595 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[6]  ; iCLK_50_3     ;
; -2.595 ns                               ; 1.000 ns                                            ; 3.595 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[7]  ; iCLK_50_3     ;
; -2.546 ns                               ; 1.000 ns                                            ; 3.546 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[24] ; iCLK_50_3     ;
; -2.546 ns                               ; 1.000 ns                                            ; 3.546 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[25] ; iCLK_50_3     ;
; -2.536 ns                               ; 1.000 ns                                            ; 3.536 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[26] ; iCLK_50_3     ;
; N/A                                     ; None                                                ; 14.170 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]                                                                                                    ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 14.133 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3]                                                                                                    ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 14.046 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[5]                                                                                                    ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.960 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[2]                                                                                                    ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.554 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]                                                                                                    ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.160 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SCLK                                                                                                             ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.756 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK                                                                                                           ; GPIO_0[2]   ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.511 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.374 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.358 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO                                                                                                              ; GPIO_1[19]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.319 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSCLK                                                                                                              ; GPIO_0[2]   ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.988 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.837 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.714 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.363 ns  ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                ; oHEX2_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.315 ns  ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.192 ns  ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                ; oHEX2_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.150 ns  ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.145 ns  ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                ; oHEX2_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.114 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[0]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.087 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.073 ns  ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.053 ns  ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                               ; oHEX2_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.916 ns  ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                ; oHEX2_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.883 ns  ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                               ; oHEX2_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.837 ns  ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                               ; oHEX2_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.829 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.784 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.729 ns  ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                ; oHEX2_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.727 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA~en                                                                                                          ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 10.697 ns  ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                ; oHEX2_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.689 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 10.652 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN                                                                                                               ; GPIO_0[30]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 10.631 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[0]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.616 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.616 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.604 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.486 ns  ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[0]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.460 ns  ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.454 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[0]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.430 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.357 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[1]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.345 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.289 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.202 ns  ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.181 ns  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK                                                                                                                      ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 10.171 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.148 ns  ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.132 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.126 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.116 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.041 ns  ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.009 ns  ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.987 ns   ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.986 ns   ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.958 ns   ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.952 ns   ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.949 ns   ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.924 ns   ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.884 ns   ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                ; oHEX0_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.866 ns   ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[1]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.785 ns   ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                ; oHEX0_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.727 ns   ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[1]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.721 ns   ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.713 ns   ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.711 ns   ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.693 ns   ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[1]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.662 ns   ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.647 ns   ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                                               ; oHEX6_D[1]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.626 ns   ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                                               ; oHEX6_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.623 ns   ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                                               ; oHEX6_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.609 ns   ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[3]  ; GPIO_CLKIN_N1 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;                                                                                                                                                                   ;             ;               ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------+


+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+-----------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To         ;
+-------+-------------------+-----------------+-----------+------------+
; N/A   ; None              ; 10.588 ns       ; iSW[3]    ; oLEDR[3]   ;
; N/A   ; None              ; 10.555 ns       ; iSW[0]    ; oLEDR[0]   ;
; N/A   ; None              ; 10.502 ns       ; iSW[2]    ; oLEDR[2]   ;
; N/A   ; None              ; 10.496 ns       ; iSW[1]    ; oLEDR[1]   ;
; N/A   ; None              ; 10.492 ns       ; iSW[7]    ; oLEDR[7]   ;
; N/A   ; None              ; 10.439 ns       ; iSW[4]    ; oLEDR[4]   ;
; N/A   ; None              ; 10.373 ns       ; iSW[6]    ; oLEDR[6]   ;
; N/A   ; None              ; 10.297 ns       ; iSW[17]   ; oLEDR[17]  ;
; N/A   ; None              ; 10.188 ns       ; iSW[8]    ; oLEDR[8]   ;
; N/A   ; None              ; 10.174 ns       ; iSW[13]   ; oLEDR[13]  ;
; N/A   ; None              ; 10.173 ns       ; iSW[5]    ; oLEDR[5]   ;
; N/A   ; None              ; 10.142 ns       ; iSW[14]   ; oLEDR[14]  ;
; N/A   ; None              ; 10.110 ns       ; iSW[16]   ; oLEDR[16]  ;
; N/A   ; None              ; 9.986 ns        ; iSW[9]    ; oLEDR[9]   ;
; N/A   ; None              ; 9.976 ns        ; iSW[15]   ; oLEDR[15]  ;
; N/A   ; None              ; 9.777 ns        ; iSW[11]   ; oLEDR[11]  ;
; N/A   ; None              ; 9.575 ns        ; iSW[10]   ; oLEDR[10]  ;
; N/A   ; None              ; 9.486 ns        ; iSW[12]   ; oLEDR[12]  ;
; N/A   ; None              ; 8.893 ns        ; iUART_RXD ; oUART_TXD  ;
; N/A   ; None              ; 8.567 ns        ; iKEY[0]   ; GPIO_0[29] ;
+-------+-------------------+-----------------+-----------+------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                            ;
+---------------+-------------+-----------+-------------+-------------------------------------------------------+---------------+
; Minimum Slack ; Required th ; Actual th ; From        ; To                                                    ; To Clock      ;
+---------------+-------------+-----------+-------------+-------------------------------------------------------+---------------+
; N/A           ; None        ; 0.553 ns  ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4 ; iCLK_50       ;
; N/A           ; None        ; 0.549 ns  ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3 ; iCLK_50       ;
; N/A           ; None        ; -0.275 ns ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2 ; iCLK_50       ;
; N/A           ; None        ; -0.524 ns ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1 ; iCLK_50       ;
; N/A           ; None        ; -1.058 ns ; DRAM_DQ[8]  ; Sdram_Control_4Port:sdram0|mDATAOUT[8]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.065 ns ; DRAM_DQ[11] ; Sdram_Control_4Port:sdram0|mDATAOUT[11]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.082 ns ; DRAM_DQ[12] ; Sdram_Control_4Port:sdram0|mDATAOUT[12]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.090 ns ; DRAM_DQ[18] ; Sdram_Control_4Port:sdram1|mDATAOUT[2]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.092 ns ; DRAM_DQ[14] ; Sdram_Control_4Port:sdram0|mDATAOUT[14]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.092 ns ; DRAM_DQ[13] ; Sdram_Control_4Port:sdram0|mDATAOUT[13]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.096 ns ; DRAM_DQ[20] ; Sdram_Control_4Port:sdram1|mDATAOUT[4]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.098 ns ; DRAM_DQ[9]  ; Sdram_Control_4Port:sdram0|mDATAOUT[9]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.098 ns ; DRAM_DQ[10] ; Sdram_Control_4Port:sdram0|mDATAOUT[10]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.103 ns ; DRAM_DQ[7]  ; Sdram_Control_4Port:sdram0|mDATAOUT[7]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.103 ns ; DRAM_DQ[6]  ; Sdram_Control_4Port:sdram0|mDATAOUT[6]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.104 ns ; DRAM_DQ[23] ; Sdram_Control_4Port:sdram1|mDATAOUT[7]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.106 ns ; DRAM_DQ[22] ; Sdram_Control_4Port:sdram1|mDATAOUT[6]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.106 ns ; DRAM_DQ[21] ; Sdram_Control_4Port:sdram1|mDATAOUT[5]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.106 ns ; DRAM_DQ[19] ; Sdram_Control_4Port:sdram1|mDATAOUT[3]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.112 ns ; DRAM_DQ[5]  ; Sdram_Control_4Port:sdram0|mDATAOUT[5]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.122 ns ; DRAM_DQ[2]  ; Sdram_Control_4Port:sdram0|mDATAOUT[2]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[25] ; Sdram_Control_4Port:sdram1|mDATAOUT[9]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[24] ; Sdram_Control_4Port:sdram1|mDATAOUT[8]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[4]  ; Sdram_Control_4Port:sdram0|mDATAOUT[4]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[3]  ; Sdram_Control_4Port:sdram0|mDATAOUT[3]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.146 ns ; DRAM_DQ[29] ; Sdram_Control_4Port:sdram1|mDATAOUT[13]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.153 ns ; DRAM_DQ[28] ; Sdram_Control_4Port:sdram1|mDATAOUT[12]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.166 ns ; DRAM_DQ[30] ; Sdram_Control_4Port:sdram1|mDATAOUT[14]               ; iCLK_50_3     ;
; N/A           ; None        ; -2.250 ns ; GPIO_1[18]  ; rCCD_FVAL                                             ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.251 ns ; GPIO_1[2]   ; rCCD_DATA[9]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.251 ns ; GPIO_1[4]   ; rCCD_DATA[7]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.258 ns ; GPIO_1[3]   ; rCCD_DATA[8]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.258 ns ; GPIO_1[5]   ; rCCD_DATA[6]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.261 ns ; GPIO_1[0]   ; rCCD_DATA[11]                                         ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.261 ns ; GPIO_1[1]   ; rCCD_DATA[10]                                         ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.270 ns ; GPIO_1[17]  ; rCCD_LVAL                                             ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.282 ns ; GPIO_1[11]  ; rCCD_DATA[0]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.307 ns ; GPIO_1[7]   ; rCCD_DATA[4]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.307 ns ; GPIO_1[9]   ; rCCD_DATA[2]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.316 ns ; GPIO_1[6]   ; rCCD_DATA[5]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.316 ns ; GPIO_1[8]   ; rCCD_DATA[3]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.327 ns ; GPIO_1[10]  ; rCCD_DATA[1]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.409 ns ; iKEY[3]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.676 ns ; iKEY[2]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -3.500 ns ; iSW[17]     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]          ; iCLK_50       ;
; N/A           ; None        ; -3.585 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[0] ; iCLK_50       ;
; N/A           ; None        ; -3.724 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A           ; None        ; -3.736 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A           ; None        ; -3.768 ns ; iSW[17]     ; RAW2RGB:raw0|mirror_sw                                ; iCLK_50       ;
; N/A           ; None        ; -4.031 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A           ; None        ; -4.036 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A           ; None        ; -4.037 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A           ; None        ; -4.039 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A           ; None        ; -4.043 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A           ; None        ; -4.043 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A           ; None        ; -4.044 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A           ; None        ; -4.097 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A           ; None        ; -4.098 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A           ; None        ; -4.229 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A           ; None        ; -4.230 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A           ; None        ; -4.429 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A           ; None        ; -4.448 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A           ; None        ; -4.510 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A           ; None        ; -4.760 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A           ; None        ; -4.864 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A           ; None        ; -7.372 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.372 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.540 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.540 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.673 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.731 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.732 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.761 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.761 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.837 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.837 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.897 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.897 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.918 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.918 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.920 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.005 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.005 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.025 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.054 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.178 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.205 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.212 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.237 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.252 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.252 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.360 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.362 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.362 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.368 ns ; iSW[9]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A           ; None        ; -8.383 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.383 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.448 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.450 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.450 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.457 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.459 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.489 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.518 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.554 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.567 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.568 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.642 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.669 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.670 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.672 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.676 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.734 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.753 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.763 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.824 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.849 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.856 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.885 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.887 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.890 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.914 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.914 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.921 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.966 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.975 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.002 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.018 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.020 ns ; iSW[8]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A           ; None        ; -9.030 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.062 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.069 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.105 ns ; iSW[7]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A           ; None        ; -9.119 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.159 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.177 ns ; iSW[5]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A           ; None        ; -9.188 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.215 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.243 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.255 ns ; iSW[3]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A           ; None        ; -9.263 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.344 ns ; iSW[4]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A           ; None        ; -9.377 ns ; iSW[2]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
; N/A           ; None        ; -9.535 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.616 ns ; iSW[6]      ; Sobel:sobel0|oDATA[9]                                 ; iCLK_50_2     ;
+---------------+-------------+-----------+-------------+-------------------------------------------------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Ignored Timing Assignments                                                                                                                                     ;
+-----------------+---------+------+----------------------------------+-------------+----------------------------------------------------------------------------+
; Option          ; Setting ; From ; To                               ; Entity Name ; Help                                                                       ;
+-----------------+---------+------+----------------------------------+-------------+----------------------------------------------------------------------------+
; tco Requirement ; 1 ns    ; *    ; CCD_Capture:u3|Pre_FVAL          ;             ; No element named CCD_Capture:u3|Pre_FVAL was found in the netlist          ;
; tco Requirement ; 1 ns    ; *    ; CCD_Capture:u3|mCCD_DATA         ;             ; No element named CCD_Capture:u3|mCCD_DATA was found in the netlist         ;
; tco Requirement ; 1 ns    ; *    ; CCD_Capture:u3|mCCD_LVAL         ;             ; No element named CCD_Capture:u3|mCCD_LVAL was found in the netlist         ;
; tco Requirement ; 1 ns    ; *    ; Sdram_Control_4Port:u11|mDATAOUT ;             ; No element named Sdram_Control_4Port:u11|mDATAOUT was found in the netlist ;
; tco Requirement ; 1 ns    ; *    ; Sdram_Control_4Port:u6|mDATAOUT  ;             ; No element named Sdram_Control_4Port:u6|mDATAOUT was found in the netlist  ;
+-----------------+---------+------+----------------------------------+-------------+----------------------------------------------------------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Mon Sep 29 16:27:49 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DE2_70 -c DE2_70 --timing_analysis_only
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Warning: Clock Setting "CLK" is unassigned
Warning: Clock Setting "VGA_CTRL_CLK" is unassigned
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK" as buffer
    Info: Detected ripple clock "lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK" as buffer
    Info: Detected ripple clock "Reset_Delay:reset0|oRST_1" as buffer
    Info: Detected ripple clock "RAW2RGB:raw0|dval_ctrl" as buffer
Info: Found timing assignments -- calculating delays
Info: Slack time is 1.144 ns for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" between source register "Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]" and destination register "Sdram_Control_4Port:sdram1|mADDR[13]"
    Info: Fmax is 205.93 MHz (period= 4.856 ns)
    Info: + Largest register to register requirement is 5.825 ns
        Info: + Setup relationship between source and destination is 6.000 ns
            Info: + Latch edge is 3.406 ns
                Info: Clock period of Destination clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is -2.594 ns
                Info: Clock period of Source clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.039 ns
            Info: + Shortest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to destination register is 2.788 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 833; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.203 ns) + CELL(0.537 ns) = 2.788 ns; Loc. = LCFF_X10_Y17_N5; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|mADDR[13]'
                Info: Total cell delay = 0.537 ns ( 19.26 % )
                Info: Total interconnect delay = 2.251 ns ( 80.74 % )
            Info: - Longest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to source register is 2.749 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 833; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.164 ns) + CELL(0.537 ns) = 2.749 ns; Loc. = LCFF_X34_Y14_N31; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]'
                Info: Total cell delay = 0.537 ns ( 19.53 % )
                Info: Total interconnect delay = 2.212 ns ( 80.47 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 4.681 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y14_N31; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]'
        Info: 2: + IC(0.466 ns) + CELL(0.414 ns) = 0.880 ns; Loc. = LCCOMB_X34_Y14_N6; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~135'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.951 ns; Loc. = LCCOMB_X34_Y14_N8; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~137'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.022 ns; Loc. = LCCOMB_X34_Y14_N10; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~139'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.093 ns; Loc. = LCCOMB_X34_Y14_N12; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~141'
        Info: 6: + IC(0.000 ns) + CELL(0.159 ns) = 1.252 ns; Loc. = LCCOMB_X34_Y14_N14; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~143'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.323 ns; Loc. = LCCOMB_X34_Y14_N16; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~145'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.394 ns; Loc. = LCCOMB_X34_Y14_N18; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~147'
        Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.465 ns; Loc. = LCCOMB_X34_Y14_N20; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~149'
        Info: 10: + IC(0.000 ns) + CELL(0.410 ns) = 1.875 ns; Loc. = LCCOMB_X34_Y14_N22; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~150'
        Info: 11: + IC(1.482 ns) + CELL(0.275 ns) = 3.632 ns; Loc. = LCCOMB_X11_Y17_N14; Fanout = 15; COMB Node = 'Sdram_Control_4Port:sdram1|mADDR[8]~374'
        Info: 12: + IC(0.389 ns) + CELL(0.660 ns) = 4.681 ns; Loc. = LCFF_X10_Y17_N5; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|mADDR[13]'
        Info: Total cell delay = 2.344 ns ( 50.07 % )
        Info: Total interconnect delay = 2.337 ns ( 49.93 % )
Info: No valid register-to-register data paths exist for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk1"
Info: No valid register-to-register data paths exist for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk2"
Info: Slack time is 10.156 ns for clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" between source memory "Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]" and destination register "touch_tcon:vga0|oLCD_B[5]"
    Info: Fmax is 103.22 MHz (period= 9.688 ns)
    Info: + Largest memory to register requirement is 14.869 ns
        Info: + Setup relationship between source and destination is 15.000 ns
            Info: + Latch edge is 27.392 ns
                Info: Clock period of Destination clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with  offset of -2.608 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 12.392 ns
                Info: Clock period of Source clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with inverted offset of 12.392 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.042 ns
            Info: + Shortest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to destination register is 2.812 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 1691; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.237 ns) + CELL(0.537 ns) = 2.812 ns; Loc. = LCFF_X43_Y20_N21; Fanout = 1; REG Node = 'touch_tcon:vga0|oLCD_B[5]'
                Info: Total cell delay = 0.537 ns ( 19.10 % )
                Info: Total interconnect delay = 2.275 ns ( 80.90 % )
            Info: - Longest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to source memory is 2.770 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 1691; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.097 ns) + CELL(0.635 ns) = 2.770 ns; Loc. = M4K_X17_Y13; Fanout = 1; MEM Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]'
                Info: Total cell delay = 0.635 ns ( 22.92 % )
                Info: Total interconnect delay = 2.135 ns ( 77.08 % )
        Info: - Micro clock to output delay of source is 0.209 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest memory to register delay is 4.713 ns
        Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X17_Y13; Fanout = 1; MEM Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]'
        Info: 2: + IC(2.740 ns) + CELL(0.419 ns) = 3.247 ns; Loc. = LCCOMB_X42_Y20_N22; Fanout = 1; COMB Node = 'touch_tcon:vga0|read_blue[5]~191'
        Info: 3: + IC(0.255 ns) + CELL(0.419 ns) = 3.921 ns; Loc. = LCCOMB_X42_Y20_N4; Fanout = 1; COMB Node = 'touch_tcon:vga0|read_blue[5]~192'
        Info: 4: + IC(0.433 ns) + CELL(0.275 ns) = 4.629 ns; Loc. = LCCOMB_X43_Y20_N20; Fanout = 1; COMB Node = 'touch_tcon:vga0|read_blue[5]~193'
        Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 4.713 ns; Loc. = LCFF_X43_Y20_N21; Fanout = 1; REG Node = 'touch_tcon:vga0|oLCD_B[5]'
        Info: Total cell delay = 1.285 ns ( 27.27 % )
        Info: Total interconnect delay = 3.428 ns ( 72.73 % )
Info: Slack time is 2.038 ns for clock "GPIO_CLKIN_N1" between source register "CCD_Capture:capture0|Y_Cont[3]" and destination register "RAW2RGB:raw0|rGreen[5]"
    Info: Fmax is 141.8 MHz (period= 7.052 ns)
    Info: + Largest register to register requirement is 8.891 ns
        Info: + Setup relationship between source and destination is 9.090 ns
            Info: + Latch edge is 9.090 ns
                Info: Clock period of Destination clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.015 ns
            Info: + Shortest clock path from clock "GPIO_CLKIN_N1" to destination register is 2.858 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.218 ns) + CELL(0.537 ns) = 2.858 ns; Loc. = LCFF_X65_Y19_N11; Fanout = 1; REG Node = 'RAW2RGB:raw0|rGreen[5]'
                Info: Total cell delay = 1.526 ns ( 53.39 % )
                Info: Total interconnect delay = 1.332 ns ( 46.61 % )
            Info: - Longest clock path from clock "GPIO_CLKIN_N1" to source register is 2.843 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.203 ns) + CELL(0.537 ns) = 2.843 ns; Loc. = LCFF_X67_Y17_N7; Fanout = 4; REG Node = 'CCD_Capture:capture0|Y_Cont[3]'
                Info: Total cell delay = 1.526 ns ( 53.68 % )
                Info: Total interconnect delay = 1.317 ns ( 46.32 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 6.853 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X67_Y17_N7; Fanout = 4; REG Node = 'CCD_Capture:capture0|Y_Cont[3]'
        Info: 2: + IC(0.755 ns) + CELL(0.275 ns) = 1.030 ns; Loc. = LCCOMB_X66_Y17_N12; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Equal6~148'
        Info: 3: + IC(0.260 ns) + CELL(0.438 ns) = 1.728 ns; Loc. = LCCOMB_X66_Y17_N28; Fanout = 31; COMB Node = 'RAW2RGB:raw0|Equal6~152'
        Info: 4: + IC(1.019 ns) + CELL(0.150 ns) = 2.897 ns; Loc. = LCCOMB_X67_Y18_N22; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Add0~9124'
        Info: 5: + IC(0.255 ns) + CELL(0.419 ns) = 3.571 ns; Loc. = LCCOMB_X67_Y18_N6; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Add0~9125'
        Info: 6: + IC(0.740 ns) + CELL(0.393 ns) = 4.704 ns; Loc. = LCCOMB_X66_Y20_N4; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~9142'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 4.775 ns; Loc. = LCCOMB_X66_Y20_N6; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~9144'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 4.846 ns; Loc. = LCCOMB_X66_Y20_N8; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~9146'
        Info: 9: + IC(0.000 ns) + CELL(0.410 ns) = 5.256 ns; Loc. = LCCOMB_X66_Y20_N10; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Add0~9147'
        Info: 10: + IC(0.699 ns) + CELL(0.420 ns) = 6.375 ns; Loc. = LCCOMB_X65_Y19_N28; Fanout = 1; COMB Node = 'RAW2RGB:raw0|rGreen~670'
        Info: 11: + IC(0.244 ns) + CELL(0.150 ns) = 6.769 ns; Loc. = LCCOMB_X65_Y19_N10; Fanout = 1; COMB Node = 'RAW2RGB:raw0|rGreen~671'
        Info: 12: + IC(0.000 ns) + CELL(0.084 ns) = 6.853 ns; Loc. = LCFF_X65_Y19_N11; Fanout = 1; REG Node = 'RAW2RGB:raw0|rGreen[5]'
        Info: Total cell delay = 2.881 ns ( 42.04 % )
        Info: Total interconnect delay = 3.972 ns ( 57.96 % )
Info: Slack time is 6.67 ns for clock "iCLK_50" between source register "lcd_3wire_config:lcd_config0|m3wire_data[14]" and destination register "lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA"
    Info: Fmax is 150.15 MHz (period= 6.66 ns)
    Info: + Largest register to register requirement is 9.786 ns
        Info: + Setup relationship between source and destination is 10.000 ns
            Info: + Latch edge is 10.000 ns
                Info: Clock period of Destination clock "iCLK_50" is 20.000 ns with inverted offset of 10.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "iCLK_50" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "iCLK_50" to destination register is 4.965 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(0.636 ns) + CELL(0.787 ns) = 2.382 ns; Loc. = LCFF_X50_Y4_N29; Fanout = 3; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK'
                Info: 3: + IC(0.824 ns) + CELL(0.000 ns) = 3.206 ns; Loc. = CLKCTRL_G13; Fanout = 37; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK~clkctrl'
                Info: 4: + IC(1.222 ns) + CELL(0.537 ns) = 4.965 ns; Loc. = LCFF_X61_Y29_N3; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA'
                Info: Total cell delay = 2.283 ns ( 45.98 % )
                Info: Total interconnect delay = 2.682 ns ( 54.02 % )
            Info: - Longest clock path from clock "iCLK_50" to source register is 4.965 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(0.636 ns) + CELL(0.787 ns) = 2.382 ns; Loc. = LCFF_X50_Y4_N29; Fanout = 3; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK'
                Info: 3: + IC(0.824 ns) + CELL(0.000 ns) = 3.206 ns; Loc. = CLKCTRL_G13; Fanout = 37; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK~clkctrl'
                Info: 4: + IC(1.222 ns) + CELL(0.537 ns) = 4.965 ns; Loc. = LCFF_X61_Y29_N21; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|m3wire_data[14]'
                Info: Total cell delay = 2.283 ns ( 45.98 % )
                Info: Total interconnect delay = 2.682 ns ( 54.02 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 3.116 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y29_N21; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|m3wire_data[14]'
        Info: 2: + IC(0.329 ns) + CELL(0.437 ns) = 0.766 ns; Loc. = LCCOMB_X61_Y29_N4; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~167'
        Info: 3: + IC(0.450 ns) + CELL(0.438 ns) = 1.654 ns; Loc. = LCCOMB_X61_Y29_N14; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~168'
        Info: 4: + IC(0.250 ns) + CELL(0.419 ns) = 2.323 ns; Loc. = LCCOMB_X61_Y29_N16; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~169'
        Info: 5: + IC(0.271 ns) + CELL(0.438 ns) = 3.032 ns; Loc. = LCCOMB_X61_Y29_N2; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~172'
        Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 3.116 ns; Loc. = LCFF_X61_Y29_N3; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA'
        Info: Total cell delay = 1.816 ns ( 58.28 % )
        Info: Total interconnect delay = 1.300 ns ( 41.72 % )
Info: No valid register-to-register data paths exist for clock "GPIO_CLKOUT_N1"
Info: No valid register-to-register data paths exist for clock "oDRAM0_CLK"
Info: No valid register-to-register data paths exist for clock "iCLK_50_3"
Info: No valid register-to-register data paths exist for clock "iCLK_50_2"
Info: Minimum slack time is 391 ps for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" between source register "Sdram_Control_4Port:sdram1|command:command1|do_rw" and destination register "Sdram_Control_4Port:sdram1|command:command1|do_rw"
    Info: + Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y17_N13; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X7_Y17_N12; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw~49'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X7_Y17_N13; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is -2.594 ns
                Info: Clock period of Destination clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is -2.594 ns
                Info: Clock period of Source clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to destination register is 2.782 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 833; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.197 ns) + CELL(0.537 ns) = 2.782 ns; Loc. = LCFF_X7_Y17_N13; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
                Info: Total cell delay = 0.537 ns ( 19.30 % )
                Info: Total interconnect delay = 2.245 ns ( 80.70 % )
            Info: - Shortest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to source register is 2.782 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 833; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.197 ns) + CELL(0.537 ns) = 2.782 ns; Loc. = LCFF_X7_Y17_N13; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
                Info: Total cell delay = 0.537 ns ( 19.30 % )
                Info: Total interconnect delay = 2.245 ns ( 80.70 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Info: Minimum slack time is 520 ps for clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" between source register "Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[0]" and destination register "Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[0]"
    Info: + Shortest register to register delay is 0.536 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X47_Y16_N29; Fanout = 3; REG Node = 'Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[0]'
        Info: 2: + IC(0.303 ns) + CELL(0.149 ns) = 0.452 ns; Loc. = LCCOMB_X47_Y16_N26; Fanout = 1; COMB Node = 'Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[0]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.536 ns; Loc. = LCFF_X47_Y16_N27; Fanout = 2; REG Node = 'Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[0]'
        Info: Total cell delay = 0.233 ns ( 43.47 % )
        Info: Total interconnect delay = 0.303 ns ( 56.53 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is -2.608 ns
                Info: Clock period of Destination clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with  offset of -2.608 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is -2.608 ns
                Info: Clock period of Source clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with  offset of -2.608 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to destination register is 2.781 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 1691; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.206 ns) + CELL(0.537 ns) = 2.781 ns; Loc. = LCFF_X47_Y16_N27; Fanout = 2; REG Node = 'Sobel:sobel0|MAC_3:x0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult2|scan_chain_a_reg[0]'
                Info: Total cell delay = 0.537 ns ( 19.31 % )
                Info: Total interconnect delay = 2.244 ns ( 80.69 % )
            Info: - Shortest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to source register is 2.781 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 1691; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.206 ns) + CELL(0.537 ns) = 2.781 ns; Loc. = LCFF_X47_Y16_N29; Fanout = 3; REG Node = 'Sobel:sobel0|MAC_3:y0|altmult_add:ALTMULT_ADD_component|mult_add_ae74:auto_generated|ded_mult_66a1:ded_mult1|scan_chain_a_reg[0]'
                Info: Total cell delay = 0.537 ns ( 19.31 % )
                Info: Total interconnect delay = 2.244 ns ( 80.69 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Info: Minimum slack time is 391 ps for clock "GPIO_CLKIN_N1" between source register "CCD_Capture:capture0|mCCD_FVAL" and destination register "CCD_Capture:capture0|mCCD_FVAL"
    Info: + Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y20_N27; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X13_Y20_N26; Fanout = 1; COMB Node = 'CCD_Capture:capture0|mCCD_FVAL~40'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X13_Y20_N27; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "GPIO_CLKIN_N1" to destination register is 2.853 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.213 ns) + CELL(0.537 ns) = 2.853 ns; Loc. = LCFF_X13_Y20_N27; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
                Info: Total cell delay = 1.526 ns ( 53.49 % )
                Info: Total interconnect delay = 1.327 ns ( 46.51 % )
            Info: - Shortest clock path from clock "GPIO_CLKIN_N1" to source register is 2.853 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.213 ns) + CELL(0.537 ns) = 2.853 ns; Loc. = LCFF_X13_Y20_N27; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
                Info: Total cell delay = 1.526 ns ( 53.49 % )
                Info: Total interconnect delay = 1.327 ns ( 46.51 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Info: Minimum slack time is 391 ps for clock "iCLK_50" between source register "rClk[0]" and destination register "rClk[0]"
    Info: + Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X94_Y3_N0; Fanout = 1; COMB Node = 'rClk[0]~3'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "iCLK_50" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "iCLK_50" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "iCLK_50" to destination register is 2.883 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(0.112 ns) + CELL(0.000 ns) = 1.071 ns; Loc. = CLKCTRL_G14; Fanout = 104; COMB Node = 'iCLK_50~clkctrl'
                Info: 3: + IC(1.275 ns) + CELL(0.537 ns) = 2.883 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
                Info: Total cell delay = 1.496 ns ( 51.89 % )
                Info: Total interconnect delay = 1.387 ns ( 48.11 % )
            Info: - Shortest clock path from clock "iCLK_50" to source register is 2.883 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(0.112 ns) + CELL(0.000 ns) = 1.071 ns; Loc. = CLKCTRL_G14; Fanout = 104; COMB Node = 'iCLK_50~clkctrl'
                Info: 3: + IC(1.275 ns) + CELL(0.537 ns) = 2.883 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
                Info: Total cell delay = 1.496 ns ( 51.89 % )
                Info: Total interconnect delay = 1.387 ns ( 48.11 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Warning: Can't achieve timing requirement tsu along 24 path(s). See Report window for details.
Info: Slack time is -330 ps for clock "iCLK_50_3" between source pin "DRAM_DQ[30]" and destination register "Sdram_Control_4Port:sdram1|mDATAOUT[14]"
    Info: + tsu requirement for source pin and destination register is 1.000 ns
    Info: - tsu from clock to input pin is 1.330 ns
        Info: + Longest pin to register delay is 1.229 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB1; Fanout = 1; PIN Node = 'DRAM_DQ[30]'
            Info: 2: + IC(0.000 ns) + CELL(1.229 ns) = 1.229 ns; Loc. = IOC_X0_Y14_N2; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|mDATAOUT[14]'
            Info: Total cell delay = 1.229 ns ( 100.00 % )
        Info: - Offset between input clock "iCLK_50_3" and output clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is -2.594 ns
        Info: + Micro setup delay of destination is 0.076 ns
        Info: - Shortest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to destination register is 2.569 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
            Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 833; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
            Info: 3: + IC(1.253 ns) + CELL(0.268 ns) = 2.569 ns; Loc. = IOC_X0_Y14_N2; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|mDATAOUT[14]'
            Info: Total cell delay = 0.268 ns ( 10.43 % )
            Info: Total interconnect delay = 2.301 ns ( 89.57 % )
Warning: Can't achieve timing requirement tco along 128 path(s). See Report window for details.
Info: Slack time is -4.93 ns for clock "iCLK_50_3" between source memory "Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]" and destination pin "DRAM_DQ[3]"
    Info: + tco requirement for source memory and destination pin is 1.000 ns
    Info: - tco from clock to output pin is 5.930 ns
        Info: + Offset between input clock "iCLK_50_3" and output clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is -2.594 ns
        Info: + Longest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to source memory is 2.836 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
            Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 833; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
            Info: 3: + IC(1.153 ns) + CELL(0.635 ns) = 2.836 ns; Loc. = M4K_X17_Y11; Fanout = 1; MEM Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]'
            Info: Total cell delay = 0.635 ns ( 22.39 % )
            Info: Total interconnect delay = 2.201 ns ( 77.61 % )
        Info: + Micro clock to output delay of source is 0.209 ns
        Info: + Longest memory to pin delay is 5.479 ns
            Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X17_Y11; Fanout = 1; MEM Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]'
            Info: 2: + IC(0.951 ns) + CELL(0.150 ns) = 1.189 ns; Loc. = LCCOMB_X16_Y8_N4; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram0|mDATAIN[3]~163'
            Info: 3: + IC(1.628 ns) + CELL(2.662 ns) = 5.479 ns; Loc. = PIN_AD1; Fanout = 0; PIN Node = 'DRAM_DQ[3]'
            Info: Total cell delay = 2.900 ns ( 52.93 % )
            Info: Total interconnect delay = 2.579 ns ( 47.07 % )
Info: Longest tpd from source pin "iSW[3]" to destination pin "oLEDR[3]" is 10.588 ns
    Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_AC27; Fanout = 2; PIN Node = 'iSW[3]'
    Info: 2: + IC(6.918 ns) + CELL(2.818 ns) = 10.588 ns; Loc. = PIN_AJ4; Fanout = 0; PIN Node = 'oLEDR[3]'
    Info: Total cell delay = 3.670 ns ( 34.66 % )
    Info: Total interconnect delay = 6.918 ns ( 65.34 % )
Info: th for register "I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4" (data pin = "GPIO_1[19]", clock pin = "iCLK_50") is 0.553 ns
    Info: + Longest clock path from clock "iCLK_50" to destination register is 7.041 ns
        Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
        Info: 2: + IC(1.911 ns) + CELL(0.787 ns) = 3.657 ns; Loc. = LCFF_X66_Y23_N17; Fanout = 3; REG Node = 'I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK'
        Info: 3: + IC(1.619 ns) + CELL(0.000 ns) = 5.276 ns; Loc. = CLKCTRL_G4; Fanout = 72; COMB Node = 'I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK~clkctrl'
        Info: 4: + IC(1.228 ns) + CELL(0.537 ns) = 7.041 ns; Loc. = LCFF_X72_Y24_N27; Fanout = 2; REG Node = 'I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4'
        Info: Total cell delay = 2.283 ns ( 32.42 % )
        Info: Total interconnect delay = 4.758 ns ( 67.58 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 6.754 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_P27; Fanout = 1; PIN Node = 'GPIO_1[19]'
        Info: 2: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = IOC_X95_Y30_N2; Fanout = 4; COMB Node = 'GPIO_1[19]~1'
        Info: 3: + IC(5.678 ns) + CELL(0.150 ns) = 6.670 ns; Loc. = LCCOMB_X72_Y24_N26; Fanout = 1; COMB Node = 'I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4~254'
        Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 6.754 ns; Loc. = LCFF_X72_Y24_N27; Fanout = 2; REG Node = 'I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4'
        Info: Total cell delay = 1.076 ns ( 15.93 % )
        Info: Total interconnect delay = 5.678 ns ( 84.07 % )
Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.
Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 8 warnings
    Info: Peak virtual memory: 152 megabytes
    Info: Processing ended: Mon Sep 29 16:27:53 2008
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:04


