Classic Timing Analyzer report for DE2_70
Mon Sep 29 16:08:27 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
  6. Clock Setup: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
  7. Clock Setup: 'GPIO_CLKIN_N1'
  8. Clock Setup: 'iCLK_50'
  9. Clock Hold: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
 10. Clock Hold: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
 11. Clock Hold: 'GPIO_CLKIN_N1'
 12. Clock Hold: 'iCLK_50'
 13. tsu
 14. tco
 15. tpd
 16. th
 17. Ignored Timing Assignments
 18. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



 
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
 
; Type                                                              ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                              ; To                                                                                                                                             ; From Clock                                         ; To Clock                                           ; Failed Paths ;
 
; Worst-case tsu                                                    ; -0.330 ns ; 1.000 ns                         ; 1.330 ns                         ; DRAM_DQ[30]                                                                                                                                                       ; Sdram_Control_4Port:sdram1|mDATAOUT[14]                                                                                                        ; --                                                 ; iCLK_50_3                                          ; 26           ;
; Worst-case tco                                                    ; -4.997 ns ; 1.000 ns                         ; 5.997 ns                         ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[28]                                                                                                                                    ; iCLK_50_3                                          ; --                                                 ; 128          ;
; Worst-case tpd                                                    ; N/A       ; None                             ; 10.818 ns                        ; iSW[17]                                                                                                                                                           ; oLEDR[17]                                                                                                                                      ; --                                                 ; --                                                 ; 0            ;
; Worst-case th                                                     ; N/A       ; None                             ; -1.058 ns                        ; DRAM_DQ[8]                                                                                                                                                        ; Sdram_Control_4Port:sdram0|mDATAOUT[8]                                                                                                         ; --                                                 ; iCLK_50_3                                          ; 0            ;
; Clock Setup: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0' ; 0.856 ns  ; 166.67 MHz ( period = 6.000 ns ) ; 194.40 MHz ( period = 5.144 ns ) ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                  ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'GPIO_CLKIN_N1'                                      ; 2.490 ns  ; 110.01 MHz ( period = 9.090 ns ) ; 151.52 MHz ( period = 6.600 ns ) ; CCD_Capture:capture0|Y_Cont[3]                                                                                                                                    ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1                                      ; GPIO_CLKIN_N1                                      ; 0            ;
; Clock Setup: 'iCLK_50'                                            ; 6.999 ns  ; 50.00 MHz ( period = 20.000 ns ) ; 166.61 MHz ( period = 6.002 ns ) ; lcd_3wire_config:lcd_config0|m3wire_data[11]                                                                                                                      ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA                                                                                          ; iCLK_50                                            ; iCLK_50                                            ; 0            ;
; Clock Setup: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'     ; 9.899 ns  ; 33.33 MHz ( period = 30.000 ns ) ; 98.02 MHz ( period = 10.202 ns ) ; Binary:binary0|oDVAL                                                                                                                                              ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; 0            ;
; Clock Hold: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'  ; 0.391 ns  ; 166.67 MHz ( period = 6.000 ns ) ; N/A                              ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'GPIO_CLKIN_N1'                                       ; 0.391 ns  ; 110.01 MHz ( period = 9.090 ns ) ; N/A                              ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                                    ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                 ; GPIO_CLKIN_N1                                      ; GPIO_CLKIN_N1                                      ; 0            ;
; Clock Hold: 'iCLK_50'                                             ; 0.391 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; rClk[0]                                                                                                                                                           ; rClk[0]                                                                                                                                        ; iCLK_50                                            ; iCLK_50                                            ; 0            ;
; Clock Hold: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'      ; 0.522 ns  ; 33.33 MHz ( period = 30.000 ns ) ; N/A                              ; Dilation:dilation0|X6[9]                                                                                                                                          ; Dilation:dilation0|X5[9]                                                                                                                       ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; 0            ;
; Total number of failed paths                                      ;           ;                                  ;                                  ;                                                                                                                                                                   ;                                                                                                                                                ;                                                    ;                                                    ; 154          ;
 


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                             ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
; Option                                                              ; Setting            ; From            ; To                        ; Entity Name ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
; Device Name                                                         ; EP2C70F896C6       ;                 ;                           ;             ;
; Timing Models                                                       ; Final              ;                 ;                           ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;                 ;                           ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;                 ;                           ;             ;
; Cut off read during write signal paths                              ; On                 ;                 ;                           ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;                 ;                           ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;                 ;                           ;             ;
; Ignore Clock Settings                                               ; Off                ;                 ;                           ;             ;
; Analyze latches as synchronous elements                             ; On                 ;                 ;                           ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;                 ;                           ;             ;
; Enable Clock Latency                                                ; Off                ;                 ;                           ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;                 ;                           ;             ;
; Number of source nodes to report per destination node               ; 10                 ;                 ;                           ;             ;
; Number of destination nodes to report                               ; 10                 ;                 ;                           ;             ;
; Number of paths to report                                           ; 200                ;                 ;                           ;             ;
; Report Minimum Timing Checks                                        ; Off                ;                 ;                           ;             ;
; Use Fast Timing Models                                              ; Off                ;                 ;                           ;             ;
; Report IO Paths Separately                                          ; Off                ;                 ;                           ;             ;
; Perform Multicorner Analysis                                        ; On                 ;                 ;                           ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;                 ;                           ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;                 ;                           ;             ;
; tsu Requirement                                                     ; 5 ns               ; *               ; rCCD_DATA                 ;             ;
; tsu Requirement                                                     ; 5 ns               ; *               ; rCCD_FVAL                 ;             ;
; tsu Requirement                                                     ; 5 ns               ; *               ; rCCD_LVAL                 ;             ;
; tsu Requirement                                                     ; 1 ns               ; DRAM_DQ         ; *                         ;             ;
; tco Requirement                                                     ; 1 ns               ; *               ; DRAM_DQ                   ;             ;
; Clock Settings                                                      ; CCD_PIXCLK         ;                 ; GPIO_CLKIN_N1             ;             ;
; Clock Settings                                                      ; CCD_MCLK           ;                 ; GPIO_CLKOUT_N1            ;             ;
; Clock Settings                                                      ; CLK50              ;                 ; iCLK_50                   ;             ;
; Clock Settings                                                      ; DRAM0_CLK          ;                 ; oDRAM0_CLK                ;             ;
; Cut Timing Path                                                     ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe9|dffe10a  ; dcfifo_m2o1 ;
; Cut Timing Path                                                     ; On                 ; rdptr_g         ; ws_dgrp|dffpipe11|dffe12a ; dcfifo_m2o1 ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                         ;
+----------------------------------------------------+--------------------+---------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                    ; Clock Setting Name ; Type          ; Fmax Requirement ; Early Latency ; Late Latency ; Based on  ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+----------------------------------------------------+--------------------+---------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+
; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ;                    ; PLL output    ; 166.67 MHz       ; 0.000 ns      ; 0.000 ns     ; iCLK_50_3 ; 10                    ; 3                   ; -2.594 ns ;              ;
; sdram_pll:sdram_pll0|altpll:altpll_component|_clk1 ;                    ; PLL output    ; 166.67 MHz       ; 0.000 ns      ; 0.000 ns     ; iCLK_50_3 ; 10                    ; 3                   ; -4.094 ns ;              ;
; sdram_pll:sdram_pll0|altpll:altpll_component|_clk2 ;                    ; PLL output    ; 166.67 MHz       ; 0.000 ns      ; 0.000 ns     ; iCLK_50_3 ; 10                    ; 3                   ; -4.094 ns ;              ;
; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ;                    ; PLL output    ; 33.33 MHz        ; 0.000 ns      ; 0.000 ns     ; iCLK_50_2 ; 2                     ; 3                   ; -2.608 ns ;              ;
; GPIO_CLKIN_N1                                      ; CCD_PIXCLK         ; User Pin      ; 110.01 MHz       ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; iCLK_50                                            ; CLK50              ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_CLKOUT_N1                                     ; CCD_MCLK           ; User Pin      ; 96.01 MHz        ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; oDRAM0_CLK                                         ; DRAM0_CLK          ; Internal Node ; 150.02 MHz       ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; iCLK_50_3                                          ;                    ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; iCLK_50_2                                          ;                    ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
+----------------------------------------------------+--------------------+---------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+


 
; Clock Setup: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
 
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                            ; To                                                                                                                                                                                       ; From Clock                                         ; To Clock                                           ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
 
; 0.856 ns                                ; 194.40 MHz ( period = 5.144 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.939 ns                ;
; 0.856 ns                                ; 194.40 MHz ( period = 5.144 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.939 ns                ;
; 0.856 ns                                ; 194.40 MHz ( period = 5.144 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.939 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.015 ns                                ; 200.60 MHz ( period = 4.985 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.782 ns                ;
; 1.022 ns                                ; 200.88 MHz ( period = 4.978 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.773 ns                ;
; 1.022 ns                                ; 200.88 MHz ( period = 4.978 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.773 ns                ;
; 1.022 ns                                ; 200.88 MHz ( period = 4.978 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.773 ns                ;
; 1.024 ns                                ; 200.96 MHz ( period = 4.976 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.771 ns                ;
; 1.024 ns                                ; 200.96 MHz ( period = 4.976 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.771 ns                ;
; 1.024 ns                                ; 200.96 MHz ( period = 4.976 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.771 ns                ;
; 1.120 ns                                ; 204.92 MHz ( period = 4.880 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.675 ns                ;
; 1.120 ns                                ; 204.92 MHz ( period = 4.880 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.675 ns                ;
; 1.120 ns                                ; 204.92 MHz ( period = 4.880 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.675 ns                ;
; 1.123 ns                                ; 205.04 MHz ( period = 4.877 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.672 ns                ;
; 1.123 ns                                ; 205.04 MHz ( period = 4.877 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.672 ns                ;
; 1.123 ns                                ; 205.04 MHz ( period = 4.877 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.672 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.181 ns                                ; 207.51 MHz ( period = 4.819 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.616 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.183 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.614 ns                ;
; 1.230 ns                                ; 209.64 MHz ( period = 4.770 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.556 ns                ;
; 1.247 ns                                ; 210.39 MHz ( period = 4.753 ns )                    ; Sdram_Control_4Port:sdram0|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram0|Write                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.540 ns                ;
; 1.255 ns                                ; 210.75 MHz ( period = 4.745 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.809 ns                  ; 4.554 ns                ;
; 1.255 ns                                ; 210.75 MHz ( period = 4.745 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.809 ns                  ; 4.554 ns                ;
; 1.255 ns                                ; 210.75 MHz ( period = 4.745 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.809 ns                  ; 4.554 ns                ;
; 1.268 ns                                ; 211.33 MHz ( period = 4.732 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.516 ns                ;
; 1.277 ns                                ; 211.73 MHz ( period = 4.723 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.765 ns                  ; 4.488 ns                ;
; 1.277 ns                                ; 211.73 MHz ( period = 4.723 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.765 ns                  ; 4.488 ns                ;
; 1.277 ns                                ; 211.73 MHz ( period = 4.723 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.765 ns                  ; 4.488 ns                ;
; 1.277 ns                                ; 211.73 MHz ( period = 4.723 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.765 ns                  ; 4.488 ns                ;
; 1.277 ns                                ; 211.73 MHz ( period = 4.723 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.765 ns                  ; 4.488 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.279 ns                                ; 211.82 MHz ( period = 4.721 ns )                    ; Sdram_Control_4Port:sdram0|ST[5]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.518 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.282 ns                                ; 211.95 MHz ( period = 4.718 ns )                    ; Sdram_Control_4Port:sdram0|ST[3]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.515 ns                ;
; 1.288 ns                                ; 212.22 MHz ( period = 4.712 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.507 ns                ;
; 1.288 ns                                ; 212.22 MHz ( period = 4.712 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.507 ns                ;
; 1.288 ns                                ; 212.22 MHz ( period = 4.712 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.507 ns                ;
; 1.291 ns                                ; 212.36 MHz ( period = 4.709 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.500 ns                ;
; 1.291 ns                                ; 212.36 MHz ( period = 4.709 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.500 ns                ;
; 1.291 ns                                ; 212.36 MHz ( period = 4.709 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.500 ns                ;
; 1.291 ns                                ; 212.36 MHz ( period = 4.709 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.500 ns                ;
; 1.291 ns                                ; 212.36 MHz ( period = 4.709 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.500 ns                ;
; 1.301 ns                                ; 212.81 MHz ( period = 4.699 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.485 ns                ;
; 1.309 ns                                ; 213.17 MHz ( period = 4.691 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.475 ns                ;
; 1.317 ns                                ; 213.54 MHz ( period = 4.683 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.469 ns                ;
; 1.324 ns                                ; 213.86 MHz ( period = 4.676 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|ST[0]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.462 ns                ;
; 1.339 ns                                ; 214.55 MHz ( period = 4.661 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.769 ns                  ; 4.430 ns                ;
; 1.339 ns                                ; 214.55 MHz ( period = 4.661 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.769 ns                  ; 4.430 ns                ;
; 1.339 ns                                ; 214.55 MHz ( period = 4.661 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.769 ns                  ; 4.430 ns                ;
; 1.339 ns                                ; 214.55 MHz ( period = 4.661 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.769 ns                  ; 4.430 ns                ;
; 1.339 ns                                ; 214.55 MHz ( period = 4.661 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.769 ns                  ; 4.430 ns                ;
; 1.339 ns                                ; 214.55 MHz ( period = 4.661 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.769 ns                  ; 4.430 ns                ;
; 1.339 ns                                ; 214.55 MHz ( period = 4.661 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.769 ns                  ; 4.430 ns                ;
; 1.339 ns                                ; 214.55 MHz ( period = 4.661 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.445 ns                ;
; 1.353 ns                                ; 215.19 MHz ( period = 4.647 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.442 ns                ;
; 1.353 ns                                ; 215.19 MHz ( period = 4.647 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.442 ns                ;
; 1.353 ns                                ; 215.19 MHz ( period = 4.647 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.442 ns                ;
; 1.353 ns                                ; 215.19 MHz ( period = 4.647 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.442 ns                ;
; 1.353 ns                                ; 215.19 MHz ( period = 4.647 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.442 ns                ;
; 1.353 ns                                ; 215.19 MHz ( period = 4.647 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.442 ns                ;
; 1.353 ns                                ; 215.19 MHz ( period = 4.647 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.442 ns                ;
; 1.357 ns                                ; 215.38 MHz ( period = 4.643 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.774 ns                  ; 4.417 ns                ;
; 1.357 ns                                ; 215.38 MHz ( period = 4.643 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.774 ns                  ; 4.417 ns                ;
; 1.357 ns                                ; 215.38 MHz ( period = 4.643 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.774 ns                  ; 4.417 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_datain_reg3  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.778 ns                  ; 4.410 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_datain_reg2  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.778 ns                  ; 4.410 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_datain_reg1  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.778 ns                  ; 4.410 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg8 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.794 ns                  ; 4.426 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg7 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.794 ns                  ; 4.426 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg6 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.794 ns                  ; 4.426 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg5 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.794 ns                  ; 4.426 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg4 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.794 ns                  ; 4.426 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg3 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.794 ns                  ; 4.426 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg2 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.794 ns                  ; 4.426 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg1 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.794 ns                  ; 4.426 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.794 ns                  ; 4.426 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_datain_reg0  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.778 ns                  ; 4.410 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_we_reg       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.794 ns                  ; 4.426 ns                ;
; 1.371 ns                                ; 216.03 MHz ( period = 4.629 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.800 ns                  ; 4.429 ns                ;
; 1.371 ns                                ; 216.03 MHz ( period = 4.629 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.800 ns                  ; 4.429 ns                ;
; 1.371 ns                                ; 216.03 MHz ( period = 4.629 ns )                    ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.800 ns                  ; 4.429 ns                ;
; 1.372 ns                                ; 216.08 MHz ( period = 4.628 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.414 ns                ;
; 1.373 ns                                ; 216.12 MHz ( period = 4.627 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.411 ns                ;
; 1.377 ns                                ; 216.31 MHz ( period = 4.623 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.407 ns                ;
; 1.379 ns                                ; 216.40 MHz ( period = 4.621 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.412 ns                ;
; 1.379 ns                                ; 216.40 MHz ( period = 4.621 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.412 ns                ;
; 1.379 ns                                ; 216.40 MHz ( period = 4.621 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.412 ns                ;
; 1.379 ns                                ; 216.40 MHz ( period = 4.621 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.412 ns                ;
; 1.379 ns                                ; 216.40 MHz ( period = 4.621 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.412 ns                ;
; 1.380 ns                                ; 216.45 MHz ( period = 4.620 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.404 ns                ;
; 1.380 ns                                ; 216.45 MHz ( period = 4.620 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.404 ns                ;
; 1.388 ns                                ; 216.83 MHz ( period = 4.612 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.398 ns                ;
; 1.389 ns                                ; 216.87 MHz ( period = 4.611 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.401 ns                ;
; 1.393 ns                                ; 217.06 MHz ( period = 4.607 ns )                    ; Sdram_Control_4Port:sdram1|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram1|ST[0]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.786 ns                  ; 4.393 ns                ;
; 1.407 ns                                ; 217.72 MHz ( period = 4.593 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.798 ns                  ; 4.391 ns                ;
; 1.407 ns                                ; 217.72 MHz ( period = 4.593 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.798 ns                  ; 4.391 ns                ;
; 1.407 ns                                ; 217.72 MHz ( period = 4.593 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.798 ns                  ; 4.391 ns                ;
; 1.408 ns                                ; 217.77 MHz ( period = 4.592 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.809 ns                  ; 4.401 ns                ;
; 1.408 ns                                ; 217.77 MHz ( period = 4.592 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.809 ns                  ; 4.401 ns                ;
; 1.408 ns                                ; 217.77 MHz ( period = 4.592 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.809 ns                  ; 4.401 ns                ;
; 1.410 ns                                ; 217.86 MHz ( period = 4.590 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.374 ns                ;
; 1.413 ns                                ; 218.01 MHz ( period = 4.587 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|Write                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.374 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.414 ns                                ; 218.05 MHz ( period = 4.586 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.811 ns                  ; 4.397 ns                ;
; 1.415 ns                                ; 218.10 MHz ( period = 4.585 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|Write                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.372 ns                ;
; 1.441 ns                                ; 219.35 MHz ( period = 4.559 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.354 ns                ;
; 1.441 ns                                ; 219.35 MHz ( period = 4.559 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.354 ns                ;
; 1.441 ns                                ; 219.35 MHz ( period = 4.559 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.354 ns                ;
; 1.441 ns                                ; 219.35 MHz ( period = 4.559 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.354 ns                ;
; 1.441 ns                                ; 219.35 MHz ( period = 4.559 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.354 ns                ;
; 1.441 ns                                ; 219.35 MHz ( period = 4.559 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.354 ns                ;
; 1.441 ns                                ; 219.35 MHz ( period = 4.559 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.795 ns                  ; 4.354 ns                ;
; 1.444 ns                                ; 219.49 MHz ( period = 4.556 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.340 ns                ;
; 1.445 ns                                ; 219.54 MHz ( period = 4.555 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.345 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[10]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.447 ns                                ; 219.64 MHz ( period = 4.553 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[8]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.797 ns                  ; 4.350 ns                ;
; 1.448 ns                                ; 219.68 MHz ( period = 4.552 ns )                    ; Sdram_Control_4Port:sdram1|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.343 ns                ;
; 1.448 ns                                ; 219.68 MHz ( period = 4.552 ns )                    ; Sdram_Control_4Port:sdram1|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.343 ns                ;
; 1.448 ns                                ; 219.68 MHz ( period = 4.552 ns )                    ; Sdram_Control_4Port:sdram1|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.343 ns                ;
; 1.448 ns                                ; 219.68 MHz ( period = 4.552 ns )                    ; Sdram_Control_4Port:sdram1|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.343 ns                ;
; 1.448 ns                                ; 219.68 MHz ( period = 4.552 ns )                    ; Sdram_Control_4Port:sdram1|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.791 ns                  ; 4.343 ns                ;
; 1.448 ns                                ; 219.68 MHz ( period = 4.552 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.336 ns                ;
; 1.451 ns                                ; 219.83 MHz ( period = 4.549 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.333 ns                ;
; 1.451 ns                                ; 219.83 MHz ( period = 4.549 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.784 ns                  ; 4.333 ns                ;
; 1.457 ns                                ; 220.12 MHz ( period = 4.543 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.330 ns                ;
; 1.459 ns                                ; 220.22 MHz ( period = 4.541 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.800 ns                  ; 4.341 ns                ;
; 1.459 ns                                ; 220.22 MHz ( period = 4.541 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.800 ns                  ; 4.341 ns                ;
; 1.459 ns                                ; 220.22 MHz ( period = 4.541 ns )                    ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.800 ns                  ; 4.341 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                 ;                                                                                                                                                                                          ;                                                    ;                                                    ;                             ;                           ;                         ;
 


 
; Clock Setup: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
 
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                             ; To                                                                                                                                                                                       ; From Clock                                     ; To Clock                                       ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
 
; 9.899 ns                                ; 98.02 MHz ( period = 10.202 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.898 ns                ;
; 9.970 ns                                ; 99.40 MHz ( period = 10.060 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.827 ns                ;
; 10.041 ns                               ; 100.83 MHz ( period = 9.918 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.756 ns                ;
; 10.086 ns                               ; 101.75 MHz ( period = 9.828 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 4.645 ns                ;
; 10.157 ns                               ; 103.24 MHz ( period = 9.686 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 4.574 ns                ;
; 10.200 ns                               ; 104.17 MHz ( period = 9.600 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.597 ns                ;
; 10.228 ns                               ; 104.78 MHz ( period = 9.544 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 4.503 ns                ;
; 10.271 ns                               ; 105.73 MHz ( period = 9.458 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.526 ns                ;
; 10.289 ns                               ; 106.13 MHz ( period = 9.422 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 4.453 ns                ;
; 10.289 ns                               ; 106.13 MHz ( period = 9.422 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 4.453 ns                ;
; 10.289 ns                               ; 106.13 MHz ( period = 9.422 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 4.453 ns                ;
; 10.289 ns                               ; 106.13 MHz ( period = 9.422 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 4.453 ns                ;
; 10.299 ns                               ; 106.36 MHz ( period = 9.402 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 4.432 ns                ;
; 10.342 ns                               ; 107.34 MHz ( period = 9.316 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.455 ns                ;
; 10.370 ns                               ; 107.99 MHz ( period = 9.260 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 4.361 ns                ;
; 10.413 ns                               ; 109.00 MHz ( period = 9.174 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.384 ns                ;
; 10.418 ns                               ; 109.12 MHz ( period = 9.164 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.787 ns                 ; 4.369 ns                ;
; 10.418 ns                               ; 109.12 MHz ( period = 9.164 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.787 ns                 ; 4.369 ns                ;
; 10.418 ns                               ; 109.12 MHz ( period = 9.164 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.787 ns                 ; 4.369 ns                ;
; 10.418 ns                               ; 109.12 MHz ( period = 9.164 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.787 ns                 ; 4.369 ns                ;
; 10.484 ns                               ; 110.72 MHz ( period = 9.032 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.313 ns                ;
; 10.529 ns                               ; 111.83 MHz ( period = 8.942 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 4.202 ns                ;
; 10.551 ns                               ; 112.38 MHz ( period = 8.898 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.747 ns                 ; 4.196 ns                ;
; 10.551 ns                               ; 112.38 MHz ( period = 8.898 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.747 ns                 ; 4.196 ns                ;
; 10.551 ns                               ; 112.38 MHz ( period = 8.898 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.747 ns                 ; 4.196 ns                ;
; 10.551 ns                               ; 112.38 MHz ( period = 8.898 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.747 ns                 ; 4.196 ns                ;
; 10.551 ns                               ; 112.38 MHz ( period = 8.898 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.747 ns                 ; 4.196 ns                ;
; 10.551 ns                               ; 112.38 MHz ( period = 8.898 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.747 ns                 ; 4.196 ns                ;
; 10.551 ns                               ; 112.38 MHz ( period = 8.898 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.747 ns                 ; 4.196 ns                ;
; 10.551 ns                               ; 112.38 MHz ( period = 8.898 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.747 ns                 ; 4.196 ns                ;
; 10.551 ns                               ; 112.38 MHz ( period = 8.898 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.747 ns                 ; 4.196 ns                ;
; 10.555 ns                               ; 112.49 MHz ( period = 8.890 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.242 ns                ;
; 10.600 ns                               ; 113.64 MHz ( period = 8.800 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 4.131 ns                ;
; 10.626 ns                               ; 114.31 MHz ( period = 8.748 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.171 ns                ;
; 10.668 ns                               ; 115.42 MHz ( period = 8.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.129 ns                ;
; 10.668 ns                               ; 115.42 MHz ( period = 8.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.129 ns                ;
; 10.668 ns                               ; 115.42 MHz ( period = 8.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.129 ns                ;
; 10.668 ns                               ; 115.42 MHz ( period = 8.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.129 ns                ;
; 10.668 ns                               ; 115.42 MHz ( period = 8.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 4.129 ns                ;
; 10.671 ns                               ; 115.50 MHz ( period = 8.658 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 4.060 ns                ;
; 10.706 ns                               ; 116.44 MHz ( period = 8.588 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.681 ns                 ; 3.975 ns                ;
; 10.706 ns                               ; 116.44 MHz ( period = 8.588 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.681 ns                 ; 3.975 ns                ;
; 10.706 ns                               ; 116.44 MHz ( period = 8.588 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.681 ns                 ; 3.975 ns                ;
; 10.706 ns                               ; 116.44 MHz ( period = 8.588 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.681 ns                 ; 3.975 ns                ;
; 10.742 ns                               ; 117.43 MHz ( period = 8.516 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.989 ns                ;
; 10.749 ns                               ; 117.62 MHz ( period = 8.502 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; touch_tcon:vga0|oLCD_R[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 4.054 ns                ;
; 10.781 ns                               ; 118.51 MHz ( period = 8.438 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; touch_tcon:vga0|oLCD_R[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.796 ns                 ; 4.015 ns                ;
; 10.813 ns                               ; 119.42 MHz ( period = 8.374 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.918 ns                ;
; 10.945 ns                               ; 123.30 MHz ( period = 8.110 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; touch_tcon:vga0|oLCD_R[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.800 ns                 ; 3.855 ns                ;
; 10.977 ns                               ; 124.29 MHz ( period = 8.046 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.693 ns                 ; 3.716 ns                ;
; 10.977 ns                               ; 124.29 MHz ( period = 8.046 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.693 ns                 ; 3.716 ns                ;
; 10.977 ns                               ; 124.29 MHz ( period = 8.046 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.693 ns                 ; 3.716 ns                ;
; 10.977 ns                               ; 124.29 MHz ( period = 8.046 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.693 ns                 ; 3.716 ns                ;
; 10.977 ns                               ; 124.29 MHz ( period = 8.046 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.693 ns                 ; 3.716 ns                ;
; 10.977 ns                               ; 124.29 MHz ( period = 8.046 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.693 ns                 ; 3.716 ns                ;
; 10.977 ns                               ; 124.29 MHz ( period = 8.046 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.693 ns                 ; 3.716 ns                ;
; 10.977 ns                               ; 124.29 MHz ( period = 8.046 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.693 ns                 ; 3.716 ns                ;
; 10.977 ns                               ; 124.29 MHz ( period = 8.046 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.693 ns                 ; 3.716 ns                ;
; 11.013 ns                               ; 125.41 MHz ( period = 7.974 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.797 ns                 ; 3.784 ns                ;
; 11.060 ns                               ; 126.90 MHz ( period = 7.880 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 3.708 ns                ;
; 11.060 ns                               ; 126.90 MHz ( period = 7.880 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 3.708 ns                ;
; 11.060 ns                               ; 126.90 MHz ( period = 7.880 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 3.708 ns                ;
; 11.060 ns                               ; 126.90 MHz ( period = 7.880 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 3.708 ns                ;
; 11.060 ns                               ; 126.90 MHz ( period = 7.880 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 3.708 ns                ;
; 11.060 ns                               ; 126.90 MHz ( period = 7.880 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 3.708 ns                ;
; 11.060 ns                               ; 126.90 MHz ( period = 7.880 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 3.708 ns                ;
; 11.060 ns                               ; 126.90 MHz ( period = 7.880 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 3.708 ns                ;
; 11.060 ns                               ; 126.90 MHz ( period = 7.880 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 3.708 ns                ;
; 11.066 ns                               ; 127.10 MHz ( period = 7.868 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.773 ns                 ; 3.707 ns                ;
; 11.066 ns                               ; 127.10 MHz ( period = 7.868 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.773 ns                 ; 3.707 ns                ;
; 11.066 ns                               ; 127.10 MHz ( period = 7.868 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.773 ns                 ; 3.707 ns                ;
; 11.066 ns                               ; 127.10 MHz ( period = 7.868 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.773 ns                 ; 3.707 ns                ;
; 11.066 ns                               ; 127.10 MHz ( period = 7.868 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.773 ns                 ; 3.707 ns                ;
; 11.066 ns                               ; 127.10 MHz ( period = 7.868 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.773 ns                 ; 3.707 ns                ;
; 11.066 ns                               ; 127.10 MHz ( period = 7.868 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.773 ns                 ; 3.707 ns                ;
; 11.066 ns                               ; 127.10 MHz ( period = 7.868 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.773 ns                 ; 3.707 ns                ;
; 11.066 ns                               ; 127.10 MHz ( period = 7.868 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.773 ns                 ; 3.707 ns                ;
; 11.075 ns                               ; 127.39 MHz ( period = 7.850 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.737 ns                 ; 3.662 ns                ;
; 11.075 ns                               ; 127.39 MHz ( period = 7.850 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.737 ns                 ; 3.662 ns                ;
; 11.094 ns                               ; 128.01 MHz ( period = 7.812 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.637 ns                ;
; 11.094 ns                               ; 128.01 MHz ( period = 7.812 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.637 ns                ;
; 11.094 ns                               ; 128.01 MHz ( period = 7.812 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.637 ns                ;
; 11.094 ns                               ; 128.01 MHz ( period = 7.812 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.637 ns                ;
; 11.094 ns                               ; 128.01 MHz ( period = 7.812 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.637 ns                ;
; 11.118 ns                               ; 128.80 MHz ( period = 7.764 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.798 ns                 ; 3.680 ns                ;
; 11.190 ns                               ; 131.23 MHz ( period = 7.620 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.707 ns                 ; 3.517 ns                ;
; 11.190 ns                               ; 131.23 MHz ( period = 7.620 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.707 ns                 ; 3.517 ns                ;
; 11.190 ns                               ; 131.23 MHz ( period = 7.620 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.707 ns                 ; 3.517 ns                ;
; 11.190 ns                               ; 131.23 MHz ( period = 7.620 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.707 ns                 ; 3.517 ns                ;
; 11.190 ns                               ; 131.23 MHz ( period = 7.620 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.707 ns                 ; 3.517 ns                ;
; 11.190 ns                               ; 131.23 MHz ( period = 7.620 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.707 ns                 ; 3.517 ns                ;
; 11.190 ns                               ; 131.23 MHz ( period = 7.620 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.707 ns                 ; 3.517 ns                ;
; 11.190 ns                               ; 131.23 MHz ( period = 7.620 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.707 ns                 ; 3.517 ns                ;
; 11.190 ns                               ; 131.23 MHz ( period = 7.620 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.707 ns                 ; 3.517 ns                ;
; 11.200 ns                               ; 131.58 MHz ( period = 7.600 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.531 ns                ;
; 11.211 ns                               ; 131.96 MHz ( period = 7.578 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; touch_tcon:vga0|oLCD_R[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 3.592 ns                ;
; 11.249 ns                               ; 133.30 MHz ( period = 7.502 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.849 ns                 ; 3.600 ns                ;
; 11.275 ns                               ; 134.23 MHz ( period = 7.450 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; touch_tcon:vga0|oLCD_R[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.800 ns                 ; 3.525 ns                ;
; 11.317 ns                               ; 135.76 MHz ( period = 7.366 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.795 ns                 ; 3.478 ns                ;
; 11.349 ns                               ; 136.95 MHz ( period = 7.302 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.727 ns                 ; 3.378 ns                ;
; 11.349 ns                               ; 136.95 MHz ( period = 7.302 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.727 ns                 ; 3.378 ns                ;
; 11.349 ns                               ; 136.95 MHz ( period = 7.302 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.727 ns                 ; 3.378 ns                ;
; 11.352 ns                               ; 137.06 MHz ( period = 7.296 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; touch_tcon:vga0|oLCD_B[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.862 ns                 ; 3.510 ns                ;
; 11.420 ns                               ; 139.66 MHz ( period = 7.160 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_R[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 3.383 ns                ;
; 11.432 ns                               ; 140.13 MHz ( period = 7.136 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; touch_tcon:vga0|oLCD_B[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.854 ns                 ; 3.422 ns                ;
; 11.433 ns                               ; 140.17 MHz ( period = 7.134 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_B[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 3.370 ns                ;
; 11.438 ns                               ; 140.37 MHz ( period = 7.124 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.800 ns                 ; 3.362 ns                ;
; 11.446 ns                               ; 140.69 MHz ( period = 7.108 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; touch_tcon:vga0|oLCD_B[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 3.423 ns                ;
; 11.449 ns                               ; 140.81 MHz ( period = 7.102 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.800 ns                 ; 3.351 ns                ;
; 11.479 ns                               ; 142.01 MHz ( period = 7.042 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_R[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 3.324 ns                ;
; 11.500 ns                               ; 142.86 MHz ( period = 7.000 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.719 ns                 ; 3.219 ns                ;
; 11.500 ns                               ; 142.86 MHz ( period = 7.000 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.719 ns                 ; 3.219 ns                ;
; 11.500 ns                               ; 142.86 MHz ( period = 7.000 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.719 ns                 ; 3.219 ns                ;
; 11.500 ns                               ; 142.86 MHz ( period = 7.000 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.719 ns                 ; 3.219 ns                ;
; 11.500 ns                               ; 142.86 MHz ( period = 7.000 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.719 ns                 ; 3.219 ns                ;
; 11.500 ns                               ; 142.86 MHz ( period = 7.000 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.719 ns                 ; 3.219 ns                ;
; 11.500 ns                               ; 142.86 MHz ( period = 7.000 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.719 ns                 ; 3.219 ns                ;
; 11.500 ns                               ; 142.86 MHz ( period = 7.000 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.719 ns                 ; 3.219 ns                ;
; 11.500 ns                               ; 142.86 MHz ( period = 7.000 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.719 ns                 ; 3.219 ns                ;
; 11.522 ns                               ; 143.76 MHz ( period = 6.956 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; touch_tcon:vga0|oLCD_B[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.854 ns                 ; 3.332 ns                ;
; 11.565 ns                               ; 145.56 MHz ( period = 6.870 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; touch_tcon:vga0|oLCD_B[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.850 ns                 ; 3.285 ns                ;
; 11.573 ns                               ; 145.90 MHz ( period = 6.854 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; touch_tcon:vga0|oLCD_R[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.801 ns                 ; 3.228 ns                ;
; 11.662 ns                               ; 149.79 MHz ( period = 6.676 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.795 ns                 ; 3.133 ns                ;
; 11.679 ns                               ; 150.56 MHz ( period = 6.642 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; touch_tcon:vga0|oLCD_R[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.796 ns                 ; 3.117 ns                ;
; 11.679 ns                               ; 150.56 MHz ( period = 6.642 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.849 ns                 ; 3.170 ns                ;
; 11.698 ns                               ; 151.42 MHz ( period = 6.604 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; touch_tcon:vga0|oLCD_R[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.808 ns                 ; 3.110 ns                ;
; 11.732 ns                               ; 153.00 MHz ( period = 6.536 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; touch_tcon:vga0|oLCD_B[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.849 ns                 ; 3.117 ns                ;
; 11.734 ns                               ; 153.09 MHz ( period = 6.532 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; touch_tcon:vga0|oLCD_B[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.857 ns                 ; 3.123 ns                ;
; 11.736 ns                               ; 153.19 MHz ( period = 6.528 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; touch_tcon:vga0|oLCD_B[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.850 ns                 ; 3.114 ns                ;
; 11.792 ns                               ; 155.86 MHz ( period = 6.416 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_B[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.796 ns                 ; 3.004 ns                ;
; 11.948 ns                               ; 163.83 MHz ( period = 6.104 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_G[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 2.855 ns                ;
; 11.956 ns                               ; 164.26 MHz ( period = 6.088 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_B[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.862 ns                 ; 2.906 ns                ;
; 12.040 ns                               ; 168.92 MHz ( period = 5.920 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.849 ns                 ; 2.809 ns                ;
; 12.061 ns                               ; 170.13 MHz ( period = 5.878 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; touch_tcon:vga0|oLCD_R[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.850 ns                 ; 2.789 ns                ;
; 12.083 ns                               ; 171.41 MHz ( period = 5.834 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_R[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.796 ns                 ; 2.713 ns                ;
; 12.103 ns                               ; 172.59 MHz ( period = 5.794 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; touch_tcon:vga0|oLCD_B[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.854 ns                 ; 2.751 ns                ;
; 12.115 ns                               ; 173.31 MHz ( period = 5.770 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.795 ns                 ; 2.680 ns                ;
; 12.154 ns                               ; 175.69 MHz ( period = 5.692 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_B[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.854 ns                 ; 2.700 ns                ;
; 12.170 ns                               ; 176.68 MHz ( period = 5.660 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; touch_tcon:vga0|oLCD_B[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.850 ns                 ; 2.680 ns                ;
; 12.227 ns                               ; 180.31 MHz ( period = 5.546 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_R[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 2.642 ns                ;
; 12.238 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_R[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.862 ns                 ; 2.624 ns                ;
; 12.270 ns                               ; 183.15 MHz ( period = 5.460 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_B[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 2.599 ns                ;
; 12.274 ns                               ; 183.42 MHz ( period = 5.452 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_R[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.854 ns                 ; 2.580 ns                ;
; 12.282 ns                               ; 183.96 MHz ( period = 5.436 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.861 ns                 ; 2.579 ns                ;
; 12.305 ns                               ; 185.53 MHz ( period = 5.390 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_B[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.795 ns                 ; 2.490 ns                ;
; 12.362 ns                               ; 189.54 MHz ( period = 5.276 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.861 ns                 ; 2.499 ns                ;
; 12.493 ns                               ; 199.44 MHz ( period = 5.014 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; touch_tcon:vga0|oLCD_R[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.854 ns                 ; 2.361 ns                ;
; 12.500 ns                               ; 200.00 MHz ( period = 5.000 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_G[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.795 ns                 ; 2.295 ns                ;
; 12.692 ns                               ; 216.64 MHz ( period = 4.616 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_G[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.795 ns                 ; 2.103 ns                ;
; 12.731 ns                               ; 220.36 MHz ( period = 4.538 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; touch_tcon:vga0|oLCD_G[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.850 ns                 ; 2.119 ns                ;
; 12.765 ns                               ; 223.71 MHz ( period = 4.470 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; touch_tcon:vga0|oLCD_G[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.854 ns                 ; 2.089 ns                ;
; 12.783 ns                               ; 225.53 MHz ( period = 4.434 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_G[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.862 ns                 ; 2.079 ns                ;
; 12.786 ns                               ; 225.84 MHz ( period = 4.428 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_G[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.869 ns                 ; 2.083 ns                ;
; 12.815 ns                               ; 228.83 MHz ( period = 4.370 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_G[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.854 ns                 ; 2.039 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.780 ns                 ; 5.870 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.780 ns                 ; 5.870 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg1                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.780 ns                 ; 5.870 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg9                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.899 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg8                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.899 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg7                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.899 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg6                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.899 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg5                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.899 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg4                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.899 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg3                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.899 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg2                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.899 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg1                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.899 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg0                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.899 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg9                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg8                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg7                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg6                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg5                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg4                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg3                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg2                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg1                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg0                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg0                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.780 ns                 ; 5.870 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_we_reg                      ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.871 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[29]                                        ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.756 ns                 ; 5.846 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[19]                                        ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.756 ns                 ; 5.846 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[18]                                        ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.756 ns                 ; 5.846 ns                ;
; 23.910 ns                               ; 164.20 MHz ( period = 6.090 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[9]                                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.756 ns                 ; 5.846 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.780 ns                 ; 5.757 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.780 ns                 ; 5.757 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg1                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.780 ns                 ; 5.757 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg9                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.786 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg8                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.786 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg7                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.786 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg6                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.786 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg5                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.786 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg4                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.786 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg3                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.786 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg2                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.786 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg1                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.786 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~portb_address_reg0                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.809 ns                 ; 5.786 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg9                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.758 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg8                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.758 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg7                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.758 ns                ;
; 24.023 ns                               ; 167.31 MHz ( period = 5.977 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_address_reg6                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.781 ns                 ; 5.758 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                  ;                                                                                                                                                                                          ;                                                ;                                                ;                             ;                           ;                         ;
 


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'GPIO_CLKIN_N1'                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------+-------------------------+---------------+---------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                            ; To                      ; From Clock    ; To Clock      ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------+-------------------------+---------------+---------------+-----------------------------+---------------------------+-------------------------+
; 2.490 ns                                ; 151.52 MHz ( period = 6.600 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.376 ns                ;
; 2.534 ns                                ; 152.53 MHz ( period = 6.556 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.332 ns                ;
; 2.554 ns                                ; 153.00 MHz ( period = 6.536 ns )                    ; CCD_Capture:capture0|X_Cont[0]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.862 ns                  ; 6.308 ns                ;
; 2.556 ns                                ; 153.05 MHz ( period = 6.534 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.312 ns                ;
; 2.594 ns                                ; 153.94 MHz ( period = 6.496 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.272 ns                ;
; 2.600 ns                                ; 154.08 MHz ( period = 6.490 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.268 ns                ;
; 2.606 ns                                ; 154.23 MHz ( period = 6.484 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 6.261 ns                ;
; 2.612 ns                                ; 154.37 MHz ( period = 6.478 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.254 ns                ;
; 2.625 ns                                ; 154.68 MHz ( period = 6.465 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.241 ns                ;
; 2.636 ns                                ; 154.94 MHz ( period = 6.454 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.232 ns                ;
; 2.648 ns                                ; 155.23 MHz ( period = 6.442 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.218 ns                ;
; 2.650 ns                                ; 155.28 MHz ( period = 6.440 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 6.217 ns                ;
; 2.660 ns                                ; 155.52 MHz ( period = 6.430 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.208 ns                ;
; 2.669 ns                                ; 155.74 MHz ( period = 6.421 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.197 ns                ;
; 2.670 ns                                ; 155.76 MHz ( period = 6.420 ns )                    ; CCD_Capture:capture0|X_Cont[0]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.863 ns                  ; 6.193 ns                ;
; 2.678 ns                                ; 155.96 MHz ( period = 6.412 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.190 ns                ;
; 2.680 ns                                ; 156.01 MHz ( period = 6.410 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.188 ns                ;
; 2.680 ns                                ; 156.01 MHz ( period = 6.410 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.186 ns                ;
; 2.689 ns                                ; 156.23 MHz ( period = 6.401 ns )                    ; CCD_Capture:capture0|X_Cont[0]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.862 ns                  ; 6.173 ns                ;
; 2.693 ns                                ; 156.32 MHz ( period = 6.397 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.173 ns                ;
; 2.710 ns                                ; 156.74 MHz ( period = 6.380 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 6.157 ns                ;
; 2.714 ns                                ; 156.84 MHz ( period = 6.376 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.154 ns                ;
; 2.728 ns                                ; 157.18 MHz ( period = 6.362 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 6.139 ns                ;
; 2.729 ns                                ; 157.21 MHz ( period = 6.361 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.137 ns                ;
; 2.737 ns                                ; 157.41 MHz ( period = 6.353 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.129 ns                ;
; 2.740 ns                                ; 157.48 MHz ( period = 6.350 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.128 ns                ;
; 2.746 ns                                ; 157.63 MHz ( period = 6.344 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.122 ns                ;
; 2.747 ns                                ; 157.65 MHz ( period = 6.343 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.119 ns                ;
; 2.748 ns                                ; 157.68 MHz ( period = 6.342 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 6.119 ns                ;
; 2.757 ns                                ; 157.90 MHz ( period = 6.333 ns )                    ; CCD_Capture:capture0|X_Cont[0]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.862 ns                  ; 6.105 ns                ;
; 2.758 ns                                ; 157.93 MHz ( period = 6.332 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.110 ns                ;
; 2.764 ns                                ; 158.08 MHz ( period = 6.326 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 6.103 ns                ;
; 2.766 ns                                ; 158.13 MHz ( period = 6.324 ns )                    ; CCD_Capture:capture0|Y_Cont[13] ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.100 ns                ;
; 2.783 ns                                ; 158.55 MHz ( period = 6.307 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.083 ns                ;
; 2.792 ns                                ; 158.78 MHz ( period = 6.298 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 6.075 ns                ;
; 2.794 ns                                ; 158.83 MHz ( period = 6.296 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.074 ns                ;
; 2.796 ns                                ; 158.88 MHz ( period = 6.294 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 6.071 ns                ;
; 2.797 ns                                ; 158.91 MHz ( period = 6.293 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.069 ns                ;
; 2.799 ns                                ; 158.96 MHz ( period = 6.291 ns )                    ; CCD_Capture:capture0|Y_Cont[10] ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.067 ns                ;
; 2.812 ns                                ; 159.29 MHz ( period = 6.278 ns )                    ; CCD_Capture:capture0|X_Cont[0]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.863 ns                  ; 6.051 ns                ;
; 2.815 ns                                ; 159.36 MHz ( period = 6.275 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.051 ns                ;
; 2.815 ns                                ; 159.36 MHz ( period = 6.275 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.051 ns                ;
; 2.819 ns                                ; 159.46 MHz ( period = 6.271 ns )                    ; CCD_Capture:capture0|Y_Cont[12] ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.047 ns                ;
; 2.826 ns                                ; 159.64 MHz ( period = 6.264 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.042 ns                ;
; 2.832 ns                                ; 159.80 MHz ( period = 6.258 ns )                    ; CCD_Capture:capture0|Y_Cont[13] ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.036 ns                ;
; 2.851 ns                                ; 160.28 MHz ( period = 6.239 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.015 ns                ;
; 2.852 ns                                ; 160.31 MHz ( period = 6.238 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 6.015 ns                ;
; 2.860 ns                                ; 160.51 MHz ( period = 6.230 ns )                    ; CCD_Capture:capture0|Y_Cont[1]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 6.006 ns                ;
; 2.865 ns                                ; 160.64 MHz ( period = 6.225 ns )                    ; CCD_Capture:capture0|Y_Cont[10] ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 6.003 ns                ;
; 2.870 ns                                ; 160.77 MHz ( period = 6.220 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.997 ns                ;
; 2.872 ns                                ; 160.82 MHz ( period = 6.218 ns )                    ; CCD_Capture:capture0|Y_Cont[0]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.994 ns                ;
; 2.882 ns                                ; 161.08 MHz ( period = 6.208 ns )                    ; CCD_Capture:capture0|Y_Cont[13] ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.985 ns                ;
; 2.883 ns                                ; 161.11 MHz ( period = 6.207 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.983 ns                ;
; 2.885 ns                                ; 161.16 MHz ( period = 6.205 ns )                    ; CCD_Capture:capture0|Y_Cont[12] ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.983 ns                ;
; 2.891 ns                                ; 161.32 MHz ( period = 6.199 ns )                    ; CCD_Capture:capture0|Y_Cont[8]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.975 ns                ;
; 2.901 ns                                ; 161.58 MHz ( period = 6.189 ns )                    ; CCD_Capture:capture0|Y_Cont[13] ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.965 ns                ;
; 2.906 ns                                ; 161.71 MHz ( period = 6.184 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.961 ns                ;
; 2.910 ns                                ; 161.81 MHz ( period = 6.180 ns )                    ; CCD_Capture:capture0|X_Cont[0]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.864 ns                  ; 5.954 ns                ;
; 2.912 ns                                ; 161.86 MHz ( period = 6.178 ns )                    ; CCD_Capture:capture0|Y_Cont[13] ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.956 ns                ;
; 2.915 ns                                ; 161.94 MHz ( period = 6.175 ns )                    ; CCD_Capture:capture0|Y_Cont[10] ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.952 ns                ;
; 2.926 ns                                ; 162.23 MHz ( period = 6.164 ns )                    ; CCD_Capture:capture0|Y_Cont[1]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.942 ns                ;
; 2.934 ns                                ; 162.44 MHz ( period = 6.156 ns )                    ; CCD_Capture:capture0|Y_Cont[10] ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.932 ns                ;
; 2.935 ns                                ; 162.47 MHz ( period = 6.155 ns )                    ; CCD_Capture:capture0|Y_Cont[12] ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.932 ns                ;
; 2.938 ns                                ; 162.55 MHz ( period = 6.152 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.929 ns                ;
; 2.943 ns                                ; 162.68 MHz ( period = 6.147 ns )                    ; CCD_Capture:capture0|Y_Cont[15] ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.923 ns                ;
; 2.945 ns                                ; 162.73 MHz ( period = 6.145 ns )                    ; CCD_Capture:capture0|Y_Cont[10] ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.923 ns                ;
; 2.954 ns                                ; 162.97 MHz ( period = 6.136 ns )                    ; CCD_Capture:capture0|Y_Cont[7]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.912 ns                ;
; 2.954 ns                                ; 162.97 MHz ( period = 6.136 ns )                    ; CCD_Capture:capture0|Y_Cont[12] ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.912 ns                ;
; 2.955 ns                                ; 163.00 MHz ( period = 6.135 ns )                    ; CCD_Capture:capture0|Y_Cont[6]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.911 ns                ;
; 2.957 ns                                ; 163.05 MHz ( period = 6.133 ns )                    ; CCD_Capture:capture0|Y_Cont[8]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.911 ns                ;
; 2.965 ns                                ; 163.27 MHz ( period = 6.125 ns )                    ; CCD_Capture:capture0|Y_Cont[12] ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.903 ns                ;
; 2.969 ns                                ; 163.37 MHz ( period = 6.121 ns )                    ; CCD_Capture:capture0|Y_Cont[13] ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.897 ns                ;
; 2.976 ns                                ; 163.56 MHz ( period = 6.114 ns )                    ; CCD_Capture:capture0|Y_Cont[1]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.891 ns                ;
; 2.988 ns                                ; 163.88 MHz ( period = 6.102 ns )                    ; CCD_Capture:capture0|Y_Cont[0]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.879 ns                ;
; 2.990 ns                                ; 163.93 MHz ( period = 6.100 ns )                    ; CCD_Capture:capture0|X_Cont[0]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.864 ns                  ; 5.874 ns                ;
; 2.993 ns                                ; 164.02 MHz ( period = 6.097 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.875 ns                ;
; 2.995 ns                                ; 164.07 MHz ( period = 6.095 ns )                    ; CCD_Capture:capture0|Y_Cont[1]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.871 ns                ;
; 3.002 ns                                ; 164.26 MHz ( period = 6.088 ns )                    ; CCD_Capture:capture0|Y_Cont[10] ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.864 ns                ;
; 3.006 ns                                ; 164.37 MHz ( period = 6.084 ns )                    ; CCD_Capture:capture0|Y_Cont[1]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.862 ns                ;
; 3.007 ns                                ; 164.39 MHz ( period = 6.083 ns )                    ; CCD_Capture:capture0|Y_Cont[8]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.860 ns                ;
; 3.007 ns                                ; 164.39 MHz ( period = 6.083 ns )                    ; CCD_Capture:capture0|Y_Cont[0]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.859 ns                ;
; 3.009 ns                                ; 164.45 MHz ( period = 6.081 ns )                    ; CCD_Capture:capture0|Y_Cont[15] ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.859 ns                ;
; 3.020 ns                                ; 164.74 MHz ( period = 6.070 ns )                    ; CCD_Capture:capture0|Y_Cont[7]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.848 ns                ;
; 3.021 ns                                ; 164.77 MHz ( period = 6.069 ns )                    ; CCD_Capture:capture0|Y_Cont[6]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.847 ns                ;
; 3.022 ns                                ; 164.80 MHz ( period = 6.068 ns )                    ; CCD_Capture:capture0|Y_Cont[12] ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.844 ns                ;
; 3.024 ns                                ; 164.85 MHz ( period = 6.066 ns )                    ; CCD_Capture:capture0|Y_Cont[13] ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.843 ns                ;
; 3.026 ns                                ; 164.91 MHz ( period = 6.064 ns )                    ; CCD_Capture:capture0|Y_Cont[5]  ; RAW2RGB:raw0|rGreen[11] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.840 ns                ;
; 3.026 ns                                ; 164.91 MHz ( period = 6.064 ns )                    ; CCD_Capture:capture0|Y_Cont[8]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.840 ns                ;
; 3.037 ns                                ; 165.21 MHz ( period = 6.053 ns )                    ; CCD_Capture:capture0|Y_Cont[8]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.831 ns                ;
; 3.037 ns                                ; 165.21 MHz ( period = 6.053 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.831 ns                ;
; 3.044 ns                                ; 165.40 MHz ( period = 6.046 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.824 ns                ;
; 3.057 ns                                ; 165.76 MHz ( period = 6.033 ns )                    ; CCD_Capture:capture0|Y_Cont[10] ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.810 ns                ;
; 3.059 ns                                ; 165.81 MHz ( period = 6.031 ns )                    ; CCD_Capture:capture0|Y_Cont[15] ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.808 ns                ;
; 3.063 ns                                ; 165.92 MHz ( period = 6.027 ns )                    ; CCD_Capture:capture0|Y_Cont[1]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.803 ns                ;
; 3.070 ns                                ; 166.11 MHz ( period = 6.020 ns )                    ; CCD_Capture:capture0|Y_Cont[7]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.797 ns                ;
; 3.071 ns                                ; 166.14 MHz ( period = 6.019 ns )                    ; CCD_Capture:capture0|Y_Cont[6]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.796 ns                ;
; 3.075 ns                                ; 166.25 MHz ( period = 6.015 ns )                    ; CCD_Capture:capture0|Y_Cont[0]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.791 ns                ;
; 3.077 ns                                ; 166.31 MHz ( period = 6.013 ns )                    ; CCD_Capture:capture0|Y_Cont[12] ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.790 ns                ;
; 3.078 ns                                ; 166.33 MHz ( period = 6.012 ns )                    ; CCD_Capture:capture0|Y_Cont[15] ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.788 ns                ;
; 3.088 ns                                ; 166.61 MHz ( period = 6.002 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.780 ns                ;
; 3.089 ns                                ; 166.64 MHz ( period = 6.001 ns )                    ; CCD_Capture:capture0|Y_Cont[15] ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.779 ns                ;
; 3.089 ns                                ; 166.64 MHz ( period = 6.001 ns )                    ; CCD_Capture:capture0|Y_Cont[7]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.777 ns                ;
; 3.090 ns                                ; 166.67 MHz ( period = 6.000 ns )                    ; CCD_Capture:capture0|Y_Cont[6]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.776 ns                ;
; 3.092 ns                                ; 166.72 MHz ( period = 5.998 ns )                    ; CCD_Capture:capture0|Y_Cont[5]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.776 ns                ;
; 3.094 ns                                ; 166.78 MHz ( period = 5.996 ns )                    ; CCD_Capture:capture0|Y_Cont[8]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.772 ns                ;
; 3.097 ns                                ; 166.86 MHz ( period = 5.993 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.771 ns                ;
; 3.098 ns                                ; 166.89 MHz ( period = 5.992 ns )                    ; CCD_Capture:capture0|X_Cont[0]  ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.864 ns                  ; 5.766 ns                ;
; 3.100 ns                                ; 166.94 MHz ( period = 5.990 ns )                    ; CCD_Capture:capture0|Y_Cont[7]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.768 ns                ;
; 3.101 ns                                ; 166.97 MHz ( period = 5.989 ns )                    ; CCD_Capture:capture0|Y_Cont[6]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.767 ns                ;
; 3.115 ns                                ; 167.36 MHz ( period = 5.975 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.753 ns                ;
; 3.118 ns                                ; 167.45 MHz ( period = 5.972 ns )                    ; CCD_Capture:capture0|Y_Cont[1]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.749 ns                ;
; 3.123 ns                                ; 167.59 MHz ( period = 5.967 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.745 ns                ;
; 3.130 ns                                ; 167.79 MHz ( period = 5.960 ns )                    ; CCD_Capture:capture0|Y_Cont[0]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.737 ns                ;
; 3.140 ns                                ; 168.07 MHz ( period = 5.950 ns )                    ; CCD_Capture:capture0|Y_Cont[0]  ; RAW2RGB:raw0|rGreen[6]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.728 ns                ;
; 3.140 ns                                ; 168.07 MHz ( period = 5.950 ns )                    ; CCD_Capture:capture0|X_Cont[11] ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.728 ns                ;
; 3.142 ns                                ; 168.12 MHz ( period = 5.948 ns )                    ; CCD_Capture:capture0|Y_Cont[5]  ; RAW2RGB:raw0|rGreen[12] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.725 ns                ;
; 3.146 ns                                ; 168.24 MHz ( period = 5.944 ns )                    ; CCD_Capture:capture0|Y_Cont[15] ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.720 ns                ;
; 3.148 ns                                ; 168.29 MHz ( period = 5.942 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.720 ns                ;
; 3.149 ns                                ; 168.32 MHz ( period = 5.941 ns )                    ; CCD_Capture:capture0|X_Cont[0]  ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.864 ns                  ; 5.715 ns                ;
; 3.149 ns                                ; 168.32 MHz ( period = 5.941 ns )                    ; CCD_Capture:capture0|Y_Cont[8]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.718 ns                ;
; 3.151 ns                                ; 168.38 MHz ( period = 5.939 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.717 ns                ;
; 3.157 ns                                ; 168.55 MHz ( period = 5.933 ns )                    ; CCD_Capture:capture0|Y_Cont[7]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.709 ns                ;
; 3.158 ns                                ; 168.58 MHz ( period = 5.932 ns )                    ; CCD_Capture:capture0|Y_Cont[6]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.708 ns                ;
; 3.160 ns                                ; 168.63 MHz ( period = 5.930 ns )                    ; CCD_Capture:capture0|X_Cont[3]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.708 ns                ;
; 3.161 ns                                ; 168.66 MHz ( period = 5.929 ns )                    ; CCD_Capture:capture0|Y_Cont[5]  ; RAW2RGB:raw0|rGreen[9]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.705 ns                ;
; 3.166 ns                                ; 168.80 MHz ( period = 5.924 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.702 ns                ;
; 3.167 ns                                ; 168.83 MHz ( period = 5.923 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.701 ns                ;
; 3.172 ns                                ; 168.98 MHz ( period = 5.918 ns )                    ; CCD_Capture:capture0|Y_Cont[5]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.696 ns                ;
; 3.183 ns                                ; 169.29 MHz ( period = 5.907 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.685 ns                ;
; 3.201 ns                                ; 169.81 MHz ( period = 5.889 ns )                    ; CCD_Capture:capture0|Y_Cont[15] ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.666 ns                ;
; 3.202 ns                                ; 169.84 MHz ( period = 5.888 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.666 ns                ;
; 3.207 ns                                ; 169.98 MHz ( period = 5.883 ns )                    ; CCD_Capture:capture0|X_Cont[11] ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.863 ns                  ; 5.656 ns                ;
; 3.212 ns                                ; 170.13 MHz ( period = 5.878 ns )                    ; CCD_Capture:capture0|Y_Cont[7]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.655 ns                ;
; 3.213 ns                                ; 170.15 MHz ( period = 5.877 ns )                    ; CCD_Capture:capture0|Y_Cont[6]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.654 ns                ;
; 3.220 ns                                ; 170.36 MHz ( period = 5.870 ns )                    ; CCD_Capture:capture0|Y_Cont[0]  ; RAW2RGB:raw0|rGreen[7]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.648 ns                ;
; 3.227 ns                                ; 170.56 MHz ( period = 5.863 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.641 ns                ;
; 3.227 ns                                ; 170.56 MHz ( period = 5.863 ns )                    ; CCD_Capture:capture0|X_Cont[3]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.863 ns                  ; 5.636 ns                ;
; 3.229 ns                                ; 170.62 MHz ( period = 5.861 ns )                    ; CCD_Capture:capture0|X_Cont[2]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.639 ns                ;
; 3.229 ns                                ; 170.62 MHz ( period = 5.861 ns )                    ; CCD_Capture:capture0|Y_Cont[5]  ; RAW2RGB:raw0|rGreen[8]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.866 ns                  ; 5.637 ns                ;
; 3.234 ns                                ; 170.77 MHz ( period = 5.856 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.634 ns                ;
; 3.245 ns                                ; 171.09 MHz ( period = 5.845 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.623 ns                ;
; 3.254 ns                                ; 171.35 MHz ( period = 5.836 ns )                    ; CCD_Capture:capture0|X_Cont[0]  ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.864 ns                  ; 5.610 ns                ;
; 3.258 ns                                ; 171.47 MHz ( period = 5.832 ns )                    ; CCD_Capture:capture0|X_Cont[11] ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.878 ns                  ; 5.620 ns                ;
; 3.267 ns                                ; 171.73 MHz ( period = 5.823 ns )                    ; CCD_Capture:capture0|X_Cont[9]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.601 ns                ;
; 3.269 ns                                ; 171.79 MHz ( period = 5.821 ns )                    ; CCD_Capture:capture0|Y_Cont[13] ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.599 ns                ;
; 3.269 ns                                ; 171.79 MHz ( period = 5.821 ns )                    ; CCD_Capture:capture0|X_Cont[15] ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.599 ns                ;
; 3.278 ns                                ; 172.06 MHz ( period = 5.812 ns )                    ; CCD_Capture:capture0|X_Cont[3]  ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.878 ns                  ; 5.600 ns                ;
; 3.281 ns                                ; 172.15 MHz ( period = 5.809 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.587 ns                ;
; 3.284 ns                                ; 172.24 MHz ( period = 5.806 ns )                    ; CCD_Capture:capture0|Y_Cont[5]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.867 ns                  ; 5.583 ns                ;
; 3.296 ns                                ; 172.59 MHz ( period = 5.794 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.872 ns                  ; 5.576 ns                ;
; 3.296 ns                                ; 172.59 MHz ( period = 5.794 ns )                    ; CCD_Capture:capture0|X_Cont[2]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.863 ns                  ; 5.567 ns                ;
; 3.302 ns                                ; 172.77 MHz ( period = 5.788 ns )                    ; CCD_Capture:capture0|Y_Cont[10] ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.566 ns                ;
; 3.313 ns                                ; 173.10 MHz ( period = 5.777 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.555 ns                ;
; 3.320 ns                                ; 173.31 MHz ( period = 5.770 ns )                    ; CCD_Capture:capture0|Y_Cont[13] ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.548 ns                ;
; 3.322 ns                                ; 173.37 MHz ( period = 5.768 ns )                    ; CCD_Capture:capture0|Y_Cont[12] ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.546 ns                ;
; 3.326 ns                                ; 173.49 MHz ( period = 5.764 ns )                    ; CCD_Capture:capture0|X_Cont[8]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.542 ns                ;
; 3.328 ns                                ; 173.55 MHz ( period = 5.762 ns )                    ; CCD_Capture:capture0|Y_Cont[0]  ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.540 ns                ;
; 3.334 ns                                ; 173.73 MHz ( period = 5.756 ns )                    ; CCD_Capture:capture0|X_Cont[9]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.863 ns                  ; 5.529 ns                ;
; 3.336 ns                                ; 173.79 MHz ( period = 5.754 ns )                    ; CCD_Capture:capture0|X_Cont[15] ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.863 ns                  ; 5.527 ns                ;
; 3.340 ns                                ; 173.91 MHz ( period = 5.750 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.872 ns                  ; 5.532 ns                ;
; 3.347 ns                                ; 174.13 MHz ( period = 5.743 ns )                    ; CCD_Capture:capture0|X_Cont[2]  ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.878 ns                  ; 5.531 ns                ;
; 3.353 ns                                ; 174.31 MHz ( period = 5.737 ns )                    ; CCD_Capture:capture0|Y_Cont[10] ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.515 ns                ;
; 3.363 ns                                ; 174.61 MHz ( period = 5.727 ns )                    ; CCD_Capture:capture0|Y_Cont[1]  ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.505 ns                ;
; 3.373 ns                                ; 174.92 MHz ( period = 5.717 ns )                    ; CCD_Capture:capture0|Y_Cont[12] ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.495 ns                ;
; 3.379 ns                                ; 175.10 MHz ( period = 5.711 ns )                    ; CCD_Capture:capture0|Y_Cont[0]  ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.489 ns                ;
; 3.383 ns                                ; 175.22 MHz ( period = 5.707 ns )                    ; CCD_Capture:capture0|X_Cont[12] ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.485 ns                ;
; 3.385 ns                                ; 175.28 MHz ( period = 5.705 ns )                    ; CCD_Capture:capture0|X_Cont[9]  ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.878 ns                  ; 5.493 ns                ;
; 3.387 ns                                ; 175.35 MHz ( period = 5.703 ns )                    ; CCD_Capture:capture0|X_Cont[15] ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.878 ns                  ; 5.491 ns                ;
; 3.393 ns                                ; 175.53 MHz ( period = 5.697 ns )                    ; CCD_Capture:capture0|X_Cont[8]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.863 ns                  ; 5.470 ns                ;
; 3.394 ns                                ; 175.56 MHz ( period = 5.696 ns )                    ; CCD_Capture:capture0|Y_Cont[8]  ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.474 ns                ;
; 3.399 ns                                ; 175.72 MHz ( period = 5.691 ns )                    ; CCD_Capture:capture0|Y_Cont[13] ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.469 ns                ;
; 3.400 ns                                ; 175.75 MHz ( period = 5.690 ns )                    ; CCD_Capture:capture0|Y_Cont[2]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.872 ns                  ; 5.472 ns                ;
; 3.405 ns                                ; 175.90 MHz ( period = 5.685 ns )                    ; CCD_Capture:capture0|X_Cont[11] ; RAW2RGB:raw0|rRed[7]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.873 ns                  ; 5.468 ns                ;
; 3.414 ns                                ; 176.18 MHz ( period = 5.676 ns )                    ; CCD_Capture:capture0|Y_Cont[1]  ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.454 ns                ;
; 3.414 ns                                ; 176.18 MHz ( period = 5.676 ns )                    ; CCD_Capture:capture0|Y_Cont[3]  ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.882 ns                  ; 5.468 ns                ;
; 3.418 ns                                ; 176.30 MHz ( period = 5.672 ns )                    ; CCD_Capture:capture0|Y_Cont[4]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.872 ns                  ; 5.454 ns                ;
; 3.425 ns                                ; 176.52 MHz ( period = 5.665 ns )                    ; CCD_Capture:capture0|X_Cont[3]  ; RAW2RGB:raw0|rRed[7]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.873 ns                  ; 5.448 ns                ;
; 3.432 ns                                ; 176.74 MHz ( period = 5.658 ns )                    ; CCD_Capture:capture0|Y_Cont[10] ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.436 ns                ;
; 3.435 ns                                ; 176.83 MHz ( period = 5.655 ns )                    ; CCD_Capture:capture0|X_Cont[6]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.433 ns                ;
; 3.444 ns                                ; 177.12 MHz ( period = 5.646 ns )                    ; CCD_Capture:capture0|X_Cont[8]  ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.878 ns                  ; 5.434 ns                ;
; 3.445 ns                                ; 177.15 MHz ( period = 5.645 ns )                    ; CCD_Capture:capture0|Y_Cont[8]  ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.423 ns                ;
; 3.446 ns                                ; 177.18 MHz ( period = 5.644 ns )                    ; CCD_Capture:capture0|Y_Cont[15] ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.422 ns                ;
; 3.450 ns                                ; 177.30 MHz ( period = 5.640 ns )                    ; CCD_Capture:capture0|X_Cont[12] ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.863 ns                  ; 5.413 ns                ;
; 3.452 ns                                ; 177.37 MHz ( period = 5.638 ns )                    ; CCD_Capture:capture0|Y_Cont[12] ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.416 ns                ;
; 3.454 ns                                ; 177.43 MHz ( period = 5.636 ns )                    ; CCD_Capture:capture0|Y_Cont[11] ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.872 ns                  ; 5.418 ns                ;
; 3.457 ns                                ; 177.53 MHz ( period = 5.633 ns )                    ; CCD_Capture:capture0|Y_Cont[7]  ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.411 ns                ;
; 3.458 ns                                ; 177.56 MHz ( period = 5.632 ns )                    ; CCD_Capture:capture0|Y_Cont[6]  ; RAW2RGB:raw0|rGreen[3]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.410 ns                ;
; 3.458 ns                                ; 177.56 MHz ( period = 5.632 ns )                    ; CCD_Capture:capture0|Y_Cont[9]  ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.882 ns                  ; 5.424 ns                ;
; 3.466 ns                                ; 177.81 MHz ( period = 5.624 ns )                    ; CCD_Capture:capture0|X_Cont[14] ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.402 ns                ;
; 3.470 ns                                ; 177.94 MHz ( period = 5.620 ns )                    ; CCD_Capture:capture0|X_Cont[5]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.398 ns                ;
; 3.478 ns                                ; 178.19 MHz ( period = 5.612 ns )                    ; CCD_Capture:capture0|X_Cont[13] ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.390 ns                ;
; 3.484 ns                                ; 178.38 MHz ( period = 5.606 ns )                    ; CCD_Capture:capture0|Y_Cont[0]  ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.384 ns                ;
; 3.486 ns                                ; 178.44 MHz ( period = 5.604 ns )                    ; CCD_Capture:capture0|X_Cont[11] ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.864 ns                  ; 5.378 ns                ;
; 3.486 ns                                ; 178.44 MHz ( period = 5.604 ns )                    ; CCD_Capture:capture0|Y_Cont[14] ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.872 ns                  ; 5.386 ns                ;
; 3.493 ns                                ; 178.67 MHz ( period = 5.597 ns )                    ; CCD_Capture:capture0|Y_Cont[1]  ; RAW2RGB:raw0|rGreen[5]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.375 ns                ;
; 3.494 ns                                ; 178.70 MHz ( period = 5.596 ns )                    ; CCD_Capture:capture0|X_Cont[2]  ; RAW2RGB:raw0|rRed[7]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.873 ns                  ; 5.379 ns                ;
; 3.497 ns                                ; 178.79 MHz ( period = 5.593 ns )                    ; CCD_Capture:capture0|Y_Cont[15] ; RAW2RGB:raw0|rGreen[4]  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.371 ns                ;
; 3.498 ns                                ; 178.83 MHz ( period = 5.592 ns )                    ; CCD_Capture:capture0|X_Cont[1]  ; RAW2RGB:raw0|rRed[11]   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.868 ns                  ; 5.370 ns                ;
; 3.501 ns                                ; 178.92 MHz ( period = 5.589 ns )                    ; CCD_Capture:capture0|X_Cont[12] ; RAW2RGB:raw0|rRed[6]    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.878 ns                  ; 5.377 ns                ;
; 3.502 ns                                ; 178.95 MHz ( period = 5.588 ns )                    ; CCD_Capture:capture0|X_Cont[6]  ; RAW2RGB:raw0|rGreen[10] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.863 ns                  ; 5.361 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                 ;                         ;               ;               ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------+-------------------------+---------------+---------------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'iCLK_50'                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                           ; To                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 6.999 ns                                ; 166.61 MHz ( period = 6.002 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[11]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.787 ns                ;
; 7.165 ns                                ; 176.37 MHz ( period = 5.670 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[14]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.621 ns                ;
; 7.268 ns                                ; 183.02 MHz ( period = 5.464 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[10]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.518 ns                ;
; 7.466 ns                                ; 197.32 MHz ( period = 5.068 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[15]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.320 ns                ;
; 7.477 ns                                ; 198.18 MHz ( period = 5.046 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]          ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.309 ns                ;
; 7.503 ns                                ; 200.24 MHz ( period = 4.994 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[7]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.283 ns                ;
; 7.504 ns                                ; 200.32 MHz ( period = 4.992 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA~en ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.785 ns                  ; 2.281 ns                ;
; 7.504 ns                                ; 200.32 MHz ( period = 4.992 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]          ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.282 ns                ;
; 7.571 ns                                ; 205.85 MHz ( period = 4.858 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[3]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.215 ns                ;
; 7.594 ns                                ; 207.81 MHz ( period = 4.812 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]          ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.192 ns                ;
; 7.621 ns                                ; 210.17 MHz ( period = 4.758 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]          ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.165 ns                ;
; 7.655 ns                                ; 213.22 MHz ( period = 4.690 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[5]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.131 ns                ;
; 7.679 ns                                ; 215.42 MHz ( period = 4.642 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.787 ns                  ; 2.108 ns                ;
; 7.783 ns                                ; 225.53 MHz ( period = 4.434 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]          ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.003 ns                ;
; 7.784 ns                                ; 225.63 MHz ( period = 4.432 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]          ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.002 ns                ;
; 7.837 ns                                ; 231.16 MHz ( period = 4.326 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[2]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.949 ns                ;
; 7.900 ns                                ; 238.10 MHz ( period = 4.200 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]          ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.886 ns                ;
; 7.901 ns                                ; 238.21 MHz ( period = 4.198 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]          ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.885 ns                ;
; 7.937 ns                                ; 242.37 MHz ( period = 4.126 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN      ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.849 ns                ;
; 7.937 ns                                ; 242.37 MHz ( period = 4.126 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSCLK     ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.849 ns                ;
; 7.972 ns                                ; 246.55 MHz ( period = 4.056 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[8]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.814 ns                ;
; 8.008 ns                                ; 251.00 MHz ( period = 3.984 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]          ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.778 ns                ;
; 8.015 ns                                ; 251.89 MHz ( period = 3.970 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[13]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.771 ns                ;
; 8.035 ns                                ; 254.45 MHz ( period = 3.930 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]          ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.751 ns                ;
; 8.139 ns                                ; 268.67 MHz ( period = 3.722 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[12]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.647 ns                ;
; 8.160 ns                                ; 271.74 MHz ( period = 3.680 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]          ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.626 ns                ;
; 8.187 ns                                ; 275.79 MHz ( period = 3.626 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]          ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.599 ns                ;
; 8.237 ns                                ; 283.61 MHz ( period = 3.526 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[4]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.549 ns                ;
; 8.253 ns                                ; 286.20 MHz ( period = 3.494 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]          ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.533 ns                ;
; 8.266 ns                                ; 288.35 MHz ( period = 3.468 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[0]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.520 ns                ;
; 8.280 ns                                ; 290.70 MHz ( period = 3.440 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]          ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.506 ns                ;
; 8.314 ns                                ; 296.56 MHz ( period = 3.372 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]          ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.472 ns                ;
; 8.315 ns                                ; 296.74 MHz ( period = 3.370 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]          ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.471 ns                ;
; 8.466 ns                                ; 325.95 MHz ( period = 3.068 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]          ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.320 ns                ;
; 8.467 ns                                ; 326.16 MHz ( period = 3.066 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]          ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.319 ns                ;
; 8.511 ns                                ; 335.80 MHz ( period = 2.978 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[6]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.275 ns                ;
; 8.545 ns                                ; 343.64 MHz ( period = 2.910 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[1]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.241 ns                ;
; 8.559 ns                                ; 346.98 MHz ( period = 2.882 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]          ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.227 ns                ;
; 8.560 ns                                ; 347.22 MHz ( period = 2.880 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]          ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.226 ns                ;
; 8.761 ns                                ; 403.55 MHz ( period = 2.478 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK      ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.025 ns                ;
; 8.761 ns                                ; 403.55 MHz ( period = 2.478 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.025 ns                ;
; 8.761 ns                                ; 403.55 MHz ( period = 2.478 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.025 ns                ;
; 8.761 ns                                ; 403.55 MHz ( period = 2.478 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.025 ns                ;
; 8.761 ns                                ; 403.55 MHz ( period = 2.478 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.025 ns                ;
; 8.761 ns                                ; 403.55 MHz ( period = 2.478 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.025 ns                ;
; 9.060 ns                                ; Restricted to 420.17 MHz ( period = 2.38 ns )       ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK            ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 0.726 ns                ;
; 9.062 ns                                ; Restricted to 420.17 MHz ( period = 2.38 ns )       ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK            ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 0.724 ns                ;
; 13.829 ns                               ; 162.05 MHz ( period = 6.171 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.955 ns                ;
; 13.851 ns                               ; 162.63 MHz ( period = 6.149 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.933 ns                ;
; 13.860 ns                               ; 162.87 MHz ( period = 6.140 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.783 ns                 ; 5.923 ns                ;
; 13.863 ns                               ; 162.95 MHz ( period = 6.137 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.782 ns                 ; 5.919 ns                ;
; 13.962 ns                               ; 165.62 MHz ( period = 6.038 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.822 ns                ;
; 13.973 ns                               ; 165.92 MHz ( period = 6.027 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[4]   ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.954 ns                 ; 6.981 ns                ;
; 13.973 ns                               ; 165.92 MHz ( period = 6.027 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[2]   ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.954 ns                 ; 6.981 ns                ;
; 13.973 ns                               ; 165.92 MHz ( period = 6.027 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[1]   ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.954 ns                 ; 6.981 ns                ;
; 13.993 ns                               ; 166.47 MHz ( period = 6.007 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.791 ns                ;
; 13.994 ns                               ; 166.50 MHz ( period = 6.006 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.783 ns                 ; 5.789 ns                ;
; 14.015 ns                               ; 167.08 MHz ( period = 5.985 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.769 ns                ;
; 14.024 ns                               ; 167.34 MHz ( period = 5.976 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.783 ns                 ; 5.759 ns                ;
; 14.027 ns                               ; 167.42 MHz ( period = 5.973 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.782 ns                 ; 5.755 ns                ;
; 14.031 ns                               ; 167.53 MHz ( period = 5.969 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.753 ns                ;
; 14.083 ns                               ; 169.00 MHz ( period = 5.917 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.692 ns                ;
; 14.122 ns                               ; 170.13 MHz ( period = 5.878 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.653 ns                ;
; 14.138 ns                               ; 170.59 MHz ( period = 5.862 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.646 ns                ;
; 14.158 ns                               ; 171.17 MHz ( period = 5.842 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.783 ns                 ; 5.625 ns                ;
; 14.160 ns                               ; 171.23 MHz ( period = 5.840 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.624 ns                ;
; 14.169 ns                               ; 171.50 MHz ( period = 5.831 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.783 ns                 ; 5.614 ns                ;
; 14.172 ns                               ; 171.59 MHz ( period = 5.828 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.782 ns                 ; 5.610 ns                ;
; 14.195 ns                               ; 172.27 MHz ( period = 5.805 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.589 ns                ;
; 14.199 ns                               ; 172.38 MHz ( period = 5.801 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[5]   ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.956 ns                 ; 6.757 ns                ;
; 14.199 ns                               ; 172.38 MHz ( period = 5.801 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[0]   ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.956 ns                 ; 6.757 ns                ;
; 14.217 ns                               ; 172.92 MHz ( period = 5.783 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3] ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.790 ns                 ; 5.573 ns                ;
; 14.246 ns                               ; 173.79 MHz ( period = 5.754 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.529 ns                ;
; 14.250 ns                               ; 173.91 MHz ( period = 5.750 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.534 ns                ;
; 14.283 ns                               ; 174.92 MHz ( period = 5.717 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.501 ns                ;
; 14.286 ns                               ; 175.01 MHz ( period = 5.714 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.489 ns                ;
; 14.297 ns                               ; 175.35 MHz ( period = 5.703 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.478 ns                ;
; 14.300 ns                               ; 175.44 MHz ( period = 5.700 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.475 ns                ;
; 14.302 ns                               ; 175.50 MHz ( period = 5.698 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.675 ns                ;
; 14.302 ns                               ; 175.50 MHz ( period = 5.698 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.675 ns                ;
; 14.303 ns                               ; 175.53 MHz ( period = 5.697 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.783 ns                 ; 5.480 ns                ;
; 14.305 ns                               ; 175.59 MHz ( period = 5.695 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[20]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.952 ns                 ; 6.647 ns                ;
; 14.305 ns                               ; 175.59 MHz ( period = 5.695 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[22]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.952 ns                 ; 6.647 ns                ;
; 14.305 ns                               ; 175.59 MHz ( period = 5.695 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[23]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.952 ns                 ; 6.647 ns                ;
; 14.305 ns                               ; 175.59 MHz ( period = 5.695 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[21]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.952 ns                 ; 6.647 ns                ;
; 14.326 ns                               ; 176.24 MHz ( period = 5.674 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.976 ns                 ; 6.650 ns                ;
; 14.326 ns                               ; 176.24 MHz ( period = 5.674 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[18]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.976 ns                 ; 6.650 ns                ;
; 14.326 ns                               ; 176.24 MHz ( period = 5.674 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[16]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.976 ns                 ; 6.650 ns                ;
; 14.326 ns                               ; 176.24 MHz ( period = 5.674 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.976 ns                 ; 6.650 ns                ;
; 14.326 ns                               ; 176.24 MHz ( period = 5.674 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.976 ns                 ; 6.650 ns                ;
; 14.333 ns                               ; 176.46 MHz ( period = 5.667 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.442 ns                ;
; 14.333 ns                               ; 176.46 MHz ( period = 5.667 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.442 ns                ;
; 14.340 ns                               ; 176.68 MHz ( period = 5.660 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.444 ns                ;
; 14.349 ns                               ; 176.96 MHz ( period = 5.651 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[21]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.965 ns                 ; 6.616 ns                ;
; 14.349 ns                               ; 176.96 MHz ( period = 5.651 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[20]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.965 ns                 ; 6.616 ns                ;
; 14.349 ns                               ; 176.96 MHz ( period = 5.651 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[23]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.965 ns                 ; 6.616 ns                ;
; 14.349 ns                               ; 176.96 MHz ( period = 5.651 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.965 ns                 ; 6.616 ns                ;
; 14.349 ns                               ; 176.96 MHz ( period = 5.651 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[6]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.965 ns                 ; 6.616 ns                ;
; 14.349 ns                               ; 176.96 MHz ( period = 5.651 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[13]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.965 ns                 ; 6.616 ns                ;
; 14.357 ns                               ; 177.21 MHz ( period = 5.643 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.427 ns                ;
; 14.366 ns                               ; 177.49 MHz ( period = 5.634 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.783 ns                 ; 5.417 ns                ;
; 14.369 ns                               ; 177.59 MHz ( period = 5.631 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.782 ns                 ; 5.413 ns                ;
; 14.375 ns                               ; 177.78 MHz ( period = 5.625 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.978 ns                 ; 6.603 ns                ;
; 14.375 ns                               ; 177.78 MHz ( period = 5.625 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[19]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.978 ns                 ; 6.603 ns                ;
; 14.375 ns                               ; 177.78 MHz ( period = 5.625 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[22]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.978 ns                 ; 6.603 ns                ;
; 14.375 ns                               ; 177.78 MHz ( period = 5.625 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.978 ns                 ; 6.603 ns                ;
; 14.375 ns                               ; 177.78 MHz ( period = 5.625 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.978 ns                 ; 6.603 ns                ;
; 14.375 ns                               ; 177.78 MHz ( period = 5.625 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.978 ns                 ; 6.603 ns                ;
; 14.375 ns                               ; 177.78 MHz ( period = 5.625 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.978 ns                 ; 6.603 ns                ;
; 14.406 ns                               ; 178.76 MHz ( period = 5.594 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.378 ns                ;
; 14.414 ns                               ; 179.02 MHz ( period = 5.586 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.370 ns                ;
; 14.415 ns                               ; 179.05 MHz ( period = 5.585 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.369 ns                ;
; 14.415 ns                               ; 179.05 MHz ( period = 5.585 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.783 ns                 ; 5.368 ns                ;
; 14.418 ns                               ; 179.15 MHz ( period = 5.582 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.782 ns                 ; 5.364 ns                ;
; 14.431 ns                               ; 179.57 MHz ( period = 5.569 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.344 ns                ;
; 14.439 ns                               ; 179.82 MHz ( period = 5.561 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.348 ns                ;
; 14.439 ns                               ; 179.82 MHz ( period = 5.561 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.348 ns                ;
; 14.439 ns                               ; 179.82 MHz ( period = 5.561 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.348 ns                ;
; 14.439 ns                               ; 179.82 MHz ( period = 5.561 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.348 ns                ;
; 14.439 ns                               ; 179.82 MHz ( period = 5.561 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[13]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.348 ns                ;
; 14.464 ns                               ; 180.64 MHz ( period = 5.536 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[15]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.323 ns                ;
; 14.464 ns                               ; 180.64 MHz ( period = 5.536 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.323 ns                ;
; 14.464 ns                               ; 180.64 MHz ( period = 5.536 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.323 ns                ;
; 14.464 ns                               ; 180.64 MHz ( period = 5.536 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.323 ns                ;
; 14.464 ns                               ; 180.64 MHz ( period = 5.536 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.323 ns                ;
; 14.464 ns                               ; 180.64 MHz ( period = 5.536 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[8]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.323 ns                ;
; 14.464 ns                               ; 180.64 MHz ( period = 5.536 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[1]                      ; lcd_3wire_config:lcd_config0|m3wire_data[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.323 ns                ;
; 14.468 ns                               ; 180.77 MHz ( period = 5.532 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.307 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.481 ns                               ; 181.19 MHz ( period = 5.519 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.297 ns                ;
; 14.484 ns                               ; 181.29 MHz ( period = 5.516 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[0] ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.790 ns                 ; 5.306 ns                ;
; 14.485 ns                               ; 181.32 MHz ( period = 5.515 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[17]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.976 ns                 ; 6.491 ns                ;
; 14.485 ns                               ; 181.32 MHz ( period = 5.515 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[6]   ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.976 ns                 ; 6.491 ns                ;
; 14.497 ns                               ; 181.72 MHz ( period = 5.503 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.775 ns                 ; 5.278 ns                ;
; 14.499 ns                               ; 181.79 MHz ( period = 5.501 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[3]   ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.978 ns                 ; 6.479 ns                ;
; 14.500 ns                               ; 181.82 MHz ( period = 5.500 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.783 ns                 ; 5.283 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.511 ns                               ; 182.18 MHz ( period = 5.489 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.778 ns                 ; 5.267 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[18]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[19]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[16]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[15]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[8]   ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[11]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[12]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[13]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[14]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[9]   ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[10]  ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.516 ns                               ; 182.35 MHz ( period = 5.484 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[7]   ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.977 ns                 ; 6.461 ns                ;
; 14.540 ns                               ; 183.15 MHz ( period = 5.460 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.771 ns                 ; 5.231 ns                ;
; 14.549 ns                               ; 183.45 MHz ( period = 5.451 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.783 ns                 ; 5.234 ns                ;
; 14.571 ns                               ; 184.20 MHz ( period = 5.429 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.213 ns                ;
; 14.576 ns                               ; 184.37 MHz ( period = 5.424 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[2]                      ; lcd_3wire_config:lcd_config0|m3wire_data[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.211 ns                ;
; 14.576 ns                               ; 184.37 MHz ( period = 5.424 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[2]                      ; lcd_3wire_config:lcd_config0|m3wire_data[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.211 ns                ;
; 14.576 ns                               ; 184.37 MHz ( period = 5.424 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[2]                      ; lcd_3wire_config:lcd_config0|m3wire_data[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.211 ns                ;
; 14.576 ns                               ; 184.37 MHz ( period = 5.424 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[2]                      ; lcd_3wire_config:lcd_config0|m3wire_data[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.211 ns                ;
; 14.576 ns                               ; 184.37 MHz ( period = 5.424 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[2]                      ; lcd_3wire_config:lcd_config0|m3wire_data[13]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.211 ns                ;
; 14.579 ns                               ; 184.47 MHz ( period = 5.421 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.205 ns                ;
; 14.583 ns                               ; 184.60 MHz ( period = 5.417 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.969 ns                 ; 6.386 ns                ;
; 14.583 ns                               ; 184.60 MHz ( period = 5.417 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.969 ns                 ; 6.386 ns                ;
; 14.583 ns                               ; 184.60 MHz ( period = 5.417 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.969 ns                 ; 6.386 ns                ;
; 14.583 ns                               ; 184.60 MHz ( period = 5.417 ns )                    ; Reset_Delay:reset0|oRST_1                                      ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 20.969 ns                 ; 6.386 ns                ;
; 14.583 ns                               ; 184.60 MHz ( period = 5.417 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.784 ns                 ; 5.201 ns                ;
; 14.588 ns                               ; 184.77 MHz ( period = 5.412 ns )                    ; Reset_Delay:reset0|oRST_0                                      ; lcd_3wire_config:lcd_config0|m3wire_data[2]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 24.185 ns                 ; 9.597 ns                ;
; 14.588 ns                               ; 184.77 MHz ( period = 5.412 ns )                    ; Reset_Delay:reset0|oRST_0                                      ; lcd_3wire_config:lcd_config0|m3wire_data[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 24.185 ns                 ; 9.597 ns                ;
; 14.588 ns                               ; 184.77 MHz ( period = 5.412 ns )                    ; Reset_Delay:reset0|oRST_0                                      ; lcd_3wire_config:lcd_config0|m3wire_data[1]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 24.185 ns                 ; 9.597 ns                ;
; 14.588 ns                               ; 184.77 MHz ( period = 5.412 ns )                    ; Reset_Delay:reset0|oRST_0                                      ; lcd_3wire_config:lcd_config0|m3wire_data[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 24.185 ns                 ; 9.597 ns                ;
; 14.588 ns                               ; 184.77 MHz ( period = 5.412 ns )                    ; Reset_Delay:reset0|oRST_0                                      ; lcd_3wire_config:lcd_config0|m3wire_data[13]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 24.185 ns                 ; 9.597 ns                ;
; 14.601 ns                               ; 185.22 MHz ( period = 5.399 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[2]                      ; lcd_3wire_config:lcd_config0|m3wire_data[15]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.186 ns                ;
; 14.601 ns                               ; 185.22 MHz ( period = 5.399 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[2]                      ; lcd_3wire_config:lcd_config0|m3wire_data[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.186 ns                ;
; 14.601 ns                               ; 185.22 MHz ( period = 5.399 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[2]                      ; lcd_3wire_config:lcd_config0|m3wire_data[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.186 ns                ;
; 14.601 ns                               ; 185.22 MHz ( period = 5.399 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[2]                      ; lcd_3wire_config:lcd_config0|m3wire_data[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.186 ns                ;
; 14.601 ns                               ; 185.22 MHz ( period = 5.399 ns )                    ; lcd_3wire_config:lcd_config0|lut_index[2]                      ; lcd_3wire_config:lcd_config0|m3wire_data[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.787 ns                 ; 5.186 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                ;                                                          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


 
; Clock Hold: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
 
; Minimum Slack                           ; From                                                                                                                                                            ; To                                                                                                                                                                                        ; From Clock                                         ; To Clock                                           ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
 
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                               ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_rw                                                                                                               ; Sdram_Control_4Port:sdram0|command:command1|do_rw                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rw_flag                                                                                                             ; Sdram_Control_4Port:sdram1|command:command1|rw_flag                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rw_flag                                                                                                             ; Sdram_Control_4Port:sdram0|command:command1|rw_flag                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|OUT_VALID                                                                                                                            ; Sdram_Control_4Port:sdram1|OUT_VALID                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|IN_REQ                                                                                                                               ; Sdram_Control_4Port:sdram1|IN_REQ                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|Write                                                                                                                                ; Sdram_Control_4Port:sdram1|Write                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|Read                                                                                                                                 ; Sdram_Control_4Port:sdram1|Read                                                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|mWR_DONE                                                                                                                             ; Sdram_Control_4Port:sdram1|mWR_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|CM_ACK                                                                                                              ; Sdram_Control_4Port:sdram1|command:command1|CM_ACK                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|mRD_DONE                                                                                                                             ; Sdram_Control_4Port:sdram1|mRD_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|ST[0]                                                                                                                                ; Sdram_Control_4Port:sdram1|ST[0]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|CMD_ACK                                                                                                   ; Sdram_Control_4Port:sdram1|control_interface:control1|CMD_ACK                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|RD_MASK[0]                                                                                                                           ; Sdram_Control_4Port:sdram1|RD_MASK[0]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|ex_read                                                                                                             ; Sdram_Control_4Port:sdram1|command:command1|ex_read                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|ex_write                                                                                                            ; Sdram_Control_4Port:sdram1|command:command1|ex_write                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|REF_ACK                                                                                                             ; Sdram_Control_4Port:sdram1|command:command1|REF_ACK                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|REF_REQ                                                                                                   ; Sdram_Control_4Port:sdram1|control_interface:control1|REF_REQ                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_precharge                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|do_precharge                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|do_load_mode                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|OUT_VALID                                                                                                                            ; Sdram_Control_4Port:sdram0|OUT_VALID                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|IN_REQ                                                                                                                               ; Sdram_Control_4Port:sdram0|IN_REQ                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|Write                                                                                                                                ; Sdram_Control_4Port:sdram0|Write                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|Read                                                                                                                                 ; Sdram_Control_4Port:sdram0|Read                                                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|mWR_DONE                                                                                                                             ; Sdram_Control_4Port:sdram0|mWR_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|CM_ACK                                                                                                              ; Sdram_Control_4Port:sdram0|command:command1|CM_ACK                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|mRD_DONE                                                                                                                             ; Sdram_Control_4Port:sdram0|mRD_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|ST[0]                                                                                                                                ; Sdram_Control_4Port:sdram0|ST[0]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|ex_read                                                                                                             ; Sdram_Control_4Port:sdram0|command:command1|ex_read                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|ex_write                                                                                                            ; Sdram_Control_4Port:sdram0|command:command1|ex_write                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|CMD_ACK                                                                                                   ; Sdram_Control_4Port:sdram0|control_interface:control1|CMD_ACK                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|RD_MASK[0]                                                                                                                           ; Sdram_Control_4Port:sdram0|RD_MASK[0]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|REF_ACK                                                                                                             ; Sdram_Control_4Port:sdram0|command:command1|REF_ACK                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|REF_REQ                                                                                                   ; Sdram_Control_4Port:sdram0|control_interface:control1|REF_REQ                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[0]                                                                                             ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[0]                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_precharge                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|do_precharge                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|do_load_mode                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.516 ns                                ; Sdram_Control_4Port:sdram1|command:command1|CS_N[0]                                                                                                             ; Sdram_Control_4Port:sdram1|CS_N[0]                                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.532 ns                 ;
; 0.520 ns                                ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                                            ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[20]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.536 ns                 ;
; 0.521 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[20]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|BA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.537 ns                 ;
; 0.521 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[16]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[8]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.537 ns                 ;
; 0.522 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[21]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|BA[1]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Sdram_Control_4Port:sdram0|command:command1|CS_N[0]                                                                                                             ; Sdram_Control_4Port:sdram0|CS_N[0]                                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[12]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[4]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[9]                                                                                                  ; Sdram_Control_4Port:sdram0|command:command1|SA[1]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[8]                                                                                                  ; Sdram_Control_4Port:sdram0|command:command1|SA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.527 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                               ; Sdram_Control_4Port:sdram1|command:command1|SA[10]                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.543 ns                 ;
; 0.527 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram0|rWR1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.543 ns                 ;
; 0.530 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.546 ns                 ;
; 0.530 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.546 ns                 ;
; 0.530 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.546 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram0|rRD1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[15]                                                                                                 ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[15]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[15]                                                                                                 ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[15]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.534 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.550 ns                 ;
; 0.535 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.551 ns                 ;
; 0.535 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.551 ns                 ;
; 0.540 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_refresh                                                                                                          ; Sdram_Control_4Port:sdram1|command:command1|CM_ACK                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.556 ns                 ;
; 0.541 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|SA[6]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.557 ns                 ;
; 0.542 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[15]                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[15]                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.558 ns                 ;
; 0.543 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|BA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.559 ns                 ;
; 0.546 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.562 ns                 ;
; 0.548 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_refresh                                                                                                          ; Sdram_Control_4Port:sdram0|command:command1|CM_ACK                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.564 ns                 ;
; 0.551 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_refresh                                                                                                          ; Sdram_Control_4Port:sdram0|command:command1|REF_ACK                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.567 ns                 ;
; 0.585 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_done                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.601 ns                 ;
; 0.586 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_done                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[1]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.602 ns                 ;
; 0.587 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_done                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[3]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.603 ns                 ;
; 0.587 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_done                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[2]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.603 ns                 ;
; 0.649 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[2]                                                                                                               ; Sdram_Control_4Port:sdram0|SA[2]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.665 ns                 ;
; 0.650 ns                                ; Sdram_Control_4Port:sdram0|command:command1|WE_N                                                                                                                ; Sdram_Control_4Port:sdram0|WE_N                                                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.666 ns                 ;
; 0.655 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[2]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[1]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.671 ns                 ;
; 0.655 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[6]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|command_delay[5]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.671 ns                 ;
; 0.656 ns                                ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                            ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[21]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.672 ns                 ;
; 0.657 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[4]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[3]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.673 ns                 ;
; 0.659 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[6]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[5]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.675 ns                 ;
; 0.659 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[3]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[2]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.675 ns                 ;
; 0.664 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[2]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|command_delay[1]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.680 ns                 ;
; 0.668 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[4]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|command_delay[3]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.684 ns                 ;
; 0.670 ns                                ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                                             ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[9]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.684 ns                 ;
; 0.675 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rw_shift[1]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|rw_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.691 ns                 ;
; 0.675 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.691 ns                 ;
; 0.679 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|REF_REQ                                                                                                   ; Sdram_Control_4Port:sdram0|command:command1|do_refresh                                                                                                                                    ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.695 ns                 ;
; 0.680 ns                                ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[19]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.694 ns                 ;
; 0.681 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[7]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.697 ns                 ;
; 0.683 ns                                ; Sdram_Control_4Port:sdram0|CMD[0]                                                                                                                               ; Sdram_Control_4Port:sdram0|control_interface:control1|READA                                                                                                                               ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.699 ns                 ;
; 0.686 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.702 ns                 ;
; 0.686 ns                                ; Sdram_Control_4Port:sdram0|CMD[0]                                                                                                                               ; Sdram_Control_4Port:sdram0|control_interface:control1|WRITEA                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.702 ns                 ;
; 0.687 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~porta_address_reg1 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.038 ns                   ; 0.725 ns                 ;
; 0.687 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.703 ns                 ;
; 0.690 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[15]                                                                                                                        ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.707 ns                 ;
; 0.691 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.707 ns                 ;
; 0.692 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[2]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.708 ns                 ;
; 0.693 ns                                ; Sdram_Control_4Port:sdram0|Pre_RD                                                                                                                               ; Sdram_Control_4Port:sdram0|CMD[0]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.709 ns                 ;
; 0.695 ns                                ; Sdram_Control_4Port:sdram0|Pre_RD                                                                                                                               ; Sdram_Control_4Port:sdram0|CMD[1]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.711 ns                 ;
; 0.697 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.713 ns                 ;
; 0.702 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg6 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.733 ns                 ;
; 0.703 ns                                ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                                            ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[10]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.717 ns                 ;
; 0.704 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg4 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.735 ns                 ;
; 0.705 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg5 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.736 ns                 ;
; 0.706 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg7 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.737 ns                 ;
; 0.706 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg3 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.737 ns                 ;
; 0.707 ns                                ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                                            ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[12]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.721 ns                 ;
; 0.708 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[18]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[10]                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.722 ns                 ;
; 0.709 ns                                ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                                            ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[15]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.723 ns                 ;
; 0.711 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg2 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.742 ns                 ;
; 0.711 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.726 ns                 ;
; 0.713 ns                                ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                                            ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[16]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.727 ns                 ;
; 0.714 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.018 ns                   ; 0.732 ns                 ;
; 0.714 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.018 ns                   ; 0.732 ns                 ;
; 0.717 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[11]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[3]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.731 ns                 ;
; 0.717 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[8]                                                                    ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.734 ns                 ;
; 0.718 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[13]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[5]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.732 ns                 ;
; 0.722 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[16]                                                                                                                        ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.739 ns                 ;
; 0.725 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|WRITEA                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|do_writea                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.739 ns                 ;
; 0.726 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.741 ns                 ;
; 0.728 ns                                ; Sdram_Control_4Port:sdram1|command:command1|CM_ACK                                                                                                              ; Sdram_Control_4Port:sdram1|control_interface:control1|CMD_ACK                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.018 ns                   ; 0.746 ns                 ;
; 0.731 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[9]                                                                                                                         ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.748 ns                 ;
; 0.731 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.748 ns                 ;
; 0.731 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.748 ns                 ;
; 0.737 ns                                ; Sdram_Control_4Port:sdram0|command:command1|BA[1]                                                                                                               ; Sdram_Control_4Port:sdram0|BA[1]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.751 ns                 ;
; 0.739 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.756 ns                 ;
; 0.741 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[3]                                                                    ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.758 ns                 ;
; 0.741 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.755 ns                 ;
; 0.742 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.756 ns                 ;
; 0.742 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[2]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.756 ns                 ;
; 0.743 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.760 ns                 ;
; 0.745 ns                                ; Sdram_Control_4Port:sdram0|PM_STOP                                                                                                                              ; Sdram_Control_4Port:sdram0|command:command1|ex_write                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.006 ns                   ; 0.751 ns                 ;
; 0.748 ns                                ; Sdram_Control_4Port:sdram0|PM_STOP                                                                                                                              ; Sdram_Control_4Port:sdram0|command:command1|ex_read                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.006 ns                   ; 0.754 ns                 ;
; 0.749 ns                                ; Sdram_Control_4Port:sdram1|PM_STOP                                                                                                                              ; Sdram_Control_4Port:sdram1|command:command1|ex_write                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.018 ns                   ; 0.767 ns                 ;
; 0.753 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_rw                                                                                                               ; Sdram_Control_4Port:sdram0|command:command1|SA[10]                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.769 ns                 ;
; 0.759 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[13]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[5]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.773 ns                 ;
; 0.774 ns                                ; Sdram_Control_4Port:sdram1|Pre_RD                                                                                                                               ; Sdram_Control_4Port:sdram1|CMD[0]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.790 ns                 ;
; 0.778 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[1]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[1]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.794 ns                 ;
; 0.778 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[1]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[1]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.794 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[9]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[9]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[11]                                                                                                 ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[11]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[13]                                                                                                 ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[13]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[7]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[7]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[7]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[7]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[13]                                                                                                 ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[13]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[9]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[9]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[11]                                                                                                 ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[11]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.786 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.786 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.786 ns                                ; Sdram_Control_4Port:sdram0|CMD[1]                                                                                                                               ; Sdram_Control_4Port:sdram0|control_interface:control1|READA                                                                                                                               ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.787 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.803 ns                 ;
; 0.788 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|p0addr                                                     ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.804 ns                 ;
; 0.788 ns                                ; Sdram_Control_4Port:sdram0|RD_MASK[0]                                                                                                                           ; Sdram_Control_4Port:sdram0|Pre_RD                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.006 ns                   ; 0.794 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.790 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[19]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[11]                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.806 ns                 ;
; 0.791 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[20]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|BA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.807 ns                 ;
; 0.791 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[7]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[6]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.019 ns                   ; 0.810 ns                 ;
; 0.793 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[10]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[2]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.809 ns                 ;
; 0.793 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.809 ns                 ;
; 0.794 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rw_shift[1]                                                                                                         ; Sdram_Control_4Port:sdram0|command:command1|rw_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.810 ns                 ;
; 0.794 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[1]                                                                                                               ; Sdram_Control_4Port:sdram0|SA[1]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.810 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[4]                                                                                                               ; Sdram_Control_4Port:sdram0|SA[4]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[8]                                                                                                                         ; Sdram_Control_4Port:sdram0|rWR1_ADDR[8]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[0]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[0]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[0]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[0]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[1]                                                                                             ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[1]                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.797 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[22]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|CS_N[0]                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.813 ns                 ;
; 0.798 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[11]                                                                                                              ; Sdram_Control_4Port:sdram0|SA[11]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.798 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_done                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|do_load_mode                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.018 ns                   ; 0.816 ns                 ;
; 0.799 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[3]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[2]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.815 ns                 ;
; 0.799 ns                                ; Sdram_Control_4Port:sdram0|command:command1|REF_ACK                                                                                                             ; Sdram_Control_4Port:sdram0|control_interface:control1|REF_REQ                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.815 ns                 ;
; 0.800 ns                                ; Sdram_Control_4Port:sdram0|command:command1|CAS_N                                                                                                               ; Sdram_Control_4Port:sdram0|CAS_N                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.816 ns                 ;
; 0.800 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                      ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.816 ns                 ;
; 0.800 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.816 ns                 ;
; 0.801 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[21]                                                                                                                        ; Sdram_Control_4Port:sdram0|rWR1_ADDR[21]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[3]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|command_delay[2]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[0]                                                                                                         ; Sdram_Control_4Port:sdram0|command:command1|rp_done                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.803 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.819 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[9]                                                                                                                         ; Sdram_Control_4Port:sdram0|rWR1_ADDR[9]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[0]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|rp_done                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram0|Write                                                                                                                                ; Sdram_Control_4Port:sdram0|IN_REQ                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[2]                                                                                             ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[2]                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[9]                                                                                                                         ; Sdram_Control_4Port:sdram1|rRD1_ADDR[9]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[11]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[11]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[21]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[21]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[20]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[20]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[14]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[14]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[9]                                                                                                                         ; Sdram_Control_4Port:sdram1|rWR1_ADDR[9]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[11]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[11]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[21]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[21]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[20]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[20]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[9]                                                                                                                         ; Sdram_Control_4Port:sdram0|rRD1_ADDR[9]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[11]                                                                                                                        ; Sdram_Control_4Port:sdram0|rRD1_ADDR[11]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[14]                                                                                                                        ; Sdram_Control_4Port:sdram0|rRD1_ADDR[14]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[21]                                                                                                                        ; Sdram_Control_4Port:sdram0|rRD1_ADDR[21]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[19]                                                                                                                        ; Sdram_Control_4Port:sdram0|rWR1_ADDR[19]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                             ;                                                                                                                                                                                           ;                                                    ;                                                    ;                            ;                            ;                          ;
 


 
; Clock Hold: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
 
; Minimum Slack                           ; From                                                                                                                                              ; To                                                                                                                                                                                       ; From Clock                                     ; To Clock                                       ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
 
; 0.522 ns                                ; Dilation:dilation0|X6[9]                                                                                                                          ; Dilation:dilation0|X5[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Dilation:dilation0|X6[6]                                                                                                                          ; Dilation:dilation0|X5[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.522 ns                                ; Dilation:dilation0|X5[5]                                                                                                                          ; Dilation:dilation0|X4[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.538 ns                 ;
; 0.523 ns                                ; Dilation:dilation0|X3[4]                                                                                                                          ; Dilation:dilation0|X2[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.539 ns                 ;
; 0.524 ns                                ; Dilation:dilation0|X9[6]                                                                                                                          ; Dilation:dilation0|X8[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.540 ns                 ;
; 0.524 ns                                ; Dilation:dilation0|X5[6]                                                                                                                          ; Dilation:dilation0|X4[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.540 ns                 ;
; 0.525 ns                                ; Dilation:dilation0|X5[9]                                                                                                                          ; Dilation:dilation0|X4[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.541 ns                 ;
; 0.525 ns                                ; Dilation:dilation0|X3[9]                                                                                                                          ; Dilation:dilation0|X2[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.541 ns                 ;
; 0.525 ns                                ; Dilation:dilation0|X5[7]                                                                                                                          ; Dilation:dilation0|X4[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.541 ns                 ;
; 0.526 ns                                ; Dilation:dilation0|X3[6]                                                                                                                          ; Dilation:dilation0|X2[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.542 ns                 ;
; 0.530 ns                                ; Dilation:dilation0|X3[8]                                                                                                                          ; Dilation:dilation0|X2[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.546 ns                 ;
; 0.533 ns                                ; Dilation:dilation0|X6[4]                                                                                                                          ; Dilation:dilation0|X5[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.549 ns                 ;
; 0.534 ns                                ; Dilation:dilation0|X6[3]                                                                                                                          ; Dilation:dilation0|X5[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.550 ns                 ;
; 0.534 ns                                ; Dilation:dilation0|X6[8]                                                                                                                          ; Dilation:dilation0|X5[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.550 ns                 ;
; 0.534 ns                                ; Dilation:dilation0|X5[8]                                                                                                                          ; Dilation:dilation0|X4[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.550 ns                 ;
; 0.537 ns                                ; Dilation:dilation0|X9[3]                                                                                                                          ; Dilation:dilation0|X8[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.553 ns                 ;
; 0.539 ns                                ; Dilation:dilation0|X9[8]                                                                                                                          ; Dilation:dilation0|X8[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.555 ns                 ;
; 0.540 ns                                ; Dilation:dilation0|X3[3]                                                                                                                          ; Dilation:dilation0|X2[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.556 ns                 ;
; 0.540 ns                                ; Dilation:dilation0|X5[3]                                                                                                                          ; Dilation:dilation0|X4[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.556 ns                 ;
; 0.543 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.559 ns                 ;
; 0.545 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.561 ns                 ;
; 0.552 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.568 ns                 ;
; 0.555 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.571 ns                 ;
; 0.555 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.571 ns                 ;
; 0.580 ns                                ; Binary:binary0|oDATA[9]                                                                                                                           ; touch_tcon:vga0|oLCD_G[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.596 ns                 ;
; 0.646 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[15] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a5~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.695 ns                 ;
; 0.646 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[12] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.695 ns                 ;
; 0.647 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[4]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.696 ns                 ;
; 0.648 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[19] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[16] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a6~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[2]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_datain_reg1                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.658 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[9]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.707 ns                 ;
; 0.658 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[7]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a7~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.707 ns                 ;
; 0.658 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[6]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a6~porta_datain_reg1                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.707 ns                 ;
; 0.661 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[2]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~portb_address_reg2                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.072 ns                   ; 0.733 ns                 ;
; 0.661 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[0]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~portb_address_reg0                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.072 ns                   ; 0.733 ns                 ;
; 0.663 ns                                ; Dilation:dilation0|X2[4]                                                                                                                          ; Dilation:dilation0|X1[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.679 ns                 ;
; 0.664 ns                                ; Dilation:dilation0|X8[9]                                                                                                                          ; Dilation:dilation0|X7[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.680 ns                 ;
; 0.665 ns                                ; Dilation:dilation0|X3[7]                                                                                                                          ; Dilation:dilation0|X2[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.682 ns                 ;
; 0.665 ns                                ; Dilation:dilation0|X8[6]                                                                                                                          ; Dilation:dilation0|X7[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.681 ns                 ;
; 0.666 ns                                ; Dilation:dilation0|X2[8]                                                                                                                          ; Dilation:dilation0|X1[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.682 ns                 ;
; 0.668 ns                                ; Dilation:dilation0|X2[5]                                                                                                                          ; Dilation:dilation0|X1[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.684 ns                 ;
; 0.669 ns                                ; Dilation:dilation0|X2[9]                                                                                                                          ; Dilation:dilation0|X1[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.685 ns                 ;
; 0.670 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[1]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~portb_address_reg1                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.072 ns                   ; 0.742 ns                 ;
; 0.671 ns                                ; Dilation:dilation0|X2[3]                                                                                                                          ; Dilation:dilation0|X1[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.687 ns                 ;
; 0.674 ns                                ; Dilation:dilation0|X9[9]                                                                                                                          ; Dilation:dilation0|X8[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.690 ns                 ;
; 0.674 ns                                ; Dilation:dilation0|X5[2]                                                                                                                          ; Dilation:dilation0|X4[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.690 ns                 ;
; 0.676 ns                                ; Dilation:dilation0|X2[2]                                                                                                                          ; Dilation:dilation0|X1[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.692 ns                 ;
; 0.677 ns                                ; Dilation:dilation0|X8[4]                                                                                                                          ; Dilation:dilation0|X7[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.693 ns                 ;
; 0.679 ns                                ; Dilation:dilation0|X8[3]                                                                                                                          ; Dilation:dilation0|X7[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.695 ns                 ;
; 0.681 ns                                ; Dilation:dilation0|X8[7]                                                                                                                          ; Dilation:dilation0|X7[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.697 ns                 ;
; 0.681 ns                                ; Dilation:dilation0|X2[7]                                                                                                                          ; Dilation:dilation0|X1[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.697 ns                 ;
; 0.681 ns                                ; Dilation:dilation0|X8[2]                                                                                                                          ; Dilation:dilation0|X7[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.697 ns                 ;
; 0.682 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.698 ns                 ;
; 0.683 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.043 ns                   ; 0.726 ns                 ;
; 0.688 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.704 ns                 ;
; 0.689 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[2]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_address_reg2                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.044 ns                   ; 0.733 ns                 ;
; 0.689 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[0]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_address_reg0                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.044 ns                   ; 0.733 ns                 ;
; 0.692 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.043 ns                   ; 0.735 ns                 ;
; 0.695 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.711 ns                 ;
; 0.695 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.711 ns                 ;
; 0.698 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[1]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_address_reg1                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.044 ns                   ; 0.742 ns                 ;
; 0.701 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.717 ns                 ;
; 0.702 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.733 ns                 ;
; 0.706 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.737 ns                 ;
; 0.707 ns                                ; Dilation:dilation0|oDVAL                                                                                                                          ; Binary:binary0|oDVAL                                                                                                                                                                     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.724 ns                 ;
; 0.708 ns                                ; Dilation:dilation0|X3[5]                                                                                                                          ; Dilation:dilation0|X2[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.725 ns                 ;
; 0.714 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.731 ns                 ;
; 0.715 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.746 ns                 ;
; 0.717 ns                                ; Dilation:dilation0|X6[5]                                                                                                                          ; Dilation:dilation0|X5[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.734 ns                 ;
; 0.717 ns                                ; Dilation:dilation0|X9[5]                                                                                                                          ; Dilation:dilation0|X8[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.734 ns                 ;
; 0.717 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.748 ns                 ;
; 0.720 ns                                ; Dilation:dilation0|X9[7]                                                                                                                          ; Dilation:dilation0|X8[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.737 ns                 ;
; 0.720 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.751 ns                 ;
; 0.722 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.753 ns                 ;
; 0.723 ns                                ; touch_tcon:vga0|mden                                                                                                                              ; touch_tcon:vga0|oDEN                                                                                                                                                                     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.740 ns                 ;
; 0.728 ns                                ; Dilation:dilation0|X6[2]                                                                                                                          ; Dilation:dilation0|X5[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.745 ns                 ;
; 0.730 ns                                ; Dilation:dilation0|X3[2]                                                                                                                          ; Dilation:dilation0|X2[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.747 ns                 ;
; 0.732 ns                                ; Dilation:dilation0|X6[7]                                                                                                                          ; Dilation:dilation0|X5[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.749 ns                 ;
; 0.748 ns                                ; touch_tcon:vga0|y_cnt[9]                                                                                                                          ; touch_tcon:vga0|mvd                                                                                                                                                                      ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.763 ns                 ;
; 0.780 ns                                ; Dilation:dilation0|X7[3]                                                                                                                          ; Dilation:dilation0|oDATA[3]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.796 ns                 ;
; 0.786 ns                                ; Dilation:dilation0|X1[2]                                                                                                                          ; Dilation:dilation0|oDATA[2]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.788 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff         ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.804 ns                 ;
; 0.789 ns                                ; Dilation:dilation0|X7[7]                                                                                                                          ; Dilation:dilation0|oDATA[7]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.798 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.799 ns                                ; touch_tcon:vga0|y_cnt[1]                                                                                                                          ; touch_tcon:vga0|y_cnt[1]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.815 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.806 ns                                ; touch_tcon:vga0|y_cnt[7]                                                                                                                          ; touch_tcon:vga0|y_cnt[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; touch_tcon:vga0|x_cnt[2]                                                                                                                          ; touch_tcon:vga0|x_cnt[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; touch_tcon:vga0|x_cnt[0]                                                                                                                          ; touch_tcon:vga0|x_cnt[0]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.809 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.809 ns                                ; touch_tcon:vga0|y_cnt[4]                                                                                                                          ; touch_tcon:vga0|y_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.810 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.814 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.815 ns                                ; Dilation:dilation0|X9[3]                                                                                                                          ; Dilation:dilation0|oDATA[3]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.831 ns                 ;
; 0.815 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[4]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[4]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.831 ns                 ;
; 0.815 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff         ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.831 ns                 ;
; 0.816 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[9]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[9]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.816 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[6]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[6]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.816 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.821 ns                                ; touch_tcon:vga0|x_cnt[7]                                                                                                                          ; touch_tcon:vga0|x_cnt[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.837 ns                 ;
; 0.822 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.822 ns                                ; touch_tcon:vga0|x_cnt[9]                                                                                                                          ; touch_tcon:vga0|x_cnt[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.824 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[8]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[8]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.840 ns                 ;
; 0.825 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.841 ns                 ;
; 0.826 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.842 ns                 ;
; 0.827 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.843 ns                 ;
; 0.829 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.845 ns                 ;
; 0.829 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.845 ns                 ;
; 0.830 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.846 ns                 ;
; 0.830 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.846 ns                 ;
; 0.833 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.849 ns                 ;
; 0.833 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.849 ns                 ;
; 0.834 ns                                ; touch_tcon:vga0|y_cnt[8]                                                                                                                          ; touch_tcon:vga0|y_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.850 ns                 ;
; 0.834 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.850 ns                 ;
; 0.838 ns                                ; touch_tcon:vga0|y_cnt[6]                                                                                                                          ; touch_tcon:vga0|y_cnt[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.841 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[0]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[0]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.857 ns                 ;
; 0.842 ns                                ; touch_tcon:vga0|y_cnt[5]                                                                                                                          ; touch_tcon:vga0|y_cnt[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.844 ns                                ; Dilation:dilation0|X8[8]                                                                                                                          ; Dilation:dilation0|X7[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.860 ns                 ;
; 0.845 ns                                ; Dilation:dilation0|X8[5]                                                                                                                          ; Dilation:dilation0|X7[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; touch_tcon:vga0|x_cnt[1]                                                                                                                          ; touch_tcon:vga0|x_cnt[1]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.846 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[2]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[2]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.848 ns                                ; Dilation:dilation0|X2[6]                                                                                                                          ; Dilation:dilation0|X1[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.864 ns                 ;
; 0.848 ns                                ; touch_tcon:vga0|x_cnt[6]                                                                                                                          ; touch_tcon:vga0|x_cnt[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.864 ns                 ;
; 0.849 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; touch_tcon:vga0|x_cnt[8]                                                                                                                          ; touch_tcon:vga0|x_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; touch_tcon:vga0|x_cnt[4]                                                                                                                          ; touch_tcon:vga0|x_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; touch_tcon:vga0|x_cnt[3]                                                                                                                          ; touch_tcon:vga0|x_cnt[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.850 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.851 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[4]  ; Dilation:dilation0|X9[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.023 ns                   ; 0.874 ns                 ;
; 0.851 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[3]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[3]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.867 ns                 ;
; 0.851 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.867 ns                 ;
; 0.852 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[7]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[7]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.868 ns                 ;
; 0.852 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[5]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[5]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.868 ns                 ;
; 0.852 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.868 ns                 ;
; 0.853 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.869 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.856 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.872 ns                 ;
; 0.858 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.874 ns                 ;
; 0.860 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.876 ns                 ;
; 0.861 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.877 ns                 ;
; 0.895 ns                                ; Binary:binary0|oDATA[9]                                                                                                                           ; touch_tcon:vga0|oLCD_G[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.911 ns                 ;
; 0.916 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[5]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a5~porta_datain_reg1                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.049 ns                   ; 0.965 ns                 ;
; 0.917 ns                                ; Dilation:dilation0|X1[5]                                                                                                                          ; Dilation:dilation0|oDATA[5]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.933 ns                 ;
; 0.918 ns                                ; Dilation:dilation0|X4[2]                                                                                                                          ; Dilation:dilation0|oDATA[2]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.934 ns                 ;
; 0.922 ns                                ; Dilation:dilation0|X6[3]                                                                                                                          ; Dilation:dilation0|oDATA[3]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.938 ns                 ;
; 0.930 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[13] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.054 ns                   ; 0.984 ns                 ;
; 0.930 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[4]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~portb_address_reg4                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.072 ns                   ; 1.002 ns                 ;
; 0.932 ns                                ; Dilation:dilation0|X1[3]                                                                                                                          ; Dilation:dilation0|oDATA[3]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.948 ns                 ;
; 0.937 ns                                ; Binary:binary0|oDATA[9]                                                                                                                           ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~porta_datain_reg1                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.035 ns                   ; 0.972 ns                 ;
; 0.943 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[3]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.044 ns                   ; 0.987 ns                 ;
; 0.945 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[14] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a5~porta_datain_reg2                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.056 ns                   ; 1.001 ns                 ;
; 0.945 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.022 ns                   ; 0.967 ns                 ;
; 0.947 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[25] ; Dilation:dilation0|X3[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.029 ns                   ; 0.976 ns                 ;
; 0.947 ns                                ; Binary:binary0|oDATA[9]                                                                                                                           ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~porta_datain_reg0                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.035 ns                   ; 0.982 ns                 ;
; 0.948 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.012 ns                   ; 0.960 ns                 ;
; 0.950 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[6]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~portb_address_reg6                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.072 ns                   ; 1.022 ns                 ;
; 0.951 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[17] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a6~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.054 ns                   ; 1.005 ns                 ;
; 0.952 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[23] ; Dilation:dilation0|X3[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.029 ns                   ; 0.981 ns                 ;
; 0.952 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.012 ns                   ; 0.964 ns                 ;
; 0.953 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[29] ; Dilation:dilation0|X3[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.029 ns                   ; 0.982 ns                 ;
; 0.955 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.026 ns                   ; 0.981 ns                 ;
; 0.955 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.006 ns                   ; 0.961 ns                 ;
; 0.956 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[26] ; Dilation:dilation0|X3[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.029 ns                   ; 0.985 ns                 ;
; 0.957 ns                                ; Dilation:dilation0|X5[4]                                                                                                                          ; Dilation:dilation0|X4[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.010 ns                   ; 0.967 ns                 ;
; 0.957 ns                                ; Dilation:dilation0|X9[4]                                                                                                                          ; Dilation:dilation0|X8[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.022 ns                   ; 0.979 ns                 ;
; 0.958 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[9]  ; Dilation:dilation0|X9[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.029 ns                   ; 0.987 ns                 ;
; 0.958 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[4]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_address_reg4                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.044 ns                   ; 1.002 ns                 ;
; 0.958 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.043 ns                   ; 1.001 ns                 ;
; 0.960 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.043 ns                   ; 1.003 ns                 ;
; 0.961 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[19] ; Dilation:dilation0|X6[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.029 ns                   ; 0.990 ns                 ;
; 0.962 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.993 ns                 ;
; 0.963 ns                                ; Dilation:dilation0|X7[9]                                                                                                                          ; Dilation:dilation0|oDATA[9]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.980 ns                 ;
; 0.964 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[14] ; Dilation:dilation0|X6[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.029 ns                   ; 0.993 ns                 ;
; 0.964 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[8]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~portb_address_reg8                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.072 ns                   ; 1.036 ns                 ;
; 0.965 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[8]  ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a9~porta_datain_reg1                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.056 ns                   ; 1.021 ns                 ;
; 0.968 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[18] ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a7~porta_datain_reg3                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.042 ns                   ; 1.010 ns                 ;
; 0.968 ns                                ; Dilation:dilation0|X9[5]                                                                                                                          ; Dilation:dilation0|oDATA[5]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.985 ns                 ;
; 0.976 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.022 ns                   ; 0.998 ns                 ;
; 0.978 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[3]  ; Dilation:dilation0|X9[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.029 ns                   ; 1.007 ns                 ;
; 0.978 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[6]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_address_reg6                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.044 ns                   ; 1.022 ns                 ;
; 0.983 ns                                ; Dilation:dilation0|oDVAL                                                                                                                          ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 1.000 ns                 ;
; 0.986 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[2]  ; Dilation:dilation0|X9[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.029 ns                   ; 1.015 ns                 ;
; 0.988 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|q_b[15] ; Dilation:dilation0|X6[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.029 ns                   ; 1.017 ns                 ;
; 0.988 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.004 ns                 ;
; 0.989 ns                                ; Dilation:dilation0|oDATA[3]                                                                                                                       ; touch_tcon:vga0|oLCD_G[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 1.006 ns                 ;
; 0.990 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.006 ns                 ;
; 0.992 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[8]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a2~porta_address_reg8                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.044 ns                   ; 1.036 ns                 ;
; 0.993 ns                                ; Dilation:dilation0|X9[6]                                                                                                                          ; Dilation:dilation0|oDATA[6]                                                                                                                                                              ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 1.010 ns                 ;
; 0.995 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[0]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|altsyncram_gj81:altsyncram2|ram_block3a3~portb_address_reg0                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.077 ns                   ; 1.072 ns                 ;
; 0.995 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 1.026 ns                 ;
; 0.998 ns                                ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[1]            ; Dilation:dilation0|LineBuffer_dilation:b0|altshift_taps:altshift_taps_component|shift_taps_uin:auto_generated|cntr_opf:cntr1|safe_q[1]                                                   ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.014 ns                 ;
; 0.999 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.006 ns                   ; 1.005 ns                 ;
; 1.000 ns                                ; Dilation:dilation0|oDATA[8]                                                                                                                       ; touch_tcon:vga0|oLCD_G[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 1.017 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                               ;                                                                                                                                                                                          ;                                                ;                                                ;                            ;                            ;                          ;
 


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'GPIO_CLKIN_N1'                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                           ; From                                                                                                                                           ; To                                                                                                                                                                                        ; From Clock    ; To Clock      ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+-----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+----------------------------+----------------------------+--------------------------+
; 0.391 ns                                ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                 ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; CCD_Capture:capture0|mSTART                                                                                                                    ; CCD_Capture:capture0|mSTART                                                                                                                                                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; CCD_Capture:capture0|Frame_Cont[0]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[0]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.646 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[22]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a10~porta_datain_reg3                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.695 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[10]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a10~porta_datain_reg1                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[21]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a8~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[18]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a6~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[5]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a4~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.651 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[16]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a3~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.700 ns                 ;
; 0.654 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[12]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a0~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.703 ns                 ;
; 0.654 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[9]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a8~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.703 ns                 ;
; 0.658 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[0]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a0~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.707 ns                 ;
; 0.658 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[13]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a11~porta_datain_reg2                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.707 ns                 ;
; 0.658 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[6]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a6~porta_datain_reg1                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.707 ns                 ;
; 0.660 ns                                ; RAW2RGB:raw0|wData1_d2[7]                                                                                                                      ; RAW2RGB:raw0|rRed[7]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.676 ns                 ;
; 0.662 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[2]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a2~porta_datain_reg1                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.711 ns                 ;
; 0.668 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[17]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a4~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.717 ns                 ;
; 0.669 ns                                ; RAW2RGB:raw0|wData0_d1[6]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[6]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.685 ns                 ;
; 0.669 ns                                ; RAW2RGB:raw0|wData0_d1[4]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[4]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.685 ns                 ;
; 0.672 ns                                ; RAW2RGB:raw0|wData2_d1[10]                                                                                                                     ; RAW2RGB:raw0|wData2_d2[10]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.688 ns                 ;
; 0.677 ns                                ; RAW2RGB:raw0|wData1_d1[6]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[6]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.015 ns                   ; 0.692 ns                 ;
; 0.677 ns                                ; RAW2RGB:raw0|wData1_d1[8]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[8]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.693 ns                 ;
; 0.678 ns                                ; RAW2RGB:raw0|wData2_d1[3]                                                                                                                      ; RAW2RGB:raw0|wData2_d2[3]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.694 ns                 ;
; 0.686 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[1]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.702 ns                 ;
; 0.691 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[7]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg7                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.747 ns                 ;
; 0.696 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[3]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg3                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.752 ns                 ;
; 0.708 ns                                ; RAW2RGB:raw0|wData1_d1[4]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[4]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.725 ns                 ;
; 0.709 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[9]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg9                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.765 ns                 ;
; 0.709 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg8                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.765 ns                 ;
; 0.715 ns                                ; CCD_Capture:capture0|Pre_FVAL                                                                                                                  ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.731 ns                 ;
; 0.716 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[3]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.014 ns                   ; 0.730 ns                 ;
; 0.716 ns                                ; CCD_Capture:capture0|Pre_FVAL                                                                                                                  ; CCD_Capture:capture0|Frame_Cont[0]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.732 ns                 ;
; 0.719 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[7]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg7                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.747 ns                 ;
; 0.723 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[5]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg5                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.779 ns                 ;
; 0.724 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[3]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg3                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.752 ns                 ;
; 0.725 ns                                ; RAW2RGB:raw0|wData1_d1[11]                                                                                                                     ; RAW2RGB:raw0|wData1_d2[11]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.015 ns                   ; 0.740 ns                 ;
; 0.728 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg6                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.784 ns                 ;
; 0.729 ns                                ; RAW2RGB:raw0|wData1_d1[3]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[3]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.745 ns                 ;
; 0.734 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[4]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg4                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.790 ns                 ;
; 0.734 ns                                ; RAW2RGB:raw0|wData1_d1[10]                                                                                                                     ; RAW2RGB:raw0|rBlue[10]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.015 ns                   ; 0.749 ns                 ;
; 0.735 ns                                ; RAW2RGB:raw0|wData1_d1[10]                                                                                                                     ; RAW2RGB:raw0|wData1_d2[10]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.015 ns                   ; 0.750 ns                 ;
; 0.737 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[9]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg9                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.765 ns                 ;
; 0.737 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg8                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.765 ns                 ;
; 0.751 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[5]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg5                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.779 ns                 ;
; 0.756 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg6                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.784 ns                 ;
; 0.762 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[4]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg4                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.790 ns                 ;
; 0.767 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[27]            ; RAW2RGB:raw0|wData0_d1[3]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.027 ns                   ; 0.794 ns                 ;
; 0.784 ns                                ; RAW2RGB:raw0|wData0_d2[10]                                                                                                                     ; RAW2RGB:raw0|rRed[10]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.800 ns                 ;
; 0.789 ns                                ; RAW2RGB:raw0|wData0_d2[2]                                                                                                                      ; RAW2RGB:raw0|rRed[2]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.790 ns                                ; RAW2RGB:raw0|wData0_d2[8]                                                                                                                      ; RAW2RGB:raw0|rRed[8]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.806 ns                 ;
; 0.792 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.808 ns                 ;
; 0.793 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.809 ns                 ;
; 0.795 ns                                ; RAW2RGB:raw0|wData1_d2[9]                                                                                                                      ; RAW2RGB:raw0|rRed[9]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; CCD_Capture:capture0|X_Cont[0]                                                                                                                 ; CCD_Capture:capture0|X_Cont[0]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; CCD_Capture:capture0|Y_Cont[0]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[0]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; CCD_Capture:capture0|Frame_Cont[16]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[16]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.805 ns                                ; RAW2RGB:raw0|wData1_d2[2]                                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|Y_Cont[1]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[1]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|X_Cont[1]                                                                                                                 ; CCD_Capture:capture0|X_Cont[1]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|Frame_Cont[31]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[31]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|Frame_Cont[17]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[17]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[11]                                                                                                                ; CCD_Capture:capture0|Y_Cont[11]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[9]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[9]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[15]                                                                                                                ; CCD_Capture:capture0|Y_Cont[15]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[13]                                                                                                                ; CCD_Capture:capture0|Y_Cont[13]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[14]                                                                                                                ; CCD_Capture:capture0|Y_Cont[14]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[7]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[7]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[4]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[4]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[2]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[2]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[7]                                                                                                                 ; CCD_Capture:capture0|X_Cont[7]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[2]                                                                                                                 ; CCD_Capture:capture0|X_Cont[2]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[13]                                                                                                                ; CCD_Capture:capture0|X_Cont[13]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[11]                                                                                                                ; CCD_Capture:capture0|X_Cont[11]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[4]                                                                                                                 ; CCD_Capture:capture0|X_Cont[4]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[14]                                                                                                                ; CCD_Capture:capture0|X_Cont[14]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[15]                                                                                                                ; CCD_Capture:capture0|X_Cont[15]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[9]                                                                                                                 ; CCD_Capture:capture0|X_Cont[9]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[30]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[30]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[29]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[29]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[27]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[27]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[25]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[25]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[23]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[23]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[20]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[20]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[18]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[18]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[15]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[15]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[14]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[14]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[13]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[13]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.807 ns                                ; RAW2RGB:raw0|wData1_d1[7]                                                                                                                      ; RAW2RGB:raw0|rBlue[7]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.823 ns                 ;
; 0.809 ns                                ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.810 ns                                ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.812 ns                                ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.828 ns                 ;
; 0.813 ns                                ; RAW2RGB:raw0|wData1_d1[3]                                                                                                                      ; RAW2RGB:raw0|rBlue[3]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.814 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.816 ns                                ; RAW2RGB:raw0|wData1_d1[5]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[5]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.816 ns                                ; RAW2RGB:raw0|wData2_d1[11]                                                                                                                     ; RAW2RGB:raw0|wData2_d2[11]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.816 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.816 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.817 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.833 ns                 ;
; 0.819 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.835 ns                 ;
; 0.820 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.836 ns                 ;
; 0.822 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.823 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.839 ns                 ;
; 0.824 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.840 ns                 ;
; 0.825 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[4]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[4]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.841 ns                 ;
; 0.825 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.841 ns                 ;
; 0.826 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.842 ns                 ;
; 0.827 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.843 ns                 ;
; 0.827 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.843 ns                 ;
; 0.829 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.845 ns                 ;
; 0.830 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff      ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.846 ns                 ;
; 0.830 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.846 ns                 ;
; 0.834 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.850 ns                 ;
; 0.836 ns                                ; RAW2RGB:raw0|wData1_d2[11]                                                                                                                     ; RAW2RGB:raw0|rRed[11]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.852 ns                 ;
; 0.838 ns                                ; RAW2RGB:raw0|wData2_d1[10]                                                                                                                     ; RAW2RGB:raw0|rRed[10]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[10]                                                                                                                ; CCD_Capture:capture0|Y_Cont[10]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[12]                                                                                                                ; CCD_Capture:capture0|Y_Cont[12]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[8]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[8]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[3]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[3]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[3]                                                                                                                 ; CCD_Capture:capture0|X_Cont[3]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[10]                                                                                                                ; CCD_Capture:capture0|X_Cont[10]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[12]                                                                                                                ; CCD_Capture:capture0|X_Cont[12]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[8]                                                                                                                 ; CCD_Capture:capture0|X_Cont[8]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[28]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[28]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[26]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[26]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[19]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[19]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[12]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[12]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Y_Cont[6]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[6]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Y_Cont[5]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[5]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|X_Cont[6]                                                                                                                 ; CCD_Capture:capture0|X_Cont[6]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|X_Cont[5]                                                                                                                 ; CCD_Capture:capture0|X_Cont[5]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Frame_Cont[22]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[22]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Frame_Cont[21]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[21]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.840 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[5]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.856 ns                 ;
; 0.841 ns                                ; RAW2RGB:raw0|wData1_d2[5]                                                                                                                      ; RAW2RGB:raw0|rRed[5]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.857 ns                 ;
; 0.842 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.843 ns                                ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.859 ns                 ;
; 0.843 ns                                ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.859 ns                 ;
; 0.845 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.846 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[3]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[3]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.848 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[0]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[0]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.864 ns                 ;
; 0.849 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[2]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[2]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.850 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.851 ns                                ; RAW2RGB:raw0|wData2_d1[6]                                                                                                                      ; RAW2RGB:raw0|rRed[6]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.867 ns                 ;
; 0.851 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.867 ns                 ;
; 0.853 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.869 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.859 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[5]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[5]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.875 ns                 ;
; 0.860 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[7]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[7]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.876 ns                 ;
; 0.861 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[9]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[9]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.877 ns                 ;
; 0.861 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[7]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.014 ns                   ; 0.875 ns                 ;
; 0.872 ns                                ; RAW2RGB:raw0|wData1_d1[9]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[9]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.888 ns                 ;
; 0.880 ns                                ; RAW2RGB:raw0|wData0_d1[9]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[9]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.896 ns                 ;
; 0.901 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[14]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a2~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.950 ns                 ;
; 0.907 ns                                ; RAW2RGB:raw0|wData2_d1[9]                                                                                                                      ; RAW2RGB:raw0|wData2_d2[9]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.923 ns                 ;
; 0.911 ns                                ; RAW2RGB:raw0|wData0_d2[3]                                                                                                                      ; RAW2RGB:raw0|rRed[3]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.927 ns                 ;
; 0.917 ns                                ; RAW2RGB:raw0|wData0_d2[9]                                                                                                                      ; RAW2RGB:raw0|rRed[9]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.933 ns                 ;
; 0.931 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[15]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a3~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.055 ns                   ; 0.986 ns                 ;
; 0.938 ns                                ; RAW2RGB:raw0|wData2_d1[3]                                                                                                                      ; RAW2RGB:raw0|rRed[3]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.954 ns                 ;
; 0.941 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[2]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg2                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.997 ns                 ;
; 0.948 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[4]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.014 ns                   ; 0.962 ns                 ;
; 0.949 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg1                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 1.005 ns                 ;
; 0.956 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[3]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a2~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.043 ns                   ; 0.999 ns                 ;
; 0.957 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[0]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg0                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 1.013 ns                 ;
; 0.958 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg1 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.080 ns                   ; 1.038 ns                 ;
; 0.961 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~portb_address_reg1 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.094 ns                   ; 1.055 ns                 ;
; 0.966 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[2]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg2                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.994 ns                 ;
; 0.966 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[0]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg0                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.994 ns                 ;
; 0.969 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[4]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a3~porta_datain_reg1                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.040 ns                   ; 1.009 ns                 ;
; 0.972 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[20]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 1.021 ns                 ;
; 0.974 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[14]            ; RAW2RGB:raw0|wData1_d1[2]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.033 ns                   ; 1.007 ns                 ;
; 0.975 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.991 ns                 ;
; 0.975 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[3]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.053 ns                   ; 1.028 ns                 ;
; 0.977 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[1]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a11~porta_datain_reg1                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.041 ns                   ; 1.018 ns                 ;
; 0.977 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg1                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 1.005 ns                 ;
; 0.980 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a10~portb_address_reg8                              ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.063 ns                   ; 1.043 ns                 ;
; 0.991 ns                                ; RAW2RGB:raw0|wData1_d1[6]                                                                                                                      ; RAW2RGB:raw0|rBlue[6]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 1.007 ns                 ;
; 0.992 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 1.008 ns                 ;
; 0.994 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[19]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.033 ns                   ; 1.027 ns                 ;
; 0.998 ns                                ; RAW2RGB:raw0|wData1_d2[9]                                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 1.015 ns                 ;
; 1.000 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a8~portb_address_reg6                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.068 ns                   ; 1.068 ns                 ;
; 1.001 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 1.017 ns                 ;
; 1.003 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff      ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 1.019 ns                 ;
; 1.005 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[0]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.029 ns                   ; 1.034 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                            ;                                                                                                                                                                                           ;               ;               ;                            ;                            ;                          ;
+-----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+----------------------------+----------------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'iCLK_50'                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------------------+-----------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                           ; From                                                            ; To                                                              ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+-----------------------------------------+-----------------------------------------------------------------+-----------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; 0.391 ns                                ; rClk[0]                                                         ; rClk[0]                                                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SCLK           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SCLK           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO            ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|lut_index[0]                       ; lcd_3wire_config:lcd_config0|lut_index[0]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|m3wire_str                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Reset_Delay:reset0|Cont[0]                                      ; Reset_Delay:reset0|Cont[0]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Reset_Delay:reset0|oRST_2                                       ; Reset_Delay:reset0|oRST_2                                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.583 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.599 ns                 ;
; 0.597 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSCLK            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.613 ns                 ;
; 0.788 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[0]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[0]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.804 ns                 ;
; 0.788 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[1]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[1]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.804 ns                 ;
; 0.795 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[7]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[7]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.796 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.797 ns                                ; Reset_Delay:reset0|Cont[12]                                     ; Reset_Delay:reset0|Cont[12]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.813 ns                 ;
; 0.800 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.816 ns                 ;
; 0.800 ns                                ; Reset_Delay:reset0|Cont[0]                                      ; Reset_Delay:reset0|Cont[1]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.816 ns                 ;
; 0.801 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.802 ns                                ; Reset_Delay:reset0|Cont[3]                                      ; Reset_Delay:reset0|Cont[3]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.804 ns                                ; Reset_Delay:reset0|Cont[13]                                     ; Reset_Delay:reset0|Cont[13]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.820 ns                 ;
; 0.808 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[5]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[5]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.824 ns                 ;
; 0.809 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.809 ns                                ; Reset_Delay:reset0|Cont[5]                                      ; Reset_Delay:reset0|Cont[5]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.809 ns                                ; Reset_Delay:reset0|Cont[7]                                      ; Reset_Delay:reset0|Cont[7]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.809 ns                                ; Reset_Delay:reset0|Cont[21]                                     ; Reset_Delay:reset0|Cont[21]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.810 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[0]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[0]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[3]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[3]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[9]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[9]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; Reset_Delay:reset0|Cont[9]                                      ; Reset_Delay:reset0|Cont[9]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; Reset_Delay:reset0|Cont[10]                                     ; Reset_Delay:reset0|Cont[10]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.811 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.827 ns                 ;
; 0.812 ns                                ; lcd_3wire_config:lcd_config0|lut_index[3]                       ; lcd_3wire_config:lcd_config0|lut_index[3]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.828 ns                 ;
; 0.813 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[21]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[21]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; Reset_Delay:reset0|Cont[14]                                     ; Reset_Delay:reset0|Cont[14]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.814 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[23]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[23]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[16]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[16]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[19]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[19]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; Reset_Delay:reset0|Cont[11]                                     ; Reset_Delay:reset0|Cont[11]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; Reset_Delay:reset0|Cont[16]                                     ; Reset_Delay:reset0|Cont[16]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.815 ns                                ; Reset_Delay:reset0|Cont[19]                                     ; Reset_Delay:reset0|Cont[19]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.831 ns                 ;
; 0.816 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[5]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[5]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.816 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.825 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[9]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.841 ns                 ;
; 0.828 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[6]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[6]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.844 ns                 ;
; 0.828 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.844 ns                 ;
; 0.832 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[8]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[8]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.848 ns                 ;
; 0.834 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[1]           ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.850 ns                 ;
; 0.835 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[10]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[10]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[8]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[8]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[0]           ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[1]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[3]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[3]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[5]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[5]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[12] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[12] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|m3wire_str                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.838 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[1]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[1]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.839 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[2]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[2]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.841 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[20]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[20]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.857 ns                 ;
; 0.841 ns                                ; Reset_Delay:reset0|Cont[1]                                      ; Reset_Delay:reset0|Cont[1]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.857 ns                 ;
; 0.842 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[10]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 0.859 ns                 ;
; 0.842 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[22]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[22]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.842 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0001                     ; lcd_3wire_config:lcd_config0|msetup_st.0010                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.842 ns                                ; Reset_Delay:reset0|Cont[2]                                      ; Reset_Delay:reset0|Cont[2]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.843 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[4]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[4]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.859 ns                 ;
; 0.844 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[2]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[2]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.860 ns                 ;
; 0.844 ns                                ; Reset_Delay:reset0|Cont[4]                                      ; Reset_Delay:reset0|Cont[4]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.860 ns                 ;
; 0.845 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[8]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[8]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; Reset_Delay:reset0|Cont[6]                                      ; Reset_Delay:reset0|Cont[6]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; Reset_Delay:reset0|Cont[15]                                     ; Reset_Delay:reset0|Cont[15]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; Reset_Delay:reset0|Cont[22]                                     ; Reset_Delay:reset0|Cont[22]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; Reset_Delay:reset0|Cont[20]                                     ; Reset_Delay:reset0|Cont[20]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.846 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[17]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[24]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[24]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; Reset_Delay:reset0|Cont[8]                                      ; Reset_Delay:reset0|Cont[8]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; Reset_Delay:reset0|Cont[17]                                     ; Reset_Delay:reset0|Cont[17]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.847 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[18]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[18]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.863 ns                 ;
; 0.847 ns                                ; Reset_Delay:reset0|Cont[18]                                     ; Reset_Delay:reset0|Cont[18]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.863 ns                 ;
; 0.848 ns                                ; lcd_3wire_config:lcd_config0|lut_index[2]                       ; lcd_3wire_config:lcd_config0|lut_index[2]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.864 ns                 ;
; 0.848 ns                                ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.864 ns                 ;
; 0.850 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[15]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 0.867 ns                 ;
; 0.851 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[16]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[16]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 0.868 ns                 ;
; 0.852 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[20]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[20]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.003 ns                   ; 0.855 ns                 ;
; 0.856 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.872 ns                 ;
; 0.857 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[18]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[18]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 0.874 ns                 ;
; 0.860 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.876 ns                 ;
; 0.864 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[1]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[1]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.880 ns                 ;
; 0.865 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.881 ns                 ;
; 0.872 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.888 ns                 ;
; 0.879 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.895 ns                 ;
; 0.925 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2           ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.941 ns                 ;
; 0.945 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[5]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.018 ns                   ; 0.963 ns                 ;
; 0.945 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 0.962 ns                 ;
; 0.945 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 0.962 ns                 ;
; 0.948 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 0.965 ns                 ;
; 0.965 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[6]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[6]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.027 ns                   ; 0.992 ns                 ;
; 0.966 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.020 ns                   ; 0.986 ns                 ;
; 0.967 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.983 ns                 ;
; 0.969 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.020 ns                   ; 0.989 ns                 ;
; 0.976 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[7]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[7]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.992 ns                 ;
; 0.977 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.993 ns                 ;
; 0.977 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[2]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[2]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.993 ns                 ;
; 0.977 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[12]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[12]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.993 ns                 ;
; 0.978 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.994 ns                 ;
; 0.978 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.994 ns                 ;
; 0.978 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[10] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[10] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.994 ns                 ;
; 0.978 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[6]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[6]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.994 ns                 ;
; 0.979 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.995 ns                 ;
; 0.979 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[5]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[5]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.995 ns                 ;
; 0.982 ns                                ; lcd_3wire_config:lcd_config0|lut_index[2]                       ; lcd_3wire_config:lcd_config0|m3wire_data[10]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 0.999 ns                 ;
; 0.982 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[3]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[3]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.998 ns                 ;
; 0.982 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|msetup_st.0000                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.998 ns                 ;
; 0.984 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[22]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 0.998 ns                 ;
; 0.985 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.001 ns                 ;
; 0.986 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0010                     ; lcd_3wire_config:lcd_config0|m3wire_str                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.002 ns                 ;
; 0.988 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[21]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[21]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.003 ns                   ; 0.991 ns                 ;
; 0.988 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[15]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[15]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.004 ns                 ;
; 0.991 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[0]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.003 ns                   ; 0.994 ns                 ;
; 0.993 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.010 ns                 ;
; 0.993 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[0]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[0]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.009 ns                 ;
; 0.995 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[14]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.010 ns                 ;
; 1.001 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.017 ns                 ;
; 1.003 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[17]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.019 ns                 ;
; 1.004 ns                                ; lcd_3wire_config:lcd_config0|lut_index[1]                       ; lcd_3wire_config:lcd_config0|m3wire_data[13]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.021 ns                 ;
; 1.004 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.020 ns                 ;
; 1.007 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.023 ns                 ;
; 1.009 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.025 ns                 ;
; 1.009 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[9]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[9]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.025 ns                 ;
; 1.009 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.025 ns                 ;
; 1.009 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[9]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[9]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.025 ns                 ;
; 1.010 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[4]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[4]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.026 ns                 ;
; 1.011 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[1]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[1]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.027 ns                 ;
; 1.011 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[0]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[0]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.027 ns                 ;
; 1.012 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.028 ns                 ;
; 1.013 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[3]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.029 ns                 ;
; 1.013 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[11] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[11] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.029 ns                 ;
; 1.014 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[13] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[13] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.030 ns                 ;
; 1.014 ns                                ; lcd_3wire_config:lcd_config0|lut_index[5]                       ; lcd_3wire_config:lcd_config0|lut_index[5]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.030 ns                 ;
; 1.015 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.031 ns                 ;
; 1.015 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.031 ns                 ;
; 1.015 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.031 ns                 ;
; 1.016 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.032 ns                 ;
; 1.017 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[14]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[14]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.033 ns                 ;
; 1.017 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[4]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[4]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.033 ns                 ;
; 1.017 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[2]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[2]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.033 ns                 ;
; 1.017 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[14] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[14] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.033 ns                 ;
; 1.017 ns                                ; Reset_Delay:reset0|Cont[23]                                     ; Reset_Delay:reset0|Cont[23]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.033 ns                 ;
; 1.018 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[13]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[13]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.034 ns                 ;
; 1.018 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[11]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[11]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.034 ns                 ;
; 1.020 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[5]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.003 ns                   ; 1.023 ns                 ;
; 1.020 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[19]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[19]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.035 ns                 ;
; 1.020 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[11]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.035 ns                 ;
; 1.022 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[8]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.037 ns                 ;
; 1.026 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.012 ns                   ; 1.038 ns                 ;
; 1.029 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.012 ns                   ; 1.041 ns                 ;
; 1.030 ns                                ; Reset_Delay:reset0|Cont[20]                                     ; Reset_Delay:reset0|oRST_0                                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 1.044 ns                 ;
; 1.034 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[18]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.012 ns                   ; 1.046 ns                 ;
; 1.035 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.051 ns                 ;
; 1.040 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.056 ns                 ;
; 1.051 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.067 ns                 ;
; 1.059 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0100                     ; lcd_3wire_config:lcd_config0|msetup_st.0000                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.075 ns                 ;
; 1.060 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[7]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.076 ns                 ;
; 1.068 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0000                     ; lcd_3wire_config:lcd_config0|msetup_st.0001                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.084 ns                 ;
; 1.081 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.097 ns                 ;
; 1.082 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[19]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 1.096 ns                 ;
; 1.092 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.108 ns                 ;
; 1.096 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.112 ns                 ;
; 1.096 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|msetup_st.0100                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.112 ns                 ;
; 1.104 ns                                ; lcd_3wire_config:lcd_config0|lut_index[3]                       ; lcd_3wire_config:lcd_config0|m3wire_data[10]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.121 ns                 ;
; 1.105 ns                                ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; lcd_3wire_config:lcd_config0|m3wire_data[1]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.122 ns                 ;
; 1.106 ns                                ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; lcd_3wire_config:lcd_config0|m3wire_data[2]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.123 ns                 ;
; 1.108 ns                                ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; lcd_3wire_config:lcd_config0|m3wire_data[0]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.125 ns                 ;
; 1.111 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[12]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.028 ns                   ; 1.139 ns                 ;
; 1.116 ns                                ; lcd_3wire_config:lcd_config0|lut_index[0]                       ; lcd_3wire_config:lcd_config0|m3wire_data[6]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.133 ns                 ;
; 1.124 ns                                ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; lcd_3wire_config:lcd_config0|m3wire_data[5]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.141 ns                 ;
; 1.128 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[23]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[23]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.003 ns                   ; 1.131 ns                 ;
; 1.130 ns                                ; lcd_3wire_config:lcd_config0|lut_index[0]                       ; lcd_3wire_config:lcd_config0|m3wire_data[13]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.147 ns                 ;
; 1.136 ns                                ; lcd_3wire_config:lcd_config0|lut_index[3]                       ; lcd_3wire_config:lcd_config0|m3wire_data[3]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.153 ns                 ;
; 1.137 ns                                ; lcd_3wire_config:lcd_config0|lut_index[1]                       ; lcd_3wire_config:lcd_config0|m3wire_data[4]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.154 ns                 ;
; 1.145 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]              ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[13]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.039 ns                   ; 3.184 ns                 ;
; 1.146 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.162 ns                 ;
; 1.146 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[16]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.012 ns                   ; 1.158 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)             ;                                                                 ;            ;          ;                            ;                            ;                          ;
+-----------------------------------------+-----------------------------------------------------------------+-----------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                         ;
+-----------+--------------+------------+-------------+-------------------------------------------------------+---------------+
; Slack     ; Required tsu ; Actual tsu ; From        ; To                                                    ; To Clock      ;
+-----------+--------------+------------+-------------+-------------------------------------------------------+---------------+
; -0.330 ns ; 1.000 ns     ; 1.330 ns   ; DRAM_DQ[30] ; Sdram_Control_4Port:sdram1|mDATAOUT[14]               ; iCLK_50_3     ;
; -0.317 ns ; 1.000 ns     ; 1.317 ns   ; DRAM_DQ[28] ; Sdram_Control_4Port:sdram1|mDATAOUT[12]               ; iCLK_50_3     ;
; -0.317 ns ; 1.000 ns     ; 1.317 ns   ; DRAM_DQ[27] ; Sdram_Control_4Port:sdram1|mDATAOUT[11]               ; iCLK_50_3     ;
; -0.310 ns ; 1.000 ns     ; 1.310 ns   ; DRAM_DQ[29] ; Sdram_Control_4Port:sdram1|mDATAOUT[13]               ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[4]  ; Sdram_Control_4Port:sdram0|mDATAOUT[4]                ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[25] ; Sdram_Control_4Port:sdram1|mDATAOUT[9]                ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[3]  ; Sdram_Control_4Port:sdram0|mDATAOUT[3]                ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[24] ; Sdram_Control_4Port:sdram1|mDATAOUT[8]                ; iCLK_50_3     ;
; -0.286 ns ; 1.000 ns     ; 1.286 ns   ; DRAM_DQ[2]  ; Sdram_Control_4Port:sdram0|mDATAOUT[2]                ; iCLK_50_3     ;
; -0.286 ns ; 1.000 ns     ; 1.286 ns   ; DRAM_DQ[26] ; Sdram_Control_4Port:sdram1|mDATAOUT[10]               ; iCLK_50_3     ;
; -0.276 ns ; 1.000 ns     ; 1.276 ns   ; DRAM_DQ[5]  ; Sdram_Control_4Port:sdram0|mDATAOUT[5]                ; iCLK_50_3     ;
; -0.270 ns ; 1.000 ns     ; 1.270 ns   ; DRAM_DQ[22] ; Sdram_Control_4Port:sdram1|mDATAOUT[6]                ; iCLK_50_3     ;
; -0.270 ns ; 1.000 ns     ; 1.270 ns   ; DRAM_DQ[21] ; Sdram_Control_4Port:sdram1|mDATAOUT[5]                ; iCLK_50_3     ;
; -0.270 ns ; 1.000 ns     ; 1.270 ns   ; DRAM_DQ[19] ; Sdram_Control_4Port:sdram1|mDATAOUT[3]                ; iCLK_50_3     ;
; -0.268 ns ; 1.000 ns     ; 1.268 ns   ; DRAM_DQ[23] ; Sdram_Control_4Port:sdram1|mDATAOUT[7]                ; iCLK_50_3     ;
; -0.267 ns ; 1.000 ns     ; 1.267 ns   ; DRAM_DQ[7]  ; Sdram_Control_4Port:sdram0|mDATAOUT[7]                ; iCLK_50_3     ;
; -0.267 ns ; 1.000 ns     ; 1.267 ns   ; DRAM_DQ[6]  ; Sdram_Control_4Port:sdram0|mDATAOUT[6]                ; iCLK_50_3     ;
; -0.262 ns ; 1.000 ns     ; 1.262 ns   ; DRAM_DQ[10] ; Sdram_Control_4Port:sdram0|mDATAOUT[10]               ; iCLK_50_3     ;
; -0.262 ns ; 1.000 ns     ; 1.262 ns   ; DRAM_DQ[9]  ; Sdram_Control_4Port:sdram0|mDATAOUT[9]                ; iCLK_50_3     ;
; -0.260 ns ; 1.000 ns     ; 1.260 ns   ; DRAM_DQ[20] ; Sdram_Control_4Port:sdram1|mDATAOUT[4]                ; iCLK_50_3     ;
; -0.256 ns ; 1.000 ns     ; 1.256 ns   ; DRAM_DQ[14] ; Sdram_Control_4Port:sdram0|mDATAOUT[14]               ; iCLK_50_3     ;
; -0.256 ns ; 1.000 ns     ; 1.256 ns   ; DRAM_DQ[13] ; Sdram_Control_4Port:sdram0|mDATAOUT[13]               ; iCLK_50_3     ;
; -0.254 ns ; 1.000 ns     ; 1.254 ns   ; DRAM_DQ[18] ; Sdram_Control_4Port:sdram1|mDATAOUT[2]                ; iCLK_50_3     ;
; -0.246 ns ; 1.000 ns     ; 1.246 ns   ; DRAM_DQ[12] ; Sdram_Control_4Port:sdram0|mDATAOUT[12]               ; iCLK_50_3     ;
; -0.229 ns ; 1.000 ns     ; 1.229 ns   ; DRAM_DQ[11] ; Sdram_Control_4Port:sdram0|mDATAOUT[11]               ; iCLK_50_3     ;
; -0.222 ns ; 1.000 ns     ; 1.222 ns   ; DRAM_DQ[8]  ; Sdram_Control_4Port:sdram0|mDATAOUT[8]                ; iCLK_50_3     ;
; 2.509 ns  ; 5.000 ns     ; 2.491 ns   ; GPIO_1[10]  ; rCCD_DATA[1]                                          ; GPIO_CLKIN_N1 ;
; 2.520 ns  ; 5.000 ns     ; 2.480 ns   ; GPIO_1[6]   ; rCCD_DATA[5]                                          ; GPIO_CLKIN_N1 ;
; 2.520 ns  ; 5.000 ns     ; 2.480 ns   ; GPIO_1[8]   ; rCCD_DATA[3]                                          ; GPIO_CLKIN_N1 ;
; 2.529 ns  ; 5.000 ns     ; 2.471 ns   ; GPIO_1[9]   ; rCCD_DATA[2]                                          ; GPIO_CLKIN_N1 ;
; 2.529 ns  ; 5.000 ns     ; 2.471 ns   ; GPIO_1[7]   ; rCCD_DATA[4]                                          ; GPIO_CLKIN_N1 ;
; 2.554 ns  ; 5.000 ns     ; 2.446 ns   ; GPIO_1[11]  ; rCCD_DATA[0]                                          ; GPIO_CLKIN_N1 ;
; 2.566 ns  ; 5.000 ns     ; 2.434 ns   ; GPIO_1[17]  ; rCCD_LVAL                                             ; GPIO_CLKIN_N1 ;
; 2.575 ns  ; 5.000 ns     ; 2.425 ns   ; GPIO_1[1]   ; rCCD_DATA[10]                                         ; GPIO_CLKIN_N1 ;
; 2.575 ns  ; 5.000 ns     ; 2.425 ns   ; GPIO_1[0]   ; rCCD_DATA[11]                                         ; GPIO_CLKIN_N1 ;
; 2.578 ns  ; 5.000 ns     ; 2.422 ns   ; GPIO_1[5]   ; rCCD_DATA[6]                                          ; GPIO_CLKIN_N1 ;
; 2.578 ns  ; 5.000 ns     ; 2.422 ns   ; GPIO_1[3]   ; rCCD_DATA[8]                                          ; GPIO_CLKIN_N1 ;
; 2.585 ns  ; 5.000 ns     ; 2.415 ns   ; GPIO_1[2]   ; rCCD_DATA[9]                                          ; GPIO_CLKIN_N1 ;
; 2.585 ns  ; 5.000 ns     ; 2.415 ns   ; GPIO_1[4]   ; rCCD_DATA[7]                                          ; GPIO_CLKIN_N1 ;
; 2.586 ns  ; 5.000 ns     ; 2.414 ns   ; GPIO_1[18]  ; rCCD_FVAL                                             ; GPIO_CLKIN_N1 ;
; N/A       ; None         ; 10.206 ns  ; iSW[14]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 10.050 ns  ; iSW[15]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 10.039 ns  ; iSW[14]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.846 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.844 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.734 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.692 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.685 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.651 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.641 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.562 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.539 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.533 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.497 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.496 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.490 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.485 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.471 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.377 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.369 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.357 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.301 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.276 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.257 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.215 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.208 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.201 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.173 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.160 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.044 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.030 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.019 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.017 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.004 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 9.002 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.994 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.968 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.965 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.888 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.846 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.835 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.719 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.683 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.594 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.553 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.500 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.500 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.491 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.491 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.471 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.471 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.314 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.314 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.305 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.305 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.285 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.285 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.255 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.231 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.069 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.999 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.999 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.996 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.996 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.987 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.987 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.967 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.967 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.813 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.813 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.495 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.495 ns   ; iSW[13]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A       ; None         ; 7.095 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A       ; None         ; 6.491 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A       ; None         ; 5.527 ns   ; iSW[17]     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]          ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A       ; None         ; 5.514 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A       ; None         ; 5.385 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A       ; None         ; 4.191 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[0] ; iCLK_50       ;
; N/A       ; None         ; 3.483 ns   ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1 ; iCLK_50       ;
; N/A       ; None         ; 3.152 ns   ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2 ; iCLK_50       ;
; N/A       ; None         ; 2.906 ns   ; iKEY[2]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A       ; None         ; 2.640 ns   ; iKEY[3]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A       ; None         ; 2.629 ns   ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3 ; iCLK_50       ;
; N/A       ; None         ; 2.340 ns   ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4 ; iCLK_50       ;
; N/A       ; None         ; 1.341 ns   ; iSW[17]     ; RAW2RGB:raw0|mirror_sw                                ; iCLK_50       ;
+-----------+--------------+------------+-------------+-------------------------------------------------------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------+
; Slack                                   ; Required tco                                        ; Actual tco ; From                                                                                                                                                              ; To          ; From Clock    ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------+
; -4.997 ns                               ; 1.000 ns                                            ; 5.997 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[28] ; iCLK_50_3     ;
; -4.986 ns                               ; 1.000 ns                                            ; 5.986 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[20] ; iCLK_50_3     ;
; -4.963 ns                               ; 1.000 ns                                            ; 5.963 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[9]  ; iCLK_50_3     ;
; -4.944 ns                               ; 1.000 ns                                            ; 5.944 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[10] ; iCLK_50_3     ;
; -4.931 ns                               ; 1.000 ns                                            ; 5.931 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[0]  ; iCLK_50_3     ;
; -4.907 ns                               ; 1.000 ns                                            ; 5.907 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[27] ; iCLK_50_3     ;
; -4.905 ns                               ; 1.000 ns                                            ; 5.905 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[16] ; iCLK_50_3     ;
; -4.884 ns                               ; 1.000 ns                                            ; 5.884 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[7]  ; iCLK_50_3     ;
; -4.867 ns                               ; 1.000 ns                                            ; 5.867 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[10] ; iCLK_50_3     ;
; -4.865 ns                               ; 1.000 ns                                            ; 5.865 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[21] ; iCLK_50_3     ;
; -4.860 ns                               ; 1.000 ns                                            ; 5.860 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[20] ; iCLK_50_3     ;
; -4.854 ns                               ; 1.000 ns                                            ; 5.854 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[29] ; iCLK_50_3     ;
; -4.848 ns                               ; 1.000 ns                                            ; 5.848 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[1]  ; iCLK_50_3     ;
; -4.847 ns                               ; 1.000 ns                                            ; 5.847 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[27] ; iCLK_50_3     ;
; -4.838 ns                               ; 1.000 ns                                            ; 5.838 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[15] ; iCLK_50_3     ;
; -4.833 ns                               ; 1.000 ns                                            ; 5.833 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[13] ; iCLK_50_3     ;
; -4.827 ns                               ; 1.000 ns                                            ; 5.827 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[27] ; iCLK_50_3     ;
; -4.817 ns                               ; 1.000 ns                                            ; 5.817 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[26] ; iCLK_50_3     ;
; -4.816 ns                               ; 1.000 ns                                            ; 5.816 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[15] ; iCLK_50_3     ;
; -4.806 ns                               ; 1.000 ns                                            ; 5.806 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[29] ; iCLK_50_3     ;
; -4.801 ns                               ; 1.000 ns                                            ; 5.801 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[25] ; iCLK_50_3     ;
; -4.791 ns                               ; 1.000 ns                                            ; 5.791 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[19] ; iCLK_50_3     ;
; -4.782 ns                               ; 1.000 ns                                            ; 5.782 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[0]  ; iCLK_50_3     ;
; -4.779 ns                               ; 1.000 ns                                            ; 5.779 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[30] ; iCLK_50_3     ;
; -4.776 ns                               ; 1.000 ns                                            ; 5.776 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[8]  ; iCLK_50_3     ;
; -4.754 ns                               ; 1.000 ns                                            ; 5.754 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[24] ; iCLK_50_3     ;
; -4.752 ns                               ; 1.000 ns                                            ; 5.752 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[16] ; iCLK_50_3     ;
; -4.749 ns                               ; 1.000 ns                                            ; 5.749 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[7]  ; iCLK_50_3     ;
; -4.742 ns                               ; 1.000 ns                                            ; 5.742 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[9]  ; iCLK_50_3     ;
; -4.727 ns                               ; 1.000 ns                                            ; 5.727 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[12] ; iCLK_50_3     ;
; -4.724 ns                               ; 1.000 ns                                            ; 5.724 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[12] ; iCLK_50_3     ;
; -4.721 ns                               ; 1.000 ns                                            ; 5.721 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[6]  ; iCLK_50_3     ;
; -4.712 ns                               ; 1.000 ns                                            ; 5.712 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[15] ; iCLK_50_3     ;
; -4.709 ns                               ; 1.000 ns                                            ; 5.709 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[18] ; iCLK_50_3     ;
; -4.701 ns                               ; 1.000 ns                                            ; 5.701 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[30] ; iCLK_50_3     ;
; -4.701 ns                               ; 1.000 ns                                            ; 5.701 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[26] ; iCLK_50_3     ;
; -4.697 ns                               ; 1.000 ns                                            ; 5.697 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[4]  ; iCLK_50_3     ;
; -4.694 ns                               ; 1.000 ns                                            ; 5.694 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[24] ; iCLK_50_3     ;
; -4.690 ns                               ; 1.000 ns                                            ; 5.690 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[17] ; iCLK_50_3     ;
; -4.686 ns                               ; 1.000 ns                                            ; 5.686 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[28] ; iCLK_50_3     ;
; -4.672 ns                               ; 1.000 ns                                            ; 5.672 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[1]  ; iCLK_50_3     ;
; -4.654 ns                               ; 1.000 ns                                            ; 5.654 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[2]  ; iCLK_50_3     ;
; -4.650 ns                               ; 1.000 ns                                            ; 5.650 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[31] ; iCLK_50_3     ;
; -4.646 ns                               ; 1.000 ns                                            ; 5.646 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[21] ; iCLK_50_3     ;
; -4.639 ns                               ; 1.000 ns                                            ; 5.639 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[25] ; iCLK_50_3     ;
; -4.635 ns                               ; 1.000 ns                                            ; 5.635 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[8]  ; iCLK_50_3     ;
; -4.630 ns                               ; 1.000 ns                                            ; 5.630 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[12] ; iCLK_50_3     ;
; -4.627 ns                               ; 1.000 ns                                            ; 5.627 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[11] ; iCLK_50_3     ;
; -4.623 ns                               ; 1.000 ns                                            ; 5.623 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[16] ; iCLK_50_3     ;
; -4.617 ns                               ; 1.000 ns                                            ; 5.617 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[13] ; iCLK_50_3     ;
; -4.615 ns                               ; 1.000 ns                                            ; 5.615 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[29] ; iCLK_50_3     ;
; -4.603 ns                               ; 1.000 ns                                            ; 5.603 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[10] ; iCLK_50_3     ;
; -4.595 ns                               ; 1.000 ns                                            ; 5.595 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[30] ; iCLK_50_3     ;
; -4.588 ns                               ; 1.000 ns                                            ; 5.588 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[19] ; iCLK_50_3     ;
; -4.587 ns                               ; 1.000 ns                                            ; 5.587 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[0]  ; iCLK_50_3     ;
; -4.583 ns                               ; 1.000 ns                                            ; 5.583 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[11] ; iCLK_50_3     ;
; -4.581 ns                               ; 1.000 ns                                            ; 5.581 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[20] ; iCLK_50_3     ;
; -4.577 ns                               ; 1.000 ns                                            ; 5.577 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[22] ; iCLK_50_3     ;
; -4.572 ns                               ; 1.000 ns                                            ; 5.572 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[23] ; iCLK_50_3     ;
; -4.557 ns                               ; 1.000 ns                                            ; 5.557 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[18] ; iCLK_50_3     ;
; -4.546 ns                               ; 1.000 ns                                            ; 5.546 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[18] ; iCLK_50_3     ;
; -4.545 ns                               ; 1.000 ns                                            ; 5.545 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[6]  ; iCLK_50_3     ;
; -4.531 ns                               ; 1.000 ns                                            ; 5.531 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[2]  ; iCLK_50_3     ;
; -4.520 ns                               ; 1.000 ns                                            ; 5.520 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[13] ; iCLK_50_3     ;
; -4.512 ns                               ; 1.000 ns                                            ; 5.512 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[2]  ; iCLK_50_3     ;
; -4.512 ns                               ; 1.000 ns                                            ; 5.512 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[4]  ; iCLK_50_3     ;
; -4.504 ns                               ; 1.000 ns                                            ; 5.504 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[31] ; iCLK_50_3     ;
; -4.489 ns                               ; 1.000 ns                                            ; 5.489 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[22] ; iCLK_50_3     ;
; -4.485 ns                               ; 1.000 ns                                            ; 5.485 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[26] ; iCLK_50_3     ;
; -4.473 ns                               ; 1.000 ns                                            ; 5.473 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[3]  ; iCLK_50_3     ;
; -4.464 ns                               ; 1.000 ns                                            ; 5.464 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[17] ; iCLK_50_3     ;
; -4.462 ns                               ; 1.000 ns                                            ; 5.462 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[5]  ; iCLK_50_3     ;
; -4.454 ns                               ; 1.000 ns                                            ; 5.454 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[9]  ; iCLK_50_3     ;
; -4.444 ns                               ; 1.000 ns                                            ; 5.444 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[11] ; iCLK_50_3     ;
; -4.440 ns                               ; 1.000 ns                                            ; 5.440 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[28] ; iCLK_50_3     ;
; -4.439 ns                               ; 1.000 ns                                            ; 5.439 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[7]  ; iCLK_50_3     ;
; -4.428 ns                               ; 1.000 ns                                            ; 5.428 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[31] ; iCLK_50_3     ;
; -4.424 ns                               ; 1.000 ns                                            ; 5.424 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[23] ; iCLK_50_3     ;
; -4.422 ns                               ; 1.000 ns                                            ; 5.422 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[21] ; iCLK_50_3     ;
; -4.401 ns                               ; 1.000 ns                                            ; 5.401 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[1]  ; iCLK_50_3     ;
; -4.400 ns                               ; 1.000 ns                                            ; 5.400 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[3]  ; iCLK_50_3     ;
; -4.397 ns                               ; 1.000 ns                                            ; 5.397 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[5]  ; iCLK_50_3     ;
; -4.393 ns                               ; 1.000 ns                                            ; 5.393 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[19] ; iCLK_50_3     ;
; -4.384 ns                               ; 1.000 ns                                            ; 5.384 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[8]  ; iCLK_50_3     ;
; -4.347 ns                               ; 1.000 ns                                            ; 5.347 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[14] ; iCLK_50_3     ;
; -4.345 ns                               ; 1.000 ns                                            ; 5.345 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[6]  ; iCLK_50_3     ;
; -4.331 ns                               ; 1.000 ns                                            ; 5.331 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[14] ; iCLK_50_3     ;
; -4.303 ns                               ; 1.000 ns                                            ; 5.303 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[22] ; iCLK_50_3     ;
; -4.302 ns                               ; 1.000 ns                                            ; 5.302 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[23] ; iCLK_50_3     ;
; -4.290 ns                               ; 1.000 ns                                            ; 5.290 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[3]  ; iCLK_50_3     ;
; -4.268 ns                               ; 1.000 ns                                            ; 5.268 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[5]  ; iCLK_50_3     ;
; -4.260 ns                               ; 1.000 ns                                            ; 5.260 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[14] ; iCLK_50_3     ;
; -4.236 ns                               ; 1.000 ns                                            ; 5.236 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[25] ; iCLK_50_3     ;
; -4.236 ns                               ; 1.000 ns                                            ; 5.236 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[17] ; iCLK_50_3     ;
; -4.215 ns                               ; 1.000 ns                                            ; 5.215 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[24] ; iCLK_50_3     ;
; -4.211 ns                               ; 1.000 ns                                            ; 5.211 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[4]  ; iCLK_50_3     ;
; -3.215 ns                               ; 1.000 ns                                            ; 4.215 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[13] ; iCLK_50_3     ;
; -3.215 ns                               ; 1.000 ns                                            ; 4.215 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[14] ; iCLK_50_3     ;
; -3.215 ns                               ; 1.000 ns                                            ; 4.215 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[15] ; iCLK_50_3     ;
; -3.211 ns                               ; 1.000 ns                                            ; 4.211 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[11] ; iCLK_50_3     ;
; -3.205 ns                               ; 1.000 ns                                            ; 4.205 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[12] ; iCLK_50_3     ;
; -3.199 ns                               ; 1.000 ns                                            ; 4.199 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[10] ; iCLK_50_3     ;
; -3.199 ns                               ; 1.000 ns                                            ; 4.199 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[9]  ; iCLK_50_3     ;
; -3.196 ns                               ; 1.000 ns                                            ; 4.196 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[8]  ; iCLK_50_3     ;
; -3.173 ns                               ; 1.000 ns                                            ; 4.173 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[16] ; iCLK_50_3     ;
; -3.173 ns                               ; 1.000 ns                                            ; 4.173 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[17] ; iCLK_50_3     ;
; -2.889 ns                               ; 1.000 ns                                            ; 3.889 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[6]  ; iCLK_50_3     ;
; -2.889 ns                               ; 1.000 ns                                            ; 3.889 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[7]  ; iCLK_50_3     ;
; -2.878 ns                               ; 1.000 ns                                            ; 3.878 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[30] ; iCLK_50_3     ;
; -2.878 ns                               ; 1.000 ns                                            ; 3.878 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[31] ; iCLK_50_3     ;
; -2.873 ns                               ; 1.000 ns                                            ; 3.873 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[28] ; iCLK_50_3     ;
; -2.873 ns                               ; 1.000 ns                                            ; 3.873 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[27] ; iCLK_50_3     ;
; -2.858 ns                               ; 1.000 ns                                            ; 3.858 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[29] ; iCLK_50_3     ;
; -2.853 ns                               ; 1.000 ns                                            ; 3.853 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[18] ; iCLK_50_3     ;
; -2.851 ns                               ; 1.000 ns                                            ; 3.851 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[5]  ; iCLK_50_3     ;
; -2.847 ns                               ; 1.000 ns                                            ; 3.847 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[19] ; iCLK_50_3     ;
; -2.847 ns                               ; 1.000 ns                                            ; 3.847 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[21] ; iCLK_50_3     ;
; -2.847 ns                               ; 1.000 ns                                            ; 3.847 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[22] ; iCLK_50_3     ;
; -2.847 ns                               ; 1.000 ns                                            ; 3.847 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[0]  ; iCLK_50_3     ;
; -2.847 ns                               ; 1.000 ns                                            ; 3.847 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[1]  ; iCLK_50_3     ;
; -2.846 ns                               ; 1.000 ns                                            ; 3.846 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[24] ; iCLK_50_3     ;
; -2.846 ns                               ; 1.000 ns                                            ; 3.846 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[25] ; iCLK_50_3     ;
; -2.837 ns                               ; 1.000 ns                                            ; 3.837 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[20] ; iCLK_50_3     ;
; -2.836 ns                               ; 1.000 ns                                            ; 3.836 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[26] ; iCLK_50_3     ;
; -2.568 ns                               ; 1.000 ns                                            ; 3.568 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[3]  ; iCLK_50_3     ;
; -2.568 ns                               ; 1.000 ns                                            ; 3.568 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[4]  ; iCLK_50_3     ;
; -2.558 ns                               ; 1.000 ns                                            ; 3.558 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[2]  ; iCLK_50_3     ;
; -2.536 ns                               ; 1.000 ns                                            ; 3.536 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[23] ; iCLK_50_3     ;
; N/A                                     ; None                                                ; 13.570 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.453 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.377 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSCLK                                                                                                              ; GPIO_0[2]   ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.039 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.887 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.794 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.682 ns  ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.579 ns  ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                               ; oHEX2_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.503 ns  ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                ; oHEX2_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.150 ns  ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                ; oHEX2_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.082 ns  ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.982 ns  ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                               ; oHEX2_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.948 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[2]                                                                                                    ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.903 ns  ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                ; oHEX2_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.883 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3]                                                                                                    ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.873 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]                                                                                                    ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.822 ns  ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.720 ns  ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                               ; oHEX2_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.643 ns  ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                ; oHEX2_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.606 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[5]                                                                                                    ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.554 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA~en                                                                                                          ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.551 ns  ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                ; oHEX2_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.348 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]                                                                                                    ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.322 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN                                                                                                               ; GPIO_0[30]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.289 ns  ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                ; oHEX2_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.255 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA                                                                                                             ; GPIO_0[31]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.245 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[0]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.234 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.230 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SCLK                                                                                                             ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.076 ns  ; Reset_Delay:reset0|oRST_1                                                                                                                                         ; GPIO_1[14]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 10.979 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.978 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.880 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[0]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.870 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.813 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[0]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.812 ns  ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[0]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.802 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.800 ns  ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.780 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.768 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.759 ns  ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                ; oHEX0_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.746 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO                                                                                                              ; GPIO_1[19]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 10.623 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.619 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.566 ns  ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.563 ns  ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.547 ns  ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.543 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.542 ns  ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.537 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.520 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[1]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.512 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK                                                                                                           ; GPIO_0[2]   ; iCLK_50       ;
; N/A                                     ; None                                                ; 10.473 ns  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK                                                                                                                      ; GPIO_1[20]  ; iCLK_50       ;
; N/A                                     ; None                                                ; 10.471 ns  ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.440 ns  ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                ; oHEX0_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.426 ns  ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.423 ns  ; CCD_Capture:capture0|Frame_Cont[0]                                                                                                                                ; oHEX0_D[0]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.408 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.397 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.397 ns  ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.343 ns  ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.341 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.331 ns  ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.330 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.320 ns  ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                ; oHEX0_D[5]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.305 ns  ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.300 ns  ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.279 ns  ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[6]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.246 ns  ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[3]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.202 ns  ; CCD_Capture:capture0|Frame_Cont[0]                                                                                                                                ; oHEX0_D[4]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.183 ns  ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                ; oHEX0_D[2]  ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.162 ns  ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                ; oHEX0_D[1]  ; GPIO_CLKIN_N1 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;                                                                                                                                                                   ;             ;               ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------+


+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+-----------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To         ;
+-------+-------------------+-----------------+-----------+------------+
; N/A   ; None              ; 10.818 ns       ; iSW[17]   ; oLEDR[17]  ;
; N/A   ; None              ; 10.585 ns       ; iSW[3]    ; oLEDR[3]   ;
; N/A   ; None              ; 10.515 ns       ; iSW[2]    ; oLEDR[2]   ;
; N/A   ; None              ; 10.496 ns       ; iSW[1]    ; oLEDR[1]   ;
; N/A   ; None              ; 10.470 ns       ; iSW[0]    ; oLEDR[0]   ;
; N/A   ; None              ; 10.327 ns       ; iSW[6]    ; oLEDR[6]   ;
; N/A   ; None              ; 10.244 ns       ; iSW[4]    ; oLEDR[4]   ;
; N/A   ; None              ; 10.193 ns       ; iSW[7]    ; oLEDR[7]   ;
; N/A   ; None              ; 10.175 ns       ; iSW[13]   ; oLEDR[13]  ;
; N/A   ; None              ; 10.166 ns       ; iSW[8]    ; oLEDR[8]   ;
; N/A   ; None              ; 10.152 ns       ; iSW[5]    ; oLEDR[5]   ;
; N/A   ; None              ; 10.114 ns       ; iSW[14]   ; oLEDR[14]  ;
; N/A   ; None              ; 10.110 ns       ; iSW[16]   ; oLEDR[16]  ;
; N/A   ; None              ; 9.976 ns        ; iSW[15]   ; oLEDR[15]  ;
; N/A   ; None              ; 9.882 ns        ; iSW[9]    ; oLEDR[9]   ;
; N/A   ; None              ; 9.614 ns        ; iSW[11]   ; oLEDR[11]  ;
; N/A   ; None              ; 9.483 ns        ; iSW[12]   ; oLEDR[12]  ;
; N/A   ; None              ; 9.300 ns        ; iSW[10]   ; oLEDR[10]  ;
; N/A   ; None              ; 8.893 ns        ; iUART_RXD ; oUART_TXD  ;
; N/A   ; None              ; 8.567 ns        ; iKEY[0]   ; GPIO_0[29] ;
+-------+-------------------+-----------------+-----------+------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                            ;
+---------------+-------------+-----------+-------------+-------------------------------------------------------+---------------+
; Minimum Slack ; Required th ; Actual th ; From        ; To                                                    ; To Clock      ;
+---------------+-------------+-----------+-------------+-------------------------------------------------------+---------------+
; N/A           ; None        ; -1.058 ns ; DRAM_DQ[8]  ; Sdram_Control_4Port:sdram0|mDATAOUT[8]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.065 ns ; DRAM_DQ[11] ; Sdram_Control_4Port:sdram0|mDATAOUT[11]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.082 ns ; DRAM_DQ[12] ; Sdram_Control_4Port:sdram0|mDATAOUT[12]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.090 ns ; DRAM_DQ[18] ; Sdram_Control_4Port:sdram1|mDATAOUT[2]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.092 ns ; DRAM_DQ[14] ; Sdram_Control_4Port:sdram0|mDATAOUT[14]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.092 ns ; DRAM_DQ[13] ; Sdram_Control_4Port:sdram0|mDATAOUT[13]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.096 ns ; DRAM_DQ[20] ; Sdram_Control_4Port:sdram1|mDATAOUT[4]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.098 ns ; DRAM_DQ[9]  ; Sdram_Control_4Port:sdram0|mDATAOUT[9]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.098 ns ; DRAM_DQ[10] ; Sdram_Control_4Port:sdram0|mDATAOUT[10]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.103 ns ; DRAM_DQ[7]  ; Sdram_Control_4Port:sdram0|mDATAOUT[7]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.103 ns ; DRAM_DQ[6]  ; Sdram_Control_4Port:sdram0|mDATAOUT[6]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.104 ns ; DRAM_DQ[23] ; Sdram_Control_4Port:sdram1|mDATAOUT[7]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.106 ns ; DRAM_DQ[22] ; Sdram_Control_4Port:sdram1|mDATAOUT[6]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.106 ns ; DRAM_DQ[21] ; Sdram_Control_4Port:sdram1|mDATAOUT[5]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.106 ns ; DRAM_DQ[19] ; Sdram_Control_4Port:sdram1|mDATAOUT[3]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.111 ns ; iSW[17]     ; RAW2RGB:raw0|mirror_sw                                ; iCLK_50       ;
; N/A           ; None        ; -1.112 ns ; DRAM_DQ[5]  ; Sdram_Control_4Port:sdram0|mDATAOUT[5]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.122 ns ; DRAM_DQ[26] ; Sdram_Control_4Port:sdram1|mDATAOUT[10]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.122 ns ; DRAM_DQ[2]  ; Sdram_Control_4Port:sdram0|mDATAOUT[2]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[25] ; Sdram_Control_4Port:sdram1|mDATAOUT[9]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[24] ; Sdram_Control_4Port:sdram1|mDATAOUT[8]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[4]  ; Sdram_Control_4Port:sdram0|mDATAOUT[4]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[3]  ; Sdram_Control_4Port:sdram0|mDATAOUT[3]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.146 ns ; DRAM_DQ[29] ; Sdram_Control_4Port:sdram1|mDATAOUT[13]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.153 ns ; DRAM_DQ[27] ; Sdram_Control_4Port:sdram1|mDATAOUT[11]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.153 ns ; DRAM_DQ[28] ; Sdram_Control_4Port:sdram1|mDATAOUT[12]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.166 ns ; DRAM_DQ[30] ; Sdram_Control_4Port:sdram1|mDATAOUT[14]               ; iCLK_50_3     ;
; N/A           ; None        ; -2.110 ns ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4 ; iCLK_50       ;
; N/A           ; None        ; -2.250 ns ; GPIO_1[18]  ; rCCD_FVAL                                             ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.251 ns ; GPIO_1[4]   ; rCCD_DATA[7]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.251 ns ; GPIO_1[2]   ; rCCD_DATA[9]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.258 ns ; GPIO_1[3]   ; rCCD_DATA[8]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.258 ns ; GPIO_1[5]   ; rCCD_DATA[6]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.261 ns ; GPIO_1[0]   ; rCCD_DATA[11]                                         ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.261 ns ; GPIO_1[1]   ; rCCD_DATA[10]                                         ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.270 ns ; GPIO_1[17]  ; rCCD_LVAL                                             ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.282 ns ; GPIO_1[11]  ; rCCD_DATA[0]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.307 ns ; GPIO_1[7]   ; rCCD_DATA[4]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.307 ns ; GPIO_1[9]   ; rCCD_DATA[2]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.316 ns ; GPIO_1[8]   ; rCCD_DATA[3]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.316 ns ; GPIO_1[6]   ; rCCD_DATA[5]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.327 ns ; GPIO_1[10]  ; rCCD_DATA[1]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.399 ns ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3 ; iCLK_50       ;
; N/A           ; None        ; -2.410 ns ; iKEY[3]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.676 ns ; iKEY[2]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.922 ns ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2 ; iCLK_50       ;
; N/A           ; None        ; -3.253 ns ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1 ; iCLK_50       ;
; N/A           ; None        ; -3.961 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[0] ; iCLK_50       ;
; N/A           ; None        ; -4.060 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A           ; None        ; -4.327 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A           ; None        ; -4.332 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A           ; None        ; -4.334 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A           ; None        ; -4.338 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A           ; None        ; -4.339 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A           ; None        ; -4.339 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A           ; None        ; -4.340 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A           ; None        ; -4.399 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A           ; None        ; -4.399 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A           ; None        ; -4.538 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A           ; None        ; -4.563 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A           ; None        ; -4.564 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A           ; None        ; -4.565 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A           ; None        ; -4.565 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A           ; None        ; -4.911 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A           ; None        ; -5.155 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A           ; None        ; -5.284 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A           ; None        ; -5.297 ns ; iSW[17]     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]          ; iCLK_50       ;
; N/A           ; None        ; -6.839 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.044 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.085 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.097 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.265 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.265 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.348 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.399 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.439 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.440 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.583 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.583 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.593 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.737 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.737 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.757 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.757 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.766 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.766 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.839 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.875 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.936 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.938 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.963 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.001 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.025 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.055 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.055 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.070 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.075 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.075 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.084 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.084 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.112 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.119 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.126 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.174 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.176 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.185 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.207 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.218 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.268 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.282 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.283 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.313 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.332 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.341 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.343 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.364 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.413 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.419 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.419 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.434 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.456 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.469 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.478 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.479 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.489 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.499 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.590 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.646 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.651 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.701 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.701 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.761 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.764 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.789 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.841 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.896 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.896 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.956 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -9.027 ns ; iSW[13]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
+---------------+-------------+-----------+-------------+-------------------------------------------------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Ignored Timing Assignments                                                                                                                                     ;
+-----------------+---------+------+----------------------------------+-------------+----------------------------------------------------------------------------+
; Option          ; Setting ; From ; To                               ; Entity Name ; Help                                                                       ;
+-----------------+---------+------+----------------------------------+-------------+----------------------------------------------------------------------------+
; tco Requirement ; 1 ns    ; *    ; CCD_Capture:u3|Pre_FVAL          ;             ; No element named CCD_Capture:u3|Pre_FVAL was found in the netlist          ;
; tco Requirement ; 1 ns    ; *    ; CCD_Capture:u3|mCCD_DATA         ;             ; No element named CCD_Capture:u3|mCCD_DATA was found in the netlist         ;
; tco Requirement ; 1 ns    ; *    ; CCD_Capture:u3|mCCD_LVAL         ;             ; No element named CCD_Capture:u3|mCCD_LVAL was found in the netlist         ;
; tco Requirement ; 1 ns    ; *    ; Sdram_Control_4Port:u11|mDATAOUT ;             ; No element named Sdram_Control_4Port:u11|mDATAOUT was found in the netlist ;
; tco Requirement ; 1 ns    ; *    ; Sdram_Control_4Port:u6|mDATAOUT  ;             ; No element named Sdram_Control_4Port:u6|mDATAOUT was found in the netlist  ;
+-----------------+---------+------+----------------------------------+-------------+----------------------------------------------------------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Mon Sep 29 16:08:25 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DE2_70 -c DE2_70 --timing_analysis_only
Info: Parallel compilation is enabled and will use up to 2 processors
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Warning: Clock Setting "CLK" is unassigned
Warning: Clock Setting "VGA_CTRL_CLK" is unassigned
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK" as buffer
    Info: Detected ripple clock "lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK" as buffer
    Info: Detected ripple clock "Reset_Delay:reset0|oRST_1" as buffer
    Info: Detected ripple clock "RAW2RGB:raw0|dval_ctrl" as buffer
Info: Found timing assignments -- calculating delays
Info: Slack time is 856 ps for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" between source register "Sdram_Control_4Port:sdram0|ST[4]" and destination register "Sdram_Control_4Port:sdram0|mADDR[16]"
    Info: Fmax is 194.4 MHz (period= 5.144 ns)
    Info: + Largest register to register requirement is 5.795 ns
        Info: + Setup relationship between source and destination is 6.000 ns
            Info: + Latch edge is 3.406 ns
                Info: Clock period of Destination clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is -2.594 ns
                Info: Clock period of Source clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.009 ns
            Info: + Shortest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to destination register is 2.814 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.229 ns) + CELL(0.537 ns) = 2.814 ns; Loc. = LCFF_X14_Y10_N15; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram0|mADDR[16]'
                Info: Total cell delay = 0.537 ns ( 19.08 % )
                Info: Total interconnect delay = 2.277 ns ( 80.92 % )
            Info: - Longest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to source register is 2.805 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.220 ns) + CELL(0.537 ns) = 2.805 ns; Loc. = LCFF_X14_Y11_N23; Fanout = 4; REG Node = 'Sdram_Control_4Port:sdram0|ST[4]'
                Info: Total cell delay = 0.537 ns ( 19.14 % )
                Info: Total interconnect delay = 2.268 ns ( 80.86 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 4.939 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y11_N23; Fanout = 4; REG Node = 'Sdram_Control_4Port:sdram0|ST[4]'
        Info: 2: + IC(0.357 ns) + CELL(0.378 ns) = 0.735 ns; Loc. = LCCOMB_X14_Y11_N10; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram0|Equal5~103'
        Info: 3: + IC(0.270 ns) + CELL(0.438 ns) = 1.443 ns; Loc. = LCCOMB_X14_Y11_N16; Fanout = 5; COMB Node = 'Sdram_Control_4Port:sdram0|Equal5~104'
        Info: 4: + IC(0.286 ns) + CELL(0.438 ns) = 2.167 ns; Loc. = LCCOMB_X14_Y11_N26; Fanout = 6; COMB Node = 'Sdram_Control_4Port:sdram0|Equal5~105'
        Info: 5: + IC(0.758 ns) + CELL(0.275 ns) = 3.200 ns; Loc. = LCCOMB_X15_Y10_N8; Fanout = 3; COMB Node = 'Sdram_Control_4Port:sdram0|always3~5'
        Info: 6: + IC(0.263 ns) + CELL(0.420 ns) = 3.883 ns; Loc. = LCCOMB_X15_Y10_N14; Fanout = 15; COMB Node = 'Sdram_Control_4Port:sdram0|mADDR[8]~374'
        Info: 7: + IC(0.396 ns) + CELL(0.660 ns) = 4.939 ns; Loc. = LCFF_X14_Y10_N15; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram0|mADDR[16]'
        Info: Total cell delay = 2.609 ns ( 52.82 % )
        Info: Total interconnect delay = 2.330 ns ( 47.18 % )
Info: No valid register-to-register data paths exist for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk1"
Info: No valid register-to-register data paths exist for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk2"
Info: Slack time is 9.899 ns for clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" between source register "Binary:binary0|oDVAL" and destination register "Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]"
    Info: Fmax is 98.02 MHz (period= 10.202 ns)
    Info: + Largest register to register requirement is 14.797 ns
        Info: + Setup relationship between source and destination is 15.000 ns
            Info: + Latch edge is 12.392 ns
                Info: Clock period of Destination clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with inverted offset of 12.392 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is -2.608 ns
                Info: Clock period of Source clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with  offset of -2.608 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.011 ns
            Info: + Shortest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to destination register is 2.823 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 471; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.248 ns) + CELL(0.537 ns) = 2.823 ns; Loc. = LCFF_X18_Y21_N21; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]'
                Info: Total cell delay = 0.537 ns ( 19.02 % )
                Info: Total interconnect delay = 2.286 ns ( 80.98 % )
            Info: - Longest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to source register is 2.812 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 471; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.237 ns) + CELL(0.537 ns) = 2.812 ns; Loc. = LCFF_X39_Y21_N15; Fanout = 4; REG Node = 'Binary:binary0|oDVAL'
                Info: Total cell delay = 0.537 ns ( 19.10 % )
                Info: Total interconnect delay = 2.275 ns ( 80.90 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 4.898 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y21_N15; Fanout = 4; REG Node = 'Binary:binary0|oDVAL'
        Info: 2: + IC(2.514 ns) + CELL(0.275 ns) = 2.789 ns; Loc. = LCCOMB_X19_Y21_N16; Fanout = 22; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdcnt_addr_ena'
        Info: 3: + IC(0.474 ns) + CELL(0.414 ns) = 3.677 ns; Loc. = LCCOMB_X18_Y21_N0; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity~COUT'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 3.748 ns; Loc. = LCCOMB_X18_Y21_N2; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera0~COUT'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 3.819 ns; Loc. = LCCOMB_X18_Y21_N4; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera1~COUT'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 3.890 ns; Loc. = LCCOMB_X18_Y21_N6; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera2~COUT'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 3.961 ns; Loc. = LCCOMB_X18_Y21_N8; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera3~COUT'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 4.032 ns; Loc. = LCCOMB_X18_Y21_N10; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera4~COUT'
        Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 4.103 ns; Loc. = LCCOMB_X18_Y21_N12; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera5~COUT'
        Info: 10: + IC(0.000 ns) + CELL(0.159 ns) = 4.262 ns; Loc. = LCCOMB_X18_Y21_N14; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera6~COUT'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 4.333 ns; Loc. = LCCOMB_X18_Y21_N16; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera7~COUT'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 4.404 ns; Loc. = LCCOMB_X18_Y21_N18; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera8~COUT'
        Info: 13: + IC(0.000 ns) + CELL(0.410 ns) = 4.814 ns; Loc. = LCCOMB_X18_Y21_N20; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera9'
        Info: 14: + IC(0.000 ns) + CELL(0.084 ns) = 4.898 ns; Loc. = LCFF_X18_Y21_N21; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]'
        Info: Total cell delay = 1.910 ns ( 39.00 % )
        Info: Total interconnect delay = 2.988 ns ( 61.00 % )
Info: Slack time is 2.49 ns for clock "GPIO_CLKIN_N1" between source register "CCD_Capture:capture0|Y_Cont[3]" and destination register "RAW2RGB:raw0|rGreen[11]"
    Info: Fmax is 151.52 MHz (period= 6.6 ns)
    Info: + Largest register to register requirement is 8.866 ns
        Info: + Setup relationship between source and destination is 9.090 ns
            Info: + Latch edge is 9.090 ns
                Info: Clock period of Destination clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is -0.010 ns
            Info: + Shortest clock path from clock "GPIO_CLKIN_N1" to destination register is 2.848 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.208 ns) + CELL(0.537 ns) = 2.848 ns; Loc. = LCFF_X60_Y19_N7; Fanout = 1; REG Node = 'RAW2RGB:raw0|rGreen[11]'
                Info: Total cell delay = 1.526 ns ( 53.58 % )
                Info: Total interconnect delay = 1.322 ns ( 46.42 % )
            Info: - Longest clock path from clock "GPIO_CLKIN_N1" to source register is 2.858 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.218 ns) + CELL(0.537 ns) = 2.858 ns; Loc. = LCFF_X66_Y19_N7; Fanout = 4; REG Node = 'CCD_Capture:capture0|Y_Cont[3]'
                Info: Total cell delay = 1.526 ns ( 53.39 % )
                Info: Total interconnect delay = 1.332 ns ( 46.61 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 6.376 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X66_Y19_N7; Fanout = 4; REG Node = 'CCD_Capture:capture0|Y_Cont[3]'
        Info: 2: + IC(0.748 ns) + CELL(0.275 ns) = 1.023 ns; Loc. = LCCOMB_X65_Y19_N20; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Equal6~144'
        Info: 3: + IC(0.271 ns) + CELL(0.438 ns) = 1.732 ns; Loc. = LCCOMB_X65_Y19_N0; Fanout = 40; COMB Node = 'RAW2RGB:raw0|Equal6~148'
        Info: 4: + IC(1.088 ns) + CELL(0.437 ns) = 3.257 ns; Loc. = LCCOMB_X62_Y22_N14; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Add0~6183'
        Info: 5: + IC(0.256 ns) + CELL(0.245 ns) = 3.758 ns; Loc. = LCCOMB_X62_Y22_N2; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6184'
        Info: 6: + IC(0.775 ns) + CELL(0.414 ns) = 4.947 ns; Loc. = LCCOMB_X61_Y19_N16; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6224'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 5.018 ns; Loc. = LCCOMB_X61_Y19_N18; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6226'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 5.089 ns; Loc. = LCCOMB_X61_Y19_N20; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6228'
        Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 5.160 ns; Loc. = LCCOMB_X61_Y19_N22; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6230'
        Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 5.231 ns; Loc. = LCCOMB_X61_Y19_N24; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6237'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 5.302 ns; Loc. = LCCOMB_X61_Y19_N26; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6243'
        Info: 12: + IC(0.000 ns) + CELL(0.410 ns) = 5.712 ns; Loc. = LCCOMB_X61_Y19_N28; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Add0~6248'
        Info: 13: + IC(0.430 ns) + CELL(0.150 ns) = 6.292 ns; Loc. = LCCOMB_X60_Y19_N6; Fanout = 1; COMB Node = 'RAW2RGB:raw0|rGreen~679'
        Info: 14: + IC(0.000 ns) + CELL(0.084 ns) = 6.376 ns; Loc. = LCFF_X60_Y19_N7; Fanout = 1; REG Node = 'RAW2RGB:raw0|rGreen[11]'
        Info: Total cell delay = 2.808 ns ( 44.04 % )
        Info: Total interconnect delay = 3.568 ns ( 55.96 % )
Info: Slack time is 6.999 ns for clock "iCLK_50" between source register "lcd_3wire_config:lcd_config0|m3wire_data[11]" and destination register "lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA"
    Info: Fmax is 166.61 MHz (period= 6.002 ns)
    Info: + Largest register to register requirement is 9.786 ns
        Info: + Setup relationship between source and destination is 10.000 ns
            Info: + Latch edge is 10.000 ns
                Info: Clock period of Destination clock "iCLK_50" is 20.000 ns with inverted offset of 10.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "iCLK_50" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "iCLK_50" to destination register is 7.236 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(2.069 ns) + CELL(0.787 ns) = 3.815 ns; Loc. = LCFF_X69_Y27_N25; Fanout = 3; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK'
                Info: 3: + IC(1.627 ns) + CELL(0.000 ns) = 5.442 ns; Loc. = CLKCTRL_G4; Fanout = 37; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK~clkctrl'
                Info: 4: + IC(1.257 ns) + CELL(0.537 ns) = 7.236 ns; Loc. = LCFF_X90_Y29_N17; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA'
                Info: Total cell delay = 2.283 ns ( 31.55 % )
                Info: Total interconnect delay = 4.953 ns ( 68.45 % )
            Info: - Longest clock path from clock "iCLK_50" to source register is 7.236 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(2.069 ns) + CELL(0.787 ns) = 3.815 ns; Loc. = LCFF_X69_Y27_N25; Fanout = 3; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK'
                Info: 3: + IC(1.627 ns) + CELL(0.000 ns) = 5.442 ns; Loc. = CLKCTRL_G4; Fanout = 37; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK~clkctrl'
                Info: 4: + IC(1.257 ns) + CELL(0.537 ns) = 7.236 ns; Loc. = LCFF_X91_Y29_N29; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|m3wire_data[11]'
                Info: Total cell delay = 2.283 ns ( 31.55 % )
                Info: Total interconnect delay = 4.953 ns ( 68.45 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 2.787 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X91_Y29_N29; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|m3wire_data[11]'
        Info: 2: + IC(0.303 ns) + CELL(0.420 ns) = 0.723 ns; Loc. = LCCOMB_X91_Y29_N16; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~165'
        Info: 3: + IC(0.264 ns) + CELL(0.438 ns) = 1.425 ns; Loc. = LCCOMB_X91_Y29_N26; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~166'
        Info: 4: + IC(0.469 ns) + CELL(0.275 ns) = 2.169 ns; Loc. = LCCOMB_X90_Y29_N4; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~169'
        Info: 5: + IC(0.259 ns) + CELL(0.275 ns) = 2.703 ns; Loc. = LCCOMB_X90_Y29_N16; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~172'
        Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.787 ns; Loc. = LCFF_X90_Y29_N17; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA'
        Info: Total cell delay = 1.492 ns ( 53.53 % )
        Info: Total interconnect delay = 1.295 ns ( 46.47 % )
Info: No valid register-to-register data paths exist for clock "GPIO_CLKOUT_N1"
Info: No valid register-to-register data paths exist for clock "oDRAM0_CLK"
Info: No valid register-to-register data paths exist for clock "iCLK_50_3"
Info: No valid register-to-register data paths exist for clock "iCLK_50_2"
Info: Minimum slack time is 391 ps for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" between source register "Sdram_Control_4Port:sdram1|command:command1|do_rw" and destination register "Sdram_Control_4Port:sdram1|command:command1|do_rw"
    Info: + Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y18_N3; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X8_Y18_N2; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw~49'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X8_Y18_N3; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is -2.594 ns
                Info: Clock period of Destination clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is -2.594 ns
                Info: Clock period of Source clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to destination register is 2.792 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.207 ns) + CELL(0.537 ns) = 2.792 ns; Loc. = LCFF_X8_Y18_N3; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
                Info: Total cell delay = 0.537 ns ( 19.23 % )
                Info: Total interconnect delay = 2.255 ns ( 80.77 % )
            Info: - Shortest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to source register is 2.792 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.207 ns) + CELL(0.537 ns) = 2.792 ns; Loc. = LCFF_X8_Y18_N3; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
                Info: Total cell delay = 0.537 ns ( 19.23 % )
                Info: Total interconnect delay = 2.255 ns ( 80.77 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Info: Minimum slack time is 522 ps for clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" between source register "Dilation:dilation0|X6[9]" and destination register "Dilation:dilation0|X5[9]"
    Info: + Shortest register to register delay is 0.538 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y25_N29; Fanout = 2; REG Node = 'Dilation:dilation0|X6[9]'
        Info: 2: + IC(0.305 ns) + CELL(0.149 ns) = 0.454 ns; Loc. = LCCOMB_X38_Y25_N18; Fanout = 1; COMB Node = 'Dilation:dilation0|X5[9]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.538 ns; Loc. = LCFF_X38_Y25_N19; Fanout = 2; REG Node = 'Dilation:dilation0|X5[9]'
        Info: Total cell delay = 0.233 ns ( 43.31 % )
        Info: Total interconnect delay = 0.305 ns ( 56.69 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is -2.608 ns
                Info: Clock period of Destination clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with  offset of -2.608 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is -2.608 ns
                Info: Clock period of Source clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with  offset of -2.608 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to destination register is 2.822 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 471; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.247 ns) + CELL(0.537 ns) = 2.822 ns; Loc. = LCFF_X38_Y25_N19; Fanout = 2; REG Node = 'Dilation:dilation0|X5[9]'
                Info: Total cell delay = 0.537 ns ( 19.03 % )
                Info: Total interconnect delay = 2.285 ns ( 80.97 % )
            Info: - Shortest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to source register is 2.822 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 471; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.247 ns) + CELL(0.537 ns) = 2.822 ns; Loc. = LCFF_X38_Y25_N29; Fanout = 2; REG Node = 'Dilation:dilation0|X6[9]'
                Info: Total cell delay = 0.537 ns ( 19.03 % )
                Info: Total interconnect delay = 2.285 ns ( 80.97 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Info: Minimum slack time is 391 ps for clock "GPIO_CLKIN_N1" between source register "CCD_Capture:capture0|mCCD_FVAL" and destination register "CCD_Capture:capture0|mCCD_FVAL"
    Info: + Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y23_N1; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X24_Y23_N0; Fanout = 1; COMB Node = 'CCD_Capture:capture0|mCCD_FVAL~40'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X24_Y23_N1; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "GPIO_CLKIN_N1" to destination register is 2.880 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.240 ns) + CELL(0.537 ns) = 2.880 ns; Loc. = LCFF_X24_Y23_N1; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
                Info: Total cell delay = 1.526 ns ( 52.99 % )
                Info: Total interconnect delay = 1.354 ns ( 47.01 % )
            Info: - Shortest clock path from clock "GPIO_CLKIN_N1" to source register is 2.880 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.240 ns) + CELL(0.537 ns) = 2.880 ns; Loc. = LCFF_X24_Y23_N1; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
                Info: Total cell delay = 1.526 ns ( 52.99 % )
                Info: Total interconnect delay = 1.354 ns ( 47.01 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Info: Minimum slack time is 391 ps for clock "iCLK_50" between source register "rClk[0]" and destination register "rClk[0]"
    Info: + Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X94_Y3_N0; Fanout = 1; COMB Node = 'rClk[0]~3'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "iCLK_50" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "iCLK_50" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "iCLK_50" to destination register is 2.883 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(0.112 ns) + CELL(0.000 ns) = 1.071 ns; Loc. = CLKCTRL_G14; Fanout = 104; COMB Node = 'iCLK_50~clkctrl'
                Info: 3: + IC(1.275 ns) + CELL(0.537 ns) = 2.883 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
                Info: Total cell delay = 1.496 ns ( 51.89 % )
                Info: Total interconnect delay = 1.387 ns ( 48.11 % )
            Info: - Shortest clock path from clock "iCLK_50" to source register is 2.883 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(0.112 ns) + CELL(0.000 ns) = 1.071 ns; Loc. = CLKCTRL_G14; Fanout = 104; COMB Node = 'iCLK_50~clkctrl'
                Info: 3: + IC(1.275 ns) + CELL(0.537 ns) = 2.883 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
                Info: Total cell delay = 1.496 ns ( 51.89 % )
                Info: Total interconnect delay = 1.387 ns ( 48.11 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Warning: Can't achieve timing requirement tsu along 26 path(s). See Report window for details.
Info: Slack time is -330 ps for clock "iCLK_50_3" between source pin "DRAM_DQ[30]" and destination register "Sdram_Control_4Port:sdram1|mDATAOUT[14]"
    Info: + tsu requirement for source pin and destination register is 1.000 ns
    Info: - tsu from clock to input pin is 1.330 ns
        Info: + Longest pin to register delay is 1.229 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB1; Fanout = 1; PIN Node = 'DRAM_DQ[30]'
            Info: 2: + IC(0.000 ns) + CELL(1.229 ns) = 1.229 ns; Loc. = IOC_X0_Y14_N2; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|mDATAOUT[14]'
            Info: Total cell delay = 1.229 ns ( 100.00 % )
        Info: - Offset between input clock "iCLK_50_3" and output clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is -2.594 ns
        Info: + Micro setup delay of destination is 0.076 ns
        Info: - Shortest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to destination register is 2.569 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
            Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
            Info: 3: + IC(1.253 ns) + CELL(0.268 ns) = 2.569 ns; Loc. = IOC_X0_Y14_N2; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|mDATAOUT[14]'
            Info: Total cell delay = 0.268 ns ( 10.43 % )
            Info: Total interconnect delay = 2.301 ns ( 89.57 % )
Warning: Can't achieve timing requirement tco along 128 path(s). See Report window for details.
Info: Slack time is -4.997 ns for clock "iCLK_50_3" between source memory "Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12]" and destination pin "DRAM_DQ[28]"
    Info: + tco requirement for source memory and destination pin is 1.000 ns
    Info: - tco from clock to output pin is 5.997 ns
        Info: + Offset between input clock "iCLK_50_3" and output clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is -2.594 ns
        Info: + Longest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to source memory is 2.842 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
            Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
            Info: 3: + IC(1.159 ns) + CELL(0.635 ns) = 2.842 ns; Loc. = M4K_X17_Y19; Fanout = 1; MEM Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12]'
            Info: Total cell delay = 0.635 ns ( 22.34 % )
            Info: Total interconnect delay = 2.207 ns ( 77.66 % )
        Info: + Micro clock to output delay of source is 0.209 ns
        Info: + Longest memory to pin delay is 5.540 ns
            Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X17_Y19; Fanout = 1; MEM Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12]'
            Info: 2: + IC(0.722 ns) + CELL(0.438 ns) = 1.248 ns; Loc. = LCCOMB_X16_Y18_N28; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|mDATAIN[12]~172'
            Info: 3: + IC(1.640 ns) + CELL(2.652 ns) = 5.540 ns; Loc. = PIN_AA2; Fanout = 0; PIN Node = 'DRAM_DQ[28]'
            Info: Total cell delay = 3.178 ns ( 57.36 % )
            Info: Total interconnect delay = 2.362 ns ( 42.64 % )
Info: Longest tpd from source pin "iSW[17]" to destination pin "oLEDR[17]" is 10.818 ns
    Info: 1: + IC(0.000 ns) + CELL(0.812 ns) = 0.812 ns; Loc. = PIN_L8; Fanout = 3; PIN Node = 'iSW[17]'
    Info: 2: + IC(7.198 ns) + CELL(2.808 ns) = 10.818 ns; Loc. = PIN_AJ7; Fanout = 0; PIN Node = 'oLEDR[17]'
    Info: Total cell delay = 3.620 ns ( 33.46 % )
    Info: Total interconnect delay = 7.198 ns ( 66.54 % )
Info: th for register "Sdram_Control_4Port:sdram0|mDATAOUT[8]" (data pin = "DRAM_DQ[8]", clock pin = "iCLK_50_3") is -1.058 ns
    Info: + Offset between input clock "iCLK_50_3" and output clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is -2.594 ns
    Info: + Longest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to destination register is 2.667 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
        Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
        Info: 3: + IC(1.351 ns) + CELL(0.268 ns) = 2.667 ns; Loc. = IOC_X0_Y4_N2; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram0|mDATAOUT[8]'
        Info: Total cell delay = 0.268 ns ( 10.05 % )
        Info: Total interconnect delay = 2.399 ns ( 89.95 % )
    Info: + Micro hold delay of destination is 0.088 ns
    Info: - Shortest pin to register delay is 1.219 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AE3; Fanout = 1; PIN Node = 'DRAM_DQ[8]'
        Info: 2: + IC(0.000 ns) + CELL(1.219 ns) = 1.219 ns; Loc. = IOC_X0_Y4_N2; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram0|mDATAOUT[8]'
        Info: Total cell delay = 1.219 ns ( 100.00 % )
Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.
Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 8 warnings
    Info: Peak virtual memory: 145 megabytes
    Info: Processing ended: Mon Sep 29 16:08:28 2008
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:03


