Classic Timing Analyzer report for DE2_70
Sat Sep 27 16:44:24 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
  6. Clock Setup: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
  7. Clock Setup: 'GPIO_CLKIN_N1'
  8. Clock Setup: 'iCLK_50'
  9. Clock Hold: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
 10. Clock Hold: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
 11. Clock Hold: 'GPIO_CLKIN_N1'
 12. Clock Hold: 'iCLK_50'
 13. tsu
 14. tco
 15. tpd
 16. th
 17. Ignored Timing Assignments
 18. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



 
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
 
; Type                                                              ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                             ; To                                                                                                                                             ; From Clock                                         ; To Clock                                           ; Failed Paths ;
 
; Worst-case tsu                                                    ; -0.330 ns ; 1.000 ns                         ; 1.330 ns                         ; DRAM_DQ[30]                                                                                                                                                      ; Sdram_Control_4Port:sdram1|mDATAOUT[14]                                                                                                        ; --                                                 ; iCLK_50_3                                          ; 26           ;
; Worst-case tco                                                    ; -5.033 ns ; 1.000 ns                         ; 6.033 ns                         ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3] ; DRAM_DQ[19]                                                                                                                                    ; iCLK_50_3                                          ; --                                                 ; 128          ;
; Worst-case tpd                                                    ; N/A       ; None                             ; 11.343 ns                        ; iSW[14]                                                                                                                                                          ; oLEDR[14]                                                                                                                                      ; --                                                 ; --                                                 ; 0            ;
; Worst-case th                                                     ; N/A       ; None                             ; -0.986 ns                        ; iSW[17]                                                                                                                                                          ; RAW2RGB:raw0|mirror_sw                                                                                                                         ; --                                                 ; iCLK_50                                            ; 0            ;
; Clock Setup: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0' ; 0.938 ns  ; 166.67 MHz ( period = 6.000 ns ) ; 197.55 MHz ( period = 5.062 ns ) ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                                ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'GPIO_CLKIN_N1'                                      ; 2.171 ns  ; 110.01 MHz ( period = 9.090 ns ) ; 144.53 MHz ( period = 6.919 ns ) ; CCD_Capture:capture0|Y_Cont[7]                                                                                                                                   ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1                                      ; GPIO_CLKIN_N1                                      ; 0            ;
; Clock Setup: 'iCLK_50'                                            ; 6.848 ns  ; 50.00 MHz ( period = 20.000 ns ) ; 158.63 MHz ( period = 6.304 ns ) ; lcd_3wire_config:lcd_config0|m3wire_data[14]                                                                                                                     ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA                                                                                          ; iCLK_50                                            ; iCLK_50                                            ; 0            ;
; Clock Setup: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'     ; 9.736 ns  ; 33.33 MHz ( period = 30.000 ns ) ; 94.98 MHz ( period = 10.528 ns ) ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; 0            ;
; Clock Hold: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'  ; 0.391 ns  ; 166.67 MHz ( period = 6.000 ns ) ; N/A                              ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                                ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'GPIO_CLKIN_N1'                                       ; 0.391 ns  ; 110.01 MHz ( period = 9.090 ns ) ; N/A                              ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                                   ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                 ; GPIO_CLKIN_N1                                      ; GPIO_CLKIN_N1                                      ; 0            ;
; Clock Hold: 'iCLK_50'                                             ; 0.391 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; rClk[0]                                                                                                                                                          ; rClk[0]                                                                                                                                        ; iCLK_50                                            ; iCLK_50                                            ; 0            ;
; Clock Hold: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'      ; 0.528 ns  ; 33.33 MHz ( period = 30.000 ns ) ; N/A                              ; touch_tcon:vga0|mvd                                                                                                                                              ; touch_tcon:vga0|oVD                                                                                                                            ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ; 0            ;
; Total number of failed paths                                      ;           ;                                  ;                                  ;                                                                                                                                                                  ;                                                                                                                                                ;                                                    ;                                                    ; 154          ;
 


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                             ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
; Option                                                              ; Setting            ; From            ; To                        ; Entity Name ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
; Device Name                                                         ; EP2C70F896C6       ;                 ;                           ;             ;
; Timing Models                                                       ; Final              ;                 ;                           ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;                 ;                           ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;                 ;                           ;             ;
; Cut off read during write signal paths                              ; On                 ;                 ;                           ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;                 ;                           ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;                 ;                           ;             ;
; Ignore Clock Settings                                               ; Off                ;                 ;                           ;             ;
; Analyze latches as synchronous elements                             ; On                 ;                 ;                           ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;                 ;                           ;             ;
; Enable Clock Latency                                                ; Off                ;                 ;                           ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;                 ;                           ;             ;
; Number of source nodes to report per destination node               ; 10                 ;                 ;                           ;             ;
; Number of destination nodes to report                               ; 10                 ;                 ;                           ;             ;
; Number of paths to report                                           ; 200                ;                 ;                           ;             ;
; Report Minimum Timing Checks                                        ; Off                ;                 ;                           ;             ;
; Use Fast Timing Models                                              ; Off                ;                 ;                           ;             ;
; Report IO Paths Separately                                          ; Off                ;                 ;                           ;             ;
; Perform Multicorner Analysis                                        ; On                 ;                 ;                           ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;                 ;                           ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;                 ;                           ;             ;
; tsu Requirement                                                     ; 5 ns               ; *               ; rCCD_DATA                 ;             ;
; tsu Requirement                                                     ; 5 ns               ; *               ; rCCD_FVAL                 ;             ;
; tsu Requirement                                                     ; 5 ns               ; *               ; rCCD_LVAL                 ;             ;
; tsu Requirement                                                     ; 1 ns               ; DRAM_DQ         ; *                         ;             ;
; tco Requirement                                                     ; 1 ns               ; *               ; DRAM_DQ                   ;             ;
; Clock Settings                                                      ; CCD_PIXCLK         ;                 ; GPIO_CLKIN_N1             ;             ;
; Clock Settings                                                      ; CCD_MCLK           ;                 ; GPIO_CLKOUT_N1            ;             ;
; Clock Settings                                                      ; CLK50              ;                 ; iCLK_50                   ;             ;
; Clock Settings                                                      ; DRAM0_CLK          ;                 ; oDRAM0_CLK                ;             ;
; Cut Timing Path                                                     ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe9|dffe10a  ; dcfifo_m2o1 ;
; Cut Timing Path                                                     ; On                 ; rdptr_g         ; ws_dgrp|dffpipe11|dffe12a ; dcfifo_m2o1 ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                         ;
+----------------------------------------------------+--------------------+---------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                    ; Clock Setting Name ; Type          ; Fmax Requirement ; Early Latency ; Late Latency ; Based on  ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+----------------------------------------------------+--------------------+---------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+
; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ;                    ; PLL output    ; 166.67 MHz       ; 0.000 ns      ; 0.000 ns     ; iCLK_50_3 ; 10                    ; 3                   ; -2.594 ns ;              ;
; sdram_pll:sdram_pll0|altpll:altpll_component|_clk1 ;                    ; PLL output    ; 166.67 MHz       ; 0.000 ns      ; 0.000 ns     ; iCLK_50_3 ; 10                    ; 3                   ; -4.094 ns ;              ;
; sdram_pll:sdram_pll0|altpll:altpll_component|_clk2 ;                    ; PLL output    ; 166.67 MHz       ; 0.000 ns      ; 0.000 ns     ; iCLK_50_3 ; 10                    ; 3                   ; -4.094 ns ;              ;
; vga_pll:vga_pll0|altpll:altpll_component|_clk0     ;                    ; PLL output    ; 33.33 MHz        ; 0.000 ns      ; 0.000 ns     ; iCLK_50_2 ; 2                     ; 3                   ; -2.608 ns ;              ;
; GPIO_CLKIN_N1                                      ; CCD_PIXCLK         ; User Pin      ; 110.01 MHz       ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; iCLK_50                                            ; CLK50              ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_CLKOUT_N1                                     ; CCD_MCLK           ; User Pin      ; 96.01 MHz        ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; oDRAM0_CLK                                         ; DRAM0_CLK          ; Internal Node ; 150.02 MHz       ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; iCLK_50_3                                          ;                    ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
; iCLK_50_2                                          ;                    ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --        ; N/A                   ; N/A                 ; N/A       ;              ;
+----------------------------------------------------+--------------------+---------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+


 
; Clock Setup: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
 
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                            ; To                                                                                                                                              ; From Clock                                         ; To Clock                                           ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
 
; 0.938 ns                                ; 197.55 MHz ( period = 5.062 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.869 ns                ;
; 0.938 ns                                ; 197.55 MHz ( period = 5.062 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.869 ns                ;
; 0.938 ns                                ; 197.55 MHz ( period = 5.062 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.869 ns                ;
; 1.051 ns                                ; 202.06 MHz ( period = 4.949 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.756 ns                ;
; 1.051 ns                                ; 202.06 MHz ( period = 4.949 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.756 ns                ;
; 1.051 ns                                ; 202.06 MHz ( period = 4.949 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.756 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.104 ns                                ; 204.25 MHz ( period = 4.896 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.701 ns                ;
; 1.126 ns                                ; 205.17 MHz ( period = 4.874 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.681 ns                ;
; 1.126 ns                                ; 205.17 MHz ( period = 4.874 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.681 ns                ;
; 1.126 ns                                ; 205.17 MHz ( period = 4.874 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.681 ns                ;
; 1.154 ns                                ; 206.36 MHz ( period = 4.846 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.634 ns                ;
; 1.159 ns                                ; 206.57 MHz ( period = 4.841 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.648 ns                ;
; 1.159 ns                                ; 206.57 MHz ( period = 4.841 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.648 ns                ;
; 1.159 ns                                ; 206.57 MHz ( period = 4.841 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.648 ns                ;
; 1.196 ns                                ; 208.16 MHz ( period = 4.804 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.611 ns                ;
; 1.196 ns                                ; 208.16 MHz ( period = 4.804 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.611 ns                ;
; 1.196 ns                                ; 208.16 MHz ( period = 4.804 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.611 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.217 ns                                ; 209.07 MHz ( period = 4.783 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.588 ns                ;
; 1.219 ns                                ; 209.16 MHz ( period = 4.781 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.569 ns                ;
; 1.225 ns                                ; 209.42 MHz ( period = 4.775 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.563 ns                ;
; 1.276 ns                                ; 211.69 MHz ( period = 4.724 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.531 ns                ;
; 1.276 ns                                ; 211.69 MHz ( period = 4.724 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.531 ns                ;
; 1.276 ns                                ; 211.69 MHz ( period = 4.724 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.531 ns                ;
; 1.280 ns                                ; 211.86 MHz ( period = 4.720 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.510 ns                ;
; 1.287 ns                                ; 212.18 MHz ( period = 4.713 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.503 ns                ;
; 1.290 ns                                ; 212.31 MHz ( period = 4.710 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.498 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.292 ns                                ; 212.40 MHz ( period = 4.708 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.513 ns                ;
; 1.294 ns                                ; 212.49 MHz ( period = 4.706 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.494 ns                ;
; 1.296 ns                                ; 212.59 MHz ( period = 4.704 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.492 ns                ;
; 1.300 ns                                ; 212.77 MHz ( period = 4.700 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.488 ns                ;
; 1.302 ns                                ; 212.86 MHz ( period = 4.698 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.505 ns                ;
; 1.302 ns                                ; 212.86 MHz ( period = 4.698 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.505 ns                ;
; 1.302 ns                                ; 212.86 MHz ( period = 4.698 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.505 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.325 ns                                ; 213.90 MHz ( period = 4.675 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.480 ns                ;
; 1.332 ns                                ; 214.22 MHz ( period = 4.668 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.770 ns                  ; 4.438 ns                ;
; 1.332 ns                                ; 214.22 MHz ( period = 4.668 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.770 ns                  ; 4.438 ns                ;
; 1.338 ns                                ; 214.50 MHz ( period = 4.662 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.469 ns                ;
; 1.338 ns                                ; 214.50 MHz ( period = 4.662 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.469 ns                ;
; 1.338 ns                                ; 214.50 MHz ( period = 4.662 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.469 ns                ;
; 1.341 ns                                ; 214.64 MHz ( period = 4.659 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.447 ns                ;
; 1.345 ns                                ; 214.82 MHz ( period = 4.655 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.830 ns                  ; 4.485 ns                ;
; 1.345 ns                                ; 214.82 MHz ( period = 4.655 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.830 ns                  ; 4.485 ns                ;
; 1.351 ns                                ; 215.10 MHz ( period = 4.649 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.439 ns                ;
; 1.351 ns                                ; 215.10 MHz ( period = 4.649 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.437 ns                ;
; 1.354 ns                                ; 215.24 MHz ( period = 4.646 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.770 ns                  ; 4.416 ns                ;
; 1.354 ns                                ; 215.24 MHz ( period = 4.646 ns )                    ; Sdram_Control_4Port:sdram0|ST[6]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.770 ns                  ; 4.416 ns                ;
; 1.358 ns                                ; 215.42 MHz ( period = 4.642 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.432 ns                ;
; 1.361 ns                                ; 215.56 MHz ( period = 4.639 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.427 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.362 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[1]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.443 ns                ;
; 1.363 ns                                ; 215.66 MHz ( period = 4.637 ns )                    ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|ST[8]                                                                                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.763 ns                  ; 4.400 ns                ;
; 1.365 ns                                ; 215.75 MHz ( period = 4.635 ns )                    ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|ST[7]                                                                                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.763 ns                  ; 4.398 ns                ;
; 1.365 ns                                ; 215.75 MHz ( period = 4.635 ns )                    ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|ST[4]                                                                                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.763 ns                  ; 4.398 ns                ;
; 1.365 ns                                ; 215.75 MHz ( period = 4.635 ns )                    ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|ST[3]                                                                                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.763 ns                  ; 4.398 ns                ;
; 1.365 ns                                ; 215.75 MHz ( period = 4.635 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.423 ns                ;
; 1.367 ns                                ; 215.84 MHz ( period = 4.633 ns )                    ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|ST[5]                                                                                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.763 ns                  ; 4.396 ns                ;
; 1.367 ns                                ; 215.84 MHz ( period = 4.633 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.421 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|ST[9]                                                                                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.763 ns                  ; 4.395 ns                ;
; 1.368 ns                                ; 215.89 MHz ( period = 4.632 ns )                    ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|ST[2]                                                                                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.763 ns                  ; 4.395 ns                ;
; 1.369 ns                                ; 215.94 MHz ( period = 4.631 ns )                    ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|ST[6]                                                                                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.763 ns                  ; 4.394 ns                ;
; 1.371 ns                                ; 216.03 MHz ( period = 4.629 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.417 ns                ;
; 1.372 ns                                ; 216.08 MHz ( period = 4.628 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[4]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.435 ns                ;
; 1.372 ns                                ; 216.08 MHz ( period = 4.628 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[4]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.435 ns                ;
; 1.372 ns                                ; 216.08 MHz ( period = 4.628 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[4]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.435 ns                ;
; 1.400 ns                                ; 217.39 MHz ( period = 4.600 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                               ; Sdram_Control_4Port:sdram1|RD_MASK[0]                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.787 ns                  ; 4.387 ns                ;
; 1.405 ns                                ; 217.63 MHz ( period = 4.595 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[4]                               ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.402 ns                ;
; 1.405 ns                                ; 217.63 MHz ( period = 4.595 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[4]                               ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.402 ns                ;
; 1.405 ns                                ; 217.63 MHz ( period = 4.595 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[4]                               ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.807 ns                  ; 4.402 ns                ;
; 1.412 ns                                ; 217.96 MHz ( period = 4.588 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.376 ns                ;
; 1.422 ns                                ; 218.44 MHz ( period = 4.578 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.368 ns                ;
; 1.422 ns                                ; 218.44 MHz ( period = 4.578 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.366 ns                ;
; 1.429 ns                                ; 218.77 MHz ( period = 4.571 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.361 ns                ;
; 1.432 ns                                ; 218.91 MHz ( period = 4.568 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.356 ns                ;
; 1.434 ns                                ; 219.01 MHz ( period = 4.566 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.356 ns                ;
; 1.435 ns                                ; 219.06 MHz ( period = 4.565 ns )                    ; Sdram_Control_4Port:sdram1|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.370 ns                ;
; 1.435 ns                                ; 219.06 MHz ( period = 4.565 ns )                    ; Sdram_Control_4Port:sdram1|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.370 ns                ;
; 1.435 ns                                ; 219.06 MHz ( period = 4.565 ns )                    ; Sdram_Control_4Port:sdram1|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram1|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.370 ns                ;
; 1.436 ns                                ; 219.11 MHz ( period = 4.564 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.352 ns                ;
; 1.438 ns                                ; 219.20 MHz ( period = 4.562 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.350 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.363 ns                ;
; 1.442 ns                                ; 219.39 MHz ( period = 4.558 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.346 ns                ;
; 1.446 ns                                ; 219.59 MHz ( period = 4.554 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.342 ns                ;
; 1.466 ns                                ; 220.56 MHz ( period = 4.534 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.770 ns                  ; 4.304 ns                ;
; 1.466 ns                                ; 220.56 MHz ( period = 4.534 ns )                    ; Sdram_Control_4Port:sdram0|ST[9]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[14]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.770 ns                  ; 4.304 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.468 ns                                ; 220.65 MHz ( period = 4.532 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.337 ns                ;
; 1.474 ns                                ; 220.95 MHz ( period = 4.526 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.314 ns                ;
; 1.483 ns                                ; 221.39 MHz ( period = 4.517 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.305 ns                ;
; 1.493 ns                                ; 221.88 MHz ( period = 4.507 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.297 ns                ;
; 1.493 ns                                ; 221.88 MHz ( period = 4.507 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.295 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[21]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[20]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[22]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[18]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[13]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[12]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[11]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[10]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[9]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.495 ns                                ; 221.98 MHz ( period = 4.505 ns )                    ; Sdram_Control_4Port:sdram0|ST[7]                                                                                                                                ; Sdram_Control_4Port:sdram0|mADDR[8]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.771 ns                  ; 4.276 ns                ;
; 1.500 ns                                ; 222.22 MHz ( period = 4.500 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.290 ns                ;
; 1.503 ns                                ; 222.37 MHz ( period = 4.497 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.285 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[20]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[22]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[18]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[17]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[16]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[15]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[13]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[12]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[11]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[10]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.504 ns                                ; 222.42 MHz ( period = 4.496 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp|dffe10a[3]                               ; Sdram_Control_4Port:sdram1|mADDR[8]                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.805 ns                  ; 4.301 ns                ;
; 1.505 ns                                ; 222.47 MHz ( period = 4.495 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.790 ns                  ; 4.285 ns                ;
; 1.507 ns                                ; 222.57 MHz ( period = 4.493 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.788 ns                  ; 4.281 ns                ;
; 1.508 ns                                ; 222.62 MHz ( period = 4.492 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[21]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.831 ns                  ; 4.323 ns                ;
; 1.508 ns                                ; 222.62 MHz ( period = 4.492 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[20]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.831 ns                  ; 4.323 ns                ;
; 1.508 ns                                ; 222.62 MHz ( period = 4.492 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[22]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.831 ns                  ; 4.323 ns                ;
; 1.508 ns                                ; 222.62 MHz ( period = 4.492 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.831 ns                  ; 4.323 ns                ;
; 1.508 ns                                ; 222.62 MHz ( period = 4.492 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[18]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.831 ns                  ; 4.323 ns                ;
; 1.508 ns                                ; 222.62 MHz ( period = 4.492 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                               ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 6.000 ns                    ; 5.831 ns                  ; 4.323 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                 ;                                                                                                                                                 ;                                                    ;                                                    ;                             ;                           ;                         ;
 


 
; Clock Setup: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
 
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                             ; To                                                                                                                                                                                       ; From Clock                                     ; To Clock                                       ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
 
; 9.736 ns                                ; 94.98 MHz ( period = 10.528 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 5.129 ns                ;
; 9.807 ns                                ; 96.28 MHz ( period = 10.386 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 5.058 ns                ;
; 9.878 ns                                ; 97.62 MHz ( period = 10.244 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 4.987 ns                ;
; 9.949 ns                                ; 98.99 MHz ( period = 10.102 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 4.916 ns                ;
; 10.020 ns                               ; 100.40 MHz ( period = 9.960 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 4.845 ns                ;
; 10.091 ns                               ; 101.85 MHz ( period = 9.818 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 4.774 ns                ;
; 10.162 ns                               ; 103.35 MHz ( period = 9.676 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 4.703 ns                ;
; 10.321 ns                               ; 106.86 MHz ( period = 9.358 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 4.544 ns                ;
; 10.392 ns                               ; 108.51 MHz ( period = 9.216 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 4.473 ns                ;
; 10.463 ns                               ; 110.20 MHz ( period = 9.074 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 4.402 ns                ;
; 10.850 ns                               ; 120.48 MHz ( period = 8.300 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 4.015 ns                ;
; 10.917 ns                               ; 122.46 MHz ( period = 8.166 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 3.821 ns                ;
; 11.007 ns                               ; 125.22 MHz ( period = 7.986 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.806 ns                 ; 3.799 ns                ;
; 11.007 ns                               ; 125.22 MHz ( period = 7.986 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.806 ns                 ; 3.799 ns                ;
; 11.007 ns                               ; 125.22 MHz ( period = 7.986 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.806 ns                 ; 3.799 ns                ;
; 11.007 ns                               ; 125.22 MHz ( period = 7.986 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.806 ns                 ; 3.799 ns                ;
; 11.007 ns                               ; 125.22 MHz ( period = 7.986 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.806 ns                 ; 3.799 ns                ;
; 11.007 ns                               ; 125.22 MHz ( period = 7.986 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.806 ns                 ; 3.799 ns                ;
; 11.007 ns                               ; 125.22 MHz ( period = 7.986 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.806 ns                 ; 3.799 ns                ;
; 11.007 ns                               ; 125.22 MHz ( period = 7.986 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.806 ns                 ; 3.799 ns                ;
; 11.007 ns                               ; 125.22 MHz ( period = 7.986 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.806 ns                 ; 3.799 ns                ;
; 11.052 ns                               ; 126.65 MHz ( period = 7.896 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.730 ns                 ; 3.678 ns                ;
; 11.114 ns                               ; 128.67 MHz ( period = 7.772 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.832 ns                 ; 3.718 ns                ;
; 11.114 ns                               ; 128.67 MHz ( period = 7.772 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.832 ns                 ; 3.718 ns                ;
; 11.114 ns                               ; 128.67 MHz ( period = 7.772 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.832 ns                 ; 3.718 ns                ;
; 11.114 ns                               ; 128.67 MHz ( period = 7.772 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.832 ns                 ; 3.718 ns                ;
; 11.114 ns                               ; 128.67 MHz ( period = 7.772 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.832 ns                 ; 3.718 ns                ;
; 11.114 ns                               ; 128.67 MHz ( period = 7.772 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.832 ns                 ; 3.718 ns                ;
; 11.114 ns                               ; 128.67 MHz ( period = 7.772 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.832 ns                 ; 3.718 ns                ;
; 11.114 ns                               ; 128.67 MHz ( period = 7.772 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.832 ns                 ; 3.718 ns                ;
; 11.114 ns                               ; 128.67 MHz ( period = 7.772 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.832 ns                 ; 3.718 ns                ;
; 11.134 ns                               ; 129.33 MHz ( period = 7.732 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 3.604 ns                ;
; 11.141 ns                               ; 129.57 MHz ( period = 7.718 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 3.639 ns                ;
; 11.149 ns                               ; 129.84 MHz ( period = 7.702 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.840 ns                 ; 3.691 ns                ;
; 11.149 ns                               ; 129.84 MHz ( period = 7.702 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.840 ns                 ; 3.691 ns                ;
; 11.149 ns                               ; 129.84 MHz ( period = 7.702 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.840 ns                 ; 3.691 ns                ;
; 11.149 ns                               ; 129.84 MHz ( period = 7.702 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.840 ns                 ; 3.691 ns                ;
; 11.149 ns                               ; 129.84 MHz ( period = 7.702 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.840 ns                 ; 3.691 ns                ;
; 11.149 ns                               ; 129.84 MHz ( period = 7.702 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.840 ns                 ; 3.691 ns                ;
; 11.149 ns                               ; 129.84 MHz ( period = 7.702 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.840 ns                 ; 3.691 ns                ;
; 11.149 ns                               ; 129.84 MHz ( period = 7.702 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.840 ns                 ; 3.691 ns                ;
; 11.149 ns                               ; 129.84 MHz ( period = 7.702 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.840 ns                 ; 3.691 ns                ;
; 11.155 ns                               ; 130.04 MHz ( period = 7.690 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.730 ns                 ; 3.575 ns                ;
; 11.212 ns                               ; 132.00 MHz ( period = 7.576 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 3.568 ns                ;
; 11.283 ns                               ; 134.52 MHz ( period = 7.434 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 3.497 ns                ;
; 11.317 ns                               ; 135.76 MHz ( period = 7.366 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.814 ns                 ; 3.497 ns                ;
; 11.317 ns                               ; 135.76 MHz ( period = 7.366 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.814 ns                 ; 3.497 ns                ;
; 11.317 ns                               ; 135.76 MHz ( period = 7.366 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.814 ns                 ; 3.497 ns                ;
; 11.317 ns                               ; 135.76 MHz ( period = 7.366 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.814 ns                 ; 3.497 ns                ;
; 11.442 ns                               ; 140.53 MHz ( period = 7.116 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 3.338 ns                ;
; 11.457 ns                               ; 141.12 MHz ( period = 7.086 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; touch_tcon:vga0|oLCD_R[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.739 ns                 ; 3.282 ns                ;
; 11.461 ns                               ; 141.28 MHz ( period = 7.078 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; touch_tcon:vga0|oLCD_B[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.739 ns                 ; 3.278 ns                ;
; 11.464 ns                               ; 141.40 MHz ( period = 7.072 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; touch_tcon:vga0|oLCD_G[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.739 ns                 ; 3.275 ns                ;
; 11.480 ns                               ; 142.05 MHz ( period = 7.040 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 3.258 ns                ;
; 11.513 ns                               ; 143.39 MHz ( period = 6.974 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 3.267 ns                ;
; 11.575 ns                               ; 145.99 MHz ( period = 6.850 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.757 ns                 ; 3.182 ns                ;
; 11.575 ns                               ; 145.99 MHz ( period = 6.850 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.757 ns                 ; 3.182 ns                ;
; 11.575 ns                               ; 145.99 MHz ( period = 6.850 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.757 ns                 ; 3.182 ns                ;
; 11.575 ns                               ; 145.99 MHz ( period = 6.850 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.757 ns                 ; 3.182 ns                ;
; 11.578 ns                               ; 146.11 MHz ( period = 6.844 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_B[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.153 ns                ;
; 11.581 ns                               ; 146.24 MHz ( period = 6.838 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_R[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.150 ns                ;
; 11.584 ns                               ; 146.37 MHz ( period = 6.832 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 3.196 ns                ;
; 11.585 ns                               ; 146.41 MHz ( period = 6.830 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_G[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.146 ns                ;
; 11.599 ns                               ; 147.02 MHz ( period = 6.802 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_B[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.132 ns                ;
; 11.602 ns                               ; 147.15 MHz ( period = 6.796 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_R[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.129 ns                ;
; 11.611 ns                               ; 147.54 MHz ( period = 6.778 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_G[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.120 ns                ;
; 11.625 ns                               ; 148.15 MHz ( period = 6.750 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; touch_tcon:vga0|oLCD_G[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 3.113 ns                ;
; 11.634 ns                               ; 148.54 MHz ( period = 6.732 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; touch_tcon:vga0|oLCD_B[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 3.104 ns                ;
; 11.653 ns                               ; 149.39 MHz ( period = 6.694 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; touch_tcon:vga0|oLCD_B[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 3.085 ns                ;
; 11.655 ns                               ; 149.48 MHz ( period = 6.690 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 3.125 ns                ;
; 11.657 ns                               ; 149.57 MHz ( period = 6.686 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_R[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 3.081 ns                ;
; 11.659 ns                               ; 149.66 MHz ( period = 6.682 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_B[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 3.079 ns                ;
; 11.668 ns                               ; 150.06 MHz ( period = 6.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.794 ns                 ; 3.126 ns                ;
; 11.668 ns                               ; 150.06 MHz ( period = 6.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.794 ns                 ; 3.126 ns                ;
; 11.668 ns                               ; 150.06 MHz ( period = 6.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.794 ns                 ; 3.126 ns                ;
; 11.668 ns                               ; 150.06 MHz ( period = 6.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.794 ns                 ; 3.126 ns                ;
; 11.668 ns                               ; 150.06 MHz ( period = 6.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.794 ns                 ; 3.126 ns                ;
; 11.668 ns                               ; 150.06 MHz ( period = 6.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.794 ns                 ; 3.126 ns                ;
; 11.668 ns                               ; 150.06 MHz ( period = 6.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.794 ns                 ; 3.126 ns                ;
; 11.668 ns                               ; 150.06 MHz ( period = 6.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.794 ns                 ; 3.126 ns                ;
; 11.668 ns                               ; 150.06 MHz ( period = 6.664 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.794 ns                 ; 3.126 ns                ;
; 11.681 ns                               ; 150.65 MHz ( period = 6.638 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.801 ns                 ; 3.120 ns                ;
; 11.687 ns                               ; 150.92 MHz ( period = 6.626 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; touch_tcon:vga0|oLCD_B[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 3.044 ns                ;
; 11.699 ns                               ; 151.47 MHz ( period = 6.602 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_G[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 3.039 ns                ;
; 11.726 ns                               ; 152.72 MHz ( period = 6.548 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 3.054 ns                ;
; 11.791 ns                               ; 155.81 MHz ( period = 6.418 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; touch_tcon:vga0|oLCD_B[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 2.947 ns                ;
; 11.792 ns                               ; 155.86 MHz ( period = 6.416 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; touch_tcon:vga0|oLCD_R[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 2.946 ns                ;
; 11.797 ns                               ; 156.10 MHz ( period = 6.406 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 2.983 ns                ;
; 11.802 ns                               ; 156.35 MHz ( period = 6.396 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 3.063 ns                ;
; 11.802 ns                               ; 156.35 MHz ( period = 6.396 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.865 ns                 ; 3.063 ns                ;
; 11.838 ns                               ; 158.13 MHz ( period = 6.324 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.904 ns                ;
; 11.838 ns                               ; 158.13 MHz ( period = 6.324 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.904 ns                ;
; 11.838 ns                               ; 158.13 MHz ( period = 6.324 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12]                         ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.904 ns                ;
; 11.838 ns                               ; 158.13 MHz ( period = 6.324 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.904 ns                ;
; 11.838 ns                               ; 158.13 MHz ( period = 6.324 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.904 ns                ;
; 11.838 ns                               ; 158.13 MHz ( period = 6.324 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.904 ns                ;
; 11.838 ns                               ; 158.13 MHz ( period = 6.324 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.904 ns                ;
; 11.838 ns                               ; 158.13 MHz ( period = 6.324 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.904 ns                ;
; 11.838 ns                               ; 158.13 MHz ( period = 6.324 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]                          ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.742 ns                 ; 2.904 ns                ;
; 11.849 ns                               ; 158.68 MHz ( period = 6.302 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; touch_tcon:vga0|oLCD_B[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 2.889 ns                ;
; 11.868 ns                               ; 159.64 MHz ( period = 6.264 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 2.912 ns                ;
; 11.936 ns                               ; 163.19 MHz ( period = 6.128 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.864 ns                 ; 2.928 ns                ;
; 11.936 ns                               ; 163.19 MHz ( period = 6.128 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.864 ns                 ; 2.928 ns                ;
; 11.936 ns                               ; 163.19 MHz ( period = 6.128 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.864 ns                 ; 2.928 ns                ;
; 11.936 ns                               ; 163.19 MHz ( period = 6.128 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.864 ns                 ; 2.928 ns                ;
; 11.936 ns                               ; 163.19 MHz ( period = 6.128 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.864 ns                 ; 2.928 ns                ;
; 11.936 ns                               ; 163.19 MHz ( period = 6.128 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.864 ns                 ; 2.928 ns                ;
; 11.936 ns                               ; 163.19 MHz ( period = 6.128 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.864 ns                 ; 2.928 ns                ;
; 11.936 ns                               ; 163.19 MHz ( period = 6.128 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.864 ns                 ; 2.928 ns                ;
; 11.937 ns                               ; 163.24 MHz ( period = 6.126 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; touch_tcon:vga0|oLCD_B[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.739 ns                 ; 2.802 ns                ;
; 11.989 ns                               ; 166.06 MHz ( period = 6.022 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.783 ns                 ; 2.794 ns                ;
; 11.989 ns                               ; 166.06 MHz ( period = 6.022 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.783 ns                 ; 2.794 ns                ;
; 11.989 ns                               ; 166.06 MHz ( period = 6.022 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.783 ns                 ; 2.794 ns                ;
; 11.989 ns                               ; 166.06 MHz ( period = 6.022 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.783 ns                 ; 2.794 ns                ;
; 11.989 ns                               ; 166.06 MHz ( period = 6.022 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.783 ns                 ; 2.794 ns                ;
; 11.989 ns                               ; 166.06 MHz ( period = 6.022 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.783 ns                 ; 2.794 ns                ;
; 11.989 ns                               ; 166.06 MHz ( period = 6.022 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.783 ns                 ; 2.794 ns                ;
; 11.989 ns                               ; 166.06 MHz ( period = 6.022 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.783 ns                 ; 2.794 ns                ;
; 11.989 ns                               ; 166.06 MHz ( period = 6.022 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.783 ns                 ; 2.794 ns                ;
; 12.119 ns                               ; 173.55 MHz ( period = 5.762 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.787 ns                 ; 2.668 ns                ;
; 12.119 ns                               ; 173.55 MHz ( period = 5.762 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; touch_tcon:vga0|oLCD_B[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.739 ns                 ; 2.620 ns                ;
; 12.146 ns                               ; 175.19 MHz ( period = 5.708 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; touch_tcon:vga0|oLCD_B[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.738 ns                 ; 2.592 ns                ;
; 12.156 ns                               ; 175.81 MHz ( period = 5.688 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.787 ns                 ; 2.631 ns                ;
; 12.255 ns                               ; 182.15 MHz ( period = 5.490 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.780 ns                 ; 2.525 ns                ;
; 12.263 ns                               ; 182.68 MHz ( period = 5.474 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 2.505 ns                ;
; 12.263 ns                               ; 182.68 MHz ( period = 5.474 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 2.505 ns                ;
; 12.263 ns                               ; 182.68 MHz ( period = 5.474 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 2.505 ns                ;
; 12.263 ns                               ; 182.68 MHz ( period = 5.474 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 2.505 ns                ;
; 12.263 ns                               ; 182.68 MHz ( period = 5.474 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 2.505 ns                ;
; 12.263 ns                               ; 182.68 MHz ( period = 5.474 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 2.505 ns                ;
; 12.263 ns                               ; 182.68 MHz ( period = 5.474 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 2.505 ns                ;
; 12.263 ns                               ; 182.68 MHz ( period = 5.474 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 2.505 ns                ;
; 12.263 ns                               ; 182.68 MHz ( period = 5.474 ns )                    ; Binary:binary0|oDVAL                                                                                                                                             ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.768 ns                 ; 2.505 ns                ;
; 12.321 ns                               ; 186.64 MHz ( period = 5.358 ns )                    ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; touch_tcon:vga0|oLCD_B[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.731 ns                 ; 2.410 ns                ;
; 12.475 ns                               ; 198.02 MHz ( period = 5.050 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 2.327 ns                ;
; 13.020 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; touch_tcon:vga0|oLCD_R[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.788 ns                 ; 1.768 ns                ;
; 13.022 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.780 ns                ;
; 13.164 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; Binary:binary0|oDATA[9]                                                                                                                                                                  ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.638 ns                ;
; 13.213 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; touch_tcon:vga0|oLCD_R[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.788 ns                 ; 1.575 ns                ;
; 13.288 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; touch_tcon:vga0|oLCD_R[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 1.515 ns                ;
; 13.322 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; touch_tcon:vga0|oLCD_R[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 1.481 ns                ;
; 13.372 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_R[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 1.431 ns                ;
; 13.377 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_G[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 1.426 ns                ;
; 13.377 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; touch_tcon:vga0|oLCD_B[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.803 ns                 ; 1.426 ns                ;
; 13.461 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_G[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.341 ns                ;
; 13.481 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; touch_tcon:vga0|oLCD_R[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.321 ns                ;
; 13.498 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; touch_tcon:vga0|oLCD_R[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.304 ns                ;
; 13.515 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_G[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.287 ns                ;
; 13.531 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; touch_tcon:vga0|oLCD_R[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.271 ns                ;
; 13.547 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; touch_tcon:vga0|oLCD_R[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.255 ns                ;
; 13.623 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_R[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.179 ns                ;
; 13.626 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; touch_tcon:vga0|oLCD_B[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.176 ns                ;
; 13.680 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_B[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.122 ns                ;
; 13.682 ns                               ; Restricted to 235.07 MHz ( period = 4.25 ns )       ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; touch_tcon:vga0|oLCD_R[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 15.000 ns                   ; 14.802 ns                 ; 1.120 ns                ;
; 24.245 ns                               ; 173.76 MHz ( period = 5.755 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|mden                                                                                                                                                                     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.799 ns                 ; 5.554 ns                ;
; 24.329 ns                               ; 176.34 MHz ( period = 5.671 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_G[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.455 ns                ;
; 24.330 ns                               ; 176.37 MHz ( period = 5.670 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_G[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.454 ns                ;
; 24.334 ns                               ; 176.49 MHz ( period = 5.666 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_G[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.450 ns                ;
; 24.334 ns                               ; 176.49 MHz ( period = 5.666 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_G[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.450 ns                ;
; 24.344 ns                               ; 176.80 MHz ( period = 5.656 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.440 ns                ;
; 24.344 ns                               ; 176.80 MHz ( period = 5.656 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.440 ns                ;
; 24.344 ns                               ; 176.80 MHz ( period = 5.656 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.440 ns                ;
; 24.344 ns                               ; 176.80 MHz ( period = 5.656 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.440 ns                ;
; 24.344 ns                               ; 176.80 MHz ( period = 5.656 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.440 ns                ;
; 24.344 ns                               ; 176.80 MHz ( period = 5.656 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.440 ns                ;
; 24.344 ns                               ; 176.80 MHz ( period = 5.656 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.440 ns                ;
; 24.344 ns                               ; 176.80 MHz ( period = 5.656 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.440 ns                ;
; 24.346 ns                               ; 176.87 MHz ( period = 5.654 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.439 ns                ;
; 24.346 ns                               ; 176.87 MHz ( period = 5.654 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.439 ns                ;
; 24.346 ns                               ; 176.87 MHz ( period = 5.654 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.439 ns                ;
; 24.346 ns                               ; 176.87 MHz ( period = 5.654 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.439 ns                ;
; 24.346 ns                               ; 176.87 MHz ( period = 5.654 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.439 ns                ;
; 24.346 ns                               ; 176.87 MHz ( period = 5.654 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.439 ns                ;
; 24.346 ns                               ; 176.87 MHz ( period = 5.654 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.439 ns                ;
; 24.346 ns                               ; 176.87 MHz ( period = 5.654 ns )                    ; touch_tcon:vga0|y_cnt[3]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.439 ns                ;
; 24.359 ns                               ; 177.27 MHz ( period = 5.641 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|mden                                                                                                                                                                     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.799 ns                 ; 5.440 ns                ;
; 24.443 ns                               ; 179.95 MHz ( period = 5.557 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_G[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.341 ns                ;
; 24.444 ns                               ; 179.99 MHz ( period = 5.556 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_G[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.340 ns                ;
; 24.448 ns                               ; 180.12 MHz ( period = 5.552 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_G[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.336 ns                ;
; 24.448 ns                               ; 180.12 MHz ( period = 5.552 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_G[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.336 ns                ;
; 24.458 ns                               ; 180.44 MHz ( period = 5.542 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.326 ns                ;
; 24.458 ns                               ; 180.44 MHz ( period = 5.542 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.326 ns                ;
; 24.458 ns                               ; 180.44 MHz ( period = 5.542 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.326 ns                ;
; 24.458 ns                               ; 180.44 MHz ( period = 5.542 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.326 ns                ;
; 24.458 ns                               ; 180.44 MHz ( period = 5.542 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.326 ns                ;
; 24.458 ns                               ; 180.44 MHz ( period = 5.542 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.326 ns                ;
; 24.458 ns                               ; 180.44 MHz ( period = 5.542 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.326 ns                ;
; 24.458 ns                               ; 180.44 MHz ( period = 5.542 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.784 ns                 ; 5.326 ns                ;
; 24.460 ns                               ; 180.51 MHz ( period = 5.540 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.325 ns                ;
; 24.460 ns                               ; 180.51 MHz ( period = 5.540 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.325 ns                ;
; 24.460 ns                               ; 180.51 MHz ( period = 5.540 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.325 ns                ;
; 24.460 ns                               ; 180.51 MHz ( period = 5.540 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.325 ns                ;
; 24.460 ns                               ; 180.51 MHz ( period = 5.540 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_R[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.325 ns                ;
; 24.460 ns                               ; 180.51 MHz ( period = 5.540 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.325 ns                ;
; 24.460 ns                               ; 180.51 MHz ( period = 5.540 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.325 ns                ;
; 24.460 ns                               ; 180.51 MHz ( period = 5.540 ns )                    ; touch_tcon:vga0|y_cnt[2]                                                                                                                                         ; touch_tcon:vga0|oLCD_B[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.785 ns                 ; 5.325 ns                ;
; 24.475 ns                               ; 181.00 MHz ( period = 5.525 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.772 ns                 ; 5.297 ns                ;
; 24.546 ns                               ; 183.35 MHz ( period = 5.454 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.772 ns                 ; 5.226 ns                ;
; 24.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.772 ns                 ; 5.188 ns                ;
; 24.587 ns                               ; 184.74 MHz ( period = 5.413 ns )                    ; touch_tcon:vga0|y_cnt[8]                                                                                                                                         ; touch_tcon:vga0|mden                                                                                                                                                                     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 30.000 ns                   ; 29.799 ns                 ; 5.212 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                  ;                                                                                                                                                                                          ;                                                ;                                                ;                             ;                           ;                         ;
 


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'GPIO_CLKIN_N1'                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                ; To                                                                                                                                             ; From Clock    ; To Clock      ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+-----------------------------+---------------------------+-------------------------+
; 2.171 ns                                ; 144.53 MHz ( period = 6.919 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.698 ns                ;
; 2.212 ns                                ; 145.39 MHz ( period = 6.878 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.657 ns                ;
; 2.262 ns                                ; 146.46 MHz ( period = 6.828 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.622 ns                ;
; 2.262 ns                                ; 146.46 MHz ( period = 6.828 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.607 ns                ;
; 2.299 ns                                ; 147.25 MHz ( period = 6.791 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.570 ns                ;
; 2.302 ns                                ; 147.32 MHz ( period = 6.788 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.567 ns                ;
; 2.303 ns                                ; 147.34 MHz ( period = 6.787 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.581 ns                ;
; 2.330 ns                                ; 147.93 MHz ( period = 6.760 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.539 ns                ;
; 2.352 ns                                ; 148.41 MHz ( period = 6.738 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[2]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 6.544 ns                ;
; 2.353 ns                                ; 148.43 MHz ( period = 6.737 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.531 ns                ;
; 2.365 ns                                ; 148.70 MHz ( period = 6.725 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.523 ns                ;
; 2.376 ns                                ; 148.94 MHz ( period = 6.714 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.493 ns                ;
; 2.390 ns                                ; 149.25 MHz ( period = 6.700 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.494 ns                ;
; 2.393 ns                                ; 149.32 MHz ( period = 6.697 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.491 ns                ;
; 2.399 ns                                ; 149.45 MHz ( period = 6.691 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[11]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.890 ns                  ; 6.491 ns                ;
; 2.406 ns                                ; 149.61 MHz ( period = 6.684 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.482 ns                ;
; 2.417 ns                                ; 149.86 MHz ( period = 6.673 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.452 ns                ;
; 2.421 ns                                ; 149.95 MHz ( period = 6.669 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.463 ns                ;
; 2.434 ns                                ; 150.24 MHz ( period = 6.656 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[2]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 6.462 ns                ;
; 2.456 ns                                ; 150.74 MHz ( period = 6.634 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.432 ns                ;
; 2.458 ns                                ; 150.78 MHz ( period = 6.632 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.411 ns                ;
; 2.467 ns                                ; 150.99 MHz ( period = 6.623 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.402 ns                ;
; 2.472 ns                                ; 151.10 MHz ( period = 6.618 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rRed[2]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 6.424 ns                ;
; 2.474 ns                                ; 151.15 MHz ( period = 6.616 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.395 ns                ;
; 2.481 ns                                ; 151.31 MHz ( period = 6.609 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[11]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.890 ns                  ; 6.409 ns                ;
; 2.487 ns                                ; 151.45 MHz ( period = 6.603 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[7]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 6.390 ns                ;
; 2.493 ns                                ; 151.58 MHz ( period = 6.597 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.395 ns                ;
; 2.496 ns                                ; 151.65 MHz ( period = 6.594 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.392 ns                ;
; 2.499 ns                                ; 151.72 MHz ( period = 6.591 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.370 ns                ;
; 2.504 ns                                ; 151.84 MHz ( period = 6.586 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.365 ns                ;
; 2.507 ns                                ; 151.91 MHz ( period = 6.583 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.362 ns                ;
; 2.519 ns                                ; 152.18 MHz ( period = 6.571 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rRed[11]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.890 ns                  ; 6.371 ns                ;
; 2.524 ns                                ; 152.30 MHz ( period = 6.566 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.364 ns                ;
; 2.527 ns                                ; 152.37 MHz ( period = 6.563 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.342 ns                ;
; 2.531 ns                                ; 152.46 MHz ( period = 6.559 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[8]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 6.346 ns                ;
; 2.532 ns                                ; 152.49 MHz ( period = 6.558 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.348 ns                ;
; 2.535 ns                                ; 152.56 MHz ( period = 6.555 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.334 ns                ;
; 2.549 ns                                ; 152.88 MHz ( period = 6.541 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.320 ns                ;
; 2.551 ns                                ; 152.93 MHz ( period = 6.539 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.318 ns                ;
; 2.565 ns                                ; 153.26 MHz ( period = 6.525 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.319 ns                ;
; 2.565 ns                                ; 153.26 MHz ( period = 6.525 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.304 ns                ;
; 2.568 ns                                ; 153.33 MHz ( period = 6.522 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.301 ns                ;
; 2.569 ns                                ; 153.35 MHz ( period = 6.521 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[7]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 6.308 ns                ;
; 2.573 ns                                ; 153.44 MHz ( period = 6.517 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.307 ns                ;
; 2.586 ns                                ; 153.75 MHz ( period = 6.504 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.283 ns                ;
; 2.589 ns                                ; 153.82 MHz ( period = 6.501 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.280 ns                ;
; 2.597 ns                                ; 154.01 MHz ( period = 6.493 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.272 ns                ;
; 2.607 ns                                ; 154.25 MHz ( period = 6.483 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rRed[7]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 6.270 ns                ;
; 2.613 ns                                ; 154.39 MHz ( period = 6.477 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[8]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 6.264 ns                ;
; 2.617 ns                                ; 154.49 MHz ( period = 6.473 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.252 ns                ;
; 2.618 ns                                ; 154.51 MHz ( period = 6.472 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.266 ns                ;
; 2.623 ns                                ; 154.63 MHz ( period = 6.467 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.257 ns                ;
; 2.624 ns                                ; 154.66 MHz ( period = 6.466 ns )                    ; CCD_Capture:capture0|X_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[2]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 6.272 ns                ;
; 2.642 ns                                ; 155.09 MHz ( period = 6.448 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.242 ns                ;
; 2.651 ns                                ; 155.30 MHz ( period = 6.439 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rRed[8]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 6.226 ns                ;
; 2.656 ns                                ; 155.42 MHz ( period = 6.434 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.228 ns                ;
; 2.659 ns                                ; 155.50 MHz ( period = 6.431 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.225 ns                ;
; 2.659 ns                                ; 155.50 MHz ( period = 6.431 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 6.220 ns                ;
; 2.660 ns                                ; 155.52 MHz ( period = 6.430 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.220 ns                ;
; 2.663 ns                                ; 155.59 MHz ( period = 6.427 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.217 ns                ;
; 2.668 ns                                ; 155.71 MHz ( period = 6.422 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.220 ns                ;
; 2.671 ns                                ; 155.79 MHz ( period = 6.419 ns )                    ; CCD_Capture:capture0|X_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[11]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.890 ns                  ; 6.219 ns                ;
; 2.673 ns                                ; 155.84 MHz ( period = 6.417 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.207 ns                ;
; 2.679 ns                                ; 155.98 MHz ( period = 6.411 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.190 ns                ;
; 2.681 ns                                ; 156.03 MHz ( period = 6.409 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.207 ns                ;
; 2.688 ns                                ; 156.20 MHz ( period = 6.402 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.196 ns                ;
; 2.691 ns                                ; 156.27 MHz ( period = 6.399 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.189 ns                ;
; 2.692 ns                                ; 156.30 MHz ( period = 6.398 ns )                    ; CCD_Capture:capture0|Y_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.177 ns                ;
; 2.694 ns                                ; 156.35 MHz ( period = 6.396 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.175 ns                ;
; 2.700 ns                                ; 156.49 MHz ( period = 6.390 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 6.179 ns                ;
; 2.701 ns                                ; 156.52 MHz ( period = 6.389 ns )                    ; CCD_Capture:capture0|X_Cont[1]                                                                                                      ; RAW2RGB:raw0|rRed[2]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 6.195 ns                ;
; 2.713 ns                                ; 156.81 MHz ( period = 6.377 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.156 ns                ;
; 2.714 ns                                ; 156.84 MHz ( period = 6.376 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.166 ns                ;
; 2.721 ns                                ; 157.01 MHz ( period = 6.369 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.167 ns                ;
; 2.722 ns                                ; 157.04 MHz ( period = 6.368 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.166 ns                ;
; 2.732 ns                                ; 157.28 MHz ( period = 6.358 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.137 ns                ;
; 2.745 ns                                ; 157.60 MHz ( period = 6.345 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.143 ns                ;
; 2.748 ns                                ; 157.68 MHz ( period = 6.342 ns )                    ; CCD_Capture:capture0|X_Cont[1]                                                                                                      ; RAW2RGB:raw0|rRed[11]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.890 ns                  ; 6.142 ns                ;
; 2.749 ns                                ; 157.70 MHz ( period = 6.341 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.887 ns                  ; 6.138 ns                ;
; 2.750 ns                                ; 157.73 MHz ( period = 6.340 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 6.129 ns                ;
; 2.756 ns                                ; 157.88 MHz ( period = 6.334 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.113 ns                ;
; 2.759 ns                                ; 157.95 MHz ( period = 6.331 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.129 ns                ;
; 2.759 ns                                ; 157.95 MHz ( period = 6.331 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[10]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.889 ns                  ; 6.130 ns                ;
; 2.759 ns                                ; 157.95 MHz ( period = 6.331 ns )                    ; CCD_Capture:capture0|X_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[7]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 6.118 ns                ;
; 2.760 ns                                ; 157.98 MHz ( period = 6.330 ns )                    ; CCD_Capture:capture0|X_Cont[6]                                                                                                      ; RAW2RGB:raw0|rRed[2]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 6.136 ns                ;
; 2.761 ns                                ; 158.00 MHz ( period = 6.329 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.108 ns                ;
; 2.762 ns                                ; 158.03 MHz ( period = 6.328 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.126 ns                ;
; 2.764 ns                                ; 158.08 MHz ( period = 6.326 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.116 ns                ;
; 2.770 ns                                ; 158.23 MHz ( period = 6.320 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.099 ns                ;
; 2.772 ns                                ; 158.28 MHz ( period = 6.318 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.116 ns                ;
; 2.773 ns                                ; 158.30 MHz ( period = 6.317 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.096 ns                ;
; 2.783 ns                                ; 158.55 MHz ( period = 6.307 ns )                    ; CCD_Capture:capture0|Y_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.101 ns                ;
; 2.785 ns                                ; 158.60 MHz ( period = 6.305 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.099 ns                ;
; 2.787 ns                                ; 158.65 MHz ( period = 6.303 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 6.092 ns                ;
; 2.790 ns                                ; 158.73 MHz ( period = 6.300 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 6.089 ns                ;
; 2.791 ns                                ; 158.76 MHz ( period = 6.299 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.097 ns                ;
; 2.801 ns                                ; 159.01 MHz ( period = 6.289 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.079 ns                ;
; 2.802 ns                                ; 159.03 MHz ( period = 6.288 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.067 ns                ;
; 2.803 ns                                ; 159.06 MHz ( period = 6.287 ns )                    ; CCD_Capture:capture0|X_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[8]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 6.074 ns                ;
; 2.804 ns                                ; 159.08 MHz ( period = 6.286 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.076 ns                ;
; 2.804 ns                                ; 159.08 MHz ( period = 6.286 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 6.080 ns                ;
; 2.807 ns                                ; 159.16 MHz ( period = 6.283 ns )                    ; CCD_Capture:capture0|X_Cont[6]                                                                                                      ; RAW2RGB:raw0|rRed[11]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.890 ns                  ; 6.083 ns                ;
; 2.809 ns                                ; 159.21 MHz ( period = 6.281 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.079 ns                ;
; 2.812 ns                                ; 159.29 MHz ( period = 6.278 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.076 ns                ;
; 2.814 ns                                ; 159.34 MHz ( period = 6.276 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.055 ns                ;
; 2.818 ns                                ; 159.44 MHz ( period = 6.272 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 6.061 ns                ;
; 2.829 ns                                ; 159.72 MHz ( period = 6.261 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.040 ns                ;
; 2.831 ns                                ; 159.77 MHz ( period = 6.259 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.887 ns                  ; 6.056 ns                ;
; 2.832 ns                                ; 159.80 MHz ( period = 6.258 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.048 ns                ;
; 2.835 ns                                ; 159.87 MHz ( period = 6.255 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 6.045 ns                ;
; 2.836 ns                                ; 159.90 MHz ( period = 6.254 ns )                    ; CCD_Capture:capture0|X_Cont[1]                                                                                                      ; RAW2RGB:raw0|rRed[7]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 6.041 ns                ;
; 2.838 ns                                ; 159.95 MHz ( period = 6.252 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.031 ns                ;
; 2.840 ns                                ; 160.00 MHz ( period = 6.250 ns )                    ; CCD_Capture:capture0|Y_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.048 ns                ;
; 2.841 ns                                ; 160.03 MHz ( period = 6.249 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[10]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.889 ns                  ; 6.048 ns                ;
; 2.852 ns                                ; 160.31 MHz ( period = 6.238 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.017 ns                ;
; 2.855 ns                                ; 160.38 MHz ( period = 6.235 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 6.014 ns                ;
; 2.869 ns                                ; 160.75 MHz ( period = 6.221 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.887 ns                  ; 6.018 ns                ;
; 2.870 ns                                ; 160.77 MHz ( period = 6.220 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 6.026 ns                ;
; 2.879 ns                                ; 161.00 MHz ( period = 6.211 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rRed[10]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.889 ns                  ; 6.010 ns                ;
; 2.880 ns                                ; 161.03 MHz ( period = 6.210 ns )                    ; CCD_Capture:capture0|X_Cont[1]                                                                                                      ; RAW2RGB:raw0|rRed[8]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 5.997 ns                ;
; 2.884 ns                                ; 161.13 MHz ( period = 6.206 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 5.985 ns                ;
; 2.886 ns                                ; 161.19 MHz ( period = 6.204 ns )                    ; CCD_Capture:capture0|Y_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.002 ns                ;
; 2.888 ns                                ; 161.24 MHz ( period = 6.202 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 6.000 ns                ;
; 2.888 ns                                ; 161.24 MHz ( period = 6.202 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[6]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.889 ns                  ; 6.001 ns                ;
; 2.888 ns                                ; 161.24 MHz ( period = 6.202 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.992 ns                ;
; 2.890 ns                                ; 161.29 MHz ( period = 6.200 ns )                    ; CCD_Capture:capture0|X_Cont[7]                                                                                                      ; RAW2RGB:raw0|rRed[2]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 6.006 ns                ;
; 2.892 ns                                ; 161.34 MHz ( period = 6.198 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[9]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 5.987 ns                ;
; 2.895 ns                                ; 161.42 MHz ( period = 6.195 ns )                    ; CCD_Capture:capture0|X_Cont[6]                                                                                                      ; RAW2RGB:raw0|rRed[7]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 5.982 ns                ;
; 2.897 ns                                ; 161.47 MHz ( period = 6.193 ns )                    ; CCD_Capture:capture0|Y_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 5.972 ns                ;
; 2.899 ns                                ; 161.52 MHz ( period = 6.191 ns )                    ; CCD_Capture:capture0|X_Cont[12]                                                                                                     ; RAW2RGB:raw0|rRed[2]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 5.997 ns                ;
; 2.899 ns                                ; 161.52 MHz ( period = 6.191 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 5.970 ns                ;
; 2.900 ns                                ; 161.55 MHz ( period = 6.190 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[3]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 5.998 ns                ;
; 2.907 ns                                ; 161.73 MHz ( period = 6.183 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.981 ns                ;
; 2.912 ns                                ; 161.86 MHz ( period = 6.178 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.968 ns                ;
; 2.917 ns                                ; 162.00 MHz ( period = 6.173 ns )                    ; RAW2RGB:raw0|dval_ctrl_en                                                                                                           ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 5.734 ns                  ; 2.817 ns                ;
; 2.918 ns                                ; 162.02 MHz ( period = 6.172 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 5.951 ns                ;
; 2.920 ns                                ; 162.07 MHz ( period = 6.170 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[6]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.884 ns                  ; 5.964 ns                ;
; 2.926 ns                                ; 162.23 MHz ( period = 6.164 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.954 ns                ;
; 2.929 ns                                ; 162.31 MHz ( period = 6.161 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.951 ns                ;
; 2.937 ns                                ; 162.52 MHz ( period = 6.153 ns )                    ; CCD_Capture:capture0|X_Cont[7]                                                                                                      ; RAW2RGB:raw0|rRed[11]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.890 ns                  ; 5.953 ns                ;
; 2.939 ns                                ; 162.58 MHz ( period = 6.151 ns )                    ; CCD_Capture:capture0|X_Cont[6]                                                                                                      ; RAW2RGB:raw0|rRed[8]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 5.938 ns                ;
; 2.946 ns                                ; 162.76 MHz ( period = 6.144 ns )                    ; CCD_Capture:capture0|X_Cont[12]                                                                                                     ; RAW2RGB:raw0|rRed[11]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.890 ns                  ; 5.944 ns                ;
; 2.948 ns                                ; 162.81 MHz ( period = 6.142 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.940 ns                ;
; 2.952 ns                                ; 162.92 MHz ( period = 6.138 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 5.944 ns                ;
; 2.958 ns                                ; 163.08 MHz ( period = 6.132 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.922 ns                ;
; 2.960 ns                                ; 163.13 MHz ( period = 6.130 ns )                    ; CCD_Capture:capture0|Y_Cont[7]                                                                                                      ; RAW2RGB:raw0|rGreen[5]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.920 ns                ;
; 2.962 ns                                ; 163.19 MHz ( period = 6.128 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 5.917 ns                ;
; 2.970 ns                                ; 163.40 MHz ( period = 6.120 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[6]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.889 ns                  ; 5.919 ns                ;
; 2.974 ns                                ; 163.51 MHz ( period = 6.116 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[9]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 5.905 ns                ;
; 2.976 ns                                ; 163.56 MHz ( period = 6.114 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.904 ns                ;
; 2.979 ns                                ; 163.64 MHz ( period = 6.111 ns )                    ; CCD_Capture:capture0|Y_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 5.890 ns                ;
; 2.981 ns                                ; 163.69 MHz ( period = 6.109 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 5.888 ns                ;
; 2.982 ns                                ; 163.72 MHz ( period = 6.108 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[3]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 5.916 ns                ;
; 2.984 ns                                ; 163.77 MHz ( period = 6.106 ns )                    ; CCD_Capture:capture0|Y_Cont[14]                                                                                                     ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.904 ns                ;
; 2.988 ns                                ; 163.88 MHz ( period = 6.102 ns )                    ; RAW2RGB:raw0|dval_ctrl_en                                                                                                           ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 5.734 ns                  ; 2.746 ns                ;
; 2.990 ns                                ; 163.93 MHz ( period = 6.100 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 5.906 ns                ;
; 2.999 ns                                ; 164.18 MHz ( period = 6.091 ns )                    ; CCD_Capture:capture0|X_Cont[13]                                                                                                     ; RAW2RGB:raw0|rRed[2]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 5.897 ns                ;
; 3.000 ns                                ; 164.20 MHz ( period = 6.090 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[8]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 5.869 ns                ;
; 3.001 ns                                ; 164.23 MHz ( period = 6.089 ns )                    ; CCD_Capture:capture0|Y_Cont[12]                                                                                                     ; RAW2RGB:raw0|rGreen[5]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.879 ns                ;
; 3.008 ns                                ; 164.42 MHz ( period = 6.082 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rRed[6]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.889 ns                  ; 5.881 ns                ;
; 3.012 ns                                ; 164.53 MHz ( period = 6.078 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rRed[9]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 5.867 ns                ;
; 3.014 ns                                ; 164.58 MHz ( period = 6.076 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rRed[4]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.874 ns                ;
; 3.015 ns                                ; 164.61 MHz ( period = 6.075 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 5.864 ns                ;
; 3.020 ns                                ; 164.74 MHz ( period = 6.070 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rRed[3]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.898 ns                  ; 5.878 ns                ;
; 3.021 ns                                ; 164.77 MHz ( period = 6.069 ns )                    ; CCD_Capture:capture0|X_Cont[11]                                                                                                     ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.887 ns                  ; 5.866 ns                ;
; 3.023 ns                                ; 164.83 MHz ( period = 6.067 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.865 ns                ;
; 3.025 ns                                ; 164.88 MHz ( period = 6.065 ns )                    ; CCD_Capture:capture0|X_Cont[7]                                                                                                      ; RAW2RGB:raw0|rRed[7]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 5.852 ns                ;
; 3.029 ns                                ; 164.99 MHz ( period = 6.061 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.851 ns                ;
; 3.030 ns                                ; 165.02 MHz ( period = 6.060 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.858 ns                ;
; 3.031 ns                                ; 165.04 MHz ( period = 6.059 ns )                    ; CCD_Capture:capture0|X_Cont[11]                                                                                                     ; RAW2RGB:raw0|rRed[10]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.889 ns                  ; 5.858 ns                ;
; 3.033 ns                                ; 165.10 MHz ( period = 6.057 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 5.844 ns                ;
; 3.034 ns                                ; 165.13 MHz ( period = 6.056 ns )                    ; CCD_Capture:capture0|X_Cont[12]                                                                                                     ; RAW2RGB:raw0|rRed[7]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 5.843 ns                ;
; 3.034 ns                                ; 165.13 MHz ( period = 6.056 ns )                    ; CCD_Capture:capture0|Y_Cont[1]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.869 ns                  ; 5.835 ns                ;
; 3.037 ns                                ; 165.21 MHz ( period = 6.053 ns )                    ; CCD_Capture:capture0|Y_Cont[5]                                                                                                      ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.851 ns                ;
; 3.039 ns                                ; 165.26 MHz ( period = 6.051 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 5.840 ns                ;
; 3.046 ns                                ; 165.45 MHz ( period = 6.044 ns )                    ; CCD_Capture:capture0|X_Cont[13]                                                                                                     ; RAW2RGB:raw0|rRed[11]                                                                                                                          ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.890 ns                  ; 5.844 ns                ;
; 3.051 ns                                ; 165.59 MHz ( period = 6.039 ns )                    ; CCD_Capture:capture0|Y_Cont[6]                                                                                                      ; RAW2RGB:raw0|rGreen[5]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.829 ns                ;
; 3.053 ns                                ; 165.65 MHz ( period = 6.037 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.827 ns                ;
; 3.053 ns                                ; 165.65 MHz ( period = 6.037 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 5.826 ns                ;
; 3.053 ns                                ; 165.65 MHz ( period = 6.037 ns )                    ; CCD_Capture:capture0|Y_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.827 ns                ;
; 3.055 ns                                ; 165.70 MHz ( period = 6.035 ns )                    ; CCD_Capture:capture0|Y_Cont[2]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.825 ns                ;
; 3.056 ns                                ; 165.73 MHz ( period = 6.034 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 5.823 ns                ;
; 3.059 ns                                ; 165.81 MHz ( period = 6.031 ns )                    ; RAW2RGB:raw0|dval_ctrl_en                                                                                                           ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 5.734 ns                  ; 2.675 ns                ;
; 3.061 ns                                ; 165.86 MHz ( period = 6.029 ns )                    ; CCD_Capture:capture0|Y_Cont[4]                                                                                                      ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.827 ns                ;
; 3.062 ns                                ; 165.89 MHz ( period = 6.028 ns )                    ; CCD_Capture:capture0|X_Cont[0]                                                                                                      ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 5.815 ns                ;
; 3.067 ns                                ; 166.03 MHz ( period = 6.023 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.813 ns                ;
; 3.068 ns                                ; 166.06 MHz ( period = 6.022 ns )                    ; CCD_Capture:capture0|X_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.820 ns                ;
; 3.069 ns                                ; 166.09 MHz ( period = 6.021 ns )                    ; CCD_Capture:capture0|X_Cont[7]                                                                                                      ; RAW2RGB:raw0|rRed[8]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 5.808 ns                ;
; 3.070 ns                                ; 166.11 MHz ( period = 6.020 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[7]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.810 ns                ;
; 3.071 ns                                ; 166.14 MHz ( period = 6.019 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 5.806 ns                ;
; 3.074 ns                                ; 166.22 MHz ( period = 6.016 ns )                    ; CCD_Capture:capture0|Y_Cont[13]                                                                                                     ; RAW2RGB:raw0|rGreen[11]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.806 ns                ;
; 3.075 ns                                ; 166.25 MHz ( period = 6.015 ns )                    ; CCD_Capture:capture0|Y_Cont[9]                                                                                                      ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.813 ns                ;
; 3.078 ns                                ; 166.33 MHz ( period = 6.012 ns )                    ; CCD_Capture:capture0|Y_Cont[15]                                                                                                     ; RAW2RGB:raw0|rGreen[4]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.810 ns                ;
; 3.078 ns                                ; 166.33 MHz ( period = 6.012 ns )                    ; CCD_Capture:capture0|X_Cont[12]                                                                                                     ; RAW2RGB:raw0|rRed[8]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.877 ns                  ; 5.799 ns                ;
; 3.078 ns                                ; 166.33 MHz ( period = 6.012 ns )                    ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[26] ; RAW2RGB:raw0|rGreen[10]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.883 ns                  ; 5.805 ns                ;
; 3.085 ns                                ; 166.53 MHz ( period = 6.005 ns )                    ; CCD_Capture:capture0|Y_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[12]                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.879 ns                  ; 5.794 ns                ;
; 3.088 ns                                ; 166.61 MHz ( period = 6.002 ns )                    ; CCD_Capture:capture0|Y_Cont[10]                                                                                                     ; RAW2RGB:raw0|rGreen[5]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.792 ns                ;
; 3.091 ns                                ; 166.69 MHz ( period = 5.999 ns )                    ; CCD_Capture:capture0|Y_Cont[8]                                                                                                      ; RAW2RGB:raw0|rGreen[5]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.880 ns                  ; 5.789 ns                ;
; 3.095 ns                                ; 166.81 MHz ( period = 5.995 ns )                    ; CCD_Capture:capture0|X_Cont[3]                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                         ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.896 ns                  ; 5.801 ns                ;
; 3.096 ns                                ; 166.83 MHz ( period = 5.994 ns )                    ; CCD_Capture:capture0|X_Cont[2]                                                                                                      ; RAW2RGB:raw0|rRed[4]                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 9.090 ns                    ; 8.888 ns                  ; 5.792 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                     ;                                                                                                                                                ;               ;               ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'iCLK_50'                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                           ; To                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 6.848 ns                                ; 158.63 MHz ( period = 6.304 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[14]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.938 ns                ;
; 7.156 ns                                ; 175.81 MHz ( period = 5.688 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[15]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.630 ns                ;
; 7.265 ns                                ; 182.82 MHz ( period = 5.470 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]          ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.517 ns                ;
; 7.329 ns                                ; 187.20 MHz ( period = 5.342 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[11]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.788 ns                  ; 2.459 ns                ;
; 7.376 ns                                ; 190.55 MHz ( period = 5.248 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]          ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.406 ns                ;
; 7.436 ns                                ; 195.01 MHz ( period = 5.128 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[5]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.777 ns                  ; 2.341 ns                ;
; 7.541 ns                                ; 203.33 MHz ( period = 4.918 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]          ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.241 ns                ;
; 7.543 ns                                ; 203.50 MHz ( period = 4.914 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]          ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.239 ns                ;
; 7.543 ns                                ; 203.50 MHz ( period = 4.914 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]          ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.239 ns                ;
; 7.592 ns                                ; 207.64 MHz ( period = 4.816 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[13]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.194 ns                ;
; 7.625 ns                                ; 210.53 MHz ( period = 4.750 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.789 ns                  ; 2.164 ns                ;
; 7.652 ns                                ; 212.95 MHz ( period = 4.696 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]          ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.130 ns                ;
; 7.654 ns                                ; 213.13 MHz ( period = 4.692 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]          ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.128 ns                ;
; 7.654 ns                                ; 213.13 MHz ( period = 4.692 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]          ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 2.128 ns                ;
; 7.662 ns                                ; 213.86 MHz ( period = 4.676 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA~en ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.792 ns                  ; 2.130 ns                ;
; 7.711 ns                                ; 218.44 MHz ( period = 4.578 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[7]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.777 ns                  ; 2.066 ns                ;
; 7.776 ns                                ; 224.82 MHz ( period = 4.448 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[10]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 2.010 ns                ;
; 7.812 ns                                ; 228.52 MHz ( period = 4.376 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]          ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.970 ns                ;
; 7.830 ns                                ; 230.41 MHz ( period = 4.340 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN      ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.960 ns                ;
; 7.830 ns                                ; 230.41 MHz ( period = 4.340 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSCLK     ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.960 ns                ;
; 7.870 ns                                ; 234.74 MHz ( period = 4.260 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[2]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.788 ns                  ; 1.918 ns                ;
; 7.872 ns                                ; 234.96 MHz ( period = 4.256 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[12]                   ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.914 ns                ;
; 7.901 ns                                ; 238.21 MHz ( period = 4.198 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[8]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.786 ns                  ; 1.885 ns                ;
; 7.963 ns                                ; 245.46 MHz ( period = 4.074 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]          ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.819 ns                ;
; 8.056 ns                                ; 257.20 MHz ( period = 3.888 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]          ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.726 ns                ;
; 8.066 ns                                ; 258.53 MHz ( period = 3.868 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[6]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.777 ns                  ; 1.711 ns                ;
; 8.088 ns                                ; 261.51 MHz ( period = 3.824 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]          ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.694 ns                ;
; 8.090 ns                                ; 261.78 MHz ( period = 3.820 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]          ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.692 ns                ;
; 8.090 ns                                ; 261.78 MHz ( period = 3.820 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]          ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.692 ns                ;
; 8.162 ns                                ; 272.03 MHz ( period = 3.676 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[3]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.788 ns                  ; 1.626 ns                ;
; 8.201 ns                                ; 277.93 MHz ( period = 3.598 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[0]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.788 ns                  ; 1.587 ns                ;
; 8.239 ns                                ; 283.93 MHz ( period = 3.522 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]          ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.543 ns                ;
; 8.241 ns                                ; 284.25 MHz ( period = 3.518 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]          ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.541 ns                ;
; 8.241 ns                                ; 284.25 MHz ( period = 3.518 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]          ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.541 ns                ;
; 8.260 ns                                ; 287.36 MHz ( period = 3.480 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[1]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.788 ns                  ; 1.528 ns                ;
; 8.332 ns                                ; 299.76 MHz ( period = 3.336 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]          ; lcd_3wire_config:lcd_config0|m3wire_str                  ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.450 ns                ;
; 8.334 ns                                ; 300.12 MHz ( period = 3.332 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]          ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.448 ns                ;
; 8.334 ns                                ; 300.12 MHz ( period = 3.332 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]          ; lcd_3wire_config:lcd_config0|msetup_st.0011              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.448 ns                ;
; 8.374 ns                                ; 307.50 MHz ( period = 3.252 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_data[4]                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.777 ns                  ; 1.403 ns                ;
; 8.525 ns                                ; 338.98 MHz ( period = 2.950 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK      ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.265 ns                ;
; 8.525 ns                                ; 338.98 MHz ( period = 2.950 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.265 ns                ;
; 8.525 ns                                ; 338.98 MHz ( period = 2.950 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.265 ns                ;
; 8.525 ns                                ; 338.98 MHz ( period = 2.950 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.265 ns                ;
; 8.525 ns                                ; 338.98 MHz ( period = 2.950 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.265 ns                ;
; 8.525 ns                                ; 338.98 MHz ( period = 2.950 ns )                    ; lcd_3wire_config:lcd_config0|m3wire_str                        ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]    ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.790 ns                  ; 1.265 ns                ;
; 8.681 ns                                ; 379.08 MHz ( period = 2.638 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK            ; lcd_3wire_config:lcd_config0|msetup_st.0000              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.101 ns                ;
; 8.681 ns                                ; 379.08 MHz ( period = 2.638 ns )                    ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK            ; lcd_3wire_config:lcd_config0|msetup_st.0100              ; iCLK_50    ; iCLK_50  ; 10.000 ns                   ; 9.782 ns                  ; 1.101 ns                ;
; 14.038 ns                               ; 167.73 MHz ( period = 5.962 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[0] ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.801 ns                 ; 5.763 ns                ;
; 14.151 ns                               ; 170.97 MHz ( period = 5.849 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.649 ns                ;
; 14.240 ns                               ; 173.61 MHz ( period = 5.760 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.803 ns                 ; 5.563 ns                ;
; 14.263 ns                               ; 174.31 MHz ( period = 5.737 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[1] ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.801 ns                 ; 5.538 ns                ;
; 14.309 ns                               ; 175.72 MHz ( period = 5.691 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.491 ns                ;
; 14.311 ns                               ; 175.78 MHz ( period = 5.689 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.790 ns                 ; 5.479 ns                ;
; 14.349 ns                               ; 176.96 MHz ( period = 5.651 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.790 ns                 ; 5.441 ns                ;
; 14.372 ns                               ; 177.68 MHz ( period = 5.628 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.428 ns                ;
; 14.374 ns                               ; 177.75 MHz ( period = 5.626 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.438 ns                ;
; 14.398 ns                               ; 178.51 MHz ( period = 5.602 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.803 ns                 ; 5.405 ns                ;
; 14.414 ns                               ; 179.02 MHz ( period = 5.586 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.398 ns                ;
; 14.420 ns                               ; 179.21 MHz ( period = 5.580 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.380 ns                ;
; 14.424 ns                               ; 179.34 MHz ( period = 5.576 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.376 ns                ;
; 14.432 ns                               ; 179.60 MHz ( period = 5.568 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.803 ns                 ; 5.371 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.438 ns                               ; 179.79 MHz ( period = 5.562 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.348 ns                ;
; 14.457 ns                               ; 180.41 MHz ( period = 5.543 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.790 ns                 ; 5.333 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.476 ns                               ; 181.03 MHz ( period = 5.524 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.310 ns                ;
; 14.487 ns                               ; 181.39 MHz ( period = 5.513 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.814 ns                 ; 5.327 ns                ;
; 14.513 ns                               ; 182.25 MHz ( period = 5.487 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.803 ns                 ; 5.290 ns                ;
; 14.521 ns                               ; 182.52 MHz ( period = 5.479 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.291 ns                ;
; 14.530 ns                               ; 182.82 MHz ( period = 5.470 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.270 ns                ;
; 14.532 ns                               ; 182.88 MHz ( period = 5.468 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.280 ns                ;
; 14.562 ns                               ; 183.89 MHz ( period = 5.438 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.799 ns                 ; 5.237 ns                ;
; 14.572 ns                               ; 184.23 MHz ( period = 5.428 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.240 ns                ;
; 14.578 ns                               ; 184.43 MHz ( period = 5.422 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.222 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.202 ns                ;
; 14.607 ns                               ; 185.43 MHz ( period = 5.393 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.790 ns                 ; 5.183 ns                ;
; 14.612 ns                               ; 185.60 MHz ( period = 5.388 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.803 ns                 ; 5.191 ns                ;
; 14.619 ns                               ; 185.84 MHz ( period = 5.381 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.193 ns                ;
; 14.621 ns                               ; 185.91 MHz ( period = 5.379 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.803 ns                 ; 5.182 ns                ;
; 14.635 ns                               ; 186.39 MHz ( period = 5.365 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.803 ns                 ; 5.168 ns                ;
; 14.645 ns                               ; 186.74 MHz ( period = 5.355 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.814 ns                 ; 5.169 ns                ;
; 14.645 ns                               ; 186.74 MHz ( period = 5.355 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.155 ns                ;
; 14.647 ns                               ; 186.81 MHz ( period = 5.353 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.165 ns                ;
; 14.662 ns                               ; 187.34 MHz ( period = 5.338 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3] ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.801 ns                 ; 5.139 ns                ;
; 14.664 ns                               ; 187.41 MHz ( period = 5.336 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.799 ns                 ; 5.135 ns                ;
; 14.679 ns                               ; 187.93 MHz ( period = 5.321 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.133 ns                ;
; 14.687 ns                               ; 188.22 MHz ( period = 5.313 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.125 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.689 ns                               ; 188.29 MHz ( period = 5.311 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.106 ns                ;
; 14.693 ns                               ; 188.43 MHz ( period = 5.307 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.107 ns                ;
; 14.696 ns                               ; 188.54 MHz ( period = 5.304 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[4]         ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.790 ns                 ; 5.094 ns                ;
; 14.699 ns                               ; 188.64 MHz ( period = 5.301 ns )                    ; Reset_Delay:reset0|Cont[15]                                    ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.884 ns                 ; 5.185 ns                ;
; 14.705 ns                               ; 188.86 MHz ( period = 5.295 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.799 ns                 ; 5.094 ns                ;
; 14.733 ns                               ; 189.86 MHz ( period = 5.267 ns )                    ; Reset_Delay:reset0|Cont[13]                                    ; Reset_Delay:reset0|oRST_1                                ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.884 ns                 ; 5.151 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.734 ns                               ; 189.90 MHz ( period = 5.266 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.786 ns                 ; 5.052 ns                ;
; 14.741 ns                               ; 190.15 MHz ( period = 5.259 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.059 ns                ;
; 14.746 ns                               ; 190.33 MHz ( period = 5.254 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.066 ns                ;
; 14.750 ns                               ; 190.48 MHz ( period = 5.250 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                   ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.799 ns                 ; 5.049 ns                ;
; 14.754 ns                               ; 190.62 MHz ( period = 5.246 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[10]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.046 ns                ;
; 14.755 ns                               ; 190.66 MHz ( period = 5.245 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[14]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.057 ns                ;
; 14.760 ns                               ; 190.84 MHz ( period = 5.240 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]             ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.814 ns                 ; 5.054 ns                ;
; 14.777 ns                               ; 191.46 MHz ( period = 5.223 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.035 ns                ;
; 14.786 ns                               ; 191.79 MHz ( period = 5.214 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.026 ns                ;
; 14.789 ns                               ; 191.90 MHz ( period = 5.211 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 5.011 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.791 ns                               ; 191.98 MHz ( period = 5.209 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 5.004 ns                ;
; 14.793 ns                               ; 192.05 MHz ( period = 5.207 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[18]        ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO     ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.793 ns                 ; 5.000 ns                ;
; 14.794 ns                               ; 192.09 MHz ( period = 5.206 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.018 ns                ;
; 14.795 ns                               ; 192.12 MHz ( period = 5.205 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.812 ns                 ; 5.017 ns                ;
; 14.802 ns                               ; 192.38 MHz ( period = 5.198 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.800 ns                 ; 4.998 ns                ;
; 14.811 ns                               ; 192.72 MHz ( period = 5.189 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[4]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.799 ns                 ; 4.988 ns                ;
; 14.817 ns                               ; 192.94 MHz ( period = 5.183 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[2]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.799 ns                 ; 4.982 ns                ;
; 14.829 ns                               ; 193.39 MHz ( period = 5.171 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]              ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.803 ns                 ; 4.974 ns                ;
; 14.832 ns                               ; 193.50 MHz ( period = 5.168 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 4.963 ns                ;
; 14.832 ns                               ; 193.50 MHz ( period = 5.168 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 4.963 ns                ;
; 14.832 ns                               ; 193.50 MHz ( period = 5.168 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 4.963 ns                ;
; 14.832 ns                               ; 193.50 MHz ( period = 5.168 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 4.963 ns                ;
; 14.832 ns                               ; 193.50 MHz ( period = 5.168 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 4.963 ns                ;
; 14.832 ns                               ; 193.50 MHz ( period = 5.168 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]       ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 4.963 ns                ;
; 14.832 ns                               ; 193.50 MHz ( period = 5.168 ns )                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                    ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]        ; iCLK_50    ; iCLK_50  ; 20.000 ns                   ; 19.795 ns                 ; 4.963 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                ;                                                          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


 
; Clock Hold: 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
 
; Minimum Slack                           ; From                                                                                                                                                            ; To                                                                                                                                                                                        ; From Clock                                         ; To Clock                                           ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
 
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                               ; Sdram_Control_4Port:sdram1|command:command1|do_rw                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_rw                                                                                                               ; Sdram_Control_4Port:sdram0|command:command1|do_rw                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rw_flag                                                                                                             ; Sdram_Control_4Port:sdram1|command:command1|rw_flag                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rw_flag                                                                                                             ; Sdram_Control_4Port:sdram0|command:command1|rw_flag                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|OUT_VALID                                                                                                                            ; Sdram_Control_4Port:sdram1|OUT_VALID                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|IN_REQ                                                                                                                               ; Sdram_Control_4Port:sdram1|IN_REQ                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|Write                                                                                                                                ; Sdram_Control_4Port:sdram1|Write                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|Read                                                                                                                                 ; Sdram_Control_4Port:sdram1|Read                                                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|mWR_DONE                                                                                                                             ; Sdram_Control_4Port:sdram1|mWR_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|CM_ACK                                                                                                              ; Sdram_Control_4Port:sdram1|command:command1|CM_ACK                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|mRD_DONE                                                                                                                             ; Sdram_Control_4Port:sdram1|mRD_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|ST[0]                                                                                                                                ; Sdram_Control_4Port:sdram1|ST[0]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|CMD_ACK                                                                                                   ; Sdram_Control_4Port:sdram1|control_interface:control1|CMD_ACK                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|RD_MASK[0]                                                                                                                           ; Sdram_Control_4Port:sdram1|RD_MASK[0]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|ex_read                                                                                                             ; Sdram_Control_4Port:sdram1|command:command1|ex_read                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|ex_write                                                                                                            ; Sdram_Control_4Port:sdram1|command:command1|ex_write                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|REF_ACK                                                                                                             ; Sdram_Control_4Port:sdram1|command:command1|REF_ACK                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|REF_REQ                                                                                                   ; Sdram_Control_4Port:sdram1|control_interface:control1|REF_REQ                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_precharge                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|do_precharge                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|do_load_mode                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|OUT_VALID                                                                                                                            ; Sdram_Control_4Port:sdram0|OUT_VALID                                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|IN_REQ                                                                                                                               ; Sdram_Control_4Port:sdram0|IN_REQ                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|Write                                                                                                                                ; Sdram_Control_4Port:sdram0|Write                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|Read                                                                                                                                 ; Sdram_Control_4Port:sdram0|Read                                                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|mWR_DONE                                                                                                                             ; Sdram_Control_4Port:sdram0|mWR_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|CM_ACK                                                                                                              ; Sdram_Control_4Port:sdram0|command:command1|CM_ACK                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|mRD_DONE                                                                                                                             ; Sdram_Control_4Port:sdram0|mRD_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                  ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|ST[0]                                                                                                                                ; Sdram_Control_4Port:sdram0|ST[0]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|CMD_ACK                                                                                                   ; Sdram_Control_4Port:sdram0|control_interface:control1|CMD_ACK                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|RD_MASK[0]                                                                                                                           ; Sdram_Control_4Port:sdram0|RD_MASK[0]                                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|ex_write                                                                                                            ; Sdram_Control_4Port:sdram0|command:command1|ex_write                                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|ex_read                                                                                                             ; Sdram_Control_4Port:sdram0|command:command1|ex_read                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|REF_ACK                                                                                                             ; Sdram_Control_4Port:sdram0|command:command1|REF_ACK                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|REF_REQ                                                                                                   ; Sdram_Control_4Port:sdram0|control_interface:control1|REF_REQ                                                                                                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[0]                                                                                             ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[0]                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_precharge                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|do_precharge                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|do_load_mode                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.516 ns                                ; Sdram_Control_4Port:sdram0|mADDR[17]                                                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[17]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.532 ns                 ;
; 0.518 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[21]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|BA[1]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.534 ns                 ;
; 0.518 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[15]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[7]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.534 ns                 ;
; 0.519 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[20]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|BA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.535 ns                 ;
; 0.520 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rw_shift[0]                                                                                                         ; Sdram_Control_4Port:sdram0|command:command1|do_rw                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.536 ns                 ;
; 0.521 ns                                ; Sdram_Control_4Port:sdram1|command:command1|SA[0]                                                                                                               ; Sdram_Control_4Port:sdram1|SA[0]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.537 ns                 ;
; 0.527 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.543 ns                 ;
; 0.530 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram0|rRD1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.546 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[22]                                                                                                                        ; Sdram_Control_4Port:sdram0|rWR1_ADDR[22]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[15]                                                                                                 ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[15]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.531 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[15]                                                                                                 ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[15]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.547 ns                 ;
; 0.532 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rw_flag                                                                                                             ; Sdram_Control_4Port:sdram0|command:command1|WE_N                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.548 ns                 ;
; 0.535 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.551 ns                 ;
; 0.535 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.551 ns                 ;
; 0.535 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.551 ns                 ;
; 0.536 ns                                ; Sdram_Control_4Port:sdram0|command:command1|do_reada                                                                                                            ; Sdram_Control_4Port:sdram0|command:command1|rw_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.552 ns                 ;
; 0.536 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_done                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[3]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.552 ns                 ;
; 0.536 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.552 ns                 ;
; 0.537 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.553 ns                 ;
; 0.537 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.553 ns                 ;
; 0.539 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[15]                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[15]                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.555 ns                 ;
; 0.540 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_refresh                                                                                                          ; Sdram_Control_4Port:sdram1|command:command1|REF_ACK                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.556 ns                 ;
; 0.542 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_refresh                                                                                                          ; Sdram_Control_4Port:sdram1|command:command1|CM_ACK                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.558 ns                 ;
; 0.549 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.565 ns                 ;
; 0.550 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.566 ns                 ;
; 0.563 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_precharge                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|CAS_N                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.579 ns                 ;
; 0.563 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_done                                                                                                        ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[3]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.579 ns                 ;
; 0.564 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[0]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[2]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.580 ns                 ;
; 0.572 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[0]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[1]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.588 ns                 ;
; 0.573 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[0]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.589 ns                 ;
; 0.574 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[0]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|rp_done                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.590 ns                 ;
; 0.646 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[9]                                                                                                  ; Sdram_Control_4Port:sdram0|command:command1|SA[1]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.662 ns                 ;
; 0.647 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[13]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[5]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.663 ns                 ;
; 0.651 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[20]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|BA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.667 ns                 ;
; 0.654 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[6]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[5]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.670 ns                 ;
; 0.656 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[4]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[3]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.672 ns                 ;
; 0.657 ns                                ; Sdram_Control_4Port:sdram0|Read                                                                                                                                 ; Sdram_Control_4Port:sdram0|DQM[0]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.673 ns                 ;
; 0.658 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~portb_address_reg0  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.066 ns                   ; 0.724 ns                 ;
; 0.658 ns                                ; Sdram_Control_4Port:sdram0|command:command1|command_delay[6]                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|command_delay[5]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.674 ns                 ;
; 0.659 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[3]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[2]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.675 ns                 ;
; 0.663 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[3]                                                                                                         ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[2]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.679 ns                 ;
; 0.663 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[2]                                                                                                         ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[1]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.679 ns                 ;
; 0.664 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[1]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|rp_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.680 ns                 ;
; 0.665 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[18]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[10]                                                                                                                                        ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.681 ns                 ;
; 0.666 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rp_shift[0]                                                                                                         ; Sdram_Control_4Port:sdram0|command:command1|rp_done                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.682 ns                 ;
; 0.670 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.686 ns                 ;
; 0.674 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.690 ns                 ;
; 0.676 ns                                ; Sdram_Control_4Port:sdram0|mADDR[19]                                                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[19]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.691 ns                 ;
; 0.677 ns                                ; Sdram_Control_4Port:sdram0|command:command1|WE_N                                                                                                                ; Sdram_Control_4Port:sdram0|WE_N                                                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.691 ns                 ;
; 0.685 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.701 ns                 ;
; 0.687 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg1 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.039 ns                   ; 0.726 ns                 ;
; 0.689 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.705 ns                 ;
; 0.690 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.706 ns                 ;
; 0.691 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[8]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.707 ns                 ;
; 0.694 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg2 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.725 ns                 ;
; 0.698 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.714 ns                 ;
; 0.699 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[4]                                                                    ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.715 ns                 ;
; 0.700 ns                                ; Sdram_Control_4Port:sdram1|mADDR[21]                                                                                                                            ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[21]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.714 ns                 ;
; 0.702 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg7 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.733 ns                 ;
; 0.703 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[10]                                                                                                              ; Sdram_Control_4Port:sdram0|SA[10]                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.717 ns                 ;
; 0.703 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg5 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.734 ns                 ;
; 0.704 ns                                ; Sdram_Control_4Port:sdram0|mADDR[16]                                                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[16]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.719 ns                 ;
; 0.704 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg3 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.735 ns                 ;
; 0.704 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg6 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.735 ns                 ;
; 0.705 ns                                ; Sdram_Control_4Port:sdram0|mADDR[15]                                                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[15]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.720 ns                 ;
; 0.706 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg4 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.737 ns                 ;
; 0.707 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg3 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.738 ns                 ;
; 0.707 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[5]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.721 ns                 ;
; 0.709 ns                                ; Sdram_Control_4Port:sdram0|mADDR[22]                                                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[22]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.724 ns                 ;
; 0.709 ns                                ; Sdram_Control_4Port:sdram0|command:command1|CAS_N                                                                                                               ; Sdram_Control_4Port:sdram0|CAS_N                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.723 ns                 ;
; 0.711 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg4 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.742 ns                 ;
; 0.714 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg6 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.745 ns                 ;
; 0.714 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg5 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.745 ns                 ;
; 0.718 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_qdb:rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.735 ns                 ;
; 0.718 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.733 ns                 ;
; 0.720 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~porta_address_reg7 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.031 ns                   ; 0.751 ns                 ;
; 0.721 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.736 ns                 ;
; 0.721 ns                                ; Sdram_Control_4Port:sdram0|RD_MASK[0]                                                                                                                           ; Sdram_Control_4Port:sdram0|Pre_RD                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.737 ns                 ;
; 0.729 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.744 ns                 ;
; 0.729 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[2]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.744 ns                 ;
; 0.731 ns                                ; Sdram_Control_4Port:sdram1|CMD[0]                                                                                                                               ; Sdram_Control_4Port:sdram1|control_interface:control1|READA                                                                                                                               ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.745 ns                 ;
; 0.732 ns                                ; Sdram_Control_4Port:sdram1|CMD[0]                                                                                                                               ; Sdram_Control_4Port:sdram1|control_interface:control1|WRITEA                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.746 ns                 ;
; 0.734 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[7]                                                                    ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.749 ns                 ;
; 0.737 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[5]                                                                    ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.752 ns                 ;
; 0.741 ns                                ; Sdram_Control_4Port:sdram1|Write                                                                                                                                ; Sdram_Control_4Port:sdram1|mWR_DONE                                                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.757 ns                 ;
; 0.744 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[0]                                                                    ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.018 ns                   ; 0.762 ns                 ;
; 0.744 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[2]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.758 ns                 ;
; 0.745 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.759 ns                 ;
; 0.746 ns                                ; Sdram_Control_4Port:sdram1|Write                                                                                                                                ; Sdram_Control_4Port:sdram1|IN_REQ                                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.762 ns                 ;
; 0.746 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1]                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.760 ns                 ;
; 0.775 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|WRITEA                                                                                                    ; Sdram_Control_4Port:sdram0|command:command1|do_writea                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.791 ns                 ;
; 0.778 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[1]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[1]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.794 ns                 ;
; 0.778 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[1]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[1]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.794 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[7]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[7]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[11]                                                                                                 ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[11]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[9]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[9]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[13]                                                                                                 ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[13]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[13]                                                                                                 ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[13]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[11]                                                                                                 ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[11]                                                                                                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[9]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[9]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.779 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[7]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[7]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.795 ns                 ;
; 0.781 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|p0addr                                                     ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.797 ns                 ;
; 0.785 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.801 ns                 ;
; 0.786 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.787 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[11]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[3]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.803 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram1|command:command1|do_load_mode                                                                                                        ; Sdram_Control_4Port:sdram1|command:command1|CAS_N                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[16]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[8]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|REF_REQ                                                                                                   ; Sdram_Control_4Port:sdram1|command:command1|do_writea                                                                                                                                     ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.790 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.806 ns                 ;
; 0.791 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[13]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|SA[5]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.807 ns                 ;
; 0.792 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[8]                                                                                                  ; Sdram_Control_4Port:sdram1|command:command1|SA[0]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.808 ns                 ;
; 0.792 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|p0addr                                                     ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.808 ns                 ;
; 0.793 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                             ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.809 ns                 ;
; 0.794 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|SADDR[21]                                                                                                 ; Sdram_Control_4Port:sdram0|command:command1|BA[1]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.810 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[8]                                                                                                                         ; Sdram_Control_4Port:sdram1|rWR1_ADDR[8]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[8]                                                                                                                         ; Sdram_Control_4Port:sdram0|rRD1_ADDR[8]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[0]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[0]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.795 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[0]                                                                                                  ; Sdram_Control_4Port:sdram0|control_interface:control1|timer[0]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.796 ns                                ; Sdram_Control_4Port:sdram1|command:command1|rw_shift[1]                                                                                                         ; Sdram_Control_4Port:sdram1|command:command1|rw_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.796 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[12]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[4]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.796 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[4]                                                                                                               ; Sdram_Control_4Port:sdram0|SA[4]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.796 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[2]                                                                                                               ; Sdram_Control_4Port:sdram0|SA[2]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.796 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[5]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[4]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.797 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[10]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[2]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.813 ns                 ;
; 0.797 ns                                ; Sdram_Control_4Port:sdram0|command:command1|rw_shift[1]                                                                                                         ; Sdram_Control_4Port:sdram0|command:command1|rw_shift[0]                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.813 ns                 ;
; 0.797 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[9]                                                                                                               ; Sdram_Control_4Port:sdram0|SA[9]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.813 ns                 ;
; 0.797 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[2]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[1]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.813 ns                 ;
; 0.798 ns                                ; Sdram_Control_4Port:sdram0|command:command1|SA[0]                                                                                                               ; Sdram_Control_4Port:sdram0|SA[0]                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.798 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.798 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                 ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.798 ns                                ; Sdram_Control_4Port:sdram1|command:command1|command_delay[1]                                                                                                    ; Sdram_Control_4Port:sdram1|command:command1|command_delay[0]                                                                                                                              ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.801 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[10]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[10]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.801 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.801 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[9]                                                                                             ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[9]                                                                                                                       ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|SADDR[17]                                                                                                 ; Sdram_Control_4Port:sdram1|command:command1|SA[9]                                                                                                                                         ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[12]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[12]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram1|rWR1_ADDR[21]                                                                                                                        ; Sdram_Control_4Port:sdram1|rWR1_ADDR[21]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[11]                                                                                            ; Sdram_Control_4Port:sdram0|control_interface:control1|init_timer[11]                                                                                                                      ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram0|command:command1|RAS_N                                                                                                               ; Sdram_Control_4Port:sdram0|RAS_N                                                                                                                                                          ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[8]                                                                                                                         ; Sdram_Control_4Port:sdram1|rRD1_ADDR[8]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[16]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[16]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[14]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[14]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[9]                                                                                                                         ; Sdram_Control_4Port:sdram1|rRD1_ADDR[9]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[11]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[11]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[21]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[21]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[20]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[20]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|rRD1_ADDR[18]                                                                                                                        ; Sdram_Control_4Port:sdram1|rRD1_ADDR[18]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[10]                                                                                                                        ; Sdram_Control_4Port:sdram0|rRD1_ADDR[10]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[15]                                                                                                                        ; Sdram_Control_4Port:sdram0|rRD1_ADDR[15]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[12]                                                                                                                        ; Sdram_Control_4Port:sdram0|rRD1_ADDR[12]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rRD1_ADDR[21]                                                                                                                        ; Sdram_Control_4Port:sdram0|rRD1_ADDR[21]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[14]                                                                                                                        ; Sdram_Control_4Port:sdram0|rWR1_ADDR[14]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[9]                                                                                                                         ; Sdram_Control_4Port:sdram0|rWR1_ADDR[9]                                                                                                                                                   ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[11]                                                                                                                        ; Sdram_Control_4Port:sdram0|rWR1_ADDR[11]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[21]                                                                                                                        ; Sdram_Control_4Port:sdram0|rWR1_ADDR[21]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|rWR1_ADDR[20]                                                                                                                        ; Sdram_Control_4Port:sdram0|rWR1_ADDR[20]                                                                                                                                                  ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                 ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[4]                                                                                                  ; Sdram_Control_4Port:sdram1|control_interface:control1|timer[4]                                                                                                                            ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; sdram_pll:sdram_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                             ;                                                                                                                                                                                           ;                                                    ;                                                    ;                            ;                            ;                          ;
 


 
; Clock Hold: 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
 
; Minimum Slack                           ; From                                                                                                                                           ; To                                                                                                                                                                                       ; From Clock                                     ; To Clock                                       ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
 
; 0.528 ns                                ; touch_tcon:vga0|mvd                                                                                                                            ; touch_tcon:vga0|oVD                                                                                                                                                                      ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.544 ns                 ;
; 0.537 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.553 ns                 ;
; 0.538 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.554 ns                 ;
; 0.595 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_B[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.611 ns                 ;
; 0.597 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_G[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.613 ns                 ;
; 0.597 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_G[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.613 ns                 ;
; 0.600 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_R[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.616 ns                 ;
; 0.600 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_B[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.616 ns                 ;
; 0.601 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_G[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.617 ns                 ;
; 0.601 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_B[5]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.617 ns                 ;
; 0.603 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_R[2]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.619 ns                 ;
; 0.603 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_R[1]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.619 ns                 ;
; 0.604 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_R[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.620 ns                 ;
; 0.605 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_G[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.621 ns                 ;
; 0.605 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_B[4]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.621 ns                 ;
; 0.682 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.043 ns                   ; 0.725 ns                 ;
; 0.693 ns                                ; touch_tcon:vga0|mhd                                                                                                                            ; touch_tcon:vga0|oHD                                                                                                                                                                      ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.019 ns                   ; 0.712 ns                 ;
; 0.697 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.713 ns                 ;
; 0.698 ns                                ; touch_tcon:vga0|mden                                                                                                                           ; touch_tcon:vga0|oDEN                                                                                                                                                                     ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.715 ns                 ;
; 0.709 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.724 ns                 ;
; 0.723 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.738 ns                 ;
; 0.723 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.738 ns                 ;
; 0.731 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.746 ns                 ;
; 0.785 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.801 ns                 ;
; 0.786 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.786 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.787 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.803 ns                 ;
; 0.788 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff      ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.804 ns                 ;
; 0.793 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.809 ns                 ;
; 0.799 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff      ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.815 ns                 ;
; 0.801 ns                                ; touch_tcon:vga0|y_cnt[7]                                                                                                                       ; touch_tcon:vga0|y_cnt[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.801 ns                                ; touch_tcon:vga0|x_cnt[6]                                                                                                                       ; touch_tcon:vga0|x_cnt[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.802 ns                                ; touch_tcon:vga0|x_cnt[8]                                                                                                                       ; touch_tcon:vga0|x_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.805 ns                                ; touch_tcon:vga0|y_cnt[5]                                                                                                                       ; touch_tcon:vga0|y_cnt[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.809 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.812 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.828 ns                 ;
; 0.812 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.828 ns                 ;
; 0.812 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.828 ns                 ;
; 0.813 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.814 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.818 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.834 ns                 ;
; 0.818 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.834 ns                 ;
; 0.818 ns                                ; touch_tcon:vga0|x_cnt[1]                                                                                                                       ; touch_tcon:vga0|x_cnt[1]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.834 ns                 ;
; 0.818 ns                                ; touch_tcon:vga0|x_cnt[4]                                                                                                                       ; touch_tcon:vga0|x_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.834 ns                 ;
; 0.823 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_B[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.840 ns                 ;
; 0.823 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.839 ns                 ;
; 0.823 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.839 ns                 ;
; 0.824 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_B[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.841 ns                 ;
; 0.825 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_R[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.842 ns                 ;
; 0.826 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_B[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.843 ns                 ;
; 0.827 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.842 ns                 ;
; 0.829 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_R[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.846 ns                 ;
; 0.831 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_R[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.848 ns                 ;
; 0.832 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_B[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 0.849 ns                 ;
; 0.838 ns                                ; touch_tcon:vga0|y_cnt[6]                                                                                                                       ; touch_tcon:vga0|y_cnt[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; touch_tcon:vga0|y_cnt[8]                                                                                                                       ; touch_tcon:vga0|y_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; touch_tcon:vga0|y_cnt[4]                                                                                                                       ; touch_tcon:vga0|y_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; touch_tcon:vga0|y_cnt[1]                                                                                                                       ; touch_tcon:vga0|y_cnt[1]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; touch_tcon:vga0|x_cnt[9]                                                                                                                       ; touch_tcon:vga0|x_cnt[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; touch_tcon:vga0|x_cnt[7]                                                                                                                       ; touch_tcon:vga0|x_cnt[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.845 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.846 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.849 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.849 ns                                ; touch_tcon:vga0|x_cnt[0]                                                                                                                       ; touch_tcon:vga0|x_cnt[0]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.850 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.850 ns                                ; touch_tcon:vga0|x_cnt[2]                                                                                                                       ; touch_tcon:vga0|x_cnt[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.866 ns                 ;
; 0.855 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.871 ns                 ;
; 0.857 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.873 ns                 ;
; 0.857 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.872 ns                 ;
; 0.857 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.872 ns                 ;
; 0.858 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.874 ns                 ;
; 0.858 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.874 ns                 ;
; 0.859 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.875 ns                 ;
; 0.861 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.877 ns                 ;
; 0.862 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.878 ns                 ;
; 0.874 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.015 ns                   ; 0.889 ns                 ;
; 0.924 ns                                ; touch_tcon:vga0|y_cnt[9]                                                                                                                       ; touch_tcon:vga0|y_cnt[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.940 ns                 ;
; 0.951 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[9]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 0.981 ns                 ;
; 0.952 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.043 ns                   ; 0.995 ns                 ;
; 0.954 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.043 ns                   ; 0.997 ns                 ;
; 0.958 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 0.988 ns                 ;
; 0.964 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 0.980 ns                 ;
; 0.965 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.058 ns                   ; 1.023 ns                 ;
; 0.966 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.043 ns                   ; 1.009 ns                 ;
; 0.966 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.058 ns                   ; 1.024 ns                 ;
; 0.972 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.002 ns                 ;
; 0.973 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.003 ns                 ;
; 0.974 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.004 ns                 ;
; 0.979 ns                                ; touch_tcon:vga0|y_cnt[9]                                                                                                                       ; touch_tcon:vga0|mvd                                                                                                                                                                      ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 0.993 ns                 ;
; 0.979 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.009 ns                 ;
; 0.986 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[4]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.016 ns                 ;
; 0.987 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.017 ns                 ;
; 0.990 ns                                ; touch_tcon:vga0|x_cnt[3]                                                                                                                       ; touch_tcon:vga0|x_cnt[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.006 ns                 ;
; 0.991 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[7]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.021 ns                 ;
; 0.991 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.007 ns                 ;
; 0.993 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.009 ns                 ;
; 0.999 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[5]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.029 ns                 ;
; 1.001 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[0]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.031 ns                 ;
; 1.001 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[3]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.031 ns                 ;
; 1.025 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.041 ns                 ;
; 1.065 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.095 ns                 ;
; 1.072 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_G[3]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 1.089 ns                 ;
; 1.073 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_G[6]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 1.090 ns                 ;
; 1.075 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_G[0]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 1.092 ns                 ;
; 1.078 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_G[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 1.095 ns                 ;
; 1.102 ns                                ; Binary:binary0|oDATA[9]                                                                                                                        ; touch_tcon:vga0|oLCD_R[7]                                                                                                                                                                ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.017 ns                   ; 1.119 ns                 ;
; 1.133 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[8]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.163 ns                 ;
; 1.136 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[1]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.166 ns                 ;
; 1.151 ns                                ; touch_tcon:vga0|y_cnt[2]                                                                                                                       ; touch_tcon:vga0|mvd                                                                                                                                                                      ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 1.165 ns                 ;
; 1.171 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff      ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.187 ns                 ;
; 1.181 ns                                ; touch_tcon:vga0|y_cnt[3]                                                                                                                       ; touch_tcon:vga0|y_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.197 ns                 ;
; 1.182 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff      ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.198 ns                 ;
; 1.184 ns                                ; touch_tcon:vga0|y_cnt[7]                                                                                                                       ; touch_tcon:vga0|y_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.200 ns                 ;
; 1.184 ns                                ; touch_tcon:vga0|x_cnt[6]                                                                                                                       ; touch_tcon:vga0|x_cnt[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.200 ns                 ;
; 1.185 ns                                ; touch_tcon:vga0|x_cnt[8]                                                                                                                       ; touch_tcon:vga0|x_cnt[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.201 ns                 ;
; 1.186 ns                                ; touch_tcon:vga0|y_cnt[0]                                                                                                                       ; touch_tcon:vga0|y_cnt[1]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.202 ns                 ;
; 1.187 ns                                ; touch_tcon:vga0|x_cnt[5]                                                                                                                       ; touch_tcon:vga0|x_cnt[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.203 ns                 ;
; 1.195 ns                                ; touch_tcon:vga0|y_cnt[3]                                                                                                                       ; touch_tcon:vga0|y_cnt[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.211 ns                 ;
; 1.195 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.211 ns                 ;
; 1.196 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.212 ns                 ;
; 1.196 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.212 ns                 ;
; 1.197 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.213 ns                 ;
; 1.197 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.213 ns                 ;
; 1.201 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.217 ns                 ;
; 1.201 ns                                ; touch_tcon:vga0|x_cnt[1]                                                                                                                       ; touch_tcon:vga0|x_cnt[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.217 ns                 ;
; 1.203 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.219 ns                 ;
; 1.224 ns                                ; touch_tcon:vga0|y_cnt[6]                                                                                                                       ; touch_tcon:vga0|y_cnt[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.240 ns                 ;
; 1.224 ns                                ; touch_tcon:vga0|y_cnt[4]                                                                                                                       ; touch_tcon:vga0|y_cnt[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.240 ns                 ;
; 1.224 ns                                ; touch_tcon:vga0|x_cnt[7]                                                                                                                       ; touch_tcon:vga0|x_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.240 ns                 ;
; 1.226 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[6]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.037 ns                   ; 1.263 ns                 ;
; 1.232 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.248 ns                 ;
; 1.235 ns                                ; touch_tcon:vga0|x_cnt[0]                                                                                                                       ; touch_tcon:vga0|x_cnt[1]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.251 ns                 ;
; 1.236 ns                                ; touch_tcon:vga0|x_cnt[2]                                                                                                                       ; touch_tcon:vga0|x_cnt[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.252 ns                 ;
; 1.237 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.253 ns                 ;
; 1.237 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.253 ns                 ;
; 1.240 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.058 ns                   ; 1.298 ns                 ;
; 1.242 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff      ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.258 ns                 ;
; 1.244 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.260 ns                 ;
; 1.245 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg5 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.058 ns                   ; 1.303 ns                 ;
; 1.245 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.261 ns                 ;
; 1.247 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.058 ns                   ; 1.305 ns                 ;
; 1.247 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg7 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.022 ns                   ; 1.269 ns                 ;
; 1.248 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.264 ns                 ;
; 1.252 ns                                ; touch_tcon:vga0|y_cnt[3]                                                                                                                       ; touch_tcon:vga0|y_cnt[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.268 ns                 ;
; 1.253 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg4 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.022 ns                   ; 1.275 ns                 ;
; 1.253 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff      ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.269 ns                 ;
; 1.255 ns                                ; touch_tcon:vga0|x_cnt[6]                                                                                                                       ; touch_tcon:vga0|x_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.271 ns                 ;
; 1.258 ns                                ; touch_tcon:vga0|x_cnt[5]                                                                                                                       ; touch_tcon:vga0|x_cnt[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.274 ns                 ;
; 1.260 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg3 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.022 ns                   ; 1.282 ns                 ;
; 1.265 ns                                ; touch_tcon:vga0|y_cnt[3]                                                                                                                       ; touch_tcon:vga0|mvd                                                                                                                                                                      ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.014 ns                   ; 1.279 ns                 ;
; 1.266 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.282 ns                 ;
; 1.267 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.283 ns                 ;
; 1.267 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.283 ns                 ;
; 1.268 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.284 ns                 ;
; 1.268 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.284 ns                 ;
; 1.272 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.288 ns                 ;
; 1.272 ns                                ; touch_tcon:vga0|x_cnt[1]                                                                                                                       ; touch_tcon:vga0|x_cnt[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.288 ns                 ;
; 1.274 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.290 ns                 ;
; 1.276 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg6 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.022 ns                   ; 1.298 ns                 ;
; 1.277 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.022 ns                   ; 1.299 ns                 ;
; 1.280 ns                                ; touch_tcon:vga0|y_cnt[5]                                                                                                                       ; touch_tcon:vga0|y_cnt[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.296 ns                 ;
; 1.295 ns                                ; touch_tcon:vga0|y_cnt[6]                                                                                                                       ; touch_tcon:vga0|y_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.311 ns                 ;
; 1.295 ns                                ; touch_tcon:vga0|x_cnt[7]                                                                                                                       ; touch_tcon:vga0|x_cnt[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.311 ns                 ;
; 1.303 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg1 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.022 ns                   ; 1.325 ns                 ;
; 1.306 ns                                ; touch_tcon:vga0|x_cnt[0]                                                                                                                       ; touch_tcon:vga0|x_cnt[2]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.322 ns                 ;
; 1.307 ns                                ; touch_tcon:vga0|x_cnt[2]                                                                                                                       ; touch_tcon:vga0|x_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.323 ns                 ;
; 1.308 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.324 ns                 ;
; 1.313 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff      ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.329 ns                 ;
; 1.315 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a2~porta_address_reg2 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.022 ns                   ; 1.337 ns                 ;
; 1.315 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.331 ns                 ;
; 1.319 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.335 ns                 ;
; 1.321 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.337 ns                 ;
; 1.324 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff      ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.340 ns                 ;
; 1.326 ns                                ; touch_tcon:vga0|x_cnt[6]                                                                                                                       ; touch_tcon:vga0|x_cnt[9]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.342 ns                 ;
; 1.329 ns                                ; touch_tcon:vga0|x_cnt[5]                                                                                                                       ; touch_tcon:vga0|x_cnt[8]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.345 ns                 ;
; 1.331 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.347 ns                 ;
; 1.335 ns                                ; touch_tcon:vga0|y_cnt[0]                                                                                                                       ; touch_tcon:vga0|y_cnt[0]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.351 ns                 ;
; 1.336 ns                                ; touch_tcon:vga0|x_cnt[5]                                                                                                                       ; touch_tcon:vga0|x_cnt[5]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.352 ns                 ;
; 1.337 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.353 ns                 ;
; 1.338 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.354 ns                 ;
; 1.338 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.354 ns                 ;
; 1.339 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[1] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[5]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.355 ns                 ;
; 1.343 ns                                ; touch_tcon:vga0|x_cnt[1]                                                                                                                       ; touch_tcon:vga0|x_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.359 ns                 ;
; 1.351 ns                                ; touch_tcon:vga0|y_cnt[5]                                                                                                                       ; touch_tcon:vga0|y_cnt[7]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.367 ns                 ;
; 1.364 ns                                ; touch_tcon:vga0|x_cnt[4]                                                                                                                       ; touch_tcon:vga0|x_cnt[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.380 ns                 ;
; 1.366 ns                                ; touch_tcon:vga0|y_cnt[1]                                                                                                                       ; touch_tcon:vga0|y_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.382 ns                 ;
; 1.368 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a8~porta_address_reg8 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.398 ns                 ;
; 1.373 ns                                ; touch_tcon:vga0|x_cnt[3]                                                                                                                       ; touch_tcon:vga0|x_cnt[4]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.389 ns                 ;
; 1.374 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.390 ns                 ;
; 1.377 ns                                ; touch_tcon:vga0|x_cnt[0]                                                                                                                       ; touch_tcon:vga0|x_cnt[3]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.393 ns                 ;
; 1.379 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[6]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.395 ns                 ;
; 1.383 ns                                ; touch_tcon:vga0|y_cnt[4]                                                                                                                       ; touch_tcon:vga0|y_cnt[6]                                                                                                                                                                 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.399 ns                 ;
; 1.384 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity_ff      ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.400 ns                 ;
; 1.384 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdptr_g[2]                                                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.030 ns                   ; 1.414 ns                 ;
; 1.386 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7]                                           ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; vga_pll:vga_pll0|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.016 ns                   ; 1.402 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                            ;                                                                                                                                                                                          ;                                                ;                                                ;                            ;                            ;                          ;
 


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'GPIO_CLKIN_N1'                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                           ; From                                                                                                                                           ; To                                                                                                                                                                                        ; From Clock    ; To Clock      ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+-----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+----------------------------+----------------------------+--------------------------+
; 0.391 ns                                ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                 ; CCD_Capture:capture0|mCCD_FVAL                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; CCD_Capture:capture0|mSTART                                                                                                                    ; CCD_Capture:capture0|mSTART                                                                                                                                                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; CCD_Capture:capture0|Frame_Cont[0]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[0]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.646 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[13]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a11~porta_datain_reg2                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.695 ns                 ;
; 0.646 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[20]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.695 ns                 ;
; 0.646 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[17]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a4~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.695 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[0]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a0~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[9]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a8~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[5]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a4~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.648 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[14]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a2~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.697 ns                 ;
; 0.651 ns                                ; RAW2RGB:raw0|wData1_d2[2]                                                                                                                      ; RAW2RGB:raw0|rGreen[3]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.667 ns                 ;
; 0.653 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[6]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a6~porta_datain_reg1                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.702 ns                 ;
; 0.654 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[16]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a3~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.703 ns                 ;
; 0.655 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[21]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a8~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.704 ns                 ;
; 0.658 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[12]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a0~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.707 ns                 ;
; 0.658 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[10]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a10~porta_datain_reg1                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.707 ns                 ;
; 0.664 ns                                ; RAW2RGB:raw0|wData1_d1[9]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[9]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.680 ns                 ;
; 0.668 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[22]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a10~porta_datain_reg3                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.717 ns                 ;
; 0.675 ns                                ; RAW2RGB:raw0|wData1_d1[4]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[4]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.691 ns                 ;
; 0.675 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~portb_address_reg4 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.734 ns                 ;
; 0.677 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~portb_address_reg3 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.736 ns                 ;
; 0.681 ns                                ; RAW2RGB:raw0|wData2_d1[11]                                                                                                                     ; RAW2RGB:raw0|wData2_d2[11]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.697 ns                 ;
; 0.684 ns                                ; RAW2RGB:raw0|wData2_d1[2]                                                                                                                      ; RAW2RGB:raw0|wData2_d2[2]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.700 ns                 ;
; 0.686 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg6 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.745 ns                 ;
; 0.686 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[9]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg9                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.742 ns                 ;
; 0.690 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~portb_address_reg2 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.749 ns                 ;
; 0.691 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg4 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.750 ns                 ;
; 0.692 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg2 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.751 ns                 ;
; 0.693 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg7 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.752 ns                 ;
; 0.693 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg5 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.752 ns                 ;
; 0.694 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~portb_address_reg6 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.753 ns                 ;
; 0.695 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[4]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg4                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.751 ns                 ;
; 0.698 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~portb_address_reg7 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 0.757 ns                 ;
; 0.703 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg8                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.759 ns                 ;
; 0.703 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[7]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg7                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.759 ns                 ;
; 0.705 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[6]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.721 ns                 ;
; 0.709 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[4]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.725 ns                 ;
; 0.712 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg6                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.768 ns                 ;
; 0.714 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[9]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg9                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.742 ns                 ;
; 0.721 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[5]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg5                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.777 ns                 ;
; 0.723 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[4]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg4                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.751 ns                 ;
; 0.730 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[8]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.746 ns                 ;
; 0.731 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg8                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.759 ns                 ;
; 0.731 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[7]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg7                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.759 ns                 ;
; 0.738 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[3]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.754 ns                 ;
; 0.740 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg6                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.768 ns                 ;
; 0.749 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[5]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg5                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.777 ns                 ;
; 0.786 ns                                ; RAW2RGB:raw0|wData0_d2[8]                                                                                                                      ; RAW2RGB:raw0|rRed[8]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.802 ns                 ;
; 0.789 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.805 ns                 ;
; 0.790 ns                                ; RAW2RGB:raw0|wData1_d2[10]                                                                                                                     ; RAW2RGB:raw0|rRed[10]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.806 ns                 ;
; 0.790 ns                                ; RAW2RGB:raw0|wData1_d2[4]                                                                                                                      ; RAW2RGB:raw0|rRed[4]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.806 ns                 ;
; 0.794 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.810 ns                 ;
; 0.795 ns                                ; CCD_Capture:capture0|Frame_Cont[16]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[16]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.811 ns                 ;
; 0.798 ns                                ; RAW2RGB:raw0|wData1_d2[7]                                                                                                                      ; RAW2RGB:raw0|rGreen[8]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.799 ns                                ; CCD_Capture:capture0|Y_Cont[0]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[0]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.815 ns                 ;
; 0.801 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.817 ns                 ;
; 0.803 ns                                ; RAW2RGB:raw0|wData1_d1[5]                                                                                                                      ; RAW2RGB:raw0|rBlue[5]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.819 ns                 ;
; 0.803 ns                                ; CCD_Capture:capture0|X_Cont[0]                                                                                                                 ; CCD_Capture:capture0|X_Cont[0]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.819 ns                 ;
; 0.805 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|Y_Cont[1]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[1]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|X_Cont[1]                                                                                                                 ; CCD_Capture:capture0|X_Cont[1]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|Frame_Cont[31]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[31]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; CCD_Capture:capture0|Frame_Cont[17]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[17]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.806 ns                                ; RAW2RGB:raw0|wData1_d1[10]                                                                                                                     ; RAW2RGB:raw0|rBlue[10]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[13]                                                                                                                ; CCD_Capture:capture0|Y_Cont[13]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[15]                                                                                                                ; CCD_Capture:capture0|Y_Cont[15]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[14]                                                                                                                ; CCD_Capture:capture0|Y_Cont[14]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[9]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[9]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[11]                                                                                                                ; CCD_Capture:capture0|Y_Cont[11]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[4]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[4]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Y_Cont[2]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[2]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[7]                                                                                                                 ; CCD_Capture:capture0|X_Cont[7]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[2]                                                                                                                 ; CCD_Capture:capture0|X_Cont[2]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[13]                                                                                                                ; CCD_Capture:capture0|X_Cont[13]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[11]                                                                                                                ; CCD_Capture:capture0|X_Cont[11]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[4]                                                                                                                 ; CCD_Capture:capture0|X_Cont[4]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[14]                                                                                                                ; CCD_Capture:capture0|X_Cont[14]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[15]                                                                                                                ; CCD_Capture:capture0|X_Cont[15]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|X_Cont[9]                                                                                                                 ; CCD_Capture:capture0|X_Cont[9]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[30]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[30]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[29]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[29]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[27]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[27]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[25]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[25]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[23]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[23]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[20]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[20]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[18]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[18]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[15]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[15]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[14]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[14]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; CCD_Capture:capture0|Frame_Cont[13]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[13]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.807 ns                                ; RAW2RGB:raw0|wData1_d2[3]                                                                                                                      ; RAW2RGB:raw0|rGreen[4]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.823 ns                 ;
; 0.808 ns                                ; RAW2RGB:raw0|wData1_d2[9]                                                                                                                      ; RAW2RGB:raw0|rRed[9]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.824 ns                 ;
; 0.808 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.824 ns                 ;
; 0.809 ns                                ; RAW2RGB:raw0|wData1_d1[3]                                                                                                                      ; RAW2RGB:raw0|rBlue[3]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.809 ns                                ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.809 ns                                ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.810 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.812 ns                                ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.828 ns                 ;
; 0.813 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.814 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[1]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; CCD_Capture:capture0|Y_Cont[7]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[7]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.816 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[7]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[7]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.817 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.833 ns                 ;
; 0.821 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.837 ns                 ;
; 0.821 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.837 ns                 ;
; 0.822 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[2]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[2]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.822 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[0]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[0]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.838 ns                 ;
; 0.824 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[9]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[9]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.840 ns                 ;
; 0.825 ns                                ; RAW2RGB:raw0|wData1_d2[3]                                                                                                                      ; RAW2RGB:raw0|rRed[3]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.018 ns                   ; 0.843 ns                 ;
; 0.825 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.841 ns                 ;
; 0.826 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[9]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.842 ns                 ;
; 0.828 ns                                ; RAW2RGB:raw0|wData1_d2[8]                                                                                                                      ; RAW2RGB:raw0|rGreen[9]                                                                                                                                                                    ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.844 ns                 ;
; 0.830 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[5]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[5]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.846 ns                 ;
; 0.830 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff      ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|parity_ff                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.846 ns                 ;
; 0.831 ns                                ; RAW2RGB:raw0|wData2_d1[4]                                                                                                                      ; RAW2RGB:raw0|rRed[4]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.847 ns                 ;
; 0.838 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[12]                                                                                                                ; CCD_Capture:capture0|Y_Cont[12]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[10]                                                                                                                ; CCD_Capture:capture0|Y_Cont[10]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Y_Cont[3]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[3]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[3]                                                                                                                 ; CCD_Capture:capture0|X_Cont[3]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[10]                                                                                                                ; CCD_Capture:capture0|X_Cont[10]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[12]                                                                                                                ; CCD_Capture:capture0|X_Cont[12]                                                                                                                                                           ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|X_Cont[8]                                                                                                                 ; CCD_Capture:capture0|X_Cont[8]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[28]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[28]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[26]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[26]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[19]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[19]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[12]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[12]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Y_Cont[6]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[6]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Y_Cont[5]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[5]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|X_Cont[6]                                                                                                                 ; CCD_Capture:capture0|X_Cont[6]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|X_Cont[5]                                                                                                                 ; CCD_Capture:capture0|X_Cont[5]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Frame_Cont[22]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[22]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; CCD_Capture:capture0|Frame_Cont[21]                                                                                                            ; CCD_Capture:capture0|Frame_Cont[21]                                                                                                                                                       ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.841 ns                                ; RAW2RGB:raw0|wData1_d1[6]                                                                                                                      ; RAW2RGB:raw0|rBlue[6]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.857 ns                 ;
; 0.842 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.842 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.842 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.843 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.859 ns                 ;
; 0.843 ns                                ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.859 ns                 ;
; 0.843 ns                                ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.859 ns                 ;
; 0.845 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.846 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[3]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; CCD_Capture:capture0|Y_Cont[8]                                                                                                                 ; CCD_Capture:capture0|Y_Cont[8]                                                                                                                                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                             ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                                        ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.848 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[8]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.864 ns                 ;
; 0.853 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.869 ns                 ;
; 0.853 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.869 ns                 ;
; 0.853 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|delayed_wrptr_g[2]                                                                   ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.031 ns                   ; 0.884 ns                 ;
; 0.854 ns                                ; RAW2RGB:raw0|wData0_d1[11]                                                                                                                     ; RAW2RGB:raw0|wData0_d2[11]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.014 ns                   ; 0.868 ns                 ;
; 0.854 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[3]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[3]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[5] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[9]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.854 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.870 ns                 ;
; 0.855 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[8]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.871 ns                 ;
; 0.856 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[6]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.872 ns                 ;
; 0.857 ns                                ; RAW2RGB:raw0|wData1_d2[11]                                                                                                                     ; RAW2RGB:raw0|rRed[11]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.873 ns                 ;
; 0.861 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[4]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[4]                                                                  ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.877 ns                 ;
; 0.862 ns                                ; RAW2RGB:raw0|wData0_d1[10]                                                                                                                     ; RAW2RGB:raw0|wData0_d2[10]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.878 ns                 ;
; 0.864 ns                                ; RAW2RGB:raw0|wData0_d1[9]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[9]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.880 ns                 ;
; 0.864 ns                                ; RAW2RGB:raw0|wData1_d1[2]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[2]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.880 ns                 ;
; 0.867 ns                                ; RAW2RGB:raw0|wData0_d1[3]                                                                                                                      ; RAW2RGB:raw0|wData0_d2[3]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.883 ns                 ;
; 0.869 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.885 ns                 ;
; 0.871 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.887 ns                 ;
; 0.872 ns                                ; RAW2RGB:raw0|wData1_d1[5]                                                                                                                      ; RAW2RGB:raw0|wData1_d2[5]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.888 ns                 ;
; 0.872 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2]                                            ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.888 ns                 ;
; 0.889 ns                                ; RAW2RGB:raw0|wData2_d1[5]                                                                                                                      ; RAW2RGB:raw0|wData2_d2[5]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.015 ns                   ; 0.904 ns                 ;
; 0.910 ns                                ; CCD_Capture:capture0|mCCD_DATA[3]                                                                                                              ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a3~porta_datain_reg0                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.027 ns                   ; 0.937 ns                 ;
; 0.916 ns                                ; RAW2RGB:raw0|wData0_d2[2]                                                                                                                      ; RAW2RGB:raw0|rRed[2]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.932 ns                 ;
; 0.917 ns                                ; RAW2RGB:raw0|wData0_d2[4]                                                                                                                      ; RAW2RGB:raw0|rRed[4]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.933 ns                 ;
; 0.919 ns                                ; RAW2RGB:raw0|wData0_d2[10]                                                                                                                     ; RAW2RGB:raw0|rRed[10]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.935 ns                 ;
; 0.921 ns                                ; RAW2RGB:raw0|wData0_d2[9]                                                                                                                      ; RAW2RGB:raw0|rRed[9]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.937 ns                 ;
; 0.925 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[2]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a2~porta_datain_reg1                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 0.974 ns                 ;
; 0.935 ns                                ; RAW2RGB:raw0|wData2_d1[2]                                                                                                                      ; RAW2RGB:raw0|rRed[2]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.951 ns                 ;
; 0.936 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[4]             ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a3~porta_datain_reg1                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.060 ns                   ; 0.996 ns                 ;
; 0.937 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg2 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.074 ns                   ; 1.011 ns                 ;
; 0.940 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg1                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 0.996 ns                 ;
; 0.941 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg0 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 1.000 ns                 ;
; 0.944 ns                                ; RAW2RGB:raw0|wData2_d1[9]                                                                                                                      ; RAW2RGB:raw0|rRed[9]                                                                                                                                                                      ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.016 ns                   ; 0.960 ns                 ;
; 0.944 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[4] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg4 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.074 ns                   ; 1.018 ns                 ;
; 0.945 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[19]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_datain_reg2                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.042 ns                   ; 0.987 ns                 ;
; 0.953 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[6] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg6 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.074 ns                   ; 1.027 ns                 ;
; 0.956 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[27]            ; RAW2RGB:raw0|wData0_d1[3]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.023 ns                   ; 0.979 ns                 ;
; 0.959 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[0]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~portb_address_reg0                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.056 ns                   ; 1.015 ns                 ;
; 0.960 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~portb_address_reg7 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.069 ns                   ; 1.029 ns                 ;
; 0.960 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[33]            ; RAW2RGB:raw0|wData0_d1[9]                                                                                                                                                                 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.023 ns                   ; 0.983 ns                 ;
; 0.961 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[0] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~portb_address_reg0 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.059 ns                   ; 1.020 ns                 ;
; 0.963 ns                                ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[2] ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a0~portb_address_reg2 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.069 ns                   ; 1.032 ns                 ;
; 0.967 ns                                ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_egc:wrptr_gp|counter_ffa[7] ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a9~portb_address_reg7 ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.074 ns                   ; 1.041 ns                 ;
; 0.968 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|cntr_opf:cntr1|safe_q[1]                       ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a7~porta_address_reg1                               ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.028 ns                   ; 0.996 ns                 ;
; 0.970 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[10]            ; RAW2RGB:raw0|wData2_d1[10]                                                                                                                                                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.023 ns                   ; 0.993 ns                 ;
; 0.971 ns                                ; RAW2RGB:raw0|wData1_d1[4]                                                                                                                      ; RAW2RGB:raw0|rBlue[4]                                                                                                                                                                     ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.017 ns                   ; 0.988 ns                 ;
; 0.972 ns                                ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|q_b[18]            ; RAW2RGB:raw0|Line_Buffer:L1|altshift_taps:altshift_taps_component|shift_taps_0jn:auto_generated|altsyncram_sj81:altsyncram2|ram_block3a6~porta_datain_reg3                                ; GPIO_CLKIN_N1 ; GPIO_CLKIN_N1 ; 0.000 ns                   ; 0.049 ns                   ; 1.021 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                            ;                                                                                                                                                                                           ;               ;               ;                            ;                            ;                          ;
+-----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+----------------------------+----------------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'iCLK_50'                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------------------+-----------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                           ; From                                                            ; To                                                              ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+-----------------------------------------+-----------------------------------------------------------------+-----------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; 0.391 ns                                ; rClk[0]                                                         ; rClk[0]                                                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SCLK           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SCLK           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO            ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2           ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK                    ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|lut_index[0]                       ; lcd_3wire_config:lcd_config0|lut_index[0]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK         ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; lcd_3wire_config:lcd_config0|m3wire_str                         ; lcd_3wire_config:lcd_config0|m3wire_str                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Reset_Delay:reset0|Cont[0]                                      ; Reset_Delay:reset0|Cont[0]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.391 ns                                ; Reset_Delay:reset0|oRST_2                                       ; Reset_Delay:reset0|oRST_2                                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.407 ns                 ;
; 0.588 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.604 ns                 ;
; 0.596 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.612 ns                 ;
; 0.657 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[5]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[5]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.673 ns                 ;
; 0.667 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[2]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.683 ns                 ;
; 0.765 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 0.779 ns                 ;
; 0.770 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 0.784 ns                 ;
; 0.788 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[0]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[0]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.804 ns                 ;
; 0.788 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[0]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[0]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.804 ns                 ;
; 0.791 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[0]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.807 ns                 ;
; 0.796 ns                                ; Reset_Delay:reset0|Cont[12]                                     ; Reset_Delay:reset0|Cont[12]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.812 ns                 ;
; 0.797 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[12]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.813 ns                 ;
; 0.798 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[1]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[1]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.798 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[0]           ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[1]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.798 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.798 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[1]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[1]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.814 ns                 ;
; 0.800 ns                                ; Reset_Delay:reset0|Cont[0]                                      ; Reset_Delay:reset0|Cont[1]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.816 ns                 ;
; 0.802 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[13]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[13]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[14]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[14]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[13] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[13] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[14] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[14] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.802 ns                                ; Reset_Delay:reset0|Cont[3]                                      ; Reset_Delay:reset0|Cont[3]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.818 ns                 ;
; 0.803 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.819 ns                 ;
; 0.803 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.819 ns                 ;
; 0.805 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[13]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[5]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[5]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.805 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[7]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.821 ns                 ;
; 0.806 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[2]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[2]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[4]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[4]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[9]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[9]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[7]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[7]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[11]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[11]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[4]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[4]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[2]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[2]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[9]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[9]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[7]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[7]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.806 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[11] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[11] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.822 ns                 ;
; 0.807 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[2]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[2]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.823 ns                 ;
; 0.808 ns                                ; Reset_Delay:reset0|Cont[13]                                     ; Reset_Delay:reset0|Cont[13]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.824 ns                 ;
; 0.809 ns                                ; Reset_Delay:reset0|Cont[5]                                      ; Reset_Delay:reset0|Cont[5]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.809 ns                                ; Reset_Delay:reset0|Cont[7]                                      ; Reset_Delay:reset0|Cont[7]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.825 ns                 ;
; 0.810 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[0]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[0]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[3]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[3]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[9]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[9]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[10]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[21]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[21]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[23]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[23]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|m3wire_str                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; Reset_Delay:reset0|Cont[9]                                      ; Reset_Delay:reset0|Cont[9]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.810 ns                                ; Reset_Delay:reset0|Cont[10]                                     ; Reset_Delay:reset0|Cont[10]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.826 ns                 ;
; 0.812 ns                                ; lcd_3wire_config:lcd_config0|lut_index[3]                       ; lcd_3wire_config:lcd_config0|lut_index[3]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.828 ns                 ;
; 0.813 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[14]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.813 ns                                ; Reset_Delay:reset0|Cont[14]                                     ; Reset_Delay:reset0|Cont[14]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.829 ns                 ;
; 0.814 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[11]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[16]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[16]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; Reset_Delay:reset0|Cont[11]                                     ; Reset_Delay:reset0|Cont[11]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; Reset_Delay:reset0|Cont[16]                                     ; Reset_Delay:reset0|Cont[16]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.814 ns                                ; Reset_Delay:reset0|Cont[19]                                     ; Reset_Delay:reset0|Cont[19]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.830 ns                 ;
; 0.815 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[19]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[19]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.831 ns                 ;
; 0.816 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSCLK            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.816 ns                                ; Reset_Delay:reset0|Cont[21]                                     ; Reset_Delay:reset0|Cont[21]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.832 ns                 ;
; 0.818 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mI2C_GO                          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.834 ns                 ;
; 0.824 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[1]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.018 ns                   ; 0.842 ns                 ;
; 0.826 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[1]           ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.842 ns                 ;
; 0.827 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[18]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[18]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.843 ns                 ;
; 0.831 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[12]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.847 ns                 ;
; 0.832 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[4]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.848 ns                 ;
; 0.832 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.848 ns                 ;
; 0.834 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[9]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.850 ns                 ;
; 0.835 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[13]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[13]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[5]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[5]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.835 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0001                     ; lcd_3wire_config:lcd_config0|msetup_st.0010                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.851 ns                 ;
; 0.838 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[3]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[3]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[10]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[10]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[12]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[12]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[8]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[8]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[3]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[3]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[12] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[12] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[10] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[10] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.838 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[8]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[8]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.854 ns                 ;
; 0.839 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]               ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]               ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[5]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[5]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[6]                  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[6]                  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[24]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[24]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[5]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[5]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.839 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[6]  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[6]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.855 ns                 ;
; 0.840 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[5]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.856 ns                 ;
; 0.840 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.856 ns                 ;
; 0.841 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[6]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[6]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 0.855 ns                 ;
; 0.841 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[20]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[20]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.857 ns                 ;
; 0.841 ns                                ; Reset_Delay:reset0|Cont[1]                                      ; Reset_Delay:reset0|Cont[1]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.857 ns                 ;
; 0.842 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[1]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[1]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.842 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[2]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[2]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.842 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[22]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[22]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.842 ns                                ; Reset_Delay:reset0|Cont[2]                                      ; Reset_Delay:reset0|Cont[2]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.858 ns                 ;
; 0.844 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[23]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[23]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 0.863 ns                 ;
; 0.844 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[4]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[4]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.860 ns                 ;
; 0.844 ns                                ; Reset_Delay:reset0|Cont[4]                                      ; Reset_Delay:reset0|Cont[4]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.860 ns                 ;
; 0.844 ns                                ; Reset_Delay:reset0|Cont[20]                                     ; Reset_Delay:reset0|Cont[20]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.860 ns                 ;
; 0.845 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[15]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[6]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; lcd_3wire_config:lcd_config0|lut_index[2]                       ; lcd_3wire_config:lcd_config0|lut_index[2]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; Reset_Delay:reset0|Cont[6]                                      ; Reset_Delay:reset0|Cont[6]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; Reset_Delay:reset0|Cont[15]                                     ; Reset_Delay:reset0|Cont[15]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.845 ns                                ; Reset_Delay:reset0|Cont[22]                                     ; Reset_Delay:reset0|Cont[22]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.861 ns                 ;
; 0.846 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[8]                     ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[8]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[18]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[18]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[17]                    ; I2C_CCD_Config:i2c_ccd_config0|combo_cnt[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; Reset_Delay:reset0|Cont[8]                                      ; Reset_Delay:reset0|Cont[8]                                      ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.846 ns                                ; Reset_Delay:reset0|Cont[17]                                     ; Reset_Delay:reset0|Cont[17]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.862 ns                 ;
; 0.847 ns                                ; Reset_Delay:reset0|Cont[18]                                     ; Reset_Delay:reset0|Cont[18]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.863 ns                 ;
; 0.849 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.865 ns                 ;
; 0.852 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.868 ns                 ;
; 0.863 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.879 ns                 ;
; 0.865 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.881 ns                 ;
; 0.873 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.889 ns                 ;
; 0.875 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.891 ns                 ;
; 0.877 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.893 ns                 ;
; 0.885 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[1]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[1]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.901 ns                 ;
; 0.893 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.909 ns                 ;
; 0.919 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[22]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[22]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.026 ns                   ; 0.945 ns                 ;
; 0.944 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0000                     ; lcd_3wire_config:lcd_config0|msetup_st.0001                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.960 ns                 ;
; 0.946 ns                                ; lcd_3wire_config:lcd_config0|lut_index[4]                       ; lcd_3wire_config:lcd_config0|m3wire_data[10]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 0.965 ns                 ;
; 0.947 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0100                     ; lcd_3wire_config:lcd_config0|msetup_st.0000                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.963 ns                 ;
; 0.949 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[21]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.965 ns                 ;
; 0.950 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]              ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[12]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.143 ns                   ; 3.093 ns                 ;
; 0.950 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[0]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[0]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.023 ns                   ; 0.973 ns                 ;
; 0.962 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]               ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[2]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.146 ns                   ; 3.108 ns                 ;
; 0.962 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.978 ns                 ;
; 0.963 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]               ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[9]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.146 ns                   ; 3.109 ns                 ;
; 0.964 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[21]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.153 ns                   ; 3.117 ns                 ;
; 0.964 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.153 ns                   ; 3.117 ns                 ;
; 0.967 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[8]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.018 ns                   ; 0.985 ns                 ;
; 0.967 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[16]                    ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[16]         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.019 ns                   ; 0.986 ns                 ;
; 0.968 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[15] ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK_DIV[15] ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.984 ns                 ;
; 0.970 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[2]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.986 ns                 ;
; 0.977 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.993 ns                 ;
; 0.977 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[15]                 ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CLK_DIV[15]                 ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.993 ns                 ;
; 0.978 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|msetup_st.0100                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.994 ns                 ;
; 0.982 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[0]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[0]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.998 ns                 ;
; 0.982 ns                                ; lcd_3wire_config:lcd_config0|lut_index[5]                       ; lcd_3wire_config:lcd_config0|lut_index[5]                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 0.998 ns                 ;
; 0.983 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]              ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[11]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.157 ns                   ; 3.140 ns                 ;
; 0.986 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[7]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[7]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.007 ns                   ; 0.993 ns                 ;
; 0.987 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mACK             ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.003 ns                 ;
; 0.988 ns                                ; Reset_Delay:reset0|Cont[20]                                     ; Reset_Delay:reset0|oRST_0                                       ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.017 ns                   ; 1.005 ns                 ;
; 0.990 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[4]                     ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD[4]          ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.007 ns                   ; 0.997 ns                 ;
; 0.990 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]               ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[3]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.155 ns                   ; 3.145 ns                 ;
; 0.991 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0011                     ; lcd_3wire_config:lcd_config0|msetup_st.0000                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.007 ns                 ;
; 0.992 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.008 ns                 ;
; 0.996 ns                                ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]           ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSCLK            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.012 ns                 ;
; 0.996 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[21]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.153 ns                   ; 3.149 ns                 ;
; 0.996 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[3]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[17]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.153 ns                   ; 3.149 ns                 ;
; 0.997 ns                                ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0010                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.013 ns                 ;
; 0.998 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SCLK           ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.014 ns                 ;
; 1.009 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[1]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[21]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.025 ns                 ;
; 1.013 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]  ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.029 ns                 ;
; 1.014 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.172 ns                   ; 3.186 ns                 ;
; 1.014 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[1]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.172 ns                   ; 3.186 ns                 ;
; 1.014 ns                                ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[2]           ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[6]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.172 ns                   ; 3.186 ns                 ;
; 1.016 ns                                ; Reset_Delay:reset0|Cont[23]                                     ; Reset_Delay:reset0|Cont[23]                                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.032 ns                 ;
; 1.018 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]              ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[13]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.146 ns                   ; 3.164 ns                 ;
; 1.019 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.031 ns                   ; 1.050 ns                 ;
; 1.020 ns                                ; lcd_3wire_config:lcd_config0|msetup_st.0010                     ; lcd_3wire_config:lcd_config0|m3wire_str                         ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.036 ns                 ;
; 1.021 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]              ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]              ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.016 ns                   ; 1.037 ns                 ;
; 1.024 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[16]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.027 ns                   ; 1.051 ns                 ;
; 1.025 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[5]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.015 ns                   ; 1.040 ns                 ;
; 1.026 ns                                ; I2C_CCD_Config:i2c_ccd_config0|LUT_INDEX[3]                     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]                    ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.027 ns                   ; 1.053 ns                 ;
; 1.032 ns                                ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]               ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[8]                     ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 2.148 ns                   ; 3.180 ns                 ;
; 1.032 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0000                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 1.046 ns                 ;
; 1.037 ns                                ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|END            ; I2C_CCD_Config:i2c_ccd_config0|mSetup_ST.0001                   ; iCLK_50    ; iCLK_50  ; 0.000 ns                   ; 0.014 ns                   ; 1.051 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)             ;                                                                 ;            ;          ;                            ;                            ;                          ;
+-----------------------------------------+-----------------------------------------------------------------+-----------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                         ;
+-----------+--------------+------------+-------------+-------------------------------------------------------+---------------+
; Slack     ; Required tsu ; Actual tsu ; From        ; To                                                    ; To Clock      ;
+-----------+--------------+------------+-------------+-------------------------------------------------------+---------------+
; -0.330 ns ; 1.000 ns     ; 1.330 ns   ; DRAM_DQ[30] ; Sdram_Control_4Port:sdram1|mDATAOUT[14]               ; iCLK_50_3     ;
; -0.317 ns ; 1.000 ns     ; 1.317 ns   ; DRAM_DQ[27] ; Sdram_Control_4Port:sdram1|mDATAOUT[11]               ; iCLK_50_3     ;
; -0.317 ns ; 1.000 ns     ; 1.317 ns   ; DRAM_DQ[28] ; Sdram_Control_4Port:sdram1|mDATAOUT[12]               ; iCLK_50_3     ;
; -0.310 ns ; 1.000 ns     ; 1.310 ns   ; DRAM_DQ[29] ; Sdram_Control_4Port:sdram1|mDATAOUT[13]               ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[4]  ; Sdram_Control_4Port:sdram0|mDATAOUT[4]                ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[3]  ; Sdram_Control_4Port:sdram0|mDATAOUT[3]                ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[25] ; Sdram_Control_4Port:sdram1|mDATAOUT[9]                ; iCLK_50_3     ;
; -0.296 ns ; 1.000 ns     ; 1.296 ns   ; DRAM_DQ[24] ; Sdram_Control_4Port:sdram1|mDATAOUT[8]                ; iCLK_50_3     ;
; -0.286 ns ; 1.000 ns     ; 1.286 ns   ; DRAM_DQ[26] ; Sdram_Control_4Port:sdram1|mDATAOUT[10]               ; iCLK_50_3     ;
; -0.286 ns ; 1.000 ns     ; 1.286 ns   ; DRAM_DQ[2]  ; Sdram_Control_4Port:sdram0|mDATAOUT[2]                ; iCLK_50_3     ;
; -0.276 ns ; 1.000 ns     ; 1.276 ns   ; DRAM_DQ[5]  ; Sdram_Control_4Port:sdram0|mDATAOUT[5]                ; iCLK_50_3     ;
; -0.270 ns ; 1.000 ns     ; 1.270 ns   ; DRAM_DQ[19] ; Sdram_Control_4Port:sdram1|mDATAOUT[3]                ; iCLK_50_3     ;
; -0.270 ns ; 1.000 ns     ; 1.270 ns   ; DRAM_DQ[22] ; Sdram_Control_4Port:sdram1|mDATAOUT[6]                ; iCLK_50_3     ;
; -0.270 ns ; 1.000 ns     ; 1.270 ns   ; DRAM_DQ[21] ; Sdram_Control_4Port:sdram1|mDATAOUT[5]                ; iCLK_50_3     ;
; -0.268 ns ; 1.000 ns     ; 1.268 ns   ; DRAM_DQ[23] ; Sdram_Control_4Port:sdram1|mDATAOUT[7]                ; iCLK_50_3     ;
; -0.267 ns ; 1.000 ns     ; 1.267 ns   ; DRAM_DQ[7]  ; Sdram_Control_4Port:sdram0|mDATAOUT[7]                ; iCLK_50_3     ;
; -0.267 ns ; 1.000 ns     ; 1.267 ns   ; DRAM_DQ[6]  ; Sdram_Control_4Port:sdram0|mDATAOUT[6]                ; iCLK_50_3     ;
; -0.262 ns ; 1.000 ns     ; 1.262 ns   ; DRAM_DQ[9]  ; Sdram_Control_4Port:sdram0|mDATAOUT[9]                ; iCLK_50_3     ;
; -0.262 ns ; 1.000 ns     ; 1.262 ns   ; DRAM_DQ[10] ; Sdram_Control_4Port:sdram0|mDATAOUT[10]               ; iCLK_50_3     ;
; -0.260 ns ; 1.000 ns     ; 1.260 ns   ; DRAM_DQ[20] ; Sdram_Control_4Port:sdram1|mDATAOUT[4]                ; iCLK_50_3     ;
; -0.256 ns ; 1.000 ns     ; 1.256 ns   ; DRAM_DQ[14] ; Sdram_Control_4Port:sdram0|mDATAOUT[14]               ; iCLK_50_3     ;
; -0.256 ns ; 1.000 ns     ; 1.256 ns   ; DRAM_DQ[13] ; Sdram_Control_4Port:sdram0|mDATAOUT[13]               ; iCLK_50_3     ;
; -0.254 ns ; 1.000 ns     ; 1.254 ns   ; DRAM_DQ[18] ; Sdram_Control_4Port:sdram1|mDATAOUT[2]                ; iCLK_50_3     ;
; -0.246 ns ; 1.000 ns     ; 1.246 ns   ; DRAM_DQ[12] ; Sdram_Control_4Port:sdram0|mDATAOUT[12]               ; iCLK_50_3     ;
; -0.229 ns ; 1.000 ns     ; 1.229 ns   ; DRAM_DQ[11] ; Sdram_Control_4Port:sdram0|mDATAOUT[11]               ; iCLK_50_3     ;
; -0.222 ns ; 1.000 ns     ; 1.222 ns   ; DRAM_DQ[8]  ; Sdram_Control_4Port:sdram0|mDATAOUT[8]                ; iCLK_50_3     ;
; 2.509 ns  ; 5.000 ns     ; 2.491 ns   ; GPIO_1[10]  ; rCCD_DATA[1]                                          ; GPIO_CLKIN_N1 ;
; 2.520 ns  ; 5.000 ns     ; 2.480 ns   ; GPIO_1[8]   ; rCCD_DATA[3]                                          ; GPIO_CLKIN_N1 ;
; 2.520 ns  ; 5.000 ns     ; 2.480 ns   ; GPIO_1[6]   ; rCCD_DATA[5]                                          ; GPIO_CLKIN_N1 ;
; 2.529 ns  ; 5.000 ns     ; 2.471 ns   ; GPIO_1[9]   ; rCCD_DATA[2]                                          ; GPIO_CLKIN_N1 ;
; 2.529 ns  ; 5.000 ns     ; 2.471 ns   ; GPIO_1[7]   ; rCCD_DATA[4]                                          ; GPIO_CLKIN_N1 ;
; 2.554 ns  ; 5.000 ns     ; 2.446 ns   ; GPIO_1[11]  ; rCCD_DATA[0]                                          ; GPIO_CLKIN_N1 ;
; 2.566 ns  ; 5.000 ns     ; 2.434 ns   ; GPIO_1[17]  ; rCCD_LVAL                                             ; GPIO_CLKIN_N1 ;
; 2.575 ns  ; 5.000 ns     ; 2.425 ns   ; GPIO_1[1]   ; rCCD_DATA[10]                                         ; GPIO_CLKIN_N1 ;
; 2.575 ns  ; 5.000 ns     ; 2.425 ns   ; GPIO_1[0]   ; rCCD_DATA[11]                                         ; GPIO_CLKIN_N1 ;
; 2.578 ns  ; 5.000 ns     ; 2.422 ns   ; GPIO_1[5]   ; rCCD_DATA[6]                                          ; GPIO_CLKIN_N1 ;
; 2.578 ns  ; 5.000 ns     ; 2.422 ns   ; GPIO_1[3]   ; rCCD_DATA[8]                                          ; GPIO_CLKIN_N1 ;
; 2.585 ns  ; 5.000 ns     ; 2.415 ns   ; GPIO_1[4]   ; rCCD_DATA[7]                                          ; GPIO_CLKIN_N1 ;
; 2.585 ns  ; 5.000 ns     ; 2.415 ns   ; GPIO_1[2]   ; rCCD_DATA[9]                                          ; GPIO_CLKIN_N1 ;
; 2.586 ns  ; 5.000 ns     ; 2.414 ns   ; GPIO_1[18]  ; rCCD_FVAL                                             ; GPIO_CLKIN_N1 ;
; N/A       ; None         ; 8.645 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.644 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.644 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.644 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.499 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.498 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.498 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.498 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.331 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.331 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.330 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.329 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.185 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.185 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.184 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 8.183 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.925 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.903 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.902 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.901 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.901 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.901 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.901 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.893 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.892 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.892 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.883 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.881 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.880 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.878 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.878 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.878 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.878 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.878 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.878 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.878 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.878 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.878 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.877 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.876 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.876 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.876 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.876 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.876 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.876 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.876 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.876 ns   ; iSW[15]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A       ; None         ; 7.829 ns   ; iSW[14]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A       ; None         ; 6.495 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A       ; None         ; 6.038 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A       ; None         ; 5.935 ns   ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A       ; None         ; 5.911 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A       ; None         ; 5.415 ns   ; iSW[17]     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]          ; iCLK_50       ;
; N/A       ; None         ; 4.636 ns   ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[0] ; iCLK_50       ;
; N/A       ; None         ; 3.205 ns   ; iKEY[2]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A       ; None         ; 3.115 ns   ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2 ; iCLK_50       ;
; N/A       ; None         ; 3.060 ns   ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1 ; iCLK_50       ;
; N/A       ; None         ; 2.864 ns   ; iKEY[3]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A       ; None         ; 2.399 ns   ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3 ; iCLK_50       ;
; N/A       ; None         ; 2.358 ns   ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4 ; iCLK_50       ;
; N/A       ; None         ; 1.216 ns   ; iSW[17]     ; RAW2RGB:raw0|mirror_sw                                ; iCLK_50       ;
+-----------+--------------+------------+-------------+-------------------------------------------------------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+---------------+
; Slack                                   ; Required tco                                        ; Actual tco ; From                                                                                                                                                              ; To             ; From Clock    ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+---------------+
; -5.033 ns                               ; 1.000 ns                                            ; 6.033 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[19]    ; iCLK_50_3     ;
; -4.937 ns                               ; 1.000 ns                                            ; 5.937 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[13]    ; iCLK_50_3     ;
; -4.929 ns                               ; 1.000 ns                                            ; 5.929 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[14]    ; iCLK_50_3     ;
; -4.913 ns                               ; 1.000 ns                                            ; 5.913 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[17]    ; iCLK_50_3     ;
; -4.910 ns                               ; 1.000 ns                                            ; 5.910 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[29]    ; iCLK_50_3     ;
; -4.888 ns                               ; 1.000 ns                                            ; 5.888 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[15]    ; iCLK_50_3     ;
; -4.873 ns                               ; 1.000 ns                                            ; 5.873 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[20]    ; iCLK_50_3     ;
; -4.871 ns                               ; 1.000 ns                                            ; 5.871 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[21]    ; iCLK_50_3     ;
; -4.855 ns                               ; 1.000 ns                                            ; 5.855 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[14]    ; iCLK_50_3     ;
; -4.854 ns                               ; 1.000 ns                                            ; 5.854 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[7]     ; iCLK_50_3     ;
; -4.847 ns                               ; 1.000 ns                                            ; 5.847 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[11]    ; iCLK_50_3     ;
; -4.842 ns                               ; 1.000 ns                                            ; 5.842 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[1]     ; iCLK_50_3     ;
; -4.838 ns                               ; 1.000 ns                                            ; 5.838 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[13]    ; iCLK_50_3     ;
; -4.817 ns                               ; 1.000 ns                                            ; 5.817 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[13] ; DRAM_DQ[29]    ; iCLK_50_3     ;
; -4.816 ns                               ; 1.000 ns                                            ; 5.816 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[26]    ; iCLK_50_3     ;
; -4.797 ns                               ; 1.000 ns                                            ; 5.797 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[15]    ; iCLK_50_3     ;
; -4.796 ns                               ; 1.000 ns                                            ; 5.796 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[30]    ; iCLK_50_3     ;
; -4.786 ns                               ; 1.000 ns                                            ; 5.786 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[10]    ; iCLK_50_3     ;
; -4.784 ns                               ; 1.000 ns                                            ; 5.784 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[12]    ; iCLK_50_3     ;
; -4.777 ns                               ; 1.000 ns                                            ; 5.777 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[8]     ; iCLK_50_3     ;
; -4.775 ns                               ; 1.000 ns                                            ; 5.775 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[24]    ; iCLK_50_3     ;
; -4.774 ns                               ; 1.000 ns                                            ; 5.774 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[20]    ; iCLK_50_3     ;
; -4.773 ns                               ; 1.000 ns                                            ; 5.773 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[22]    ; iCLK_50_3     ;
; -4.766 ns                               ; 1.000 ns                                            ; 5.766 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[14]    ; iCLK_50_3     ;
; -4.756 ns                               ; 1.000 ns                                            ; 5.756 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[16]    ; iCLK_50_3     ;
; -4.738 ns                               ; 1.000 ns                                            ; 5.738 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[6]     ; iCLK_50_3     ;
; -4.729 ns                               ; 1.000 ns                                            ; 5.729 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[2]     ; iCLK_50_3     ;
; -4.726 ns                               ; 1.000 ns                                            ; 5.726 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[11]    ; iCLK_50_3     ;
; -4.725 ns                               ; 1.000 ns                                            ; 5.725 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[24]    ; iCLK_50_3     ;
; -4.723 ns                               ; 1.000 ns                                            ; 5.723 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[8]     ; iCLK_50_3     ;
; -4.719 ns                               ; 1.000 ns                                            ; 5.719 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[14] ; DRAM_DQ[30]    ; iCLK_50_3     ;
; -4.718 ns                               ; 1.000 ns                                            ; 5.718 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[18]    ; iCLK_50_3     ;
; -4.710 ns                               ; 1.000 ns                                            ; 5.710 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[12]    ; iCLK_50_3     ;
; -4.706 ns                               ; 1.000 ns                                            ; 5.706 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[0]     ; iCLK_50_3     ;
; -4.695 ns                               ; 1.000 ns                                            ; 5.695 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[15]    ; iCLK_50_3     ;
; -4.695 ns                               ; 1.000 ns                                            ; 5.695 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[17]    ; iCLK_50_3     ;
; -4.676 ns                               ; 1.000 ns                                            ; 5.676 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[6]     ; iCLK_50_3     ;
; -4.674 ns                               ; 1.000 ns                                            ; 5.674 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[27]    ; iCLK_50_3     ;
; -4.672 ns                               ; 1.000 ns                                            ; 5.672 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[16]    ; iCLK_50_3     ;
; -4.667 ns                               ; 1.000 ns                                            ; 5.667 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[5]     ; iCLK_50_3     ;
; -4.665 ns                               ; 1.000 ns                                            ; 5.665 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[11]    ; iCLK_50_3     ;
; -4.662 ns                               ; 1.000 ns                                            ; 5.662 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[6]  ; DRAM_DQ[22]    ; iCLK_50_3     ;
; -4.659 ns                               ; 1.000 ns                                            ; 5.659 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[3]     ; iCLK_50_3     ;
; -4.657 ns                               ; 1.000 ns                                            ; 5.657 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[25]    ; iCLK_50_3     ;
; -4.653 ns                               ; 1.000 ns                                            ; 5.653 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[21]    ; iCLK_50_3     ;
; -4.652 ns                               ; 1.000 ns                                            ; 5.652 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[13]    ; iCLK_50_3     ;
; -4.651 ns                               ; 1.000 ns                                            ; 5.651 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[31]    ; iCLK_50_3     ;
; -4.642 ns                               ; 1.000 ns                                            ; 5.642 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[0]  ; DRAM_DQ[0]     ; iCLK_50_3     ;
; -4.641 ns                               ; 1.000 ns                                            ; 5.641 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[25]    ; iCLK_50_3     ;
; -4.641 ns                               ; 1.000 ns                                            ; 5.641 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[26]    ; iCLK_50_3     ;
; -4.640 ns                               ; 1.000 ns                                            ; 5.640 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[10] ; DRAM_DQ[10]    ; iCLK_50_3     ;
; -4.628 ns                               ; 1.000 ns                                            ; 5.628 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[3]     ; iCLK_50_3     ;
; -4.626 ns                               ; 1.000 ns                                            ; 5.626 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[10]    ; iCLK_50_3     ;
; -4.626 ns                               ; 1.000 ns                                            ; 5.626 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[12]    ; iCLK_50_3     ;
; -4.614 ns                               ; 1.000 ns                                            ; 5.614 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[8]  ; DRAM_DQ[8]     ; iCLK_50_3     ;
; -4.613 ns                               ; 1.000 ns                                            ; 5.613 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[11] ; DRAM_DQ[27]    ; iCLK_50_3     ;
; -4.590 ns                               ; 1.000 ns                                            ; 5.590 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[30]    ; iCLK_50_3     ;
; -4.589 ns                               ; 1.000 ns                                            ; 5.589 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[29]    ; iCLK_50_3     ;
; -4.586 ns                               ; 1.000 ns                                            ; 5.586 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[19]    ; iCLK_50_3     ;
; -4.583 ns                               ; 1.000 ns                                            ; 5.583 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[9]     ; iCLK_50_3     ;
; -4.574 ns                               ; 1.000 ns                                            ; 5.574 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[2]     ; iCLK_50_3     ;
; -4.566 ns                               ; 1.000 ns                                            ; 5.566 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[23]    ; iCLK_50_3     ;
; -4.564 ns                               ; 1.000 ns                                            ; 5.564 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[7]     ; iCLK_50_3     ;
; -4.563 ns                               ; 1.000 ns                                            ; 5.563 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[16]    ; iCLK_50_3     ;
; -4.559 ns                               ; 1.000 ns                                            ; 5.559 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[4]     ; iCLK_50_3     ;
; -4.553 ns                               ; 1.000 ns                                            ; 5.553 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[28]    ; iCLK_50_3     ;
; -4.548 ns                               ; 1.000 ns                                            ; 5.548 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[22]    ; iCLK_50_3     ;
; -4.542 ns                               ; 1.000 ns                                            ; 5.542 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[2]  ; DRAM_DQ[18]    ; iCLK_50_3     ;
; -4.525 ns                               ; 1.000 ns                                            ; 5.525 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[1]  ; DRAM_DQ[1]     ; iCLK_50_3     ;
; -4.501 ns                               ; 1.000 ns                                            ; 5.501 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[18]    ; iCLK_50_3     ;
; -4.500 ns                               ; 1.000 ns                                            ; 5.500 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[15] ; DRAM_DQ[31]    ; iCLK_50_3     ;
; -4.495 ns                               ; 1.000 ns                                            ; 5.495 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[25]    ; iCLK_50_3     ;
; -4.491 ns                               ; 1.000 ns                                            ; 5.491 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[5]     ; iCLK_50_3     ;
; -4.491 ns                               ; 1.000 ns                                            ; 5.491 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[27]    ; iCLK_50_3     ;
; -4.464 ns                               ; 1.000 ns                                            ; 5.464 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[9]  ; DRAM_DQ[9]     ; iCLK_50_3     ;
; -4.451 ns                               ; 1.000 ns                                            ; 5.451 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[17]    ; iCLK_50_3     ;
; -4.434 ns                               ; 1.000 ns                                            ; 5.434 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[7]     ; iCLK_50_3     ;
; -4.428 ns                               ; 1.000 ns                                            ; 5.428 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[21]    ; iCLK_50_3     ;
; -4.419 ns                               ; 1.000 ns                                            ; 5.419 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[28]    ; iCLK_50_3     ;
; -4.416 ns                               ; 1.000 ns                                            ; 5.416 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[9]     ; iCLK_50_3     ;
; -4.409 ns                               ; 1.000 ns                                            ; 5.409 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]  ; DRAM_DQ[19]    ; iCLK_50_3     ;
; -4.402 ns                               ; 1.000 ns                                            ; 5.402 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[0]     ; iCLK_50_3     ;
; -4.396 ns                               ; 1.000 ns                                            ; 5.396 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[4]  ; DRAM_DQ[4]     ; iCLK_50_3     ;
; -4.394 ns                               ; 1.000 ns                                            ; 5.394 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[20]    ; iCLK_50_3     ;
; -4.383 ns                               ; 1.000 ns                                            ; 5.383 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[31]    ; iCLK_50_3     ;
; -4.351 ns                               ; 1.000 ns                                            ; 5.351 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[12] ; DRAM_DQ[28]    ; iCLK_50_3     ;
; -4.326 ns                               ; 1.000 ns                                            ; 5.326 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[26]    ; iCLK_50_3     ;
; -4.321 ns                               ; 1.000 ns                                            ; 5.321 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[4]     ; iCLK_50_3     ;
; -4.293 ns                               ; 1.000 ns                                            ; 5.293 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[1]     ; iCLK_50_3     ;
; -4.274 ns                               ; 1.000 ns                                            ; 5.274 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[2]     ; iCLK_50_3     ;
; -4.238 ns                               ; 1.000 ns                                            ; 5.238 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[24]    ; iCLK_50_3     ;
; -4.232 ns                               ; 1.000 ns                                            ; 5.232 ns   ; Sdram_Control_4Port:sdram1|mWR                                                                                                                                    ; DRAM_DQ[23]    ; iCLK_50_3     ;
; -4.197 ns                               ; 1.000 ns                                            ; 5.197 ns   ; Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[7]  ; DRAM_DQ[23]    ; iCLK_50_3     ;
; -4.176 ns                               ; 1.000 ns                                            ; 5.176 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[6]     ; iCLK_50_3     ;
; -4.162 ns                               ; 1.000 ns                                            ; 5.162 ns   ; Sdram_Control_4Port:sdram0|mWR                                                                                                                                    ; DRAM_DQ[3]     ; iCLK_50_3     ;
; -4.090 ns                               ; 1.000 ns                                            ; 5.090 ns   ; Sdram_Control_4Port:sdram0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[5]  ; DRAM_DQ[5]     ; iCLK_50_3     ;
; -3.221 ns                               ; 1.000 ns                                            ; 4.221 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[11]    ; iCLK_50_3     ;
; -3.201 ns                               ; 1.000 ns                                            ; 4.201 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[8]     ; iCLK_50_3     ;
; -3.156 ns                               ; 1.000 ns                                            ; 4.156 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[16]    ; iCLK_50_3     ;
; -3.156 ns                               ; 1.000 ns                                            ; 4.156 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[17]    ; iCLK_50_3     ;
; -2.929 ns                               ; 1.000 ns                                            ; 3.929 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[13]    ; iCLK_50_3     ;
; -2.929 ns                               ; 1.000 ns                                            ; 3.929 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[14]    ; iCLK_50_3     ;
; -2.929 ns                               ; 1.000 ns                                            ; 3.929 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[15]    ; iCLK_50_3     ;
; -2.923 ns                               ; 1.000 ns                                            ; 3.923 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[10]    ; iCLK_50_3     ;
; -2.923 ns                               ; 1.000 ns                                            ; 3.923 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[9]     ; iCLK_50_3     ;
; -2.919 ns                               ; 1.000 ns                                            ; 3.919 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[12]    ; iCLK_50_3     ;
; -2.894 ns                               ; 1.000 ns                                            ; 3.894 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[3]     ; iCLK_50_3     ;
; -2.894 ns                               ; 1.000 ns                                            ; 3.894 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[4]     ; iCLK_50_3     ;
; -2.894 ns                               ; 1.000 ns                                            ; 3.894 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[0]     ; iCLK_50_3     ;
; -2.894 ns                               ; 1.000 ns                                            ; 3.894 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[1]     ; iCLK_50_3     ;
; -2.884 ns                               ; 1.000 ns                                            ; 3.884 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[2]     ; iCLK_50_3     ;
; -2.884 ns                               ; 1.000 ns                                            ; 3.884 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[6]     ; iCLK_50_3     ;
; -2.884 ns                               ; 1.000 ns                                            ; 3.884 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[7]     ; iCLK_50_3     ;
; -2.868 ns                               ; 1.000 ns                                            ; 3.868 ns   ; Sdram_Control_4Port:sdram0|command:command1|OE                                                                                                                    ; DRAM_DQ[5]     ; iCLK_50_3     ;
; -2.848 ns                               ; 1.000 ns                                            ; 3.848 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[19]    ; iCLK_50_3     ;
; -2.848 ns                               ; 1.000 ns                                            ; 3.848 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[21]    ; iCLK_50_3     ;
; -2.848 ns                               ; 1.000 ns                                            ; 3.848 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[22]    ; iCLK_50_3     ;
; -2.846 ns                               ; 1.000 ns                                            ; 3.846 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[18]    ; iCLK_50_3     ;
; -2.838 ns                               ; 1.000 ns                                            ; 3.838 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[20]    ; iCLK_50_3     ;
; -2.831 ns                               ; 1.000 ns                                            ; 3.831 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[30]    ; iCLK_50_3     ;
; -2.831 ns                               ; 1.000 ns                                            ; 3.831 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[31]    ; iCLK_50_3     ;
; -2.830 ns                               ; 1.000 ns                                            ; 3.830 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[24]    ; iCLK_50_3     ;
; -2.830 ns                               ; 1.000 ns                                            ; 3.830 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[25]    ; iCLK_50_3     ;
; -2.826 ns                               ; 1.000 ns                                            ; 3.826 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[23]    ; iCLK_50_3     ;
; -2.820 ns                               ; 1.000 ns                                            ; 3.820 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[26]    ; iCLK_50_3     ;
; -2.816 ns                               ; 1.000 ns                                            ; 3.816 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[27]    ; iCLK_50_3     ;
; -2.816 ns                               ; 1.000 ns                                            ; 3.816 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[28]    ; iCLK_50_3     ;
; -2.811 ns                               ; 1.000 ns                                            ; 3.811 ns   ; Sdram_Control_4Port:sdram1|command:command1|OE                                                                                                                    ; DRAM_DQ[29]    ; iCLK_50_3     ;
; N/A                                     ; None                                                ; 14.721 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSCLK                                                                                                              ; GPIO_0[2]      ; iCLK_50       ;
; N/A                                     ; None                                                ; 14.238 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[1]                                                                                                             ; GPIO_0[31]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 14.127 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[2]                                                                                                             ; GPIO_0[31]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.691 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[3]                                                                                                             ; GPIO_0[31]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.540 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[0]                                                                                                             ; GPIO_0[31]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.447 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mST[4]                                                                                                             ; GPIO_0[31]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.080 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[4]                                                                                                    ; GPIO_1[20]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 13.021 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[2]                                                                                                    ; GPIO_1[20]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.882 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[5]                                                                                                    ; GPIO_1[20]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.826 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA                                                                                                             ; GPIO_0[31]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.777 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[3]                                                                                                    ; GPIO_1[20]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.767 ns  ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[5]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.721 ns  ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                               ; oHEX2_D[5]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.549 ns  ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.502 ns  ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                ; oHEX2_D[5]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.501 ns  ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                               ; oHEX2_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.433 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA~en                                                                                                          ; GPIO_0[31]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.359 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SD_COUNTER[6]                                                                                                    ; GPIO_1[20]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.359 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SDO                                                                                                              ; GPIO_1[19]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.250 ns  ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                ; oHEX2_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.232 ns  ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                ; oHEX2_D[5]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 12.113 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSEN                                                                                                               ; GPIO_0[30]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 12.051 ns  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|SCLK                                                                                                             ; GPIO_1[20]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.981 ns  ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                ; oHEX2_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.877 ns  ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.873 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[5]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.861 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[5]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.856 ns  ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                               ; oHEX2_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.855 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[0]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.845 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[0]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.610 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.609 ns  ; CCD_Capture:capture0|Frame_Cont[8]                                                                                                                                ; oHEX2_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.605 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.598 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.595 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.453 ns  ; lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK                                                                                                           ; GPIO_0[2]      ; iCLK_50       ;
; N/A                                     ; None                                                ; 11.404 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[2]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.397 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[3]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.380 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[3]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.367 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[2]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.339 ns  ; CCD_Capture:capture0|Frame_Cont[9]                                                                                                                                ; oHEX2_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.145 ns  ; CCD_Capture:capture0|Frame_Cont[5]                                                                                                                                ; oHEX1_D[1]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 11.135 ns  ; CCD_Capture:capture0|Frame_Cont[4]                                                                                                                                ; oHEX1_D[1]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.412 ns  ; I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK                                                                                                                      ; GPIO_1[20]     ; iCLK_50       ;
; N/A                                     ; None                                                ; 10.195 ns  ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                ; oHEX0_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.173 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[5]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.173 ns  ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.158 ns  ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[0]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 10.042 ns  ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.987 ns   ; touch_tcon:vga0|oLCD_B[7]                                                                                                                                         ; GPIO_CLKOUT_N0 ; iCLK_50_2     ;
; N/A                                     ; None                                                ; 9.985 ns   ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[5]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.968 ns   ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                ; oHEX0_D[2]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.965 ns   ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[0]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.956 ns   ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[1]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.947 ns   ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[2]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.910 ns   ; CCD_Capture:capture0|Frame_Cont[10]                                                                                                                               ; oHEX2_D[1]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.910 ns   ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.907 ns   ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.902 ns   ; CCD_Capture:capture0|Frame_Cont[3]                                                                                                                                ; oHEX0_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.900 ns   ; CCD_Capture:capture0|Frame_Cont[2]                                                                                                                                ; oHEX0_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.815 ns   ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[2]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.797 ns   ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                                               ; oHEX6_D[5]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.794 ns   ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                                               ; oHEX6_D[3]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.771 ns   ; CCD_Capture:capture0|Frame_Cont[1]                                                                                                                                ; oHEX0_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.767 ns   ; CCD_Capture:capture0|Frame_Cont[24]                                                                                                                               ; oHEX6_D[2]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.756 ns   ; CCD_Capture:capture0|Frame_Cont[26]                                                                                                                               ; oHEX6_D[5]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.747 ns   ; CCD_Capture:capture0|Frame_Cont[26]                                                                                                                               ; oHEX6_D[3]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.745 ns   ; CCD_Capture:capture0|Frame_Cont[11]                                                                                                                               ; oHEX2_D[2]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.725 ns   ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[6]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.716 ns   ; CCD_Capture:capture0|Frame_Cont[6]                                                                                                                                ; oHEX1_D[4]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.714 ns   ; CCD_Capture:capture0|Frame_Cont[26]                                                                                                                               ; oHEX6_D[2]     ; GPIO_CLKIN_N1 ;
; N/A                                     ; None                                                ; 9.706 ns   ; CCD_Capture:capture0|Frame_Cont[7]                                                                                                                                ; oHEX1_D[2]     ; GPIO_CLKIN_N1 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;                                                                                                                                                                   ;                ;               ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+---------------+


+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+-----------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To         ;
+-------+-------------------+-----------------+-----------+------------+
; N/A   ; None              ; 11.343 ns       ; iSW[14]   ; oLEDR[14]  ;
; N/A   ; None              ; 10.805 ns       ; iSW[17]   ; oLEDR[17]  ;
; N/A   ; None              ; 10.585 ns       ; iSW[3]    ; oLEDR[3]   ;
; N/A   ; None              ; 10.543 ns       ; iSW[0]    ; oLEDR[0]   ;
; N/A   ; None              ; 10.496 ns       ; iSW[1]    ; oLEDR[1]   ;
; N/A   ; None              ; 10.479 ns       ; iSW[2]    ; oLEDR[2]   ;
; N/A   ; None              ; 10.327 ns       ; iSW[6]    ; oLEDR[6]   ;
; N/A   ; None              ; 10.244 ns       ; iSW[4]    ; oLEDR[4]   ;
; N/A   ; None              ; 10.193 ns       ; iSW[7]    ; oLEDR[7]   ;
; N/A   ; None              ; 10.166 ns       ; iSW[8]    ; oLEDR[8]   ;
; N/A   ; None              ; 10.152 ns       ; iSW[5]    ; oLEDR[5]   ;
; N/A   ; None              ; 10.113 ns       ; iSW[16]   ; oLEDR[16]  ;
; N/A   ; None              ; 9.980 ns        ; iSW[15]   ; oLEDR[15]  ;
; N/A   ; None              ; 9.882 ns        ; iSW[9]    ; oLEDR[9]   ;
; N/A   ; None              ; 9.875 ns        ; iSW[13]   ; oLEDR[13]  ;
; N/A   ; None              ; 9.614 ns        ; iSW[11]   ; oLEDR[11]  ;
; N/A   ; None              ; 9.575 ns        ; iSW[10]   ; oLEDR[10]  ;
; N/A   ; None              ; 9.483 ns        ; iSW[12]   ; oLEDR[12]  ;
; N/A   ; None              ; 8.893 ns        ; iUART_RXD ; oUART_TXD  ;
; N/A   ; None              ; 8.567 ns        ; iKEY[0]   ; GPIO_0[29] ;
+-------+-------------------+-----------------+-----------+------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                            ;
+---------------+-------------+-----------+-------------+-------------------------------------------------------+---------------+
; Minimum Slack ; Required th ; Actual th ; From        ; To                                                    ; To Clock      ;
+---------------+-------------+-----------+-------------+-------------------------------------------------------+---------------+
; N/A           ; None        ; -0.986 ns ; iSW[17]     ; RAW2RGB:raw0|mirror_sw                                ; iCLK_50       ;
; N/A           ; None        ; -1.058 ns ; DRAM_DQ[8]  ; Sdram_Control_4Port:sdram0|mDATAOUT[8]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.065 ns ; DRAM_DQ[11] ; Sdram_Control_4Port:sdram0|mDATAOUT[11]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.082 ns ; DRAM_DQ[12] ; Sdram_Control_4Port:sdram0|mDATAOUT[12]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.090 ns ; DRAM_DQ[18] ; Sdram_Control_4Port:sdram1|mDATAOUT[2]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.092 ns ; DRAM_DQ[14] ; Sdram_Control_4Port:sdram0|mDATAOUT[14]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.092 ns ; DRAM_DQ[13] ; Sdram_Control_4Port:sdram0|mDATAOUT[13]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.096 ns ; DRAM_DQ[20] ; Sdram_Control_4Port:sdram1|mDATAOUT[4]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.098 ns ; DRAM_DQ[9]  ; Sdram_Control_4Port:sdram0|mDATAOUT[9]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.098 ns ; DRAM_DQ[10] ; Sdram_Control_4Port:sdram0|mDATAOUT[10]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.103 ns ; DRAM_DQ[7]  ; Sdram_Control_4Port:sdram0|mDATAOUT[7]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.103 ns ; DRAM_DQ[6]  ; Sdram_Control_4Port:sdram0|mDATAOUT[6]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.104 ns ; DRAM_DQ[23] ; Sdram_Control_4Port:sdram1|mDATAOUT[7]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.106 ns ; DRAM_DQ[22] ; Sdram_Control_4Port:sdram1|mDATAOUT[6]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.106 ns ; DRAM_DQ[21] ; Sdram_Control_4Port:sdram1|mDATAOUT[5]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.106 ns ; DRAM_DQ[19] ; Sdram_Control_4Port:sdram1|mDATAOUT[3]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.112 ns ; DRAM_DQ[5]  ; Sdram_Control_4Port:sdram0|mDATAOUT[5]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.122 ns ; DRAM_DQ[26] ; Sdram_Control_4Port:sdram1|mDATAOUT[10]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.122 ns ; DRAM_DQ[2]  ; Sdram_Control_4Port:sdram0|mDATAOUT[2]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[25] ; Sdram_Control_4Port:sdram1|mDATAOUT[9]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[24] ; Sdram_Control_4Port:sdram1|mDATAOUT[8]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[4]  ; Sdram_Control_4Port:sdram0|mDATAOUT[4]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.132 ns ; DRAM_DQ[3]  ; Sdram_Control_4Port:sdram0|mDATAOUT[3]                ; iCLK_50_3     ;
; N/A           ; None        ; -1.146 ns ; DRAM_DQ[29] ; Sdram_Control_4Port:sdram1|mDATAOUT[13]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.153 ns ; DRAM_DQ[28] ; Sdram_Control_4Port:sdram1|mDATAOUT[12]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.153 ns ; DRAM_DQ[27] ; Sdram_Control_4Port:sdram1|mDATAOUT[11]               ; iCLK_50_3     ;
; N/A           ; None        ; -1.166 ns ; DRAM_DQ[30] ; Sdram_Control_4Port:sdram1|mDATAOUT[14]               ; iCLK_50_3     ;
; N/A           ; None        ; -2.128 ns ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK4 ; iCLK_50       ;
; N/A           ; None        ; -2.169 ns ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK3 ; iCLK_50       ;
; N/A           ; None        ; -2.250 ns ; GPIO_1[18]  ; rCCD_FVAL                                             ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.251 ns ; GPIO_1[2]   ; rCCD_DATA[9]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.251 ns ; GPIO_1[4]   ; rCCD_DATA[7]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.258 ns ; GPIO_1[3]   ; rCCD_DATA[8]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.258 ns ; GPIO_1[5]   ; rCCD_DATA[6]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.261 ns ; GPIO_1[0]   ; rCCD_DATA[11]                                         ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.261 ns ; GPIO_1[1]   ; rCCD_DATA[10]                                         ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.270 ns ; GPIO_1[17]  ; rCCD_LVAL                                             ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.282 ns ; GPIO_1[11]  ; rCCD_DATA[0]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.307 ns ; GPIO_1[7]   ; rCCD_DATA[4]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.307 ns ; GPIO_1[9]   ; rCCD_DATA[2]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.316 ns ; GPIO_1[6]   ; rCCD_DATA[5]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.316 ns ; GPIO_1[8]   ; rCCD_DATA[3]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.327 ns ; GPIO_1[10]  ; rCCD_DATA[1]                                          ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.634 ns ; iKEY[3]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -2.830 ns ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK1 ; iCLK_50       ;
; N/A           ; None        ; -2.885 ns ; GPIO_1[19]  ; I2C_CCD_Config:i2c_ccd_config0|I2C_Controller:u0|ACK2 ; iCLK_50       ;
; N/A           ; None        ; -2.975 ns ; iKEY[2]     ; CCD_Capture:capture0|mSTART                           ; GPIO_CLKIN_N1 ;
; N/A           ; None        ; -3.936 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A           ; None        ; -3.936 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A           ; None        ; -4.013 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A           ; None        ; -4.058 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A           ; None        ; -4.058 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A           ; None        ; -4.059 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A           ; None        ; -4.062 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A           ; None        ; -4.063 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A           ; None        ; -4.253 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A           ; None        ; -4.314 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A           ; None        ; -4.315 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A           ; None        ; -4.317 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A           ; None        ; -4.320 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A           ; None        ; -4.321 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A           ; None        ; -4.322 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A           ; None        ; -4.406 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|iexposure_adj_delay[0] ; iCLK_50       ;
; N/A           ; None        ; -4.956 ns ; iSW[0]      ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A           ; None        ; -5.185 ns ; iSW[17]     ; I2C_CCD_Config:i2c_ccd_config0|mI2C_DATA[15]          ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[10]    ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[6]     ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[9]     ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[11]    ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[7]     ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[14]    ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[1]     ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[12]    ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[8]     ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[15]    ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[13]    ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[3]     ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[2]     ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[5]     ; iCLK_50       ;
; N/A           ; None        ; -5.681 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[4]     ; iCLK_50       ;
; N/A           ; None        ; -5.808 ns ; iKEY[1]     ; I2C_CCD_Config:i2c_ccd_config0|senosr_exposure[0]     ; iCLK_50       ;
; N/A           ; None        ; -7.599 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.646 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.646 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.646 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.646 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.646 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.646 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.646 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.646 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.647 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.648 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.648 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.648 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.648 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.648 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.648 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.648 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.648 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.648 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.650 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.651 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.653 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.662 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.662 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.663 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.671 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.671 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.671 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.671 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.672 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.673 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_B[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.695 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_R[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.953 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.954 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.955 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -7.955 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.099 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[5]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.100 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[4]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.101 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[2]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.101 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[1]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.268 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.268 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.268 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.269 ns ; iSW[14]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.414 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[0]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.414 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[3]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.414 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[7]                             ; iCLK_50_2     ;
; N/A           ; None        ; -8.415 ns ; iSW[15]     ; touch_tcon:vga0|oLCD_G[6]                             ; iCLK_50_2     ;
+---------------+-------------+-----------+-------------+-------------------------------------------------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Ignored Timing Assignments                                                                                                                                     ;
+-----------------+---------+------+----------------------------------+-------------+----------------------------------------------------------------------------+
; Option          ; Setting ; From ; To                               ; Entity Name ; Help                                                                       ;
+-----------------+---------+------+----------------------------------+-------------+----------------------------------------------------------------------------+
; tco Requirement ; 1 ns    ; *    ; CCD_Capture:u3|Pre_FVAL          ;             ; No element named CCD_Capture:u3|Pre_FVAL was found in the netlist          ;
; tco Requirement ; 1 ns    ; *    ; CCD_Capture:u3|mCCD_DATA         ;             ; No element named CCD_Capture:u3|mCCD_DATA was found in the netlist         ;
; tco Requirement ; 1 ns    ; *    ; CCD_Capture:u3|mCCD_LVAL         ;             ; No element named CCD_Capture:u3|mCCD_LVAL was found in the netlist         ;
; tco Requirement ; 1 ns    ; *    ; Sdram_Control_4Port:u11|mDATAOUT ;             ; No element named Sdram_Control_4Port:u11|mDATAOUT was found in the netlist ;
; tco Requirement ; 1 ns    ; *    ; Sdram_Control_4Port:u6|mDATAOUT  ;             ; No element named Sdram_Control_4Port:u6|mDATAOUT was found in the netlist  ;
+-----------------+---------+------+----------------------------------+-------------+----------------------------------------------------------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Sat Sep 27 16:44:22 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DE2_70 -c DE2_70 --timing_analysis_only
Info: Parallel compilation is enabled and will use up to 2 processors
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Warning: Clock Setting "CLK" is unassigned
Warning: Clock Setting "VGA_CTRL_CLK" is unassigned
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "I2C_CCD_Config:i2c_ccd_config0|mI2C_CTRL_CLK" as buffer
    Info: Detected ripple clock "lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK" as buffer
    Info: Detected ripple clock "Reset_Delay:reset0|oRST_1" as buffer
    Info: Detected ripple clock "RAW2RGB:raw0|dval_ctrl" as buffer
Info: Found timing assignments -- calculating delays
Info: Slack time is 938 ps for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" between source register "Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]" and destination register "Sdram_Control_4Port:sdram1|mADDR[19]"
    Info: Fmax is 197.55 MHz (period= 5.062 ns)
    Info: + Largest register to register requirement is 5.807 ns
        Info: + Setup relationship between source and destination is 6.000 ns
            Info: + Latch edge is 3.406 ns
                Info: Clock period of Destination clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is -2.594 ns
                Info: Clock period of Source clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.021 ns
            Info: + Shortest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to destination register is 2.802 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.217 ns) + CELL(0.537 ns) = 2.802 ns; Loc. = LCFF_X13_Y18_N25; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|mADDR[19]'
                Info: Total cell delay = 0.537 ns ( 19.16 % )
                Info: Total interconnect delay = 2.265 ns ( 80.84 % )
            Info: - Longest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to source register is 2.781 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.196 ns) + CELL(0.537 ns) = 2.781 ns; Loc. = LCFF_X35_Y12_N31; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]'
                Info: Total cell delay = 0.537 ns ( 19.31 % )
                Info: Total interconnect delay = 2.244 ns ( 80.69 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 4.869 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y12_N31; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp|dffe10a[0]'
        Info: 2: + IC(0.478 ns) + CELL(0.414 ns) = 0.892 ns; Loc. = LCCOMB_X35_Y12_N6; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~135'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.963 ns; Loc. = LCCOMB_X35_Y12_N8; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~137'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.034 ns; Loc. = LCCOMB_X35_Y12_N10; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~139'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.105 ns; Loc. = LCCOMB_X35_Y12_N12; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~141'
        Info: 6: + IC(0.000 ns) + CELL(0.159 ns) = 1.264 ns; Loc. = LCCOMB_X35_Y12_N14; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~143'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.335 ns; Loc. = LCCOMB_X35_Y12_N16; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~145'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.406 ns; Loc. = LCCOMB_X35_Y12_N18; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~147'
        Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.477 ns; Loc. = LCCOMB_X35_Y12_N20; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~149'
        Info: 10: + IC(0.000 ns) + CELL(0.410 ns) = 1.887 ns; Loc. = LCCOMB_X35_Y12_N22; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_2~150'
        Info: 11: + IC(1.775 ns) + CELL(0.150 ns) = 3.812 ns; Loc. = LCCOMB_X12_Y18_N30; Fanout = 15; COMB Node = 'Sdram_Control_4Port:sdram1|mADDR[8]~374'
        Info: 12: + IC(0.397 ns) + CELL(0.660 ns) = 4.869 ns; Loc. = LCFF_X13_Y18_N25; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|mADDR[19]'
        Info: Total cell delay = 2.219 ns ( 45.57 % )
        Info: Total interconnect delay = 2.650 ns ( 54.43 % )
Info: No valid register-to-register data paths exist for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk1"
Info: No valid register-to-register data paths exist for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk2"
Info: Slack time is 9.736 ns for clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" between source register "Binary:binary0|oDVAL" and destination register "Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]"
    Info: Fmax is 94.98 MHz (period= 10.528 ns)
    Info: + Largest register to register requirement is 14.865 ns
        Info: + Setup relationship between source and destination is 15.000 ns
            Info: + Latch edge is 12.392 ns
                Info: Clock period of Destination clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with inverted offset of 12.392 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is -2.608 ns
                Info: Clock period of Source clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with  offset of -2.608 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.079 ns
            Info: + Shortest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to destination register is 2.815 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 182; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.240 ns) + CELL(0.537 ns) = 2.815 ns; Loc. = LCFF_X20_Y7_N29; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]'
                Info: Total cell delay = 0.537 ns ( 19.08 % )
                Info: Total interconnect delay = 2.278 ns ( 80.92 % )
            Info: - Longest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to source register is 2.736 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 182; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.161 ns) + CELL(0.537 ns) = 2.736 ns; Loc. = LCFF_X32_Y14_N17; Fanout = 4; REG Node = 'Binary:binary0|oDVAL'
                Info: Total cell delay = 0.537 ns ( 19.63 % )
                Info: Total interconnect delay = 2.199 ns ( 80.37 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 5.129 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y14_N17; Fanout = 4; REG Node = 'Binary:binary0|oDVAL'
        Info: 2: + IC(1.877 ns) + CELL(0.420 ns) = 2.297 ns; Loc. = LCCOMB_X19_Y7_N24; Fanout = 22; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|rdcnt_addr_ena'
        Info: 3: + IC(1.197 ns) + CELL(0.414 ns) = 3.908 ns; Loc. = LCCOMB_X20_Y7_N8; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|parity~COUT'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 3.979 ns; Loc. = LCCOMB_X20_Y7_N10; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera0~COUT'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 4.050 ns; Loc. = LCCOMB_X20_Y7_N12; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera1~COUT'
        Info: 6: + IC(0.000 ns) + CELL(0.159 ns) = 4.209 ns; Loc. = LCCOMB_X20_Y7_N14; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera2~COUT'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 4.280 ns; Loc. = LCCOMB_X20_Y7_N16; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera3~COUT'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 4.351 ns; Loc. = LCCOMB_X20_Y7_N18; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera4~COUT'
        Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 4.422 ns; Loc. = LCCOMB_X20_Y7_N20; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera5~COUT'
        Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 4.493 ns; Loc. = LCCOMB_X20_Y7_N22; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera6~COUT'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 4.564 ns; Loc. = LCCOMB_X20_Y7_N24; Fanout = 2; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera7~COUT'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 4.635 ns; Loc. = LCCOMB_X20_Y7_N26; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera8~COUT'
        Info: 13: + IC(0.000 ns) + CELL(0.410 ns) = 5.045 ns; Loc. = LCCOMB_X20_Y7_N28; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|countera9'
        Info: 14: + IC(0.000 ns) + CELL(0.084 ns) = 5.129 ns; Loc. = LCFF_X20_Y7_N29; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram0|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]'
        Info: Total cell delay = 2.055 ns ( 40.07 % )
        Info: Total interconnect delay = 3.074 ns ( 59.93 % )
Info: Slack time is 2.171 ns for clock "GPIO_CLKIN_N1" between source register "CCD_Capture:capture0|Y_Cont[7]" and destination register "RAW2RGB:raw0|rGreen[10]"
    Info: Fmax is 144.53 MHz (period= 6.919 ns)
    Info: + Largest register to register requirement is 8.869 ns
        Info: + Setup relationship between source and destination is 9.090 ns
            Info: + Latch edge is 9.090 ns
                Info: Clock period of Destination clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is -0.007 ns
            Info: + Shortest clock path from clock "GPIO_CLKIN_N1" to destination register is 2.838 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.198 ns) + CELL(0.537 ns) = 2.838 ns; Loc. = LCFF_X59_Y18_N5; Fanout = 1; REG Node = 'RAW2RGB:raw0|rGreen[10]'
                Info: Total cell delay = 1.526 ns ( 53.77 % )
                Info: Total interconnect delay = 1.312 ns ( 46.23 % )
            Info: - Longest clock path from clock "GPIO_CLKIN_N1" to source register is 2.845 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.205 ns) + CELL(0.537 ns) = 2.845 ns; Loc. = LCFF_X58_Y19_N15; Fanout = 4; REG Node = 'CCD_Capture:capture0|Y_Cont[7]'
                Info: Total cell delay = 1.526 ns ( 53.64 % )
                Info: Total interconnect delay = 1.319 ns ( 46.36 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 6.698 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X58_Y19_N15; Fanout = 4; REG Node = 'CCD_Capture:capture0|Y_Cont[7]'
        Info: 2: + IC(0.738 ns) + CELL(0.275 ns) = 1.013 ns; Loc. = LCCOMB_X59_Y19_N16; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Equal6~145'
        Info: 3: + IC(0.264 ns) + CELL(0.438 ns) = 1.715 ns; Loc. = LCCOMB_X59_Y19_N26; Fanout = 40; COMB Node = 'RAW2RGB:raw0|Equal6~148'
        Info: 4: + IC(0.799 ns) + CELL(0.275 ns) = 2.789 ns; Loc. = LCCOMB_X59_Y21_N2; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Add0~6198'
        Info: 5: + IC(0.253 ns) + CELL(0.149 ns) = 3.191 ns; Loc. = LCCOMB_X59_Y21_N30; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Add0~6199'
        Info: 6: + IC(1.004 ns) + CELL(0.414 ns) = 4.609 ns; Loc. = LCCOMB_X60_Y19_N10; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6218'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 4.680 ns; Loc. = LCCOMB_X60_Y19_N12; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6220'
        Info: 8: + IC(0.000 ns) + CELL(0.159 ns) = 4.839 ns; Loc. = LCCOMB_X60_Y19_N14; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6222'
        Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 4.910 ns; Loc. = LCCOMB_X60_Y19_N16; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6224'
        Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 4.981 ns; Loc. = LCCOMB_X60_Y19_N18; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6226'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 5.052 ns; Loc. = LCCOMB_X60_Y19_N20; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6228'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 5.123 ns; Loc. = LCCOMB_X60_Y19_N22; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6230'
        Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 5.194 ns; Loc. = LCCOMB_X60_Y19_N24; Fanout = 2; COMB Node = 'RAW2RGB:raw0|Add0~6237'
        Info: 14: + IC(0.000 ns) + CELL(0.410 ns) = 5.604 ns; Loc. = LCCOMB_X60_Y19_N26; Fanout = 1; COMB Node = 'RAW2RGB:raw0|Add0~6242'
        Info: 15: + IC(0.735 ns) + CELL(0.275 ns) = 6.614 ns; Loc. = LCCOMB_X59_Y18_N4; Fanout = 1; COMB Node = 'RAW2RGB:raw0|rGreen~676'
        Info: 16: + IC(0.000 ns) + CELL(0.084 ns) = 6.698 ns; Loc. = LCFF_X59_Y18_N5; Fanout = 1; REG Node = 'RAW2RGB:raw0|rGreen[10]'
        Info: Total cell delay = 2.905 ns ( 43.37 % )
        Info: Total interconnect delay = 3.793 ns ( 56.63 % )
Info: Slack time is 6.848 ns for clock "iCLK_50" between source register "lcd_3wire_config:lcd_config0|m3wire_data[14]" and destination register "lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA"
    Info: Fmax is 158.63 MHz (period= 6.304 ns)
    Info: + Largest register to register requirement is 9.786 ns
        Info: + Setup relationship between source and destination is 10.000 ns
            Info: + Latch edge is 10.000 ns
                Info: Clock period of Destination clock "iCLK_50" is 20.000 ns with inverted offset of 10.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "iCLK_50" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "iCLK_50" to destination register is 5.092 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(0.725 ns) + CELL(0.787 ns) = 2.471 ns; Loc. = LCFF_X48_Y1_N17; Fanout = 3; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK'
                Info: 3: + IC(0.885 ns) + CELL(0.000 ns) = 3.356 ns; Loc. = CLKCTRL_G13; Fanout = 37; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK~clkctrl'
                Info: 4: + IC(1.199 ns) + CELL(0.537 ns) = 5.092 ns; Loc. = LCFF_X12_Y11_N31; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA'
                Info: Total cell delay = 2.283 ns ( 44.84 % )
                Info: Total interconnect delay = 2.809 ns ( 55.16 % )
            Info: - Longest clock path from clock "iCLK_50" to source register is 5.092 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(0.725 ns) + CELL(0.787 ns) = 2.471 ns; Loc. = LCFF_X48_Y1_N17; Fanout = 3; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK'
                Info: 3: + IC(0.885 ns) + CELL(0.000 ns) = 3.356 ns; Loc. = CLKCTRL_G13; Fanout = 37; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mI2S_CLK~clkctrl'
                Info: 4: + IC(1.199 ns) + CELL(0.537 ns) = 5.092 ns; Loc. = LCFF_X12_Y11_N21; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|m3wire_data[14]'
                Info: Total cell delay = 2.283 ns ( 44.84 % )
                Info: Total interconnect delay = 2.809 ns ( 55.16 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 2.938 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y11_N21; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|m3wire_data[14]'
        Info: 2: + IC(0.329 ns) + CELL(0.437 ns) = 0.766 ns; Loc. = LCCOMB_X12_Y11_N24; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~167'
        Info: 3: + IC(0.272 ns) + CELL(0.438 ns) = 1.476 ns; Loc. = LCCOMB_X12_Y11_N12; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~168'
        Info: 4: + IC(0.268 ns) + CELL(0.438 ns) = 2.182 ns; Loc. = LCCOMB_X12_Y11_N22; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~169'
        Info: 5: + IC(0.253 ns) + CELL(0.419 ns) = 2.854 ns; Loc. = LCCOMB_X12_Y11_N30; Fanout = 1; COMB Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|Mux0~172'
        Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.938 ns; Loc. = LCFF_X12_Y11_N31; Fanout = 1; REG Node = 'lcd_3wire_config:lcd_config0|I2S_Controller:u0|mSDATA'
        Info: Total cell delay = 1.816 ns ( 61.81 % )
        Info: Total interconnect delay = 1.122 ns ( 38.19 % )
Info: No valid register-to-register data paths exist for clock "GPIO_CLKOUT_N1"
Info: No valid register-to-register data paths exist for clock "oDRAM0_CLK"
Info: No valid register-to-register data paths exist for clock "iCLK_50_3"
Info: No valid register-to-register data paths exist for clock "iCLK_50_2"
Info: Minimum slack time is 391 ps for clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" between source register "Sdram_Control_4Port:sdram1|command:command1|do_rw" and destination register "Sdram_Control_4Port:sdram1|command:command1|do_rw"
    Info: + Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y18_N13; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X9_Y18_N12; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw~49'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X9_Y18_N13; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is -2.594 ns
                Info: Clock period of Destination clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is -2.594 ns
                Info: Clock period of Source clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is 6.000 ns with  offset of -2.594 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to destination register is 2.795 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.210 ns) + CELL(0.537 ns) = 2.795 ns; Loc. = LCFF_X9_Y18_N13; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
                Info: Total cell delay = 0.537 ns ( 19.21 % )
                Info: Total interconnect delay = 2.258 ns ( 80.79 % )
            Info: - Shortest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to source register is 2.795 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.210 ns) + CELL(0.537 ns) = 2.795 ns; Loc. = LCFF_X9_Y18_N13; Fanout = 3; REG Node = 'Sdram_Control_4Port:sdram1|command:command1|do_rw'
                Info: Total cell delay = 0.537 ns ( 19.21 % )
                Info: Total interconnect delay = 2.258 ns ( 80.79 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Info: Minimum slack time is 528 ps for clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" between source register "touch_tcon:vga0|mvd" and destination register "touch_tcon:vga0|oVD"
    Info: + Shortest register to register delay is 0.544 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y14_N11; Fanout = 1; REG Node = 'touch_tcon:vga0|mvd'
        Info: 2: + IC(0.310 ns) + CELL(0.150 ns) = 0.460 ns; Loc. = LCCOMB_X33_Y14_N0; Fanout = 1; COMB Node = 'touch_tcon:vga0|oVD~2'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.544 ns; Loc. = LCFF_X33_Y14_N1; Fanout = 1; REG Node = 'touch_tcon:vga0|oVD'
        Info: Total cell delay = 0.234 ns ( 43.01 % )
        Info: Total interconnect delay = 0.310 ns ( 56.99 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is -2.608 ns
                Info: Clock period of Destination clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with  offset of -2.608 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is -2.608 ns
                Info: Clock period of Source clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" is 30.000 ns with  offset of -2.608 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to destination register is 2.738 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 182; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.163 ns) + CELL(0.537 ns) = 2.738 ns; Loc. = LCFF_X33_Y14_N1; Fanout = 1; REG Node = 'touch_tcon:vga0|oVD'
                Info: Total cell delay = 0.537 ns ( 19.61 % )
                Info: Total interconnect delay = 2.201 ns ( 80.39 % )
            Info: - Shortest clock path from clock "vga_pll:vga_pll0|altpll:altpll_component|_clk0" to source register is 2.738 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.038 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G11; Fanout = 182; COMB Node = 'vga_pll:vga_pll0|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(1.163 ns) + CELL(0.537 ns) = 2.738 ns; Loc. = LCFF_X33_Y14_N11; Fanout = 1; REG Node = 'touch_tcon:vga0|mvd'
                Info: Total cell delay = 0.537 ns ( 19.61 % )
                Info: Total interconnect delay = 2.201 ns ( 80.39 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Info: Minimum slack time is 391 ps for clock "GPIO_CLKIN_N1" between source register "CCD_Capture:capture0|mCCD_FVAL" and destination register "CCD_Capture:capture0|mCCD_FVAL"
    Info: + Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y24_N11; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X12_Y24_N10; Fanout = 1; COMB Node = 'CCD_Capture:capture0|mCCD_FVAL~40'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X12_Y24_N11; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "GPIO_CLKIN_N1" is 9.090 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "GPIO_CLKIN_N1" to destination register is 2.866 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.226 ns) + CELL(0.537 ns) = 2.866 ns; Loc. = LCFF_X12_Y24_N11; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
                Info: Total cell delay = 1.526 ns ( 53.24 % )
                Info: Total interconnect delay = 1.340 ns ( 46.76 % )
            Info: - Shortest clock path from clock "GPIO_CLKIN_N1" to source register is 2.866 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AH14; Fanout = 2; CLK Node = 'GPIO_CLKIN_N1'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G15; Fanout = 665; COMB Node = 'GPIO_CLKIN_N1~clkctrl'
                Info: 3: + IC(1.226 ns) + CELL(0.537 ns) = 2.866 ns; Loc. = LCFF_X12_Y24_N11; Fanout = 20; REG Node = 'CCD_Capture:capture0|mCCD_FVAL'
                Info: Total cell delay = 1.526 ns ( 53.24 % )
                Info: Total interconnect delay = 1.340 ns ( 46.76 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Info: Minimum slack time is 391 ps for clock "iCLK_50" between source register "rClk[0]" and destination register "rClk[0]"
    Info: + Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X94_Y3_N0; Fanout = 1; COMB Node = 'rClk[0]~3'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "iCLK_50" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "iCLK_50" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "iCLK_50" to destination register is 2.883 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(0.112 ns) + CELL(0.000 ns) = 1.071 ns; Loc. = CLKCTRL_G14; Fanout = 104; COMB Node = 'iCLK_50~clkctrl'
                Info: 3: + IC(1.275 ns) + CELL(0.537 ns) = 2.883 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
                Info: Total cell delay = 1.496 ns ( 51.89 % )
                Info: Total interconnect delay = 1.387 ns ( 48.11 % )
            Info: - Shortest clock path from clock "iCLK_50" to source register is 2.883 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
                Info: 2: + IC(0.112 ns) + CELL(0.000 ns) = 1.071 ns; Loc. = CLKCTRL_G14; Fanout = 104; COMB Node = 'iCLK_50~clkctrl'
                Info: 3: + IC(1.275 ns) + CELL(0.537 ns) = 2.883 ns; Loc. = LCFF_X94_Y3_N1; Fanout = 2; REG Node = 'rClk[0]'
                Info: Total cell delay = 1.496 ns ( 51.89 % )
                Info: Total interconnect delay = 1.387 ns ( 48.11 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Warning: Can't achieve timing requirement tsu along 26 path(s). See Report window for details.
Info: Slack time is -330 ps for clock "iCLK_50_3" between source pin "DRAM_DQ[30]" and destination register "Sdram_Control_4Port:sdram1|mDATAOUT[14]"
    Info: + tsu requirement for source pin and destination register is 1.000 ns
    Info: - tsu from clock to input pin is 1.330 ns
        Info: + Longest pin to register delay is 1.229 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB1; Fanout = 1; PIN Node = 'DRAM_DQ[30]'
            Info: 2: + IC(0.000 ns) + CELL(1.229 ns) = 1.229 ns; Loc. = IOC_X0_Y14_N2; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|mDATAOUT[14]'
            Info: Total cell delay = 1.229 ns ( 100.00 % )
        Info: - Offset between input clock "iCLK_50_3" and output clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is -2.594 ns
        Info: + Micro setup delay of destination is 0.076 ns
        Info: - Shortest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to destination register is 2.569 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
            Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
            Info: 3: + IC(1.253 ns) + CELL(0.268 ns) = 2.569 ns; Loc. = IOC_X0_Y14_N2; Fanout = 1; REG Node = 'Sdram_Control_4Port:sdram1|mDATAOUT[14]'
            Info: Total cell delay = 0.268 ns ( 10.43 % )
            Info: Total interconnect delay = 2.301 ns ( 89.57 % )
Warning: Can't achieve timing requirement tco along 128 path(s). See Report window for details.
Info: Slack time is -5.033 ns for clock "iCLK_50_3" between source memory "Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]" and destination pin "DRAM_DQ[19]"
    Info: + tco requirement for source memory and destination pin is 1.000 ns
    Info: - tco from clock to output pin is 6.033 ns
        Info: + Offset between input clock "iCLK_50_3" and output clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" is -2.594 ns
        Info: + Longest clock path from clock "sdram_pll:sdram_pll0|altpll:altpll_component|_clk0" to source memory is 2.826 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0'
            Info: 2: + IC(1.048 ns) + CELL(0.000 ns) = 1.048 ns; Loc. = CLKCTRL_G7; Fanout = 839; COMB Node = 'sdram_pll:sdram_pll0|altpll:altpll_component|_clk0~clkctrl'
            Info: 3: + IC(1.143 ns) + CELL(0.635 ns) = 2.826 ns; Loc. = M4K_X17_Y17; Fanout = 1; MEM Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]'
            Info: Total cell delay = 0.635 ns ( 22.47 % )
            Info: Total interconnect delay = 2.191 ns ( 77.53 % )
        Info: + Micro clock to output delay of source is 0.209 ns
        Info: + Longest memory to pin delay is 5.592 ns
            Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X17_Y17; Fanout = 1; MEM Node = 'Sdram_Control_4Port:sdram1|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|q_a[3]'
            Info: 2: + IC(0.932 ns) + CELL(0.271 ns) = 1.291 ns; Loc. = LCCOMB_X16_Y18_N12; Fanout = 1; COMB Node = 'Sdram_Control_4Port:sdram1|mDATAIN[3]~163'
            Info: 3: + IC(1.659 ns) + CELL(2.642 ns) = 5.592 ns; Loc. = PIN_V2; Fanout = 0; PIN Node = 'DRAM_DQ[19]'
            Info: Total cell delay = 3.001 ns ( 53.67 % )
            Info: Total interconnect delay = 2.591 ns ( 46.33 % )
Info: Longest tpd from source pin "iSW[14]" to destination pin "oLEDR[14]" is 11.343 ns
    Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L5; Fanout = 18; PIN Node = 'iSW[14]'
    Info: 2: + IC(7.743 ns) + CELL(2.768 ns) = 11.343 ns; Loc. = PIN_AC11; Fanout = 0; PIN Node = 'oLEDR[14]'
    Info: Total cell delay = 3.600 ns ( 31.74 % )
    Info: Total interconnect delay = 7.743 ns ( 68.26 % )
Info: th for register "RAW2RGB:raw0|mirror_sw" (data pin = "iSW[17]", clock pin = "iCLK_50") is -0.986 ns
    Info: + Longest clock path from clock "iCLK_50" to destination register is 6.767 ns
        Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_AD15; Fanout = 4; CLK Node = 'iCLK_50'
        Info: 2: + IC(1.420 ns) + CELL(0.787 ns) = 3.166 ns; Loc. = LCFF_X48_Y20_N29; Fanout = 4; REG Node = 'Reset_Delay:reset0|oRST_1'
        Info: 3: + IC(1.839 ns) + CELL(0.000 ns) = 5.005 ns; Loc. = CLKCTRL_G9; Fanout = 146; COMB Node = 'Reset_Delay:reset0|oRST_1~clkctrl'
        Info: 4: + IC(1.225 ns) + CELL(0.537 ns) = 6.767 ns; Loc. = LCFF_X56_Y20_N17; Fanout = 23; REG Node = 'RAW2RGB:raw0|mirror_sw'
        Info: Total cell delay = 2.283 ns ( 33.74 % )
        Info: Total interconnect delay = 4.484 ns ( 66.26 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 8.019 ns
        Info: 1: + IC(0.000 ns) + CELL(0.812 ns) = 0.812 ns; Loc. = PIN_L8; Fanout = 3; PIN Node = 'iSW[17]'
        Info: 2: + IC(6.974 ns) + CELL(0.149 ns) = 7.935 ns; Loc. = LCCOMB_X56_Y20_N16; Fanout = 1; COMB Node = 'RAW2RGB:raw0|mirror_sw~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 8.019 ns; Loc. = LCFF_X56_Y20_N17; Fanout = 23; REG Node = 'RAW2RGB:raw0|mirror_sw'
        Info: Total cell delay = 1.045 ns ( 13.03 % )
        Info: Total interconnect delay = 6.974 ns ( 86.97 % )
Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.
Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 8 warnings
    Info: Peak virtual memory: 144 megabytes
    Info: Processing ended: Sat Sep 27 16:44:25 2008
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:03


