/* 
(C) OOMusou 2008 http://oomusou.cnblogs.com

Filename    : Binary.v
Compiler    : Quartus II 8.0
Description : Demo how to implement binary image in Verilog
Release     : 09/20/2008 1.0
*/

module Binary (
  input            iCLK,
  input            iRST_N,
  input      [9:0] iTHRESHOLD,
  input            iDVAL,
  input      [9:0] iDATA,
  output reg       oDVAL,
  output reg [9:0] oDATA
);

always@(posedge iCLK, negedge iRST_N) begin
  if (!iRST_N) begin
    oDVAL <= 1'b0;
    oDATA <= 10'h0;
  end
  else begin
    oDVAL <= iDVAL;
    
    if (iDVAL)
      oDATA <= (iDATA > iTHRESHOLD) ? 1023 : 0;
    else
      oDATA <= 10'b0;
  end
end

endmodule