SYSTEM DE2_70_SOPC
{
   System_Wizard_Version = "7.20";
   System_Wizard_Build = "207";
   # 
   # Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF
   # Date: 2008.09.17.14:05:59
   # 
   #    clock_source "clk_50"
   #    altera_nios2 "cpu"
   #    altera_avalon_new_sdram_controller "sdram_u1"
   #    altera_avalon_new_sdram_controller "sdram_u2"
   #    altera_avalon_cy7c1380_ssram "ssram"
   #    altera_avalon_tri_state_bridge "tristate_bridge_ssram"
   #    altera_avalon_cfi_flash "cfi_flash"
   #    altera_avalon_sysid "sysid"
   #    altera_avalon_timer "timer"
   #    altera_avalon_timer "timer_stamp"
   #    altera_avalon_jtag_uart "jtag_uart"
   #    altera_avalon_pll "pll"
   #    altera_avalon_tri_state_bridge "tristate_bridge_flash"
   #    clock_source "clk_25"
   # 
   #    Contains 32 connections.
   # 
   Builder_Application = "sopc_builder_ca";
   #. values for Builder_Application are:
   #.    sopc_builder_preview --> 6.1p, 7.0p prerelease versions
   #.    sopc_builder_ca      --> 7.1 and later
   #.    (missing) --> 6.0 or earlier
   WIZARD_SCRIPT_ARGUMENTS 
   {
      hdl_language = "verilog";
      device_family = "CYCLONEII";
      device_family_id = "CYCLONEII";
      generate_sdk = "0";
      do_build_sim = "0";
      hardcopy_compatible = "0";
      CLOCKS 
      {
         CLOCK clk_50
         {
            frequency = "50000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "clk_50";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "clk_50.clk";
         }
         CLOCK pll_c0
         {
            frequency = "100000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c0 from pll";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "pll.c0";
         }
         CLOCK pll_c0_system
         {
            frequency = "100000000";
            source = "pll_c0";
            Is_Clock_Source = "0";
            display_name = "pll_c0_system";
         }
         CLOCK pll_c1
         {
            frequency = "100000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c1 from pll";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "pll.c1";
         }
         CLOCK pll_c1_memory
         {
            frequency = "100000000";
            source = "pll_c1";
            Is_Clock_Source = "0";
            display_name = "pll_c1_memory";
         }
         CLOCK pll_c2
         {
            frequency = "18181818";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c2 from pll";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "pll.c2";
         }
         CLOCK pll_c2_audio
         {
            frequency = "18181818";
            source = "pll_c2";
            Is_Clock_Source = "0";
            display_name = "pll_c2_audio";
         }
         CLOCK clk_25
         {
            frequency = "25000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "clk_25";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "clk_25.clk";
         }
      }
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      clock_freq = "50000000";
      board_class = "";
      view_master_columns = "1";
      view_master_priorities = "0";
      generate_hdl = "";
      bustype_column_width = "0";
      clock_column_width = "80";
      name_column_width = "75";
      desc_column_width = "75";
      base_column_width = "75";
      end_column_width = "75";
      BOARD_INFO 
      {
         altera_avalon_cfi_flash 
         {
            reference_designators = "";
         }
      }
   }
   MODULE cpu
   {
      MASTER instruction_master
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_address
            {
               type = "address";
               width = "28";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT i_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT i_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "28";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "";
            Linewrap_Bursts = "";
            Burst_On_Burst_Boundaries_Only = "";
            Always_Burst_Max_Burst = "";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Address_Group = "0";
            Has_IRQ = "0";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-0";
         }
         MEMORY_MAP 
         {
            Entry cpu/jtag_debug_module
            {
               address = "0x09604800";
               span = "0x00000800";
            }
            Entry sdram_u1/s1
            {
               address = "0x04000000";
               span = "0x02000000";
            }
            Entry sdram_u2/s1
            {
               address = "0x06000000";
               span = "0x02000000";
            }
            Entry ssram/s1
            {
               address = "0x09200000";
               span = "0x00200000";
            }
            Entry cfi_flash/s1
            {
               address = "0x08800000";
               span = "0x00800000";
            }
         }
      }
      MASTER custom_instruction_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Is_Custom_Instruction = "1";
            Is_Enabled = "0";
            Max_Address_Width = "8";
            Base_Address = "N/A";
            Is_Visible = "0";
         }
         PORT_WIRING 
         {
            PORT dataa
            {
               type = "dataa";
               width = "32";
               direction = "output";
            }
            PORT datab
            {
               type = "datab";
               width = "32";
               direction = "output";
            }
            PORT result
            {
               type = "result";
               width = "32";
               direction = "input";
            }
            PORT clk_en
            {
               type = "clk_en";
               width = "1";
               direction = "output";
            }
            PORT reset
            {
               type = "reset";
               width = "1";
               direction = "output";
            }
            PORT start
            {
               type = "start";
               width = "1";
               direction = "output";
            }
            PORT done
            {
               type = "done";
               width = "1";
               direction = "input";
            }
            PORT n
            {
               type = "n";
               width = "8";
               direction = "output";
            }
            PORT a
            {
               type = "a";
               width = "5";
               direction = "output";
            }
            PORT b
            {
               type = "b";
               width = "5";
               direction = "output";
            }
            PORT c
            {
               type = "c";
               width = "5";
               direction = "output";
            }
            PORT readra
            {
               type = "readra";
               width = "1";
               direction = "output";
            }
            PORT readrb
            {
               type = "readrb";
               width = "1";
               direction = "output";
            }
            PORT writerc
            {
               type = "writerc";
               width = "1";
               direction = "output";
            }
         }
      }
      SLAVE jtag_debug_module
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "2048";
            Read_Latency = "0";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "9";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Accepts_External_Connections = "1";
            Requires_Internal_Connections = "";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x09604800";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x09604800";
            }
            Base_Address = "0x09604800";
            Is_Readable = "1";
            Is_Writeable = "1";
            Uses_Tri_State_Data_Bus = "0";
            Has_IRQ = "0";
            JTAG_Hub_Base_Id = "1118278";
            JTAG_Hub_Instance_Id = "0";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
         PORT_WIRING 
         {
            PORT jtag_debug_module_address
            {
               type = "address";
               width = "9";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_begintransfer
            {
               type = "begintransfer";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_debugaccess
            {
               type = "debugaccess";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_reset
            {
               type = "reset";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_resetrequest
            {
               type = "resetrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_select
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
         }
      }
      MASTER data_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Irq_Scheme = "individual_requests";
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "28";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Data_Master = "1";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
            Interrupt_Range = "0-31";
         }
         PORT_WIRING 
         {
            PORT d_irq
            {
               type = "irq";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_address
            {
               type = "address";
               width = "28";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_debugaccess_to_roms
            {
               type = "debugaccess";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry cpu/jtag_debug_module
            {
               address = "0x09604800";
               span = "0x00000800";
            }
            Entry sdram_u1/s1
            {
               address = "0x04000000";
               span = "0x02000000";
            }
            Entry sdram_u2/s1
            {
               address = "0x06000000";
               span = "0x02000000";
            }
            Entry ssram/s1
            {
               address = "0x09200000";
               span = "0x00200000";
            }
            Entry sysid/control_slave
            {
               address = "0x096051d0";
               span = "0x00000008";
            }
            Entry timer/s1
            {
               address = "0x09605080";
               span = "0x00000020";
            }
            Entry timer_stamp/s1
            {
               address = "0x096050a0";
               span = "0x00000020";
            }
            Entry pll/s1
            {
               address = "0x096050e0";
               span = "0x00000020";
            }
            Entry cfi_flash/s1
            {
               address = "0x08800000";
               span = "0x00800000";
            }
            Entry jtag_uart/avalon_jtag_slave
            {
               address = "0x096051e8";
               span = "0x00000008";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         cache_has_dcache = "1";
         cache_dcache_size = "2048";
         cache_dcache_line_size = "32";
         cache_dcache_bursts = "0";
         cache_dcache_ram_block_type = "AUTO";
         num_tightly_coupled_data_masters = "0";
         gui_num_tightly_coupled_data_masters = "0";
         gui_include_tightly_coupled_data_masters = "0";
         gui_omit_avalon_data_master = "0";
         cache_has_icache = "1";
         cache_icache_size = "4096";
         cache_icache_line_size = "32";
         cache_icache_ram_block_type = "AUTO";
         cache_icache_bursts = "0";
         num_tightly_coupled_instruction_masters = "0";
         gui_num_tightly_coupled_instruction_masters = "0";
         gui_include_tightly_coupled_instruction_masters = "0";
         debug_level = "2";
         include_oci = "1";
         oci_sbi_enabled = "1";
         oci_num_xbrk = "0";
         oci_num_dbrk = "0";
         oci_dbrk_trace = "0";
         oci_dbrk_pairs = "0";
         oci_onchip_trace = "0";
         oci_offchip_trace = "0";
         oci_data_trace = "0";
         include_third_party_debug_port = "0";
         oci_trace_addr_width = "7";
         oci_trigger_arming = "1";
         oci_debugreq_signals = "0";
         oci_embedded_pll = "1";
         oci_num_pm = "0";
         oci_pm_width = "32";
         performance_counters_present = "0";
         performance_counters_width = "32";
         always_encrypt = "1";
         debug_simgen = "0";
         activate_model_checker = "0";
         activate_test_end_checker = "0";
         activate_trace = "1";
         activate_monitors = "1";
         clear_x_bits_ld_non_bypass = "1";
         bit_31_bypass_dcache = "1";
         always_bypass_dcache = "0";
         hdl_sim_caches_cleared = "1";
         hbreak_test = "0";
         allow_full_address_range = "0";
         branch_prediction_type = "Dynamic";
         bht_ptr_sz = "8";
         bht_index_pc_only = "0";
         gui_branch_prediction_type = "Automatic";
         full_waveform_signals = "0";
         export_pcb = "0";
         avalon_debug_port_present = "0";
         gui_illegal_instructions_trap = "0";
         gui_illegal_memory_access_detection = "0";
         illegal_mem_exc = "0";
         slave_access_error_exc = "0";
         division_error_exc = "0";
         gui_mmu_present = "0";
         process_id_num_bits = "10";
         dtlb_ptr_sz = "7";
         itlb_ptr_sz = "7";
         dtlb_num_ways = "4";
         itlb_num_ways = "4";
         udtlb_num_entries = "6";
         uitlb_num_entries = "4";
         fast_tlb_miss_exc_slave = "";
         fast_tlb_miss_exc_offset = "0x00000000";
         hardware_divide_present = "0";
         gui_hardware_divide_setting = "0";
         hardware_multiply_present = "1";
         hardware_multiply_impl = "embedded_mul";
         shift_rot_impl = "fast_le_shift";
         gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";
         reset_slave = "cfi_flash/s1";
         break_slave = "cpu/jtag_debug_module";
         exc_slave = "ssram/s1";
         reset_offset = "0x00000000";
         break_offset = "0x00000020";
         exc_offset = "0x00000020";
         cpu_reset = "0";
         CPU_Implementation = "fast";
         cpu_selection = "f";
         device_family_id = "CYCLONEII";
         address_stall_present = "1";
         dsp_block_supports_shift = "0";
         mrams_present = "0";
         do_generate = "1";
         cpuid_value = "0";
         cpuid_sz = "1";
         dont_overwrite_cpuid = "1";
         allow_legacy_sdk = "1";
         legacy_sdk_support = "1";
         inst_addr_width = "28";
         data_addr_width = "28";
         asp_debug = "0";
         asp_core_debug = "0";
         CPU_Architecture = "nios2";
         cache_icache_burst_type = "none";
         include_debug = "0";
         include_trace = "0";
         hardware_multiply_uses_les = "0";
         hardware_multiply_omits_msw = "1";
         big_endian = "0";
         break_slave_override = "";
         break_offset_override = "0x20";
         altera_show_unreleased_features = "0";
         altera_show_unpublished_features = "0";
         altera_internal_test = "0";
         alt_log_port_base = "";
         alt_log_port_type = "";
         mmu_present = "0";
         nmi_present = "0";
         fast_intr_present = "0";
         num_shadow_regs = "0";
         illegal_instructions_trap = "0";
         illegal_memory_access_detection = "0";
         cache_omit_dcache = "0";
         cache_omit_icache = "0";
         omit_instruction_master = "0";
         omit_data_master = "0";
         ras_ptr_sz = "4";
         jtb_ptr_sz = "5";
         ibuf_ptr_sz = "4";
         iss_trace_on = "0";
         iss_trace_warning = "1";
         iss_trace_info = "1";
         iss_trace_disassembly = "0";
         iss_trace_registers = "0";
         iss_trace_instr_count = "0";
         iss_software_debug = "0";
         iss_software_debug_port = "9996";
         iss_memory_dump_start = "";
         iss_memory_dump_end = "";
         Boot_Copier = "boot_loader_cfi.srec";
         Boot_Copier_EPCS = "boot_loader_epcs.srec";
         Boot_Copier_EPCS_SII_CIII = "boot_loader_epcs_sii_ciii.srec";
         Boot_Copier_BE = "boot_loader_cfi_be.srec";
         Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";
         Boot_Copier_EPCS_SII_CIII_BE = "boot_loader_epcs_sii_ciii_be.srec";
         CONSTANTS 
         {
            CONSTANT __nios_catch_irqs__
            {
               value = "1";
               comment = "Include panic handler for all irqs (needs uart)";
            }
            CONSTANT __nios_use_constructors__
            {
               value = "1";
               comment = "Call c++ static constructors";
            }
            CONSTANT __nios_use_small_printf__
            {
               value = "1";
               comment = "Smaller non-ANSI printf, with no floating point";
            }
            CONSTANT nasys_has_icache
            {
               value = "1";
               comment = "True if instruction cache present";
            }
            CONSTANT nasys_icache_size
            {
               value = "4096";
               comment = "Size in bytes of instruction cache";
            }
            CONSTANT nasys_icache_line_size
            {
               value = "32";
               comment = "Size in bytes of each icache line";
            }
            CONSTANT nasys_icache_line_size_log2
            {
               value = "5";
               comment = "Log2 size in bytes of each icache line";
            }
            CONSTANT nasys_has_dcache
            {
               value = "1";
               comment = "True if instruction cache present";
            }
            CONSTANT nasys_dcache_size
            {
               value = "2048";
               comment = "Size in bytes of data cache";
            }
            CONSTANT nasys_dcache_line_size
            {
               value = "32";
               comment = "Size in bytes of each dcache line";
            }
            CONSTANT nasys_dcache_line_size_log2
            {
               value = "5";
               comment = "Log2 size in bytes of each dcache line";
            }
         }
         license_status = "";
         mainmem_slave = "cfi_flash/s1";
         datamem_slave = "cfi_flash/s1";
         maincomm_slave = "";
         germs_monitor_id = "";
         advanced_exc = "0";
      }
      class = "altera_nios2";
      class_version = "7.071";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
         Parameters_Signature = "";
         Is_CPU = "1";
         Instantiate_In_System_Module = "1";
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,CYCLONE,CYCLONEII,CYCLONEIII";
         Default_Module_Name = "cpu";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = "Nios II/f
            <br>&nbsp;&nbsp;4-Kbyte Instruction Cache
            <br>&nbsp;&nbsp;2-Kbyte Data Cache
            <br>&nbsp;&nbsp;JTAG Debug Module
            ";
            MESSAGES 
            {
            }
         }
      }
      iss_model_name = "altera_nios2";
      HDL_INFO 
      {
         # The list of files associated with this module (for synthesis
         # and other purposes) depends on the users' wizard-choices.
         # This section will be filled-in by the Generator_Program
         # after the module logic has been created and the
         # various filenames are known.
      }
      MASTER tightly_coupled_instruction_master_0
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_1
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_2
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_3
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER data_master2
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
         }
      }
      MASTER tightly_coupled_data_master_0
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_1
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_2
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_3
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      PORT_WIRING 
      {
         PORT jtag_debug_trigout
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_clk
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_data
         {
            width = "18";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT clkx2
         {
            width = "1";
            direction = "input";
            Is_Enabled = "0";
            visible = "0";
         }
      }
   }
   MODULE sdram_u1
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_addr
            {
               type = "address";
               width = "24";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_be_n
            {
               type = "byteenable_n";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_cs
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_data
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_rd_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_wr_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT za_data
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT za_valid
            {
               type = "readdatavalid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT za_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT zs_addr
            {
               direction = "output";
               width = "13";
               Is_Enabled = "1";
            }
            PORT zs_ba
            {
               direction = "output";
               width = "2";
               Is_Enabled = "1";
            }
            PORT zs_cas_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_cke
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_cs_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_dq
            {
               direction = "inout";
               width = "16";
               Is_Enabled = "1";
            }
            PORT zs_dqm
            {
               direction = "output";
               width = "2";
               Is_Enabled = "1";
            }
            PORT zs_ras_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_we_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "33554432";
            Read_Latency = "0";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "7";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "24";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x04000000";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x04000000";
            }
            Base_Address = "0x04000000";
            Has_IRQ = "0";
            Simulation_Num_Lanes = "1";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT zs_addr
         {
            type = "zs_addr";
            width = "13";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_ba
         {
            type = "zs_ba";
            width = "2";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_cas_n
         {
            type = "zs_cas_n";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_cke
         {
            type = "zs_cke";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_cs_n
         {
            type = "zs_cs_n";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_dq
         {
            type = "zs_dq";
            width = "16";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_dqm
         {
            type = "zs_dqm";
            width = "2";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_ras_n
         {
            type = "zs_ras_n";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_we_n
         {
            type = "zs_we_n";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      iss_model_name = "altera_memory";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         register_data_in = "1";
         sim_model_base = "1";
         sdram_data_width = "16";
         sdram_addr_width = "13";
         sdram_row_width = "13";
         sdram_col_width = "9";
         sdram_num_chipselects = "1";
         sdram_num_banks = "4";
         refresh_period = "7.8125";
         powerup_delay = "200.0";
         cas_latency = "3";
         t_rfc = "70.0";
         t_rp = "20.0";
         t_mrd = "3";
         t_rcd = "20.0";
         t_ac = "5.5";
         t_wr = "14.0";
         init_refresh_commands = "2";
         init_nop_delay = "0.0";
         shared_data = "0";
         sdram_bank_width = "2";
         tristate_bridge_slave = "";
         starvation_indicator = "0";
         is_initialized = "1";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "az_addr";
               radix = "hexadecimal";
            }
            SIGNAL b
            {
               name = "az_be_n";
               radix = "hexadecimal";
            }
            SIGNAL c
            {
               name = "az_cs";
            }
            SIGNAL d
            {
               name = "az_data";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "az_rd_n";
            }
            SIGNAL f
            {
               name = "az_wr_n";
            }
            SIGNAL h
            {
               name = "za_data";
               radix = "hexadecimal";
            }
            SIGNAL i
            {
               name = "za_valid";
            }
            SIGNAL j
            {
               name = "za_waitrequest";
            }
            SIGNAL l
            {
               name = "CODE";
               radix = "ascii";
            }
            SIGNAL g
            {
               name = "clk";
            }
            SIGNAL k
            {
               name = "za_cannotrefresh";
               suppress = "1";
            }
            SIGNAL m
            {
               name = "zs_addr";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL n
            {
               name = "zs_ba";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL o
            {
               name = "zs_cs_n";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL p
            {
               name = "zs_ras_n";
               suppress = "0";
            }
            SIGNAL q
            {
               name = "zs_cas_n";
               suppress = "0";
            }
            SIGNAL r
            {
               name = "zs_we_n";
               suppress = "0";
            }
            SIGNAL s
            {
               name = "zs_dq";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL t
            {
               name = "zs_dqm";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL u
            {
               name = "zt_addr";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL v
            {
               name = "zt_ba";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL w
            {
               name = "zt_oe";
               suppress = "1";
            }
            SIGNAL x
            {
               name = "zt_cke";
               suppress = "1";
            }
            SIGNAL y
            {
               name = "zt_chipselect";
               suppress = "1";
            }
            SIGNAL z0
            {
               name = "zt_lock_n";
               suppress = "1";
            }
            SIGNAL z1
            {
               name = "zt_ras_n";
               suppress = "1";
            }
            SIGNAL z2
            {
               name = "zt_cas_n";
               suppress = "1";
            }
            SIGNAL z3
            {
               name = "zt_we_n";
               suppress = "1";
            }
            SIGNAL z4
            {
               name = "zt_cs_n";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z5
            {
               name = "zt_dqm";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z6
            {
               name = "zt_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z7
            {
               name = "tz_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z8
            {
               name = "tz_waitrequest";
               suppress = "1";
            }
         }
         Fix_Me_Up = "";
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sdram";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
         Disable_Simulation_Port_Wiring = "0";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = "16777216 x 16<br>
                Memory size: 32 MBytes<br>
                256 MBits
                ";
         }
      }
      class = "altera_avalon_new_sdram_controller";
      class_version = "7.071";
   }
   MODULE sdram_u2
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_addr
            {
               type = "address";
               width = "24";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_be_n
            {
               type = "byteenable_n";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_cs
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_data
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_rd_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT az_wr_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT za_data
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT za_valid
            {
               type = "readdatavalid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT za_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT zs_addr
            {
               direction = "output";
               width = "13";
               Is_Enabled = "1";
            }
            PORT zs_ba
            {
               direction = "output";
               width = "2";
               Is_Enabled = "1";
            }
            PORT zs_cas_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_cke
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_cs_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_dq
            {
               direction = "inout";
               width = "16";
               Is_Enabled = "1";
            }
            PORT zs_dqm
            {
               direction = "output";
               width = "2";
               Is_Enabled = "1";
            }
            PORT zs_ras_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_we_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "33554432";
            Read_Latency = "0";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "7";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "24";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x06000000";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x06000000";
            }
            Base_Address = "0x06000000";
            Has_IRQ = "0";
            Simulation_Num_Lanes = "1";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT zs_addr
         {
            type = "zs_addr";
            width = "13";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_ba
         {
            type = "zs_ba";
            width = "2";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_cas_n
         {
            type = "zs_cas_n";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_cke
         {
            type = "zs_cke";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_cs_n
         {
            type = "zs_cs_n";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_dq
         {
            type = "zs_dq";
            width = "16";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_dqm
         {
            type = "zs_dqm";
            width = "2";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_ras_n
         {
            type = "zs_ras_n";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT zs_we_n
         {
            type = "zs_we_n";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      iss_model_name = "altera_memory";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         register_data_in = "1";
         sim_model_base = "1";
         sdram_data_width = "16";
         sdram_addr_width = "13";
         sdram_row_width = "13";
         sdram_col_width = "9";
         sdram_num_chipselects = "1";
         sdram_num_banks = "4";
         refresh_period = "7.8125";
         powerup_delay = "200.0";
         cas_latency = "3";
         t_rfc = "70.0";
         t_rp = "20.0";
         t_mrd = "3";
         t_rcd = "20.0";
         t_ac = "5.5";
         t_wr = "14.0";
         init_refresh_commands = "2";
         init_nop_delay = "0.0";
         shared_data = "0";
         sdram_bank_width = "2";
         tristate_bridge_slave = "";
         starvation_indicator = "0";
         is_initialized = "1";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "az_addr";
               radix = "hexadecimal";
            }
            SIGNAL b
            {
               name = "az_be_n";
               radix = "hexadecimal";
            }
            SIGNAL c
            {
               name = "az_cs";
            }
            SIGNAL d
            {
               name = "az_data";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "az_rd_n";
            }
            SIGNAL f
            {
               name = "az_wr_n";
            }
            SIGNAL h
            {
               name = "za_data";
               radix = "hexadecimal";
            }
            SIGNAL i
            {
               name = "za_valid";
            }
            SIGNAL j
            {
               name = "za_waitrequest";
            }
            SIGNAL l
            {
               name = "CODE";
               radix = "ascii";
            }
            SIGNAL g
            {
               name = "clk";
            }
            SIGNAL k
            {
               name = "za_cannotrefresh";
               suppress = "1";
            }
            SIGNAL m
            {
               name = "zs_addr";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL n
            {
               name = "zs_ba";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL o
            {
               name = "zs_cs_n";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL p
            {
               name = "zs_ras_n";
               suppress = "0";
            }
            SIGNAL q
            {
               name = "zs_cas_n";
               suppress = "0";
            }
            SIGNAL r
            {
               name = "zs_we_n";
               suppress = "0";
            }
            SIGNAL s
            {
               name = "zs_dq";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL t
            {
               name = "zs_dqm";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL u
            {
               name = "zt_addr";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL v
            {
               name = "zt_ba";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL w
            {
               name = "zt_oe";
               suppress = "1";
            }
            SIGNAL x
            {
               name = "zt_cke";
               suppress = "1";
            }
            SIGNAL y
            {
               name = "zt_chipselect";
               suppress = "1";
            }
            SIGNAL z0
            {
               name = "zt_lock_n";
               suppress = "1";
            }
            SIGNAL z1
            {
               name = "zt_ras_n";
               suppress = "1";
            }
            SIGNAL z2
            {
               name = "zt_cas_n";
               suppress = "1";
            }
            SIGNAL z3
            {
               name = "zt_we_n";
               suppress = "1";
            }
            SIGNAL z4
            {
               name = "zt_cs_n";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z5
            {
               name = "zt_dqm";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z6
            {
               name = "zt_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z7
            {
               name = "tz_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z8
            {
               name = "tz_waitrequest";
               suppress = "1";
            }
         }
         Fix_Me_Up = "";
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sdram";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
         Disable_Simulation_Port_Wiring = "0";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = "16777216 x 16<br>
                Memory size: 32 MBytes<br>
                256 MBits
                ";
         }
      }
      class = "altera_avalon_new_sdram_controller";
      class_version = "7.071";
   }
   MODULE ssram
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "1";
               visible = "0";
            }
            PORT address
            {
               type = "address";
               width = "19";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT adsc_n
            {
               type = "begintransfer_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT bw_n
            {
               type = "byteenable_n";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT bwe_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT chipenable1_n
            {
               type = "chipselect_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT data
            {
               type = "data";
               width = "32";
               direction = "inout";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT outputenable_n
            {
               type = "outputenable_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "0cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "2097152";
            Read_Latency = "2";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Active_CS_Through_Read_Latency = "1";
            Data_Width = "32";
            Address_Width = "19";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY tristate_bridge_ssram/tristate_master
            {
               priority = "1";
               Offset_Address = "0x09200000";
            }
            Base_Address = "0x09200000";
            Has_IRQ = "0";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         sram_memory_size = "2";
         sram_memory_units = "1048576";
         ssram_data_width = "32";
         ssram_read_latency = "2";
         simulation_model_num_lanes = "4";
      }
      class = "altera_avalon_cy7c1380_ssram";
      class_version = "7.071";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
         Instantiate_In_System_Module = "0";
         Default_Module_Name = "ssram";
         Make_Memory_Model = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      iss_model_name = "altera_memory";
      HDL_INFO 
      {
         # An interface to this memory requires no additional files
         # in the target project directory.
      }
   }
   MODULE tristate_bridge_ssram
   {
      SLAVE avalon_slave
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "1";
            Register_Outgoing_Signals = "1";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            Bridges_To = "tristate_master";
            Base_Address = "N/A";
            Has_IRQ = "0";
            IRQ = "N/A";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Bridges_To = "avalon_slave";
         }
         PORT_WIRING 
         {
         }
         MEMORY_MAP 
         {
            Entry ssram/s1
            {
               address = "0x09200000";
               span = "0x00200000";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      class = "altera_avalon_tri_state_bridge";
      class_version = "7.071";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
   }
   MODULE cfi_flash
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               type = "data";
               width = "16";
               direction = "inout";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT address
            {
               type = "address";
               width = "22";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT select_n
            {
               type = "chipselect_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Write_Wait_States = "100ns";
            Read_Wait_States = "100ns";
            Hold_Time = "0ns";
            Setup_Time = "0ns";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "1";
            Address_Span = "8388608";
            Read_Latency = "0";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "1";
            Active_CS_Through_Read_Latency = "0";
            Data_Width = "16";
            Address_Width = "22";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY tristate_bridge_flash/tristate_master
            {
               priority = "1";
               Offset_Address = "0x08800000";
            }
            Base_Address = "0x08800000";
            Has_IRQ = "0";
            Simulation_Num_Lanes = "1";
            Convert_Xs_To_0 = "1";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_cfi_flash";
            Supports_Flash_File_System = "1";
            flash_reference_designator = "";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Setup_Value = "0";
         Wait_Value = "100";
         Hold_Value = "0";
         Timing_Units = "ns";
         Unit_Multiplier = "1";
         Size = "8388608";
      }
      SYSTEM_BUILDER_INFO 
      {
         Simulation_Num_Lanes = "2";
         Is_Enabled = "1";
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
         Make_Memory_Model = "1";
         Instantiate_In_System_Module = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      class = "altera_avalon_cfi_flash";
      class_version = "7.071";
      iss_model_name = "altera_avalon_flash";
      HDL_INFO 
      {
      }
   }
   MODULE sysid
   {
      SLAVE control_slave
      {
         PORT_WIRING 
         {
            PORT clock
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x096051d0";
            }
            Base_Address = "0x096051d0";
            Has_IRQ = "0";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      class = "altera_avalon_sysid";
      class_version = "7.071";
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Fixed_Module_Name = "sysid";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
         View 
         {
            Settings_Summary = "No system ID yet.  <br> 
                                  A unique ID is assigned every time <br> 
                                  the system is generated.";
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         id = "1982916607";
         timestamp = "1221631551";
         regenerate_values = "0";
      }
      HDL_INFO 
      {
         # The list of files associated with this module (for synthesis
         # and other purposes) depends on the users' wizard-choices.
         # This section will be filled-in by the Generator_Program
         # after the module logic has been created and the
         # various filenames are known.
      }
      PORT_WIRING 
      {
         # The number and kind of ports that appear on this module
         # depends on the user's wizard-choices.
         # This section will be filled-in by the Generator_Program
         # after the module logic has been created and the ports are known.
         #
      }
   }
   MODULE timer
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x09605080";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "0";
            }
            Base_Address = "0x09605080";
            Address_Group = "0";
         }
      }
      class = "altera_avalon_timer";
      class_version = "7.071";
      iss_model_name = "altera_avalon_timer";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = "Timer with 1 ms timeout period.";
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         always_run = "0";
         fixed_period = "0";
         snapshot = "1";
         period = "1.0";
         period_units = "ms";
         reset_output = "0";
         timeout_pulse_output = "0";
         load_value = "99999";
         mult = "0.001";
      }
   }
   MODULE timer_stamp
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x096050a0";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "1";
            }
            Base_Address = "0x096050a0";
            Address_Group = "0";
         }
      }
      class = "altera_avalon_timer";
      class_version = "7.071";
      iss_model_name = "altera_avalon_timer";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = "Timer with 1 ms timeout period.";
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         always_run = "0";
         fixed_period = "0";
         snapshot = "1";
         period = "1.0";
         period_units = "ms";
         reset_output = "0";
         timeout_pulse_output = "0";
         load_value = "99999";
         mult = "0.001";
      }
   }
   MODULE jtag_uart
   {
      SLAVE avalon_jtag_slave
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT av_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_address
            {
               type = "address";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT av_write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               type = "dataavailable";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT readyfordata
            {
               type = "readyfordata";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT rst_n
            {
               type = "reset_n";
               direction = "input";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            JTAG_Hub_Base_Id = "262254";
            JTAG_Hub_Instance_Id = "0";
            Connection_Limit = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "2";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x096051e8";
            }
            Base_Address = "0x096051e8";
            Address_Group = "0";
         }
      }
      class = "altera_avalon_jtag_uart";
      class_version = "7.071";
      iss_model_name = "altera_avalon_jtag_uart";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         write_depth = "64";
         read_depth = "64";
         write_threshold = "8";
         read_threshold = "8";
         read_char_stream = "";
         showascii = "1";
         read_le = "0";
         write_le = "0";
         altera_show_unreleased_jtag_uart_features = "0";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL av_chipselect
            {
               name = "av_chipselect";
            }
            SIGNAL av_address
            {
               name = "av_address";
               radix = "hexadecimal";
            }
            SIGNAL av_read_n
            {
               name = "av_read_n";
            }
            SIGNAL av_readdata
            {
               name = "av_readdata";
               radix = "hexadecimal";
            }
            SIGNAL av_write_n
            {
               name = "av_write_n";
            }
            SIGNAL av_writedata
            {
               name = "av_writedata";
               radix = "hexadecimal";
            }
            SIGNAL av_waitrequest
            {
               name = "av_waitrequest";
            }
            SIGNAL dataavailable
            {
               name = "dataavailable";
            }
            SIGNAL readyfordata
            {
               name = "readyfordata";
            }
            SIGNAL av_irq
            {
               name = "av_irq";
            }
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "nios2-terminal";
         }
         INTERACTIVE_OUT log
         {
            enable = "1";
            exe = "perl -- atail-f.pl";
            file = "_output_stream.dat";
            radix = "ascii";
            signals = "temp,list";
         }
         Fix_Me_Up = "";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         Iss_Launch_Telnet = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
                <br>Read  Depth: 64; Read  IRQ Threshold: 8";
         }
      }
   }
   MODULE pll
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT inclk0
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT resetrequest
            {
               type = "resetrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x096050e0";
            }
            Clock_Source = "clk_50";
            Has_Clock = "1";
            Base_Address = "0x096050e0";
            Has_IRQ = "0";
            Date_Modified = "";
            Instantiate_In_System_Module = "1";
            Requires_Internal_Clock_Promotion = "Yes";
            Is_Clock_Source = "1";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT c0
         {
            type = "out_clk";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT c1
         {
            type = "out_clk";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT c2
         {
            type = "out_clk";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT areset
         {
            Is_Enabled = "0";
            direction = "input";
            width = "1";
         }
         PORT locked
         {
            Is_Enabled = "0";
            direction = "output";
            width = "1";
         }
         PORT pfdena
         {
            Is_Enabled = "0";
            direction = "input";
            width = "1";
         }
         PORT pllena
         {
            Is_Enabled = "0";
            direction = "input";
            width = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         areset = "None";
         pfdena = "None";
         locked = "None";
         pllena = "None";
         scanclk = "None";
         scandata = "None";
         scanread = "None";
         scanwrite = "None";
         scanclkena = "None";
         scanaclr = "None";
         scandataout = "None";
         scandone = "None";
         configupdate = "None";
         phasecounterselect = "None";
         phasedone = "None";
         phaseupdown = "None";
         phasestep = "None";
         UI_CONTROL 
         {
            pllena_port_exist = "0";
            areset_port_exist = "0";
            pfdena_port_exist = "0";
            locked_port_exist = "0";
         }
         ALTPLL_PORTS 
         {
            PORT inclk0
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT c0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT c1
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT c2
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
         }
         CLOCK_SOURCES 
         {
            CLOCK c0
            {
               DIVIDE_BY = "1";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "2";
               PHASE_SHIFT = "0";
               clk_index = "0";
               clock_freq = "100000000";
               clock_unit = "MHz";
               type = "out_clk";
            }
            CLOCK c1
            {
               DIVIDE_BY = "1";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "2";
               PHASE_SHIFT = "-1806";
               clk_index = "1";
               clock_freq = "100000000";
               clock_unit = "MHz";
               type = "out_clk";
            }
            CLOCK c2
            {
               DIVIDE_BY = "11";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "4";
               PHASE_SHIFT = "0";
               clk_index = "2";
               clock_freq = "18181818";
               clock_unit = "MHz";
               type = "out_clk";
            }
         }
         CLOCK_INFO 
         {
            CLOCK inclk0
            {
               clock_freq = "50000000";
               clock_unit = "MHz";
               type = "in_clk";
            }
         }
         CNX_INFO 
         {
            CONSTANT 
            {
               NUMERIC 
               {
                  CLK0_DIVIDE_BY = "1";
                  CLK0_DUTY_CYCLE = "50";
                  CLK0_MULTIPLY_BY = "2";
                  CLK1_DIVIDE_BY = "1";
                  CLK1_DUTY_CYCLE = "50";
                  CLK1_MULTIPLY_BY = "2";
                  CLK2_DIVIDE_BY = "11";
                  CLK2_DUTY_CYCLE = "50";
                  CLK2_MULTIPLY_BY = "4";
                  INCLK0_INPUT_FREQUENCY = "20000";
               }
               STRING 
               {
                  CLK0_PHASE_SHIFT = "0";
                  CLK1_PHASE_SHIFT = "-1806";
                  CLK2_PHASE_SHIFT = "0";
                  COMPENSATE_CLOCK = "CLK0";
                  INTENDED_DEVICE_FAMILY = "Cyclone II";
                  LPM_TYPE = "altpll";
                  OPERATION_MODE = "NORMAL";
                  PORT_ACTIVECLOCK = "PORT_UNUSED";
                  PORT_ARESET = "PORT_UNUSED";
                  PORT_CLKBAD0 = "PORT_UNUSED";
                  PORT_CLKBAD1 = "PORT_UNUSED";
                  PORT_CLKLOSS = "PORT_UNUSED";
                  PORT_CLKSWITCH = "PORT_UNUSED";
                  PORT_CONFIGUPDATE = "PORT_UNUSED";
                  PORT_FBIN = "PORT_UNUSED";
                  PORT_INCLK0 = "PORT_USED";
                  PORT_INCLK1 = "PORT_UNUSED";
                  PORT_LOCKED = "PORT_UNUSED";
                  PORT_PFDENA = "PORT_UNUSED";
                  PORT_PHASECOUNTERSELECT = "PORT_UNUSED";
                  PORT_PHASEDONE = "PORT_UNUSED";
                  PORT_PHASESTEP = "PORT_UNUSED";
                  PORT_PHASEUPDOWN = "PORT_UNUSED";
                  PORT_PLLENA = "PORT_UNUSED";
                  PORT_SCANACLR = "PORT_UNUSED";
                  PORT_SCANCLK = "PORT_UNUSED";
                  PORT_SCANCLKENA = "PORT_UNUSED";
                  PORT_SCANDATA = "PORT_UNUSED";
                  PORT_SCANDATAOUT = "PORT_UNUSED";
                  PORT_SCANDONE = "PORT_UNUSED";
                  PORT_SCANREAD = "PORT_UNUSED";
                  PORT_SCANWRITE = "PORT_UNUSED";
                  PORT_clk0 = "PORT_USED";
                  PORT_clk1 = "PORT_USED";
                  PORT_clk2 = "PORT_USED";
                  PORT_clk3 = "PORT_UNUSED";
                  PORT_clk4 = "PORT_UNUSED";
                  PORT_clk5 = "PORT_UNUSED";
                  PORT_clkena0 = "PORT_UNUSED";
                  PORT_clkena1 = "PORT_UNUSED";
                  PORT_clkena2 = "PORT_UNUSED";
                  PORT_clkena3 = "PORT_UNUSED";
                  PORT_clkena4 = "PORT_UNUSED";
                  PORT_clkena5 = "PORT_UNUSED";
                  PORT_extclk0 = "PORT_UNUSED";
                  PORT_extclk1 = "PORT_UNUSED";
                  PORT_extclk2 = "PORT_UNUSED";
                  PORT_extclk3 = "PORT_UNUSED";
               }
            }
            GEN_FILE 
            {
               TYPE_NORMAL 
               {
                  TRUE 
                  {
                     File1 = ".v";
                     File2 = ".ppf";
                  }
                  FALSE 
                  {
                     File3 = ".inc";
                     File4 = ".cmp";
                     File5 = ".bsf";
                     File6 = "_inst.v";
                     File7 = "_bb.v";
                     File8 = "_waveforms.html";
                     File9 = "_wave*.jpg";
                  }
               }
            }
            LIBRARY = "altera_mf altera_mf.altera_mf_components.all";
            PRIVATE 
            {
               STRING 
               {
                  ACTIVECLK_CHECK = "0";
                  BANDWIDTH = "1.000";
                  BANDWIDTH_FEATURE_ENABLED = "0";
                  BANDWIDTH_FREQ_UNIT = "MHz";
                  BANDWIDTH_PRESET = "Low";
                  BANDWIDTH_USE_AUTO = "1";
                  BANDWIDTH_USE_CUSTOM = "0";
                  BANDWIDTH_USE_PRESET = "0";
                  CLKBAD_SWITCHOVER_CHECK = "0";
                  CLKLOSS_CHECK = "0";
                  CLKSWITCH_CHECK = "0";
                  CNX_NO_COMPENSATE_RADIO = "0";
                  CREATE_CLKBAD_CHECK = "0";
                  CREATE_INCLK1_CHECK = "0";
                  CUR_DEDICATED_CLK = "c0";
                  CUR_FBIN_CLK = "e0";
                  DEVICE_SPEED_GRADE = "Any";
                  DUTY_CYCLE0 = "50.00000000";
                  DUTY_CYCLE1 = "50.00000000";
                  DUTY_CYCLE2 = "50.00000000";
                  EXPLICIT_SWITCHOVER_COUNTER = "0";
                  EXT_FEEDBACK_RADIO = "0";
                  GLOCKED_COUNTER_EDIT_CHANGED = "1";
                  GLOCKED_FEATURE_ENABLED = "1";
                  GLOCKED_MODE_CHECK = "0";
                  HAS_MANUAL_SWITCHOVER = "1";
                  INCLK0_FREQ_EDIT = "50.000";
                  INCLK0_FREQ_UNIT_COMBO = "MHz";
                  INCLK1_FREQ_EDIT = "100.000";
                  INCLK1_FREQ_EDIT_CHANGED = "1";
                  INCLK1_FREQ_UNIT_CHANGED = "1";
                  INCLK1_FREQ_UNIT_COMBO = "MHz";
                  INTENDED_DEVICE_FAMILY = "Cyclone II";
                  INT_FEEDBACK__MODE_RADIO = "1";
                  LOCKED_OUTPUT_CHECK = "0";
                  LONG_SCAN_RADIO = "1";
                  LVDS_MODE_DATA_RATE = "Not Available";
                  LVDS_PHASE_SHIFT_UNIT0 = "ps";
                  LVDS_PHASE_SHIFT_UNIT1 = "ps";
                  LVDS_PHASE_SHIFT_UNIT2 = "ps";
                  MIRROR_CLK0 = "0";
                  MIRROR_CLK1 = "0";
                  MIRROR_CLK2 = "0";
                  NORMAL_MODE_RADIO = "1";
                  OUTPUT_FREQ0 = "0.00010000";
                  OUTPUT_FREQ1 = "100.00000000";
                  OUTPUT_FREQ2 = "18.32400000";
                  OUTPUT_FREQ_MODE0 = "0";
                  OUTPUT_FREQ_MODE1 = "0";
                  OUTPUT_FREQ_MODE2 = "0";
                  OUTPUT_FREQ_UNIT0 = "MHz";
                  OUTPUT_FREQ_UNIT1 = "MHz";
                  OUTPUT_FREQ_UNIT2 = "MHz";
                  PHASE_RECONFIG_FEATURE_ENABLED = "0";
                  PHASE_RECONFIG_INPUTS_CHECK = "0";
                  PHASE_SHIFT0 = "0.00000000";
                  PHASE_SHIFT1 = "-65.00000000";
                  PHASE_SHIFT2 = "0.00000000";
                  PHASE_SHIFT_STEP_ENABLED_CHECK = "0";
                  PHASE_SHIFT_UNIT0 = "ps";
                  PHASE_SHIFT_UNIT1 = "deg";
                  PHASE_SHIFT_UNIT2 = "deg";
                  PLL_ADVANCED_PARAM_CHECK = "0";
                  PLL_ARESET_CHECK = "0";
                  PLL_ENA_CHECK = "0";
                  PLL_FBMIMIC_CHECK = "0";
                  PLL_PFDENA_CHECK = "0";
                  PRIMARY_CLK_COMBO = "inclk0";
                  SACN_INPUTS_CHECK = "0";
                  SCAN_FEATURE_ENABLED = "0";
                  SELF_RESET_LOCK_LOSS = "0";
                  SHORT_SCAN_RADIO = "0";
                  SPREAD_FEATURE_ENABLED = "0";
                  SPREAD_FREQ = "50.000";
                  SPREAD_FREQ_UNIT = "KHz";
                  SPREAD_PERCENT = "0.500";
                  SPREAD_USE = "0";
                  SRC_SYNCH_COMP_RADIO = "0";
                  STICKY_CLK0 = "1";
                  STICKY_CLK1 = "1";
                  STICKY_CLK2 = "1";
                  SWITCHOVER_FEATURE_ENABLED = "1";
                  SYNTH_WRAPPER_GEN_POSTFIX = "0";
                  USE_CLK0 = "1";
                  USE_CLK1 = "1";
                  USE_CLK2 = "1";
                  USE_CLKENA0 = "0";
                  USE_CLKENA1 = "0";
                  USE_CLKENA2 = "0";
                  ZERO_DELAY_RADIO = "0";
               }
               NUMERIC 
               {
                  DIV_FACTOR0 = "1";
                  DIV_FACTOR1 = "1";
                  DIV_FACTOR2 = "11";
                  GLOCK_COUNTER_EDIT = "1048575";
                  LVDS_MODE_DATA_RATE_DIRTY = "0";
                  MULT_FACTOR0 = "2";
                  MULT_FACTOR1 = "2";
                  MULT_FACTOR2 = "4";
                  PLL_AUTOPLL_CHECK = "1";
                  PLL_ENHPLL_CHECK = "0";
                  PLL_FASTPLL_CHECK = "0";
                  PLL_LVDS_PLL_CHECK = "0";
                  PLL_TARGET_HARCOPY_CHECK = "0";
                  SWITCHOVER_COUNT_EDIT = "1";
               }
            }
            USED_PORT 
            {
               c0 
               {
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "0";
                  VALUE_5 = "OUTPUT_CLK_EXT";
                  VALUE_6 = "VCC";
                  VALUE_7 = "c0";
               }
               c1 
               {
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "0";
                  VALUE_5 = "OUTPUT_CLK_EXT";
                  VALUE_6 = "VCC";
                  VALUE_7 = "c1";
               }
               c2 
               {
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "0";
                  VALUE_5 = "OUTPUT_CLK_EXT";
                  VALUE_6 = "VCC";
                  VALUE_7 = "c2";
               }
               inclk0 
               {
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "0";
                  VALUE_5 = "INPUT_CLK_EXT";
                  VALUE_6 = "GND";
                  VALUE_7 = "inclk0";
               }
            }
         }
         Config_Done = "0";
      }
      SYSTEM_BUILDER_INFO 
      {
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIII,STRATIXIIGX,CYCLONE,CYCLONEII,CYCLONEIII,ARRIAGX,STRATIXIIGXLITE";
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "pll";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk_50";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " Avalon PLL: <br>
         input clock configured: <b>clk_50</b>
        ";
         }
      }
      class = "altera_avalon_pll";
      class_version = "7.071";
      HDL_INFO 
      {
         # The list of files associated with this module (for synthesis
         # and other purposes) depends on the users' wizard-choices.
         # This section will be filled-in by the Generator_Program
         # after the module logic has been created and the
         # various filenames are known.
      }
   }
   MODULE tristate_bridge_flash
   {
      SLAVE avalon_slave
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "1";
            Register_Outgoing_Signals = "1";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            Bridges_To = "tristate_master";
            Base_Address = "N/A";
            Has_IRQ = "0";
            IRQ = "N/A";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Bridges_To = "avalon_slave";
         }
         PORT_WIRING 
         {
         }
         MEMORY_MAP 
         {
            Entry cfi_flash/s1
            {
               address = "0x08800000";
               span = "0x00800000";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      class = "altera_avalon_tri_state_bridge";
      class_version = "7.071";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "pll_c0_system";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
   }
}
