Classic Timing Analyzer report for Altshift_tabs_lab0
Tue Aug 26 17:05:13 2008
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clock'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                         ;
+------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                                                                                                            ; To                                                                                                                             ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 3.126 ns                                       ; shiftin[2]                                                                                                                      ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg2 ; --         ; clock    ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.039 ns                                       ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[10]                         ; shiftout[2]                                                                                                                    ; clock      ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.574 ns                                       ; shiftin[1]                                                                                                                      ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg1 ; --         ; clock    ; 0            ;
; Clock Setup: 'clock'         ; N/A   ; None          ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[11]                        ; clock      ; clock    ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                                                                 ;                                                                                                                                ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C70F896C6       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                                            ; To                                                                                                                              ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[0]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[0]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[1]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[1]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[2]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[2]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[3]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[3]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[4]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[4]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[5]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[5]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[6]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[6]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[7]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[7]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[8]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[8]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[9]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[9]                          ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[10]                         ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[10]                         ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[11]                         ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[11]                         ; clock      ; clock    ; None                        ; None                      ; 2.892 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg0  ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg1  ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a1~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg2  ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a2~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg3  ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a3~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg4  ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a4~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg5  ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a5~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg6  ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a6~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg7  ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a7~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg8  ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a8~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg9  ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a9~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg10 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a10~porta_memory_reg0 ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg11 ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a11~porta_memory_reg0 ; clock      ; clock    ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[1]                          ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg5  ; clock      ; clock    ; None                        ; None                      ; 1.162 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|dffe3a[1]                                                   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg1 ; clock      ; clock    ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[3]                          ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg7  ; clock      ; clock    ; None                        ; None                      ; 0.960 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[4]                          ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg8  ; clock      ; clock    ; None                        ; None                      ; 0.955 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[0]                          ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg4  ; clock      ; clock    ; None                        ; None                      ; 0.948 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[0]                           ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_address_reg0 ; clock      ; clock    ; None                        ; None                      ; 0.728 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[1]                           ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_address_reg1 ; clock      ; clock    ; None                        ; None                      ; 0.717 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|dffe3a[0]                                                   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0 ; clock      ; clock    ; None                        ; None                      ; 0.719 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[2]                          ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg6  ; clock      ; clock    ; None                        ; None                      ; 0.706 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[5]                          ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg9  ; clock      ; clock    ; None                        ; None                      ; 0.706 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[7]                          ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg11 ; clock      ; clock    ; None                        ; None                      ; 0.702 ns                ;
; N/A   ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[6]                          ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg10 ; clock      ; clock    ; None                        ; None                      ; 0.697 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[0]                           ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|dffe3a[0]                                                   ; clock      ; clock    ; None                        ; None                      ; 0.555 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[1]                           ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[0]                           ; clock      ; clock    ; None                        ; None                      ; 0.554 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[0]                           ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[1]                           ; clock      ; clock    ; None                        ; None                      ; 0.554 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[1]                           ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|dffe3a[1]                                                   ; clock      ; clock    ; None                        ; None                      ; 0.554 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[0]                           ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[0]                           ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[1]                           ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|cntr_kkf:cntr1|current_reg_q_w[1]                           ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                                                        ;
+-------+--------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From       ; To                                                                                                                             ; To Clock ;
+-------+--------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------+----------+
; N/A   ; None         ; 3.126 ns   ; shiftin[3] ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg3 ; clock    ;
; N/A   ; None         ; 3.126 ns   ; shiftin[2] ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg2 ; clock    ;
; N/A   ; None         ; -0.132 ns  ; shiftin[0] ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg0 ; clock    ;
; N/A   ; None         ; -0.305 ns  ; shiftin[1] ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg1 ; clock    ;
+-------+--------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------+----------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                    ;
+-------+--------------+------------+---------------------------------------------------------------------------------------------------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                                                    ; To          ; From Clock ;
+-------+--------------+------------+---------------------------------------------------------------------------------------------------------+-------------+------------+
; N/A   ; None         ; 7.039 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[10] ; shiftout[2] ; clock      ;
; N/A   ; None         ; 7.034 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[8]  ; shiftout[0] ; clock      ;
; N/A   ; None         ; 7.028 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[6]  ; taps1x[2]   ; clock      ;
; N/A   ; None         ; 7.027 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[10] ; taps2x[2]   ; clock      ;
; N/A   ; None         ; 7.001 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[9]  ; shiftout[1] ; clock      ;
; N/A   ; None         ; 6.847 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[7]  ; taps1x[3]   ; clock      ;
; N/A   ; None         ; 6.833 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[0]  ; taps0x[0]   ; clock      ;
; N/A   ; None         ; 6.830 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[4]  ; taps1x[0]   ; clock      ;
; N/A   ; None         ; 6.819 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[8]  ; taps2x[0]   ; clock      ;
; N/A   ; None         ; 6.812 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[11] ; taps2x[3]   ; clock      ;
; N/A   ; None         ; 6.812 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[2]  ; taps0x[2]   ; clock      ;
; N/A   ; None         ; 6.812 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[11] ; shiftout[3] ; clock      ;
; N/A   ; None         ; 6.803 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[3]  ; taps0x[3]   ; clock      ;
; N/A   ; None         ; 6.775 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[9]  ; taps2x[1]   ; clock      ;
; N/A   ; None         ; 6.593 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[5]  ; taps1x[1]   ; clock      ;
; N/A   ; None         ; 6.577 ns   ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[1]  ; taps0x[1]   ; clock      ;
+-------+--------------+------------+---------------------------------------------------------------------------------------------------------+-------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                                                               ;
+---------------+-------------+-----------+------------+--------------------------------------------------------------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To                                                                                                                             ; To Clock ;
+---------------+-------------+-----------+------------+--------------------------------------------------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; 0.574 ns  ; shiftin[1] ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg1 ; clock    ;
; N/A           ; None        ; 0.401 ns  ; shiftin[0] ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg0 ; clock    ;
; N/A           ; None        ; -2.857 ns ; shiftin[3] ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg3 ; clock    ;
; N/A           ; None        ; -2.857 ns ; shiftin[2] ; altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg2 ; clock    ;
+---------------+-------------+-----------+------------+--------------------------------------------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Tue Aug 26 17:05:13 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Altshift_tabs_lab0 -c Altshift_tabs_lab0 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 235.07 MHz between source memory "altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0" and destination memory "altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[0]"
    Info: fmax restricted to Clock High delay (2.127 ns) plus Clock Low delay (2.127 ns) : restricted to 4.254 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 2.892 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X64_Y50; Fanout = 12; MEM Node = 'altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0'
            Info: 2: + IC(0.000 ns) + CELL(2.892 ns) = 2.892 ns; Loc. = M4K_X64_Y50; Fanout = 2; MEM Node = 'altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[0]'
            Info: Total cell delay = 2.892 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.053 ns
            Info: + Shortest clock path from clock "clock" to destination memory is 2.935 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 44; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(1.196 ns) + CELL(0.636 ns) = 2.935 ns; Loc. = M4K_X64_Y50; Fanout = 2; MEM Node = 'altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[0]'
                Info: Total cell delay = 1.625 ns ( 55.37 % )
                Info: Total interconnect delay = 1.310 ns ( 44.63 % )
            Info: - Longest clock path from clock "clock" to source memory is 2.988 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 44; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(1.196 ns) + CELL(0.689 ns) = 2.988 ns; Loc. = M4K_X64_Y50; Fanout = 12; MEM Node = 'altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~portb_address_reg0'
                Info: Total cell delay = 1.678 ns ( 56.16 % )
                Info: Total interconnect delay = 1.310 ns ( 43.84 % )
        Info: + Micro clock to output delay of source is 0.209 ns
        Info: + Micro setup delay of destination is 0.035 ns
Info: tsu for memory "altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg3" (data pin = "shiftin[3]", clock pin = "clock") is 3.126 ns
    Info: + Longest pin to memory delay is 6.050 ns
        Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_J18; Fanout = 1; PIN Node = 'shiftin[3]'
        Info: 2: + IC(5.134 ns) + CELL(0.106 ns) = 6.050 ns; Loc. = M4K_X64_Y50; Fanout = 1; MEM Node = 'altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg3'
        Info: Total cell delay = 0.916 ns ( 15.14 % )
        Info: Total interconnect delay = 5.134 ns ( 84.86 % )
    Info: + Micro setup delay of destination is 0.035 ns
    Info: - Shortest clock path from clock "clock" to destination memory is 2.959 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 44; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.196 ns) + CELL(0.660 ns) = 2.959 ns; Loc. = M4K_X64_Y50; Fanout = 1; MEM Node = 'altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg3'
        Info: Total cell delay = 1.649 ns ( 55.73 % )
        Info: Total interconnect delay = 1.310 ns ( 44.27 % )
Info: tco from clock "clock" to destination pin "shiftout[2]" through memory "altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[10]" is 7.039 ns
    Info: + Longest clock path from clock "clock" to source memory is 2.935 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 44; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.196 ns) + CELL(0.636 ns) = 2.935 ns; Loc. = M4K_X64_Y50; Fanout = 2; MEM Node = 'altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[10]'
        Info: Total cell delay = 1.625 ns ( 55.37 % )
        Info: Total interconnect delay = 1.310 ns ( 44.63 % )
    Info: + Micro clock to output delay of source is 0.209 ns
    Info: + Longest memory to pin delay is 3.895 ns
        Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X64_Y50; Fanout = 2; MEM Node = 'altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|q_b[10]'
        Info: 2: + IC(1.009 ns) + CELL(2.798 ns) = 3.895 ns; Loc. = PIN_B17; Fanout = 0; PIN Node = 'shiftout[2]'
        Info: Total cell delay = 2.886 ns ( 74.09 % )
        Info: Total interconnect delay = 1.009 ns ( 25.91 % )
Info: th for memory "altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg1" (data pin = "shiftin[1]", clock pin = "clock") is 0.574 ns
    Info: + Longest clock path from clock "clock" to destination memory is 2.959 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 44; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.196 ns) + CELL(0.660 ns) = 2.959 ns; Loc. = M4K_X64_Y50; Fanout = 1; MEM Node = 'altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg1'
        Info: Total cell delay = 1.649 ns ( 55.73 % )
        Info: Total interconnect delay = 1.310 ns ( 44.27 % )
    Info: + Micro hold delay of destination is 0.234 ns
    Info: - Shortest pin to memory delay is 2.619 ns
        Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_H15; Fanout = 1; PIN Node = 'shiftin[1]'
        Info: 2: + IC(1.554 ns) + CELL(0.106 ns) = 2.619 ns; Loc. = M4K_X64_Y50; Fanout = 1; MEM Node = 'altshift_taps:altshift_taps_component|shift_taps_vsm:auto_generated|altsyncram_9g31:altsyncram4|ram_block5a0~porta_datain_reg1'
        Info: Total cell delay = 1.065 ns ( 40.66 % )
        Info: Total interconnect delay = 1.554 ns ( 59.34 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 119 megabytes of memory during processing
    Info: Processing ended: Tue Aug 26 17:05:13 2008
    Info: Elapsed time: 00:00:00


