Classic Timing Analyzer report for Add2_always_good
Sat Oct 04 10:02:47 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'iCLK'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                    ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From         ; To           ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 3.410 ns                                       ; iA[3]        ; a[3]         ; --         ; iCLK     ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 8.517 ns                                       ; oSUM[8]~reg0 ; oSUM[8]      ; iCLK       ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.602 ns                                       ; iA[0]        ; a[0]         ; --         ; iCLK     ; 0            ;
; Clock Setup: 'iCLK'          ; N/A   ; None          ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[0]         ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;              ;              ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C70F896C6       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; iCLK            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'iCLK'                                                                                                                                                                      ;
+-------+------------------------------------------------+------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From ; To           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[0] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 2.005 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[0] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.934 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[0] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.863 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[5] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.815 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[0] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.792 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[0] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.776 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[5] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.776 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[1] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.746 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[5] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.744 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[0] ; oSUM[4]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.721 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[1] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.708 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[0] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.705 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[3] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.699 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[5] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.705 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[6] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.696 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[1] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.675 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[6] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.674 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[5] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.673 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[0] ; oSUM[3]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.650 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[4] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.640 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[1] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.637 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[7] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.635 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[0] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.634 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[3] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.628 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[5] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.634 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[6] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.625 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[1] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.604 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[6] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.603 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[7] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.597 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[4] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.593 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[2] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.587 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[0] ; oSUM[2]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.579 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[4] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.569 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[1] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.566 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[0] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.563 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[3] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.557 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[2] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.552 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[1] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.533 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[4] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.522 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[2] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.516 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[4] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.498 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[1] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.495 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[0] ; oSUM[4]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.492 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[3] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.486 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[2] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.481 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[3] ; oSUM[8]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.474 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[1] ; oSUM[4]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.462 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[4] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.451 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[2] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.445 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[4] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.427 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[1] ; oSUM[4]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.424 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[0] ; oSUM[3]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.421 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[0] ; oSUM[1]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.420 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[3] ; oSUM[4]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.415 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[2] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.410 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[3] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.403 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[1] ; oSUM[3]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.391 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[4] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.380 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[2] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.374 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[1] ; oSUM[3]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.353 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[0] ; oSUM[2]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.350 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[2] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.339 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[3] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.332 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[1] ; oSUM[2]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.320 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[2] ; oSUM[4]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.303 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[1] ; oSUM[2]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.282 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[5] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.287 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[2] ; oSUM[4]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.268 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[3] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.261 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[7] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.249 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[6] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.239 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[5] ; oSUM[5]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.247 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[2] ; oSUM[3]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.232 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[6] ; oSUM[6]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.220 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[7] ; oSUM[7]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.210 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[2] ; oSUM[3]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.197 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[0] ; oSUM[1]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.191 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[3] ; oSUM[4]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.190 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[4] ; oSUM[4]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.041 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[0] ; oSUM[0]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.033 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[3] ; oSUM[3]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 1.029 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[4] ; oSUM[4]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 0.997 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[2] ; oSUM[2]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 0.846 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[1] ; oSUM[1]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 0.844 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[2] ; oSUM[2]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 0.814 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; a[0] ; oSUM[0]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 0.808 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[1] ; oSUM[1]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 0.803 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; b[3] ; oSUM[3]~reg0 ; iCLK       ; iCLK     ; None                        ; None                      ; 0.803 ns                ;
+-------+------------------------------------------------+------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------+
; tsu                                                         ;
+-------+--------------+------------+-------+------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To   ; To Clock ;
+-------+--------------+------------+-------+------+----------+
; N/A   ; None         ; 3.410 ns   ; iA[3] ; a[3] ; iCLK     ;
; N/A   ; None         ; 3.409 ns   ; iB[2] ; b[2] ; iCLK     ;
; N/A   ; None         ; 3.397 ns   ; iA[1] ; a[1] ; iCLK     ;
; N/A   ; None         ; 3.326 ns   ; iA[4] ; a[4] ; iCLK     ;
; N/A   ; None         ; 3.213 ns   ; iB[4] ; b[4] ; iCLK     ;
; N/A   ; None         ; 3.167 ns   ; iB[5] ; b[5] ; iCLK     ;
; N/A   ; None         ; 3.165 ns   ; iA[6] ; a[6] ; iCLK     ;
; N/A   ; None         ; 3.083 ns   ; iB[3] ; b[3] ; iCLK     ;
; N/A   ; None         ; 2.925 ns   ; iB[1] ; b[1] ; iCLK     ;
; N/A   ; None         ; 2.924 ns   ; iB[6] ; b[6] ; iCLK     ;
; N/A   ; None         ; 2.914 ns   ; iA[5] ; a[5] ; iCLK     ;
; N/A   ; None         ; 2.907 ns   ; iB[7] ; b[7] ; iCLK     ;
; N/A   ; None         ; 2.906 ns   ; iA[7] ; a[7] ; iCLK     ;
; N/A   ; None         ; 2.902 ns   ; iA[2] ; a[2] ; iCLK     ;
; N/A   ; None         ; -0.284 ns  ; iB[0] ; b[0] ; iCLK     ;
; N/A   ; None         ; -0.372 ns  ; iA[0] ; a[0] ; iCLK     ;
+-------+--------------+------------+-------+------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 8.517 ns   ; oSUM[8]~reg0 ; oSUM[8] ; iCLK       ;
; N/A   ; None         ; 6.883 ns   ; oSUM[1]~reg0 ; oSUM[1] ; iCLK       ;
; N/A   ; None         ; 6.841 ns   ; oSUM[3]~reg0 ; oSUM[3] ; iCLK       ;
; N/A   ; None         ; 6.841 ns   ; oSUM[0]~reg0 ; oSUM[0] ; iCLK       ;
; N/A   ; None         ; 6.832 ns   ; oSUM[4]~reg0 ; oSUM[4] ; iCLK       ;
; N/A   ; None         ; 6.578 ns   ; oSUM[5]~reg0 ; oSUM[5] ; iCLK       ;
; N/A   ; None         ; 6.556 ns   ; oSUM[6]~reg0 ; oSUM[6] ; iCLK       ;
; N/A   ; None         ; 6.549 ns   ; oSUM[7]~reg0 ; oSUM[7] ; iCLK       ;
; N/A   ; None         ; 6.543 ns   ; oSUM[2]~reg0 ; oSUM[2] ; iCLK       ;
+-------+--------------+------------+--------------+---------+------------+


+-------------------------------------------------------------------+
; th                                                                ;
+---------------+-------------+-----------+-------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To   ; To Clock ;
+---------------+-------------+-----------+-------+------+----------+
; N/A           ; None        ; 0.602 ns  ; iA[0] ; a[0] ; iCLK     ;
; N/A           ; None        ; 0.514 ns  ; iB[0] ; b[0] ; iCLK     ;
; N/A           ; None        ; -2.672 ns ; iA[2] ; a[2] ; iCLK     ;
; N/A           ; None        ; -2.676 ns ; iA[7] ; a[7] ; iCLK     ;
; N/A           ; None        ; -2.677 ns ; iB[7] ; b[7] ; iCLK     ;
; N/A           ; None        ; -2.684 ns ; iA[5] ; a[5] ; iCLK     ;
; N/A           ; None        ; -2.694 ns ; iB[6] ; b[6] ; iCLK     ;
; N/A           ; None        ; -2.695 ns ; iB[1] ; b[1] ; iCLK     ;
; N/A           ; None        ; -2.853 ns ; iB[3] ; b[3] ; iCLK     ;
; N/A           ; None        ; -2.935 ns ; iA[6] ; a[6] ; iCLK     ;
; N/A           ; None        ; -2.937 ns ; iB[5] ; b[5] ; iCLK     ;
; N/A           ; None        ; -2.983 ns ; iB[4] ; b[4] ; iCLK     ;
; N/A           ; None        ; -3.096 ns ; iA[4] ; a[4] ; iCLK     ;
; N/A           ; None        ; -3.167 ns ; iA[1] ; a[1] ; iCLK     ;
; N/A           ; None        ; -3.179 ns ; iB[2] ; b[2] ; iCLK     ;
; N/A           ; None        ; -3.180 ns ; iA[3] ; a[3] ; iCLK     ;
+---------------+-------------+-----------+-------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Sat Oct 04 10:02:46 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Add2_always_good -c Add2_always_good --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "iCLK" is an undefined clock
Info: Clock "iCLK" Internal fmax is restricted to 420.17 MHz between source register "b[0]" and destination register "oSUM[8]~reg0"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.005 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X66_Y50_N9; Fanout = 2; REG Node = 'b[0]'
            Info: 2: + IC(0.512 ns) + CELL(0.414 ns) = 0.926 ns; Loc. = LCCOMB_X66_Y50_N12; Fanout = 2; COMB Node = 'oSUM[0]~55'
            Info: 3: + IC(0.000 ns) + CELL(0.159 ns) = 1.085 ns; Loc. = LCCOMB_X66_Y50_N14; Fanout = 2; COMB Node = 'oSUM[1]~57'
            Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.156 ns; Loc. = LCCOMB_X66_Y50_N16; Fanout = 2; COMB Node = 'oSUM[2]~59'
            Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.227 ns; Loc. = LCCOMB_X66_Y50_N18; Fanout = 2; COMB Node = 'oSUM[3]~61'
            Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.298 ns; Loc. = LCCOMB_X66_Y50_N20; Fanout = 2; COMB Node = 'oSUM[4]~63'
            Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.369 ns; Loc. = LCCOMB_X66_Y50_N22; Fanout = 2; COMB Node = 'oSUM[5]~65'
            Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.440 ns; Loc. = LCCOMB_X66_Y50_N24; Fanout = 2; COMB Node = 'oSUM[6]~67'
            Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.511 ns; Loc. = LCCOMB_X66_Y50_N26; Fanout = 1; COMB Node = 'oSUM[7]~69'
            Info: 10: + IC(0.000 ns) + CELL(0.410 ns) = 1.921 ns; Loc. = LCCOMB_X66_Y50_N28; Fanout = 1; COMB Node = 'oSUM[8]~70'
            Info: 11: + IC(0.000 ns) + CELL(0.084 ns) = 2.005 ns; Loc. = LCFF_X66_Y50_N29; Fanout = 1; REG Node = 'oSUM[8]~reg0'
            Info: Total cell delay = 1.493 ns ( 74.46 % )
            Info: Total interconnect delay = 0.512 ns ( 25.54 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "iCLK" to destination register is 2.912 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'iCLK'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'iCLK~clkctrl'
                Info: 3: + IC(1.272 ns) + CELL(0.537 ns) = 2.912 ns; Loc. = LCFF_X66_Y50_N29; Fanout = 1; REG Node = 'oSUM[8]~reg0'
                Info: Total cell delay = 1.526 ns ( 52.40 % )
                Info: Total interconnect delay = 1.386 ns ( 47.60 % )
            Info: - Longest clock path from clock "iCLK" to source register is 2.912 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'iCLK'
                Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'iCLK~clkctrl'
                Info: 3: + IC(1.272 ns) + CELL(0.537 ns) = 2.912 ns; Loc. = LCFF_X66_Y50_N9; Fanout = 2; REG Node = 'b[0]'
                Info: Total cell delay = 1.526 ns ( 52.40 % )
                Info: Total interconnect delay = 1.386 ns ( 47.60 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "a[3]" (data pin = "iA[3]", clock pin = "iCLK") is 3.410 ns
    Info: + Longest pin to register delay is 6.358 ns
        Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_A19; Fanout = 1; PIN Node = 'iA[3]'
        Info: 2: + IC(5.265 ns) + CELL(0.149 ns) = 6.274 ns; Loc. = LCCOMB_X65_Y50_N0; Fanout = 1; COMB Node = 'a[3]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.358 ns; Loc. = LCFF_X65_Y50_N1; Fanout = 2; REG Node = 'a[3]'
        Info: Total cell delay = 1.093 ns ( 17.19 % )
        Info: Total interconnect delay = 5.265 ns ( 82.81 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "iCLK" to destination register is 2.912 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'iCLK'
        Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'iCLK~clkctrl'
        Info: 3: + IC(1.272 ns) + CELL(0.537 ns) = 2.912 ns; Loc. = LCFF_X65_Y50_N1; Fanout = 2; REG Node = 'a[3]'
        Info: Total cell delay = 1.526 ns ( 52.40 % )
        Info: Total interconnect delay = 1.386 ns ( 47.60 % )
Info: tco from clock "iCLK" to destination pin "oSUM[8]" through register "oSUM[8]~reg0" is 8.517 ns
    Info: + Longest clock path from clock "iCLK" to source register is 2.912 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'iCLK'
        Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'iCLK~clkctrl'
        Info: 3: + IC(1.272 ns) + CELL(0.537 ns) = 2.912 ns; Loc. = LCFF_X66_Y50_N29; Fanout = 1; REG Node = 'oSUM[8]~reg0'
        Info: Total cell delay = 1.526 ns ( 52.40 % )
        Info: Total interconnect delay = 1.386 ns ( 47.60 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.355 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X66_Y50_N29; Fanout = 1; REG Node = 'oSUM[8]~reg0'
        Info: 2: + IC(2.586 ns) + CELL(2.769 ns) = 5.355 ns; Loc. = PIN_H23; Fanout = 0; PIN Node = 'oSUM[8]'
        Info: Total cell delay = 2.769 ns ( 51.71 % )
        Info: Total interconnect delay = 2.586 ns ( 48.29 % )
Info: th for register "a[0]" (data pin = "iA[0]", clock pin = "iCLK") is 0.602 ns
    Info: + Longest clock path from clock "iCLK" to destination register is 2.912 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'iCLK'
        Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'iCLK~clkctrl'
        Info: 3: + IC(1.272 ns) + CELL(0.537 ns) = 2.912 ns; Loc. = LCFF_X66_Y50_N3; Fanout = 2; REG Node = 'a[0]'
        Info: Total cell delay = 1.526 ns ( 52.40 % )
        Info: Total interconnect delay = 1.386 ns ( 47.60 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.576 ns
        Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_H15; Fanout = 1; PIN Node = 'iA[0]'
        Info: 2: + IC(1.384 ns) + CELL(0.149 ns) = 2.492 ns; Loc. = LCCOMB_X66_Y50_N2; Fanout = 1; COMB Node = 'a[0]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.576 ns; Loc. = LCFF_X66_Y50_N3; Fanout = 2; REG Node = 'a[0]'
        Info: Total cell delay = 1.192 ns ( 46.27 % )
        Info: Total interconnect delay = 1.384 ns ( 53.73 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 129 megabytes
    Info: Processing ended: Sat Oct 04 10:02:47 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


