module Add2_always_bad (
  input            iCLK,
  input            iRST_N,
  input      [7:0] iA,
  input      [7:0] iB,
  output reg [8:0] oSUM
);

always@(posedge iCLK, negedge iRST_N) begin
  if (!iRST_N)
    oSUM <= 0;
  else 
    oSUM <= iA + iB;
end

endmodule